1 /* 2 * Copyright (C) 2000, 2001 Broadcom Corporation 3 * 4 * This program is free software; you can redistribute it and/or 5 * modify it under the terms of the GNU General Public License 6 * as published by the Free Software Foundation; either version 2 7 * of the License, or (at your option) any later version. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 * 14 * You should have received a copy of the GNU General Public License 15 * along with this program; if not, write to the Free Software 16 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. 17 */ 18 19 /* 20 * These are routines to set up and handle interrupts from the 21 * sb1250 general purpose timer 0. We're using the timer as a 22 * system clock, so we set it up to run at 100 Hz. On every 23 * interrupt, we update our idea of what the time of day is, 24 * then call do_timer() in the architecture-independent kernel 25 * code to do general bookkeeping (e.g. update jiffies, run 26 * bottom halves, etc.) 27 */ 28 #include <linux/interrupt.h> 29 #include <linux/sched.h> 30 #include <linux/spinlock.h> 31 #include <linux/kernel_stat.h> 32 33 #include <asm/irq.h> 34 #include <asm/addrspace.h> 35 #include <asm/time.h> 36 #include <asm/io.h> 37 38 #include <asm/sibyte/sb1250.h> 39 #include <asm/sibyte/sb1250_regs.h> 40 #include <asm/sibyte/sb1250_int.h> 41 #include <asm/sibyte/sb1250_scd.h> 42 43 44 #define IMR_IP2_VAL K_INT_MAP_I0 45 #define IMR_IP3_VAL K_INT_MAP_I1 46 #define IMR_IP4_VAL K_INT_MAP_I2 47 48 #define SB1250_HPT_NUM 3 49 #define SB1250_HPT_VALUE M_SCD_TIMER_CNT /* max value */ 50 51 52 extern int sb1250_steal_irq(int irq); 53 54 static cycle_t sb1250_hpt_read(void); 55 56 void __init sb1250_hpt_setup(void) 57 { 58 int cpu = smp_processor_id(); 59 60 if (!cpu) { 61 /* Setup hpt using timer #3 but do not enable irq for it */ 62 __raw_writeq(0, IOADDR(A_SCD_TIMER_REGISTER(SB1250_HPT_NUM, R_SCD_TIMER_CFG))); 63 __raw_writeq(SB1250_HPT_VALUE, 64 IOADDR(A_SCD_TIMER_REGISTER(SB1250_HPT_NUM, R_SCD_TIMER_INIT))); 65 __raw_writeq(M_SCD_TIMER_ENABLE | M_SCD_TIMER_MODE_CONTINUOUS, 66 IOADDR(A_SCD_TIMER_REGISTER(SB1250_HPT_NUM, R_SCD_TIMER_CFG))); 67 68 mips_hpt_frequency = V_SCD_TIMER_FREQ; 69 clocksource_mips.read = sb1250_hpt_read; 70 clocksource_mips.mask = M_SCD_TIMER_INIT; 71 } 72 } 73 74 75 void sb1250_time_init(void) 76 { 77 int cpu = smp_processor_id(); 78 int irq = K_INT_TIMER_0+cpu; 79 80 /* Only have 4 general purpose timers, and we use last one as hpt */ 81 if (cpu > 2) { 82 BUG(); 83 } 84 85 sb1250_mask_irq(cpu, irq); 86 87 /* Map the timer interrupt to ip[4] of this cpu */ 88 __raw_writeq(IMR_IP4_VAL, 89 IOADDR(A_IMR_REGISTER(cpu, R_IMR_INTERRUPT_MAP_BASE) + 90 (irq << 3))); 91 92 /* the general purpose timer ticks at 1 Mhz independent if the rest of the system */ 93 /* Disable the timer and set up the count */ 94 __raw_writeq(0, IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG))); 95 #ifdef CONFIG_SIMULATION 96 __raw_writeq((50000 / HZ) - 1, 97 IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_INIT))); 98 #else 99 __raw_writeq((V_SCD_TIMER_FREQ / HZ) - 1, 100 IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_INIT))); 101 #endif 102 103 /* Set the timer running */ 104 __raw_writeq(M_SCD_TIMER_ENABLE | M_SCD_TIMER_MODE_CONTINUOUS, 105 IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG))); 106 107 sb1250_unmask_irq(cpu, irq); 108 sb1250_steal_irq(irq); 109 /* 110 * This interrupt is "special" in that it doesn't use the request_irq 111 * way to hook the irq line. The timer interrupt is initialized early 112 * enough to make this a major pain, and it's also firing enough to 113 * warrant a bit of special case code. sb1250_timer_interrupt is 114 * called directly from irq_handler.S when IP[4] is set during an 115 * interrupt 116 */ 117 } 118 119 void sb1250_timer_interrupt(void) 120 { 121 int cpu = smp_processor_id(); 122 int irq = K_INT_TIMER_0 + cpu; 123 124 /* ACK interrupt */ 125 ____raw_writeq(M_SCD_TIMER_ENABLE | M_SCD_TIMER_MODE_CONTINUOUS, 126 IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG))); 127 128 if (cpu == 0) { 129 /* 130 * CPU 0 handles the global timer interrupt job 131 */ 132 ll_timer_interrupt(irq); 133 } 134 else { 135 /* 136 * other CPUs should just do profiling and process accounting 137 */ 138 ll_local_timer_interrupt(irq); 139 } 140 } 141 142 /* 143 * The HPT is free running from SB1250_HPT_VALUE down to 0 then starts over 144 * again. 145 */ 146 static cycle_t sb1250_hpt_read(void) 147 { 148 unsigned int count; 149 150 count = G_SCD_TIMER_CNT(__raw_readq(IOADDR(A_SCD_TIMER_REGISTER(SB1250_HPT_NUM, R_SCD_TIMER_CNT)))); 151 152 return SB1250_HPT_VALUE - count; 153 } 154