11da177e4SLinus Torvalds /* 21da177e4SLinus Torvalds * Copyright (C) 2001, 2002, 2003 Broadcom Corporation 31da177e4SLinus Torvalds * 41da177e4SLinus Torvalds * This program is free software; you can redistribute it and/or 51da177e4SLinus Torvalds * modify it under the terms of the GNU General Public License 61da177e4SLinus Torvalds * as published by the Free Software Foundation; either version 2 71da177e4SLinus Torvalds * of the License, or (at your option) any later version. 81da177e4SLinus Torvalds * 91da177e4SLinus Torvalds * This program is distributed in the hope that it will be useful, 101da177e4SLinus Torvalds * but WITHOUT ANY WARRANTY; without even the implied warranty of 111da177e4SLinus Torvalds * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 121da177e4SLinus Torvalds * GNU General Public License for more details. 131da177e4SLinus Torvalds * 141da177e4SLinus Torvalds * You should have received a copy of the GNU General Public License 151da177e4SLinus Torvalds * along with this program; if not, write to the Free Software 161da177e4SLinus Torvalds * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. 171da177e4SLinus Torvalds */ 181da177e4SLinus Torvalds 191da177e4SLinus Torvalds #include <linux/init.h> 201da177e4SLinus Torvalds #include <linux/delay.h> 211da177e4SLinus Torvalds #include <linux/interrupt.h> 221da177e4SLinus Torvalds #include <linux/smp.h> 231da177e4SLinus Torvalds #include <linux/kernel_stat.h> 241da177e4SLinus Torvalds 251da177e4SLinus Torvalds #include <asm/mmu_context.h> 261da177e4SLinus Torvalds #include <asm/io.h> 27*87353d8aSRalf Baechle #include <asm/fw/cfe/cfe_api.h> 281da177e4SLinus Torvalds #include <asm/sibyte/sb1250.h> 291da177e4SLinus Torvalds #include <asm/sibyte/sb1250_regs.h> 301da177e4SLinus Torvalds #include <asm/sibyte/sb1250_int.h> 311da177e4SLinus Torvalds 321da177e4SLinus Torvalds static void *mailbox_set_regs[] = { 3365bda1a9SMaciej W. Rozycki IOADDR(A_IMR_CPU0_BASE + R_IMR_MAILBOX_SET_CPU), 3465bda1a9SMaciej W. Rozycki IOADDR(A_IMR_CPU1_BASE + R_IMR_MAILBOX_SET_CPU) 351da177e4SLinus Torvalds }; 361da177e4SLinus Torvalds 371da177e4SLinus Torvalds static void *mailbox_clear_regs[] = { 3865bda1a9SMaciej W. Rozycki IOADDR(A_IMR_CPU0_BASE + R_IMR_MAILBOX_CLR_CPU), 3965bda1a9SMaciej W. Rozycki IOADDR(A_IMR_CPU1_BASE + R_IMR_MAILBOX_CLR_CPU) 401da177e4SLinus Torvalds }; 411da177e4SLinus Torvalds 421da177e4SLinus Torvalds static void *mailbox_regs[] = { 4365bda1a9SMaciej W. Rozycki IOADDR(A_IMR_CPU0_BASE + R_IMR_MAILBOX_CPU), 4465bda1a9SMaciej W. Rozycki IOADDR(A_IMR_CPU1_BASE + R_IMR_MAILBOX_CPU) 451da177e4SLinus Torvalds }; 461da177e4SLinus Torvalds 471da177e4SLinus Torvalds /* 481da177e4SLinus Torvalds * SMP init and finish on secondary CPUs 491da177e4SLinus Torvalds */ 50d0453365SRalf Baechle void __cpuinit sb1250_smp_init(void) 511da177e4SLinus Torvalds { 521da177e4SLinus Torvalds unsigned int imask = STATUSF_IP4 | STATUSF_IP3 | STATUSF_IP2 | 531da177e4SLinus Torvalds STATUSF_IP1 | STATUSF_IP0; 541da177e4SLinus Torvalds 551da177e4SLinus Torvalds /* Set interrupt mask, but don't enable */ 561da177e4SLinus Torvalds change_c0_status(ST0_IM, imask); 571da177e4SLinus Torvalds } 581da177e4SLinus Torvalds 591da177e4SLinus Torvalds /* 601da177e4SLinus Torvalds * These are routines for dealing with the sb1250 smp capabilities 611da177e4SLinus Torvalds * independent of board/firmware 621da177e4SLinus Torvalds */ 631da177e4SLinus Torvalds 641da177e4SLinus Torvalds /* 651da177e4SLinus Torvalds * Simple enough; everything is set up, so just poke the appropriate mailbox 661da177e4SLinus Torvalds * register, and we should be set 671da177e4SLinus Torvalds */ 68*87353d8aSRalf Baechle static void sb1250_send_ipi_single(int cpu, unsigned int action) 691da177e4SLinus Torvalds { 7065bda1a9SMaciej W. Rozycki __raw_writeq((((u64)action) << 48), mailbox_set_regs[cpu]); 711da177e4SLinus Torvalds } 721da177e4SLinus Torvalds 73*87353d8aSRalf Baechle static inline void sb1250_send_ipi_mask(cpumask_t mask, unsigned int action) 74*87353d8aSRalf Baechle { 75*87353d8aSRalf Baechle unsigned int i; 76*87353d8aSRalf Baechle 77*87353d8aSRalf Baechle for_each_cpu_mask(i, mask) 78*87353d8aSRalf Baechle sb1250_send_ipi_single(i, action); 79*87353d8aSRalf Baechle } 80*87353d8aSRalf Baechle 81*87353d8aSRalf Baechle /* 82*87353d8aSRalf Baechle * Code to run on secondary just after probing the CPU 83*87353d8aSRalf Baechle */ 84*87353d8aSRalf Baechle static void __cpuinit sb1250_init_secondary(void) 85*87353d8aSRalf Baechle { 86*87353d8aSRalf Baechle extern void sb1250_smp_init(void); 87*87353d8aSRalf Baechle 88*87353d8aSRalf Baechle sb1250_smp_init(); 89*87353d8aSRalf Baechle } 90*87353d8aSRalf Baechle 91*87353d8aSRalf Baechle /* 92*87353d8aSRalf Baechle * Do any tidying up before marking online and running the idle 93*87353d8aSRalf Baechle * loop 94*87353d8aSRalf Baechle */ 95*87353d8aSRalf Baechle static void __cpuinit sb1250_smp_finish(void) 96*87353d8aSRalf Baechle { 97*87353d8aSRalf Baechle extern void sb1250_clockevent_init(void); 98*87353d8aSRalf Baechle 99*87353d8aSRalf Baechle sb1250_clockevent_init(); 100*87353d8aSRalf Baechle local_irq_enable(); 101*87353d8aSRalf Baechle } 102*87353d8aSRalf Baechle 103*87353d8aSRalf Baechle /* 104*87353d8aSRalf Baechle * Final cleanup after all secondaries booted 105*87353d8aSRalf Baechle */ 106*87353d8aSRalf Baechle static void sb1250_cpus_done(void) 107*87353d8aSRalf Baechle { 108*87353d8aSRalf Baechle } 109*87353d8aSRalf Baechle 110*87353d8aSRalf Baechle /* 111*87353d8aSRalf Baechle * Setup the PC, SP, and GP of a secondary processor and start it 112*87353d8aSRalf Baechle * running! 113*87353d8aSRalf Baechle */ 114*87353d8aSRalf Baechle static void __cpuinit sb1250_boot_secondary(int cpu, struct task_struct *idle) 115*87353d8aSRalf Baechle { 116*87353d8aSRalf Baechle int retval; 117*87353d8aSRalf Baechle 118*87353d8aSRalf Baechle retval = cfe_cpu_start(cpu_logical_map(cpu), &smp_bootstrap, 119*87353d8aSRalf Baechle __KSTK_TOS(idle), 120*87353d8aSRalf Baechle (unsigned long)task_thread_info(idle), 0); 121*87353d8aSRalf Baechle if (retval != 0) 122*87353d8aSRalf Baechle printk("cfe_start_cpu(%i) returned %i\n" , cpu, retval); 123*87353d8aSRalf Baechle } 124*87353d8aSRalf Baechle 125*87353d8aSRalf Baechle /* 126*87353d8aSRalf Baechle * Use CFE to find out how many CPUs are available, setting up 127*87353d8aSRalf Baechle * phys_cpu_present_map and the logical/physical mappings. 128*87353d8aSRalf Baechle * XXXKW will the boot CPU ever not be physical 0? 129*87353d8aSRalf Baechle * 130*87353d8aSRalf Baechle * Common setup before any secondaries are started 131*87353d8aSRalf Baechle */ 132*87353d8aSRalf Baechle static void __init sb1250_smp_setup(void) 133*87353d8aSRalf Baechle { 134*87353d8aSRalf Baechle int i, num; 135*87353d8aSRalf Baechle 136*87353d8aSRalf Baechle cpus_clear(phys_cpu_present_map); 137*87353d8aSRalf Baechle cpu_set(0, phys_cpu_present_map); 138*87353d8aSRalf Baechle __cpu_number_map[0] = 0; 139*87353d8aSRalf Baechle __cpu_logical_map[0] = 0; 140*87353d8aSRalf Baechle 141*87353d8aSRalf Baechle for (i = 1, num = 0; i < NR_CPUS; i++) { 142*87353d8aSRalf Baechle if (cfe_cpu_stop(i) == 0) { 143*87353d8aSRalf Baechle cpu_set(i, phys_cpu_present_map); 144*87353d8aSRalf Baechle __cpu_number_map[i] = ++num; 145*87353d8aSRalf Baechle __cpu_logical_map[num] = i; 146*87353d8aSRalf Baechle } 147*87353d8aSRalf Baechle } 148*87353d8aSRalf Baechle printk(KERN_INFO "Detected %i available secondary CPU(s)\n", num); 149*87353d8aSRalf Baechle } 150*87353d8aSRalf Baechle 151*87353d8aSRalf Baechle static void __init sb1250_prepare_cpus(unsigned int max_cpus) 152*87353d8aSRalf Baechle { 153*87353d8aSRalf Baechle } 154*87353d8aSRalf Baechle 155*87353d8aSRalf Baechle struct plat_smp_ops sb_smp_ops = { 156*87353d8aSRalf Baechle .send_ipi_single = sb1250_send_ipi_single, 157*87353d8aSRalf Baechle .send_ipi_mask = sb1250_send_ipi_mask, 158*87353d8aSRalf Baechle .init_secondary = sb1250_init_secondary, 159*87353d8aSRalf Baechle .smp_finish = sb1250_smp_finish, 160*87353d8aSRalf Baechle .cpus_done = sb1250_cpus_done, 161*87353d8aSRalf Baechle .boot_secondary = sb1250_boot_secondary, 162*87353d8aSRalf Baechle .smp_setup = sb1250_smp_setup, 163*87353d8aSRalf Baechle .prepare_cpus = sb1250_prepare_cpus, 164*87353d8aSRalf Baechle }; 165*87353d8aSRalf Baechle 166937a8015SRalf Baechle void sb1250_mailbox_interrupt(void) 1671da177e4SLinus Torvalds { 1681da177e4SLinus Torvalds int cpu = smp_processor_id(); 1691da177e4SLinus Torvalds unsigned int action; 1701da177e4SLinus Torvalds 1711da177e4SLinus Torvalds kstat_this_cpu.irqs[K_INT_MBOX_0]++; 1721da177e4SLinus Torvalds /* Load the mailbox register to figure out what we're supposed to do */ 17365bda1a9SMaciej W. Rozycki action = (____raw_readq(mailbox_regs[cpu]) >> 48) & 0xffff; 1741da177e4SLinus Torvalds 1751da177e4SLinus Torvalds /* Clear the mailbox to clear the interrupt */ 17665bda1a9SMaciej W. Rozycki ____raw_writeq(((u64)action) << 48, mailbox_clear_regs[cpu]); 1771da177e4SLinus Torvalds 1781da177e4SLinus Torvalds /* 1791da177e4SLinus Torvalds * Nothing to do for SMP_RESCHEDULE_YOURSELF; returning from the 1801da177e4SLinus Torvalds * interrupt will do the reschedule for us 1811da177e4SLinus Torvalds */ 1821da177e4SLinus Torvalds 1831da177e4SLinus Torvalds if (action & SMP_CALL_FUNCTION) 1841da177e4SLinus Torvalds smp_call_function_interrupt(); 1851da177e4SLinus Torvalds } 186