1 /* 2 * Copyright (C) 2000,2001,2004 Broadcom Corporation 3 * 4 * This program is free software; you can redistribute it and/or 5 * modify it under the terms of the GNU General Public License 6 * as published by the Free Software Foundation; either version 2 7 * of the License, or (at your option) any later version. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 * 14 * You should have received a copy of the GNU General Public License 15 * along with this program; if not, write to the Free Software 16 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. 17 */ 18 #include <linux/clockchips.h> 19 #include <linux/interrupt.h> 20 #include <linux/percpu.h> 21 22 #include <asm/addrspace.h> 23 #include <asm/io.h> 24 #include <asm/time.h> 25 26 #include <asm/sibyte/bcm1480_regs.h> 27 #include <asm/sibyte/sb1250_regs.h> 28 #include <asm/sibyte/bcm1480_int.h> 29 #include <asm/sibyte/bcm1480_scd.h> 30 31 #include <asm/sibyte/sb1250.h> 32 33 34 #define IMR_IP2_VAL K_BCM1480_INT_MAP_I0 35 #define IMR_IP3_VAL K_BCM1480_INT_MAP_I1 36 #define IMR_IP4_VAL K_BCM1480_INT_MAP_I2 37 38 /* 39 * The general purpose timer ticks at 1MHz independent if 40 * the rest of the system 41 */ 42 static void sibyte_set_mode(enum clock_event_mode mode, 43 struct clock_event_device *evt) 44 { 45 unsigned int cpu = smp_processor_id(); 46 void __iomem *cfg, *init; 47 48 cfg = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG)); 49 init = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_INIT)); 50 51 switch (mode) { 52 case CLOCK_EVT_MODE_PERIODIC: 53 __raw_writeq(0, cfg); 54 __raw_writeq((V_SCD_TIMER_FREQ / HZ) - 1, init); 55 __raw_writeq(M_SCD_TIMER_ENABLE | M_SCD_TIMER_MODE_CONTINUOUS, 56 cfg); 57 break; 58 59 case CLOCK_EVT_MODE_ONESHOT: 60 /* Stop the timer until we actually program a shot */ 61 case CLOCK_EVT_MODE_SHUTDOWN: 62 __raw_writeq(0, cfg); 63 break; 64 65 case CLOCK_EVT_MODE_UNUSED: /* shuddup gcc */ 66 case CLOCK_EVT_MODE_RESUME: 67 ; 68 } 69 } 70 71 static int sibyte_next_event(unsigned long delta, struct clock_event_device *cd) 72 { 73 unsigned int cpu = smp_processor_id(); 74 void __iomem *cfg, *init; 75 76 cfg = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG)); 77 init = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_INIT)); 78 79 __raw_writeq(delta - 1, init); 80 __raw_writeq(M_SCD_TIMER_ENABLE, cfg); 81 82 return 0; 83 } 84 85 static irqreturn_t sibyte_counter_handler(int irq, void *dev_id) 86 { 87 unsigned int cpu = smp_processor_id(); 88 struct clock_event_device *cd = dev_id; 89 void __iomem *cfg; 90 unsigned long tmode; 91 92 if (cd->mode == CLOCK_EVT_MODE_PERIODIC) 93 tmode = M_SCD_TIMER_ENABLE | M_SCD_TIMER_MODE_CONTINUOUS; 94 else 95 tmode = 0; 96 97 /* ACK interrupt */ 98 cfg = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG)); 99 ____raw_writeq(tmode, cfg); 100 101 cd->event_handler(cd); 102 103 return IRQ_HANDLED; 104 } 105 106 static DEFINE_PER_CPU(struct clock_event_device, sibyte_hpt_clockevent); 107 static DEFINE_PER_CPU(struct irqaction, sibyte_hpt_irqaction); 108 static DEFINE_PER_CPU(char [18], sibyte_hpt_name); 109 110 void __cpuinit sb1480_clockevent_init(void) 111 { 112 unsigned int cpu = smp_processor_id(); 113 unsigned int irq = K_BCM1480_INT_TIMER_0 + cpu; 114 struct irqaction *action = &per_cpu(sibyte_hpt_irqaction, cpu); 115 struct clock_event_device *cd = &per_cpu(sibyte_hpt_clockevent, cpu); 116 unsigned char *name = per_cpu(sibyte_hpt_name, cpu); 117 118 BUG_ON(cpu > 3); /* Only have 4 general purpose timers */ 119 120 sprintf(name, "bcm1480-counter-%d", cpu); 121 cd->name = name; 122 cd->features = CLOCK_EVT_FEAT_PERIODIC | 123 CLOCK_EVT_FEAT_ONESHOT; 124 clockevent_set_clock(cd, V_SCD_TIMER_FREQ); 125 cd->max_delta_ns = clockevent_delta2ns(0x7fffff, cd); 126 cd->min_delta_ns = clockevent_delta2ns(1, cd); 127 cd->rating = 200; 128 cd->irq = irq; 129 cd->cpumask = cpumask_of_cpu(cpu); 130 cd->set_next_event = sibyte_next_event; 131 cd->set_mode = sibyte_set_mode; 132 clockevents_register_device(cd); 133 134 bcm1480_mask_irq(cpu, irq); 135 136 /* 137 * Map the timer interrupt to IP[4] of this cpu 138 */ 139 __raw_writeq(IMR_IP4_VAL, 140 IOADDR(A_BCM1480_IMR_REGISTER(cpu, 141 R_BCM1480_IMR_INTERRUPT_MAP_BASE_H) + (irq << 3))); 142 143 bcm1480_unmask_irq(cpu, irq); 144 145 action->handler = sibyte_counter_handler; 146 action->flags = IRQF_DISABLED | IRQF_PERCPU; 147 action->name = name; 148 action->dev_id = cd; 149 setup_irq(irq, action); 150 } 151 152 static cycle_t bcm1480_hpt_read(void) 153 { 154 return (cycle_t) __raw_readq(IOADDR(A_SCD_ZBBUS_CYCLE_COUNT)); 155 } 156 157 struct clocksource bcm1480_clocksource = { 158 .name = "zbbus-cycles", 159 .rating = 200, 160 .read = bcm1480_hpt_read, 161 .mask = CLOCKSOURCE_MASK(64), 162 .flags = CLOCK_SOURCE_IS_CONTINUOUS, 163 }; 164 165 void __init sb1480_clocksource_init(void) 166 { 167 struct clocksource *cs = &bcm1480_clocksource; 168 unsigned int plldiv; 169 unsigned long zbbus; 170 171 plldiv = G_BCM1480_SYS_PLL_DIV(__raw_readq(IOADDR(A_SCD_SYSTEM_CFG))); 172 zbbus = ((plldiv >> 1) * 50000000) + ((plldiv & 1) * 25000000); 173 clocksource_set_clock(cs, zbbus); 174 clocksource_register(cs); 175 } 176 177 void __init plat_time_init(void) 178 { 179 sb1480_clocksource_init(); 180 sb1480_clockevent_init(); 181 } 182