1 /* 2 * Copyright (C) 2000,2001,2004 Broadcom Corporation 3 * 4 * This program is free software; you can redistribute it and/or 5 * modify it under the terms of the GNU General Public License 6 * as published by the Free Software Foundation; either version 2 7 * of the License, or (at your option) any later version. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 * 14 * You should have received a copy of the GNU General Public License 15 * along with this program; if not, write to the Free Software 16 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. 17 */ 18 #include <linux/clockchips.h> 19 #include <linux/interrupt.h> 20 #include <linux/irq.h> 21 #include <linux/percpu.h> 22 #include <linux/spinlock.h> 23 24 #include <asm/addrspace.h> 25 #include <asm/time.h> 26 #include <asm/io.h> 27 28 #include <asm/sibyte/bcm1480_regs.h> 29 #include <asm/sibyte/sb1250_regs.h> 30 #include <asm/sibyte/bcm1480_int.h> 31 #include <asm/sibyte/bcm1480_scd.h> 32 33 #include <asm/sibyte/sb1250.h> 34 35 36 #define IMR_IP2_VAL K_BCM1480_INT_MAP_I0 37 #define IMR_IP3_VAL K_BCM1480_INT_MAP_I1 38 #define IMR_IP4_VAL K_BCM1480_INT_MAP_I2 39 40 extern int bcm1480_steal_irq(int irq); 41 42 /* 43 * The general purpose timer ticks at 1MHz independent if 44 * the rest of the system 45 */ 46 static void sibyte_set_mode(enum clock_event_mode mode, 47 struct clock_event_device *evt) 48 { 49 unsigned int cpu = smp_processor_id(); 50 void __iomem *timer_cfg, *timer_init; 51 52 timer_cfg = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG)); 53 timer_init = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_INIT)); 54 55 switch (mode) { 56 case CLOCK_EVT_MODE_PERIODIC: 57 __raw_writeq(0, timer_cfg); 58 __raw_writeq((V_SCD_TIMER_FREQ / HZ) - 1, timer_init); 59 __raw_writeq(M_SCD_TIMER_ENABLE | M_SCD_TIMER_MODE_CONTINUOUS, 60 timer_cfg); 61 break; 62 63 case CLOCK_EVT_MODE_ONESHOT: 64 /* Stop the timer until we actually program a shot */ 65 case CLOCK_EVT_MODE_SHUTDOWN: 66 __raw_writeq(0, timer_cfg); 67 break; 68 69 case CLOCK_EVT_MODE_UNUSED: /* shuddup gcc */ 70 case CLOCK_EVT_MODE_RESUME: 71 ; 72 } 73 } 74 75 static int sibyte_next_event(unsigned long delta, struct clock_event_device *cd) 76 { 77 unsigned int cpu = smp_processor_id(); 78 void __iomem *timer_init; 79 unsigned int cnt; 80 int res; 81 82 timer_init = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_INIT)); 83 cnt = __raw_readq(timer_init); 84 cnt += delta; 85 __raw_writeq(cnt, timer_init); 86 res = ((long)(__raw_readq(timer_init) - cnt ) > 0) ? -ETIME : 0; 87 88 return res; 89 } 90 91 static irqreturn_t sibyte_counter_handler(int irq, void *dev_id) 92 { 93 unsigned int cpu = smp_processor_id(); 94 struct clock_event_device *cd = dev_id; 95 void __iomem *timer_cfg; 96 97 timer_cfg = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG)); 98 99 /* Reset the timer */ 100 __raw_writeq(M_SCD_TIMER_ENABLE | M_SCD_TIMER_MODE_CONTINUOUS, 101 timer_cfg); 102 cd->event_handler(cd); 103 104 return IRQ_HANDLED; 105 } 106 107 static DEFINE_PER_CPU(struct clock_event_device, sibyte_hpt_clockevent); 108 static DEFINE_PER_CPU(struct irqaction, sibyte_hpt_irqaction); 109 static DEFINE_PER_CPU(char [18], sibyte_hpt_name); 110 111 void __cpuinit sb1480_clockevent_init(void) 112 { 113 unsigned int cpu = smp_processor_id(); 114 unsigned int irq = K_BCM1480_INT_TIMER_0 + cpu; 115 struct irqaction *action = &per_cpu(sibyte_hpt_irqaction, cpu); 116 struct clock_event_device *cd = &per_cpu(sibyte_hpt_clockevent, cpu); 117 unsigned char *name = per_cpu(sibyte_hpt_name, cpu); 118 119 BUG_ON(cpu > 3); /* Only have 4 general purpose timers */ 120 121 sprintf(name, "bcm1480-counter %d", cpu); 122 cd->name = name; 123 cd->features = CLOCK_EVT_FEAT_PERIODIC | 124 CLOCK_EVT_MODE_ONESHOT; 125 clockevent_set_clock(cd, V_SCD_TIMER_FREQ); 126 cd->max_delta_ns = clockevent_delta2ns(0x7fffff, cd); 127 cd->min_delta_ns = clockevent_delta2ns(1, cd); 128 cd->rating = 200; 129 cd->irq = irq; 130 cd->cpumask = cpumask_of_cpu(cpu); 131 cd->set_next_event = sibyte_next_event; 132 cd->set_mode = sibyte_set_mode; 133 clockevents_register_device(cd); 134 135 bcm1480_mask_irq(cpu, irq); 136 137 /* 138 * Map timer interrupt to IP[4] of this cpu 139 */ 140 __raw_writeq(IMR_IP4_VAL, 141 IOADDR(A_BCM1480_IMR_REGISTER(cpu, 142 R_BCM1480_IMR_INTERRUPT_MAP_BASE_H) + (irq << 3))); 143 144 bcm1480_unmask_irq(cpu, irq); 145 bcm1480_steal_irq(irq); 146 147 action->handler = sibyte_counter_handler; 148 action->flags = IRQF_DISABLED | IRQF_PERCPU; 149 action->name = name; 150 action->dev_id = cd; 151 setup_irq(irq, action); 152 } 153 154 static cycle_t bcm1480_hpt_read(void) 155 { 156 return (cycle_t) __raw_readq(IOADDR(A_SCD_ZBBUS_CYCLE_COUNT)); 157 } 158 159 struct clocksource bcm1480_clocksource = { 160 .name = "zbbus-cycles", 161 .rating = 200, 162 .read = bcm1480_hpt_read, 163 .mask = CLOCKSOURCE_MASK(64), 164 .flags = CLOCK_SOURCE_IS_CONTINUOUS, 165 }; 166 167 void __init sb1480_clocksource_init(void) 168 { 169 struct clocksource *cs = &bcm1480_clocksource; 170 unsigned int plldiv; 171 unsigned long zbbus; 172 173 plldiv = G_BCM1480_SYS_PLL_DIV(__raw_readq(IOADDR(A_SCD_SYSTEM_CFG))); 174 zbbus = ((plldiv >> 1) * 50000000) + ((plldiv & 1) * 25000000); 175 clocksource_set_clock(cs, zbbus); 176 clocksource_register(cs); 177 } 178 179 void __init plat_time_init(void) 180 { 181 sb1480_clocksource_init(); 182 sb1480_clockevent_init(); 183 } 184