1 /* 2 * Copyright (C) 2001,2002,2004 Broadcom Corporation 3 * 4 * This program is free software; you can redistribute it and/or 5 * modify it under the terms of the GNU General Public License 6 * as published by the Free Software Foundation; either version 2 7 * of the License, or (at your option) any later version. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 * 14 * You should have received a copy of the GNU General Public License 15 * along with this program; if not, write to the Free Software 16 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. 17 */ 18 19 #include <linux/init.h> 20 #include <linux/delay.h> 21 #include <linux/smp.h> 22 #include <linux/kernel_stat.h> 23 24 #include <asm/mmu_context.h> 25 #include <asm/io.h> 26 #include <asm/sibyte/sb1250.h> 27 #include <asm/sibyte/bcm1480_regs.h> 28 #include <asm/sibyte/bcm1480_int.h> 29 30 extern void smp_call_function_interrupt(void); 31 32 /* 33 * These are routines for dealing with the bcm1480 smp capabilities 34 * independent of board/firmware 35 */ 36 37 static void *mailbox_0_set_regs[] = { 38 IOADDR(A_BCM1480_IMR_CPU0_BASE + R_BCM1480_IMR_MAILBOX_0_SET_CPU), 39 IOADDR(A_BCM1480_IMR_CPU1_BASE + R_BCM1480_IMR_MAILBOX_0_SET_CPU), 40 IOADDR(A_BCM1480_IMR_CPU2_BASE + R_BCM1480_IMR_MAILBOX_0_SET_CPU), 41 IOADDR(A_BCM1480_IMR_CPU3_BASE + R_BCM1480_IMR_MAILBOX_0_SET_CPU), 42 }; 43 44 static void *mailbox_0_clear_regs[] = { 45 IOADDR(A_BCM1480_IMR_CPU0_BASE + R_BCM1480_IMR_MAILBOX_0_CLR_CPU), 46 IOADDR(A_BCM1480_IMR_CPU1_BASE + R_BCM1480_IMR_MAILBOX_0_CLR_CPU), 47 IOADDR(A_BCM1480_IMR_CPU2_BASE + R_BCM1480_IMR_MAILBOX_0_CLR_CPU), 48 IOADDR(A_BCM1480_IMR_CPU3_BASE + R_BCM1480_IMR_MAILBOX_0_CLR_CPU), 49 }; 50 51 static void *mailbox_0_regs[] = { 52 IOADDR(A_BCM1480_IMR_CPU0_BASE + R_BCM1480_IMR_MAILBOX_0_CPU), 53 IOADDR(A_BCM1480_IMR_CPU1_BASE + R_BCM1480_IMR_MAILBOX_0_CPU), 54 IOADDR(A_BCM1480_IMR_CPU2_BASE + R_BCM1480_IMR_MAILBOX_0_CPU), 55 IOADDR(A_BCM1480_IMR_CPU3_BASE + R_BCM1480_IMR_MAILBOX_0_CPU), 56 }; 57 58 /* 59 * SMP init and finish on secondary CPUs 60 */ 61 void bcm1480_smp_init(void) 62 { 63 unsigned int imask = STATUSF_IP4 | STATUSF_IP3 | STATUSF_IP2 | 64 STATUSF_IP1 | STATUSF_IP0; 65 66 /* Set interrupt mask, but don't enable */ 67 change_c0_status(ST0_IM, imask); 68 } 69 70 void bcm1480_smp_finish(void) 71 { 72 extern void bcm1480_time_init(void); 73 bcm1480_time_init(); 74 local_irq_enable(); 75 } 76 77 /* 78 * These are routines for dealing with the sb1250 smp capabilities 79 * independent of board/firmware 80 */ 81 82 /* 83 * Simple enough; everything is set up, so just poke the appropriate mailbox 84 * register, and we should be set 85 */ 86 void core_send_ipi(int cpu, unsigned int action) 87 { 88 __raw_writeq((((u64)action)<< 48), mailbox_0_set_regs[cpu]); 89 } 90 91 void bcm1480_mailbox_interrupt(struct pt_regs *regs) 92 { 93 int cpu = smp_processor_id(); 94 unsigned int action; 95 96 kstat_this_cpu.irqs[K_BCM1480_INT_MBOX_0_0]++; 97 /* Load the mailbox register to figure out what we're supposed to do */ 98 action = (__raw_readq(mailbox_0_regs[cpu]) >> 48) & 0xffff; 99 100 /* Clear the mailbox to clear the interrupt */ 101 __raw_writeq(((u64)action)<<48, mailbox_0_clear_regs[cpu]); 102 103 /* 104 * Nothing to do for SMP_RESCHEDULE_YOURSELF; returning from the 105 * interrupt will do the reschedule for us 106 */ 107 108 if (action & SMP_CALL_FUNCTION) 109 smp_call_function_interrupt(); 110 } 111