1 /* 2 * Copyright (C) 2001,2002,2004 Broadcom Corporation 3 * 4 * This program is free software; you can redistribute it and/or 5 * modify it under the terms of the GNU General Public License 6 * as published by the Free Software Foundation; either version 2 7 * of the License, or (at your option) any later version. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 * 14 * You should have received a copy of the GNU General Public License 15 * along with this program; if not, write to the Free Software 16 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. 17 */ 18 19 #include <linux/init.h> 20 #include <linux/delay.h> 21 #include <linux/smp.h> 22 #include <linux/kernel_stat.h> 23 #include <linux/sched.h> 24 25 #include <asm/mmu_context.h> 26 #include <asm/io.h> 27 #include <asm/fw/cfe/cfe_api.h> 28 #include <asm/sibyte/sb1250.h> 29 #include <asm/sibyte/bcm1480_regs.h> 30 #include <asm/sibyte/bcm1480_int.h> 31 32 extern void smp_call_function_interrupt(void); 33 34 /* 35 * These are routines for dealing with the bcm1480 smp capabilities 36 * independent of board/firmware 37 */ 38 39 static void *mailbox_0_set_regs[] = { 40 IOADDR(A_BCM1480_IMR_CPU0_BASE + R_BCM1480_IMR_MAILBOX_0_SET_CPU), 41 IOADDR(A_BCM1480_IMR_CPU1_BASE + R_BCM1480_IMR_MAILBOX_0_SET_CPU), 42 IOADDR(A_BCM1480_IMR_CPU2_BASE + R_BCM1480_IMR_MAILBOX_0_SET_CPU), 43 IOADDR(A_BCM1480_IMR_CPU3_BASE + R_BCM1480_IMR_MAILBOX_0_SET_CPU), 44 }; 45 46 static void *mailbox_0_clear_regs[] = { 47 IOADDR(A_BCM1480_IMR_CPU0_BASE + R_BCM1480_IMR_MAILBOX_0_CLR_CPU), 48 IOADDR(A_BCM1480_IMR_CPU1_BASE + R_BCM1480_IMR_MAILBOX_0_CLR_CPU), 49 IOADDR(A_BCM1480_IMR_CPU2_BASE + R_BCM1480_IMR_MAILBOX_0_CLR_CPU), 50 IOADDR(A_BCM1480_IMR_CPU3_BASE + R_BCM1480_IMR_MAILBOX_0_CLR_CPU), 51 }; 52 53 static void *mailbox_0_regs[] = { 54 IOADDR(A_BCM1480_IMR_CPU0_BASE + R_BCM1480_IMR_MAILBOX_0_CPU), 55 IOADDR(A_BCM1480_IMR_CPU1_BASE + R_BCM1480_IMR_MAILBOX_0_CPU), 56 IOADDR(A_BCM1480_IMR_CPU2_BASE + R_BCM1480_IMR_MAILBOX_0_CPU), 57 IOADDR(A_BCM1480_IMR_CPU3_BASE + R_BCM1480_IMR_MAILBOX_0_CPU), 58 }; 59 60 /* 61 * SMP init and finish on secondary CPUs 62 */ 63 void __cpuinit bcm1480_smp_init(void) 64 { 65 unsigned int imask = STATUSF_IP4 | STATUSF_IP3 | STATUSF_IP2 | 66 STATUSF_IP1 | STATUSF_IP0; 67 68 /* Set interrupt mask, but don't enable */ 69 change_c0_status(ST0_IM, imask); 70 } 71 72 /* 73 * These are routines for dealing with the sb1250 smp capabilities 74 * independent of board/firmware 75 */ 76 77 /* 78 * Simple enough; everything is set up, so just poke the appropriate mailbox 79 * register, and we should be set 80 */ 81 static void bcm1480_send_ipi_single(int cpu, unsigned int action) 82 { 83 __raw_writeq((((u64)action)<< 48), mailbox_0_set_regs[cpu]); 84 } 85 86 static void bcm1480_send_ipi_mask(const struct cpumask *mask, 87 unsigned int action) 88 { 89 unsigned int i; 90 91 for_each_cpu(i, mask) 92 bcm1480_send_ipi_single(i, action); 93 } 94 95 /* 96 * Code to run on secondary just after probing the CPU 97 */ 98 static void __cpuinit bcm1480_init_secondary(void) 99 { 100 extern void bcm1480_smp_init(void); 101 102 bcm1480_smp_init(); 103 } 104 105 /* 106 * Do any tidying up before marking online and running the idle 107 * loop 108 */ 109 static void __cpuinit bcm1480_smp_finish(void) 110 { 111 extern void sb1480_clockevent_init(void); 112 113 sb1480_clockevent_init(); 114 local_irq_enable(); 115 } 116 117 /* 118 * Final cleanup after all secondaries booted 119 */ 120 static void bcm1480_cpus_done(void) 121 { 122 } 123 124 /* 125 * Setup the PC, SP, and GP of a secondary processor and start it 126 * running! 127 */ 128 static void __cpuinit bcm1480_boot_secondary(int cpu, struct task_struct *idle) 129 { 130 int retval; 131 132 retval = cfe_cpu_start(cpu_logical_map(cpu), &smp_bootstrap, 133 __KSTK_TOS(idle), 134 (unsigned long)task_thread_info(idle), 0); 135 if (retval != 0) 136 printk("cfe_start_cpu(%i) returned %i\n" , cpu, retval); 137 } 138 139 /* 140 * Use CFE to find out how many CPUs are available, setting up 141 * cpu_possible_mask and the logical/physical mappings. 142 * XXXKW will the boot CPU ever not be physical 0? 143 * 144 * Common setup before any secondaries are started 145 */ 146 static void __init bcm1480_smp_setup(void) 147 { 148 int i, num; 149 150 init_cpu_possible(cpumask_of(0)); 151 __cpu_number_map[0] = 0; 152 __cpu_logical_map[0] = 0; 153 154 for (i = 1, num = 0; i < NR_CPUS; i++) { 155 if (cfe_cpu_stop(i) == 0) { 156 set_cpu_possible(i, true); 157 __cpu_number_map[i] = ++num; 158 __cpu_logical_map[num] = i; 159 } 160 } 161 printk(KERN_INFO "Detected %i available secondary CPU(s)\n", num); 162 } 163 164 static void __init bcm1480_prepare_cpus(unsigned int max_cpus) 165 { 166 } 167 168 struct plat_smp_ops bcm1480_smp_ops = { 169 .send_ipi_single = bcm1480_send_ipi_single, 170 .send_ipi_mask = bcm1480_send_ipi_mask, 171 .init_secondary = bcm1480_init_secondary, 172 .smp_finish = bcm1480_smp_finish, 173 .cpus_done = bcm1480_cpus_done, 174 .boot_secondary = bcm1480_boot_secondary, 175 .smp_setup = bcm1480_smp_setup, 176 .prepare_cpus = bcm1480_prepare_cpus, 177 }; 178 179 void bcm1480_mailbox_interrupt(void) 180 { 181 int cpu = smp_processor_id(); 182 int irq = K_BCM1480_INT_MBOX_0_0; 183 unsigned int action; 184 185 kstat_incr_irqs_this_cpu(irq, irq_to_desc(irq)); 186 /* Load the mailbox register to figure out what we're supposed to do */ 187 action = (__raw_readq(mailbox_0_regs[cpu]) >> 48) & 0xffff; 188 189 /* Clear the mailbox to clear the interrupt */ 190 __raw_writeq(((u64)action)<<48, mailbox_0_clear_regs[cpu]); 191 192 if (action & SMP_RESCHEDULE_YOURSELF) 193 scheduler_ipi(); 194 195 if (action & SMP_CALL_FUNCTION) 196 smp_call_function_interrupt(); 197 } 198