1 /* 2 * Copyright (C) 2001,2002,2004 Broadcom Corporation 3 * 4 * This program is free software; you can redistribute it and/or 5 * modify it under the terms of the GNU General Public License 6 * as published by the Free Software Foundation; either version 2 7 * of the License, or (at your option) any later version. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 * 14 * You should have received a copy of the GNU General Public License 15 * along with this program; if not, write to the Free Software 16 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. 17 */ 18 19 #include <linux/init.h> 20 #include <linux/delay.h> 21 #include <linux/smp.h> 22 #include <linux/kernel_stat.h> 23 24 #include <asm/mmu_context.h> 25 #include <asm/io.h> 26 #include <asm/fw/cfe/cfe_api.h> 27 #include <asm/sibyte/sb1250.h> 28 #include <asm/sibyte/bcm1480_regs.h> 29 #include <asm/sibyte/bcm1480_int.h> 30 31 extern void smp_call_function_interrupt(void); 32 33 /* 34 * These are routines for dealing with the bcm1480 smp capabilities 35 * independent of board/firmware 36 */ 37 38 static void *mailbox_0_set_regs[] = { 39 IOADDR(A_BCM1480_IMR_CPU0_BASE + R_BCM1480_IMR_MAILBOX_0_SET_CPU), 40 IOADDR(A_BCM1480_IMR_CPU1_BASE + R_BCM1480_IMR_MAILBOX_0_SET_CPU), 41 IOADDR(A_BCM1480_IMR_CPU2_BASE + R_BCM1480_IMR_MAILBOX_0_SET_CPU), 42 IOADDR(A_BCM1480_IMR_CPU3_BASE + R_BCM1480_IMR_MAILBOX_0_SET_CPU), 43 }; 44 45 static void *mailbox_0_clear_regs[] = { 46 IOADDR(A_BCM1480_IMR_CPU0_BASE + R_BCM1480_IMR_MAILBOX_0_CLR_CPU), 47 IOADDR(A_BCM1480_IMR_CPU1_BASE + R_BCM1480_IMR_MAILBOX_0_CLR_CPU), 48 IOADDR(A_BCM1480_IMR_CPU2_BASE + R_BCM1480_IMR_MAILBOX_0_CLR_CPU), 49 IOADDR(A_BCM1480_IMR_CPU3_BASE + R_BCM1480_IMR_MAILBOX_0_CLR_CPU), 50 }; 51 52 static void *mailbox_0_regs[] = { 53 IOADDR(A_BCM1480_IMR_CPU0_BASE + R_BCM1480_IMR_MAILBOX_0_CPU), 54 IOADDR(A_BCM1480_IMR_CPU1_BASE + R_BCM1480_IMR_MAILBOX_0_CPU), 55 IOADDR(A_BCM1480_IMR_CPU2_BASE + R_BCM1480_IMR_MAILBOX_0_CPU), 56 IOADDR(A_BCM1480_IMR_CPU3_BASE + R_BCM1480_IMR_MAILBOX_0_CPU), 57 }; 58 59 /* 60 * SMP init and finish on secondary CPUs 61 */ 62 void __cpuinit bcm1480_smp_init(void) 63 { 64 unsigned int imask = STATUSF_IP4 | STATUSF_IP3 | STATUSF_IP2 | 65 STATUSF_IP1 | STATUSF_IP0; 66 67 /* Set interrupt mask, but don't enable */ 68 change_c0_status(ST0_IM, imask); 69 } 70 71 /* 72 * These are routines for dealing with the sb1250 smp capabilities 73 * independent of board/firmware 74 */ 75 76 /* 77 * Simple enough; everything is set up, so just poke the appropriate mailbox 78 * register, and we should be set 79 */ 80 static void bcm1480_send_ipi_single(int cpu, unsigned int action) 81 { 82 __raw_writeq((((u64)action)<< 48), mailbox_0_set_regs[cpu]); 83 } 84 85 static void bcm1480_send_ipi_mask(cpumask_t mask, unsigned int action) 86 { 87 unsigned int i; 88 89 for_each_cpu_mask(i, mask) 90 bcm1480_send_ipi_single(i, action); 91 } 92 93 /* 94 * Code to run on secondary just after probing the CPU 95 */ 96 static void __cpuinit bcm1480_init_secondary(void) 97 { 98 extern void bcm1480_smp_init(void); 99 100 bcm1480_smp_init(); 101 } 102 103 /* 104 * Do any tidying up before marking online and running the idle 105 * loop 106 */ 107 static void __cpuinit bcm1480_smp_finish(void) 108 { 109 extern void sb1480_clockevent_init(void); 110 111 sb1480_clockevent_init(); 112 local_irq_enable(); 113 } 114 115 /* 116 * Final cleanup after all secondaries booted 117 */ 118 static void bcm1480_cpus_done(void) 119 { 120 } 121 122 /* 123 * Setup the PC, SP, and GP of a secondary processor and start it 124 * running! 125 */ 126 static void __cpuinit bcm1480_boot_secondary(int cpu, struct task_struct *idle) 127 { 128 int retval; 129 130 retval = cfe_cpu_start(cpu_logical_map(cpu), &smp_bootstrap, 131 __KSTK_TOS(idle), 132 (unsigned long)task_thread_info(idle), 0); 133 if (retval != 0) 134 printk("cfe_start_cpu(%i) returned %i\n" , cpu, retval); 135 } 136 137 /* 138 * Use CFE to find out how many CPUs are available, setting up 139 * phys_cpu_present_map and the logical/physical mappings. 140 * XXXKW will the boot CPU ever not be physical 0? 141 * 142 * Common setup before any secondaries are started 143 */ 144 static void __init bcm1480_smp_setup(void) 145 { 146 int i, num; 147 148 cpus_clear(phys_cpu_present_map); 149 cpu_set(0, phys_cpu_present_map); 150 __cpu_number_map[0] = 0; 151 __cpu_logical_map[0] = 0; 152 153 for (i = 1, num = 0; i < NR_CPUS; i++) { 154 if (cfe_cpu_stop(i) == 0) { 155 cpu_set(i, phys_cpu_present_map); 156 __cpu_number_map[i] = ++num; 157 __cpu_logical_map[num] = i; 158 } 159 } 160 printk(KERN_INFO "Detected %i available secondary CPU(s)\n", num); 161 } 162 163 static void __init bcm1480_prepare_cpus(unsigned int max_cpus) 164 { 165 } 166 167 struct plat_smp_ops bcm1480_smp_ops = { 168 .send_ipi_single = bcm1480_send_ipi_single, 169 .send_ipi_mask = bcm1480_send_ipi_mask, 170 .init_secondary = bcm1480_init_secondary, 171 .smp_finish = bcm1480_smp_finish, 172 .cpus_done = bcm1480_cpus_done, 173 .boot_secondary = bcm1480_boot_secondary, 174 .smp_setup = bcm1480_smp_setup, 175 .prepare_cpus = bcm1480_prepare_cpus, 176 }; 177 178 void bcm1480_mailbox_interrupt(void) 179 { 180 int cpu = smp_processor_id(); 181 unsigned int action; 182 183 kstat_this_cpu.irqs[K_BCM1480_INT_MBOX_0_0]++; 184 /* Load the mailbox register to figure out what we're supposed to do */ 185 action = (__raw_readq(mailbox_0_regs[cpu]) >> 48) & 0xffff; 186 187 /* Clear the mailbox to clear the interrupt */ 188 __raw_writeq(((u64)action)<<48, mailbox_0_clear_regs[cpu]); 189 190 /* 191 * Nothing to do for SMP_RESCHEDULE_YOURSELF; returning from the 192 * interrupt will do the reschedule for us 193 */ 194 195 if (action & SMP_CALL_FUNCTION) 196 smp_call_function_interrupt(); 197 } 198