138b18f72SRalf Baechleconfig SIBYTE_SB1250 238b18f72SRalf Baechle bool 338b18f72SRalf Baechle select HW_HAS_PCI 438b18f72SRalf Baechle select SIBYTE_HAS_LDT 538b18f72SRalf Baechle select SIBYTE_SB1xxx_SOC 638b18f72SRalf Baechle 738b18f72SRalf Baechleconfig SIBYTE_BCM1120 838b18f72SRalf Baechle bool 938b18f72SRalf Baechle select SIBYTE_BCM112X 1038b18f72SRalf Baechle select SIBYTE_SB1xxx_SOC 1138b18f72SRalf Baechle 1238b18f72SRalf Baechleconfig SIBYTE_BCM1125 1338b18f72SRalf Baechle bool 1438b18f72SRalf Baechle select HW_HAS_PCI 1538b18f72SRalf Baechle select SIBYTE_BCM112X 1638b18f72SRalf Baechle select SIBYTE_SB1xxx_SOC 1738b18f72SRalf Baechle 1838b18f72SRalf Baechleconfig SIBYTE_BCM1125H 1938b18f72SRalf Baechle bool 2038b18f72SRalf Baechle select HW_HAS_PCI 2138b18f72SRalf Baechle select SIBYTE_BCM112X 2238b18f72SRalf Baechle select SIBYTE_HAS_LDT 2338b18f72SRalf Baechle select SIBYTE_SB1xxx_SOC 2438b18f72SRalf Baechle 2538b18f72SRalf Baechleconfig SIBYTE_BCM112X 2638b18f72SRalf Baechle bool 2738b18f72SRalf Baechle select SIBYTE_SB1xxx_SOC 2838b18f72SRalf Baechle 29f137e463SAndrew Isaacsonconfig SIBYTE_BCM1x80 30f137e463SAndrew Isaacson bool 31f137e463SAndrew Isaacson select HW_HAS_PCI 32f137e463SAndrew Isaacson select SIBYTE_SB1xxx_SOC 33f137e463SAndrew Isaacson 34f137e463SAndrew Isaacsonconfig SIBYTE_BCM1x55 35f137e463SAndrew Isaacson bool 36f137e463SAndrew Isaacson select HW_HAS_PCI 37f137e463SAndrew Isaacson select SIBYTE_SB1xxx_SOC 38f137e463SAndrew Isaacson 3938b18f72SRalf Baechleconfig SIBYTE_SB1xxx_SOC 4038b18f72SRalf Baechle bool 4138b18f72SRalf Baechle depends on EXPERIMENTAL 4238b18f72SRalf Baechle select DMA_COHERENT 4338b18f72SRalf Baechle select SIBYTE_CFE 4438b18f72SRalf Baechle select SWAP_IO_SPACE 4538b18f72SRalf Baechle select SYS_SUPPORTS_32BIT_KERNEL 4638b18f72SRalf Baechle select SYS_SUPPORTS_64BIT_KERNEL 4738b18f72SRalf Baechle 4838b18f72SRalf Baechlechoice 4938b18f72SRalf Baechle prompt "SiByte SOC Stepping" 5038b18f72SRalf Baechle depends on SIBYTE_SB1xxx_SOC 5138b18f72SRalf Baechle 5238b18f72SRalf Baechleconfig CPU_SB1_PASS_1 5338b18f72SRalf Baechle bool "1250 Pass1" 5438b18f72SRalf Baechle depends on SIBYTE_SB1250 5538b18f72SRalf Baechle select CPU_HAS_PREFETCH 5638b18f72SRalf Baechle 5738b18f72SRalf Baechleconfig CPU_SB1_PASS_2_1250 5838b18f72SRalf Baechle bool "1250 An" 5938b18f72SRalf Baechle depends on SIBYTE_SB1250 6038b18f72SRalf Baechle select CPU_SB1_PASS_2 6138b18f72SRalf Baechle help 6238b18f72SRalf Baechle Also called BCM1250 Pass 2 6338b18f72SRalf Baechle 6438b18f72SRalf Baechleconfig CPU_SB1_PASS_2_2 6538b18f72SRalf Baechle bool "1250 Bn" 6638b18f72SRalf Baechle depends on SIBYTE_SB1250 6738b18f72SRalf Baechle select CPU_HAS_PREFETCH 6838b18f72SRalf Baechle help 6938b18f72SRalf Baechle Also called BCM1250 Pass 2.2 7038b18f72SRalf Baechle 7138b18f72SRalf Baechleconfig CPU_SB1_PASS_4 7238b18f72SRalf Baechle bool "1250 Cn" 7338b18f72SRalf Baechle depends on SIBYTE_SB1250 7438b18f72SRalf Baechle select CPU_HAS_PREFETCH 7538b18f72SRalf Baechle help 7638b18f72SRalf Baechle Also called BCM1250 Pass 3 7738b18f72SRalf Baechle 7838b18f72SRalf Baechleconfig CPU_SB1_PASS_2_112x 7938b18f72SRalf Baechle bool "112x Hybrid" 8038b18f72SRalf Baechle depends on SIBYTE_BCM112X 8138b18f72SRalf Baechle select CPU_SB1_PASS_2 8238b18f72SRalf Baechle 8338b18f72SRalf Baechleconfig CPU_SB1_PASS_3 8438b18f72SRalf Baechle bool "112x An" 8538b18f72SRalf Baechle depends on SIBYTE_BCM112X 8638b18f72SRalf Baechle select CPU_HAS_PREFETCH 8738b18f72SRalf Baechle 8838b18f72SRalf Baechleendchoice 8938b18f72SRalf Baechle 9038b18f72SRalf Baechleconfig CPU_SB1_PASS_2 9138b18f72SRalf Baechle bool 9238b18f72SRalf Baechle 9338b18f72SRalf Baechleconfig SIBYTE_HAS_LDT 9438b18f72SRalf Baechle bool 9538b18f72SRalf Baechle depends on PCI && (SIBYTE_SB1250 || SIBYTE_BCM1125H) 9638b18f72SRalf Baechle default y 9738b18f72SRalf Baechle 9838b18f72SRalf Baechleconfig SIMULATION 9938b18f72SRalf Baechle bool "Running under simulation" 10038b18f72SRalf Baechle depends on SIBYTE_SB1xxx_SOC 10138b18f72SRalf Baechle help 10238b18f72SRalf Baechle Build a kernel suitable for running under the GDB simulator. 10338b18f72SRalf Baechle Primarily adjusts the kernel's notion of time. 10438b18f72SRalf Baechle 105*a4b5bd9aSAndrew Isaacsonconfig CONFIG_SB1_CEX_ALWAYS_FATAL 106*a4b5bd9aSAndrew Isaacson bool "All cache exceptions considered fatal (no recovery attempted)" 107*a4b5bd9aSAndrew Isaacson depends on SIBYTE_SB1xxx_SOC 108*a4b5bd9aSAndrew Isaacson 109*a4b5bd9aSAndrew Isaacsonconfig CONFIG_SB1_CERR_STALL 110*a4b5bd9aSAndrew Isaacson bool "Stall (rather than panic) on fatal cache error" 111*a4b5bd9aSAndrew Isaacson depends on SIBYTE_SB1xxx_SOC 112*a4b5bd9aSAndrew Isaacson 11338b18f72SRalf Baechleconfig SIBYTE_CFE 11438b18f72SRalf Baechle bool "Booting from CFE" 11538b18f72SRalf Baechle depends on SIBYTE_SB1xxx_SOC 11638b18f72SRalf Baechle help 11738b18f72SRalf Baechle Make use of the CFE API for enumerating available memory, 11838b18f72SRalf Baechle controlling secondary CPUs, and possibly console output. 11938b18f72SRalf Baechle 12038b18f72SRalf Baechleconfig SIBYTE_CFE_CONSOLE 12138b18f72SRalf Baechle bool "Use firmware console" 12238b18f72SRalf Baechle depends on SIBYTE_CFE 12338b18f72SRalf Baechle help 12438b18f72SRalf Baechle Use the CFE API's console write routines during boot. Other console 12538b18f72SRalf Baechle options (VT console, sb1250 duart console, etc.) should not be 12638b18f72SRalf Baechle configured. 12738b18f72SRalf Baechle 12838b18f72SRalf Baechleconfig SIBYTE_STANDALONE 12938b18f72SRalf Baechle bool 13038b18f72SRalf Baechle depends on SIBYTE_SB1xxx_SOC && !SIBYTE_CFE 13138b18f72SRalf Baechle default y 13238b18f72SRalf Baechle 13338b18f72SRalf Baechleconfig SIBYTE_STANDALONE_RAM_SIZE 13438b18f72SRalf Baechle int "Memory size (in megabytes)" 13538b18f72SRalf Baechle depends on SIBYTE_STANDALONE 13638b18f72SRalf Baechle default "32" 13738b18f72SRalf Baechle 13838b18f72SRalf Baechleconfig SIBYTE_BUS_WATCHER 13938b18f72SRalf Baechle bool "Support for Bus Watcher statistics" 14038b18f72SRalf Baechle depends on SIBYTE_SB1xxx_SOC 14138b18f72SRalf Baechle help 14238b18f72SRalf Baechle Handle and keep statistics on the bus error interrupts (COR_ECC, 14338b18f72SRalf Baechle BAD_ECC, IO_BUS). 14438b18f72SRalf Baechle 14538b18f72SRalf Baechleconfig SIBYTE_BW_TRACE 14638b18f72SRalf Baechle bool "Capture bus trace before bus error" 14738b18f72SRalf Baechle depends on SIBYTE_BUS_WATCHER 14838b18f72SRalf Baechle help 14938b18f72SRalf Baechle Run a continuous bus trace, dumping the raw data as soon as 15038b18f72SRalf Baechle a ZBbus error is detected. Cannot work if ZBbus profiling 15138b18f72SRalf Baechle is turned on, and also will interfere with JTAG-based trace 15238b18f72SRalf Baechle buffer activity. Raw buffer data is dumped to console, and 15338b18f72SRalf Baechle must be processed off-line. 15438b18f72SRalf Baechle 15538b18f72SRalf Baechleconfig SIBYTE_SB1250_PROF 15638b18f72SRalf Baechle bool "Support for SB1/SOC profiling - SB1/SCD perf counters" 15738b18f72SRalf Baechle depends on SIBYTE_SB1xxx_SOC 15838b18f72SRalf Baechle 15938b18f72SRalf Baechleconfig SIBYTE_TBPROF 16038b18f72SRalf Baechle bool "Support for ZBbus profiling" 16138b18f72SRalf Baechle depends on SIBYTE_SB1xxx_SOC 162