1 /* 2 * Code to handle IP32 IRQs 3 * 4 * This file is subject to the terms and conditions of the GNU General Public 5 * License. See the file "COPYING" in the main directory of this archive 6 * for more details. 7 * 8 * Copyright (C) 2000 Harald Koerfgen 9 * Copyright (C) 2001 Keith M Wesolowski 10 */ 11 #include <linux/init.h> 12 #include <linux/kernel_stat.h> 13 #include <linux/types.h> 14 #include <linux/interrupt.h> 15 #include <linux/irq.h> 16 #include <linux/bitops.h> 17 #include <linux/kernel.h> 18 #include <linux/slab.h> 19 #include <linux/mm.h> 20 #include <linux/random.h> 21 #include <linux/sched.h> 22 23 #include <asm/mipsregs.h> 24 #include <asm/signal.h> 25 #include <asm/system.h> 26 #include <asm/time.h> 27 #include <asm/ip32/crime.h> 28 #include <asm/ip32/mace.h> 29 #include <asm/ip32/ip32_ints.h> 30 31 /* issue a PIO read to make sure no PIO writes are pending */ 32 static void inline flush_crime_bus(void) 33 { 34 volatile unsigned long junk = crime->control; 35 } 36 37 static void inline flush_mace_bus(void) 38 { 39 volatile unsigned long junk = mace->perif.ctrl.misc; 40 } 41 42 #undef DEBUG_IRQ 43 #ifdef DEBUG_IRQ 44 #define DBG(x...) printk(x) 45 #else 46 #define DBG(x...) 47 #endif 48 49 /* O2 irq map 50 * 51 * IP0 -> software (ignored) 52 * IP1 -> software (ignored) 53 * IP2 -> (irq0) C crime 1.1 all interrupts; crime 1.5 ??? 54 * IP3 -> (irq1) X unknown 55 * IP4 -> (irq2) X unknown 56 * IP5 -> (irq3) X unknown 57 * IP6 -> (irq4) X unknown 58 * IP7 -> (irq5) 0 CPU count/compare timer (system timer) 59 * 60 * crime: (C) 61 * 62 * CRIME_INT_STAT 31:0: 63 * 64 * 0 -> 1 Video in 1 65 * 1 -> 2 Video in 2 66 * 2 -> 3 Video out 67 * 3 -> 4 Mace ethernet 68 * 4 -> S SuperIO sub-interrupt 69 * 5 -> M Miscellaneous sub-interrupt 70 * 6 -> A Audio sub-interrupt 71 * 7 -> 8 PCI bridge errors 72 * 8 -> 9 PCI SCSI aic7xxx 0 73 * 9 -> 10 PCI SCSI aic7xxx 1 74 * 10 -> 11 PCI slot 0 75 * 11 -> 12 unused (PCI slot 1) 76 * 12 -> 13 unused (PCI slot 2) 77 * 13 -> 14 unused (PCI shared 0) 78 * 14 -> 15 unused (PCI shared 1) 79 * 15 -> 16 unused (PCI shared 2) 80 * 16 -> 17 GBE0 (E) 81 * 17 -> 18 GBE1 (E) 82 * 18 -> 19 GBE2 (E) 83 * 19 -> 20 GBE3 (E) 84 * 20 -> 21 CPU errors 85 * 21 -> 22 Memory errors 86 * 22 -> 23 RE empty edge (E) 87 * 23 -> 24 RE full edge (E) 88 * 24 -> 25 RE idle edge (E) 89 * 25 -> 26 RE empty level 90 * 26 -> 27 RE full level 91 * 27 -> 28 RE idle level 92 * 28 -> 29 unused (software 0) (E) 93 * 29 -> 30 unused (software 1) (E) 94 * 30 -> 31 unused (software 2) - crime 1.5 CPU SysCorError (E) 95 * 31 -> 32 VICE 96 * 97 * S, M, A: Use the MACE ISA interrupt register 98 * MACE_ISA_INT_STAT 31:0 99 * 100 * 0-7 -> 33-40 Audio 101 * 8 -> 41 RTC 102 * 9 -> 42 Keyboard 103 * 10 -> X Keyboard polled 104 * 11 -> 44 Mouse 105 * 12 -> X Mouse polled 106 * 13-15 -> 46-48 Count/compare timers 107 * 16-19 -> 49-52 Parallel (16 E) 108 * 20-25 -> 53-58 Serial 1 (22 E) 109 * 26-31 -> 59-64 Serial 2 (28 E) 110 * 111 * Note that this means IRQs 5-7, 43, and 45 do not exist. This is a 112 * different IRQ map than IRIX uses, but that's OK as Linux irq handling 113 * is quite different anyway. 114 */ 115 116 /* 117 * IRQ spinlock - Ralf says not to disable CPU interrupts, 118 * and I think he knows better. 119 */ 120 static DEFINE_SPINLOCK(ip32_irq_lock); 121 122 /* Some initial interrupts to set up */ 123 extern irqreturn_t crime_memerr_intr (int irq, void *dev_id, 124 struct pt_regs *regs); 125 extern irqreturn_t crime_cpuerr_intr (int irq, void *dev_id, 126 struct pt_regs *regs); 127 128 struct irqaction memerr_irq = { crime_memerr_intr, SA_INTERRUPT, 129 CPU_MASK_NONE, "CRIME memory error", NULL, NULL }; 130 struct irqaction cpuerr_irq = { crime_cpuerr_intr, SA_INTERRUPT, 131 CPU_MASK_NONE, "CRIME CPU error", NULL, NULL }; 132 133 /* 134 * For interrupts wired from a single device to the CPU. Only the clock 135 * uses this it seems, which is IRQ 0 and IP7. 136 */ 137 138 static void enable_cpu_irq(unsigned int irq) 139 { 140 set_c0_status(STATUSF_IP7); 141 } 142 143 static unsigned int startup_cpu_irq(unsigned int irq) 144 { 145 enable_cpu_irq(irq); 146 return 0; 147 } 148 149 static void disable_cpu_irq(unsigned int irq) 150 { 151 clear_c0_status(STATUSF_IP7); 152 } 153 154 static void end_cpu_irq(unsigned int irq) 155 { 156 if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) 157 enable_cpu_irq (irq); 158 } 159 160 #define shutdown_cpu_irq disable_cpu_irq 161 #define mask_and_ack_cpu_irq disable_cpu_irq 162 163 static struct hw_interrupt_type ip32_cpu_interrupt = { 164 .typename = "IP32 CPU", 165 .startup = startup_cpu_irq, 166 .shutdown = shutdown_cpu_irq, 167 .enable = enable_cpu_irq, 168 .disable = disable_cpu_irq, 169 .ack = mask_and_ack_cpu_irq, 170 .end = end_cpu_irq, 171 }; 172 173 /* 174 * This is for pure CRIME interrupts - ie not MACE. The advantage? 175 * We get to split the register in half and do faster lookups. 176 */ 177 178 static uint64_t crime_mask; 179 180 static void enable_crime_irq(unsigned int irq) 181 { 182 unsigned long flags; 183 184 spin_lock_irqsave(&ip32_irq_lock, flags); 185 crime_mask |= 1 << (irq - 1); 186 crime->imask = crime_mask; 187 spin_unlock_irqrestore(&ip32_irq_lock, flags); 188 } 189 190 static unsigned int startup_crime_irq(unsigned int irq) 191 { 192 enable_crime_irq(irq); 193 return 0; /* This is probably not right; we could have pending irqs */ 194 } 195 196 static void disable_crime_irq(unsigned int irq) 197 { 198 unsigned long flags; 199 200 spin_lock_irqsave(&ip32_irq_lock, flags); 201 crime_mask &= ~(1 << (irq - 1)); 202 crime->imask = crime_mask; 203 flush_crime_bus(); 204 spin_unlock_irqrestore(&ip32_irq_lock, flags); 205 } 206 207 static void mask_and_ack_crime_irq(unsigned int irq) 208 { 209 unsigned long flags; 210 211 /* Edge triggered interrupts must be cleared. */ 212 if ((irq >= CRIME_GBE0_IRQ && irq <= CRIME_GBE3_IRQ) 213 || (irq >= CRIME_RE_EMPTY_E_IRQ && irq <= CRIME_RE_IDLE_E_IRQ) 214 || (irq >= CRIME_SOFT0_IRQ && irq <= CRIME_SOFT2_IRQ)) { 215 uint64_t crime_int; 216 spin_lock_irqsave(&ip32_irq_lock, flags); 217 crime_int = crime->hard_int; 218 crime_int &= ~(1 << (irq - 1)); 219 crime->hard_int = crime_int; 220 spin_unlock_irqrestore(&ip32_irq_lock, flags); 221 } 222 disable_crime_irq(irq); 223 } 224 225 static void end_crime_irq(unsigned int irq) 226 { 227 if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) 228 enable_crime_irq(irq); 229 } 230 231 #define shutdown_crime_irq disable_crime_irq 232 233 static struct hw_interrupt_type ip32_crime_interrupt = { 234 .typename = "IP32 CRIME", 235 .startup = startup_crime_irq, 236 .shutdown = shutdown_crime_irq, 237 .enable = enable_crime_irq, 238 .disable = disable_crime_irq, 239 .ack = mask_and_ack_crime_irq, 240 .end = end_crime_irq, 241 }; 242 243 /* 244 * This is for MACE PCI interrupts. We can decrease bus traffic by masking 245 * as close to the source as possible. This also means we can take the 246 * next chunk of the CRIME register in one piece. 247 */ 248 249 static unsigned long macepci_mask; 250 251 static void enable_macepci_irq(unsigned int irq) 252 { 253 unsigned long flags; 254 255 spin_lock_irqsave(&ip32_irq_lock, flags); 256 macepci_mask |= MACEPCI_CONTROL_INT(irq - 9); 257 mace->pci.control = macepci_mask; 258 crime_mask |= 1 << (irq - 1); 259 crime->imask = crime_mask; 260 spin_unlock_irqrestore(&ip32_irq_lock, flags); 261 } 262 263 static unsigned int startup_macepci_irq(unsigned int irq) 264 { 265 enable_macepci_irq (irq); 266 return 0; 267 } 268 269 static void disable_macepci_irq(unsigned int irq) 270 { 271 unsigned long flags; 272 273 spin_lock_irqsave(&ip32_irq_lock, flags); 274 crime_mask &= ~(1 << (irq - 1)); 275 crime->imask = crime_mask; 276 flush_crime_bus(); 277 macepci_mask &= ~MACEPCI_CONTROL_INT(irq - 9); 278 mace->pci.control = macepci_mask; 279 flush_mace_bus(); 280 spin_unlock_irqrestore(&ip32_irq_lock, flags); 281 } 282 283 static void end_macepci_irq(unsigned int irq) 284 { 285 if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS))) 286 enable_macepci_irq(irq); 287 } 288 289 #define shutdown_macepci_irq disable_macepci_irq 290 #define mask_and_ack_macepci_irq disable_macepci_irq 291 292 static struct hw_interrupt_type ip32_macepci_interrupt = { 293 .typename = "IP32 MACE PCI", 294 .startup = startup_macepci_irq, 295 .shutdown = shutdown_macepci_irq, 296 .enable = enable_macepci_irq, 297 .disable = disable_macepci_irq, 298 .ack = mask_and_ack_macepci_irq, 299 .end = end_macepci_irq, 300 }; 301 302 /* This is used for MACE ISA interrupts. That means bits 4-6 in the 303 * CRIME register. 304 */ 305 306 #define MACEISA_AUDIO_INT (MACEISA_AUDIO_SW_INT | \ 307 MACEISA_AUDIO_SC_INT | \ 308 MACEISA_AUDIO1_DMAT_INT | \ 309 MACEISA_AUDIO1_OF_INT | \ 310 MACEISA_AUDIO2_DMAT_INT | \ 311 MACEISA_AUDIO2_MERR_INT | \ 312 MACEISA_AUDIO3_DMAT_INT | \ 313 MACEISA_AUDIO3_MERR_INT) 314 #define MACEISA_MISC_INT (MACEISA_RTC_INT | \ 315 MACEISA_KEYB_INT | \ 316 MACEISA_KEYB_POLL_INT | \ 317 MACEISA_MOUSE_INT | \ 318 MACEISA_MOUSE_POLL_INT | \ 319 MACEISA_TIMER0_INT | \ 320 MACEISA_TIMER1_INT | \ 321 MACEISA_TIMER2_INT) 322 #define MACEISA_SUPERIO_INT (MACEISA_PARALLEL_INT | \ 323 MACEISA_PAR_CTXA_INT | \ 324 MACEISA_PAR_CTXB_INT | \ 325 MACEISA_PAR_MERR_INT | \ 326 MACEISA_SERIAL1_INT | \ 327 MACEISA_SERIAL1_TDMAT_INT | \ 328 MACEISA_SERIAL1_TDMAPR_INT | \ 329 MACEISA_SERIAL1_TDMAME_INT | \ 330 MACEISA_SERIAL1_RDMAT_INT | \ 331 MACEISA_SERIAL1_RDMAOR_INT | \ 332 MACEISA_SERIAL2_INT | \ 333 MACEISA_SERIAL2_TDMAT_INT | \ 334 MACEISA_SERIAL2_TDMAPR_INT | \ 335 MACEISA_SERIAL2_TDMAME_INT | \ 336 MACEISA_SERIAL2_RDMAT_INT | \ 337 MACEISA_SERIAL2_RDMAOR_INT) 338 339 static unsigned long maceisa_mask; 340 341 static void enable_maceisa_irq (unsigned int irq) 342 { 343 unsigned int crime_int = 0; 344 unsigned long flags; 345 346 DBG ("maceisa enable: %u\n", irq); 347 348 switch (irq) { 349 case MACEISA_AUDIO_SW_IRQ ... MACEISA_AUDIO3_MERR_IRQ: 350 crime_int = MACE_AUDIO_INT; 351 break; 352 case MACEISA_RTC_IRQ ... MACEISA_TIMER2_IRQ: 353 crime_int = MACE_MISC_INT; 354 break; 355 case MACEISA_PARALLEL_IRQ ... MACEISA_SERIAL2_RDMAOR_IRQ: 356 crime_int = MACE_SUPERIO_INT; 357 break; 358 } 359 DBG ("crime_int %08x enabled\n", crime_int); 360 spin_lock_irqsave(&ip32_irq_lock, flags); 361 crime_mask |= crime_int; 362 crime->imask = crime_mask; 363 maceisa_mask |= 1 << (irq - 33); 364 mace->perif.ctrl.imask = maceisa_mask; 365 spin_unlock_irqrestore(&ip32_irq_lock, flags); 366 } 367 368 static unsigned int startup_maceisa_irq(unsigned int irq) 369 { 370 enable_maceisa_irq(irq); 371 return 0; 372 } 373 374 static void disable_maceisa_irq(unsigned int irq) 375 { 376 unsigned int crime_int = 0; 377 unsigned long flags; 378 379 spin_lock_irqsave(&ip32_irq_lock, flags); 380 maceisa_mask &= ~(1 << (irq - 33)); 381 if(!(maceisa_mask & MACEISA_AUDIO_INT)) 382 crime_int |= MACE_AUDIO_INT; 383 if(!(maceisa_mask & MACEISA_MISC_INT)) 384 crime_int |= MACE_MISC_INT; 385 if(!(maceisa_mask & MACEISA_SUPERIO_INT)) 386 crime_int |= MACE_SUPERIO_INT; 387 crime_mask &= ~crime_int; 388 crime->imask = crime_mask; 389 flush_crime_bus(); 390 mace->perif.ctrl.imask = maceisa_mask; 391 flush_mace_bus(); 392 spin_unlock_irqrestore(&ip32_irq_lock, flags); 393 } 394 395 static void mask_and_ack_maceisa_irq(unsigned int irq) 396 { 397 unsigned long mace_int, flags; 398 399 switch (irq) { 400 case MACEISA_PARALLEL_IRQ: 401 case MACEISA_SERIAL1_TDMAPR_IRQ: 402 case MACEISA_SERIAL2_TDMAPR_IRQ: 403 /* edge triggered */ 404 spin_lock_irqsave(&ip32_irq_lock, flags); 405 mace_int = mace->perif.ctrl.istat; 406 mace_int &= ~(1 << (irq - 33)); 407 mace->perif.ctrl.istat = mace_int; 408 spin_unlock_irqrestore(&ip32_irq_lock, flags); 409 break; 410 } 411 disable_maceisa_irq(irq); 412 } 413 414 static void end_maceisa_irq(unsigned irq) 415 { 416 if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) 417 enable_maceisa_irq(irq); 418 } 419 420 #define shutdown_maceisa_irq disable_maceisa_irq 421 422 static struct hw_interrupt_type ip32_maceisa_interrupt = { 423 .typename = "IP32 MACE ISA", 424 .startup = startup_maceisa_irq, 425 .shutdown = shutdown_maceisa_irq, 426 .enable = enable_maceisa_irq, 427 .disable = disable_maceisa_irq, 428 .ack = mask_and_ack_maceisa_irq, 429 .end = end_maceisa_irq, 430 }; 431 432 /* This is used for regular non-ISA, non-PCI MACE interrupts. That means 433 * bits 0-3 and 7 in the CRIME register. 434 */ 435 436 static void enable_mace_irq(unsigned int irq) 437 { 438 unsigned long flags; 439 440 spin_lock_irqsave(&ip32_irq_lock, flags); 441 crime_mask |= 1 << (irq - 1); 442 crime->imask = crime_mask; 443 spin_unlock_irqrestore(&ip32_irq_lock, flags); 444 } 445 446 static unsigned int startup_mace_irq(unsigned int irq) 447 { 448 enable_mace_irq(irq); 449 return 0; 450 } 451 452 static void disable_mace_irq(unsigned int irq) 453 { 454 unsigned long flags; 455 456 spin_lock_irqsave(&ip32_irq_lock, flags); 457 crime_mask &= ~(1 << (irq - 1)); 458 crime->imask = crime_mask; 459 flush_crime_bus(); 460 spin_unlock_irqrestore(&ip32_irq_lock, flags); 461 } 462 463 static void end_mace_irq(unsigned int irq) 464 { 465 if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS))) 466 enable_mace_irq(irq); 467 } 468 469 #define shutdown_mace_irq disable_mace_irq 470 #define mask_and_ack_mace_irq disable_mace_irq 471 472 static struct hw_interrupt_type ip32_mace_interrupt = { 473 .typename = "IP32 MACE", 474 .startup = startup_mace_irq, 475 .shutdown = shutdown_mace_irq, 476 .enable = enable_mace_irq, 477 .disable = disable_mace_irq, 478 .ack = mask_and_ack_mace_irq, 479 .end = end_mace_irq, 480 }; 481 482 static void ip32_unknown_interrupt(struct pt_regs *regs) 483 { 484 printk ("Unknown interrupt occurred!\n"); 485 printk ("cp0_status: %08x\n", read_c0_status()); 486 printk ("cp0_cause: %08x\n", read_c0_cause()); 487 printk ("CRIME intr mask: %016lx\n", crime->imask); 488 printk ("CRIME intr status: %016lx\n", crime->istat); 489 printk ("CRIME hardware intr register: %016lx\n", crime->hard_int); 490 printk ("MACE ISA intr mask: %08lx\n", mace->perif.ctrl.imask); 491 printk ("MACE ISA intr status: %08lx\n", mace->perif.ctrl.istat); 492 printk ("MACE PCI control register: %08x\n", mace->pci.control); 493 494 printk("Register dump:\n"); 495 show_regs(regs); 496 497 printk("Please mail this report to linux-mips@linux-mips.org\n"); 498 printk("Spinning..."); 499 while(1) ; 500 } 501 502 /* CRIME 1.1 appears to deliver all interrupts to this one pin. */ 503 /* change this to loop over all edge-triggered irqs, exception masked out ones */ 504 static void ip32_irq0(struct pt_regs *regs) 505 { 506 uint64_t crime_int; 507 int irq = 0; 508 509 crime_int = crime->istat & crime_mask; 510 irq = __ffs(crime_int); 511 crime_int = 1 << irq; 512 513 if (crime_int & CRIME_MACEISA_INT_MASK) { 514 unsigned long mace_int = mace->perif.ctrl.istat; 515 irq = __ffs(mace_int & maceisa_mask) + 32; 516 } 517 irq++; 518 DBG("*irq %u*\n", irq); 519 do_IRQ(irq, regs); 520 } 521 522 static void ip32_irq1(struct pt_regs *regs) 523 { 524 ip32_unknown_interrupt(regs); 525 } 526 527 static void ip32_irq2(struct pt_regs *regs) 528 { 529 ip32_unknown_interrupt(regs); 530 } 531 532 static void ip32_irq3(struct pt_regs *regs) 533 { 534 ip32_unknown_interrupt(regs); 535 } 536 537 static void ip32_irq4(struct pt_regs *regs) 538 { 539 ip32_unknown_interrupt(regs); 540 } 541 542 static void ip32_irq5(struct pt_regs *regs) 543 { 544 ll_timer_interrupt(IP32_R4K_TIMER_IRQ, regs); 545 } 546 547 asmlinkage void plat_irq_dispatch(struct pt_regs *regs) 548 { 549 unsigned int pending = read_c0_cause(); 550 551 if (likely(pending & IE_IRQ0)) 552 ip32_irq0(regs); 553 else if (unlikely(pending & IE_IRQ1)) 554 ip32_irq1(regs); 555 else if (unlikely(pending & IE_IRQ2)) 556 ip32_irq2(regs); 557 else if (unlikely(pending & IE_IRQ3)) 558 ip32_irq3(regs); 559 else if (unlikely(pending & IE_IRQ4)) 560 ip32_irq4(regs); 561 else if (likely(pending & IE_IRQ5)) 562 ip32_irq5(regs); 563 } 564 565 void __init arch_init_irq(void) 566 { 567 unsigned int irq; 568 569 /* Install our interrupt handler, then clear and disable all 570 * CRIME and MACE interrupts. */ 571 crime->imask = 0; 572 crime->hard_int = 0; 573 crime->soft_int = 0; 574 mace->perif.ctrl.istat = 0; 575 mace->perif.ctrl.imask = 0; 576 577 for (irq = 0; irq <= IP32_IRQ_MAX; irq++) { 578 hw_irq_controller *controller; 579 580 if (irq == IP32_R4K_TIMER_IRQ) 581 controller = &ip32_cpu_interrupt; 582 else if (irq <= MACE_PCI_BRIDGE_IRQ && irq >= MACE_VID_IN1_IRQ) 583 controller = &ip32_mace_interrupt; 584 else if (irq <= MACEPCI_SHARED2_IRQ && irq >= MACEPCI_SCSI0_IRQ) 585 controller = &ip32_macepci_interrupt; 586 else if (irq <= CRIME_VICE_IRQ && irq >= CRIME_GBE0_IRQ) 587 controller = &ip32_crime_interrupt; 588 else 589 controller = &ip32_maceisa_interrupt; 590 591 irq_desc[irq].status = IRQ_DISABLED; 592 irq_desc[irq].action = 0; 593 irq_desc[irq].depth = 0; 594 irq_desc[irq].handler = controller; 595 } 596 setup_irq(CRIME_MEMERR_IRQ, &memerr_irq); 597 setup_irq(CRIME_CPUERR_IRQ, &cpuerr_irq); 598 599 #define ALLINTS (IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4 | IE_IRQ5) 600 change_c0_status(ST0_IM, ALLINTS); 601 } 602