1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * ip27-irq.c: Highlevel interrupt handling for IP27 architecture. 4 * 5 * Copyright (C) 1999, 2000 Ralf Baechle (ralf@gnu.org) 6 * Copyright (C) 1999, 2000 Silicon Graphics, Inc. 7 * Copyright (C) 1999 - 2001 Kanoj Sarcar 8 */ 9 10 #include <linux/interrupt.h> 11 #include <linux/irq.h> 12 #include <linux/ioport.h> 13 #include <linux/kernel.h> 14 #include <linux/bitops.h> 15 16 #include <asm/io.h> 17 #include <asm/irq_cpu.h> 18 #include <asm/pci/bridge.h> 19 #include <asm/sn/addrs.h> 20 #include <asm/sn/agent.h> 21 #include <asm/sn/arch.h> 22 #include <asm/sn/hub.h> 23 #include <asm/sn/intr.h> 24 25 struct hub_irq_data { 26 struct bridge_controller *bc; 27 u64 *irq_mask[2]; 28 cpuid_t cpu; 29 int bit; 30 int pin; 31 }; 32 33 static DECLARE_BITMAP(hub_irq_map, IP27_HUB_IRQ_COUNT); 34 35 static DEFINE_PER_CPU(unsigned long [2], irq_enable_mask); 36 37 static inline int alloc_level(void) 38 { 39 int level; 40 41 again: 42 level = find_first_zero_bit(hub_irq_map, IP27_HUB_IRQ_COUNT); 43 if (level >= IP27_HUB_IRQ_COUNT) 44 return -ENOSPC; 45 46 if (test_and_set_bit(level, hub_irq_map)) 47 goto again; 48 49 return level; 50 } 51 52 static void enable_hub_irq(struct irq_data *d) 53 { 54 struct hub_irq_data *hd = irq_data_get_irq_chip_data(d); 55 unsigned long *mask = per_cpu(irq_enable_mask, hd->cpu); 56 57 set_bit(hd->bit, mask); 58 __raw_writeq(mask[0], hd->irq_mask[0]); 59 __raw_writeq(mask[1], hd->irq_mask[1]); 60 } 61 62 static void disable_hub_irq(struct irq_data *d) 63 { 64 struct hub_irq_data *hd = irq_data_get_irq_chip_data(d); 65 unsigned long *mask = per_cpu(irq_enable_mask, hd->cpu); 66 67 clear_bit(hd->bit, mask); 68 __raw_writeq(mask[0], hd->irq_mask[0]); 69 __raw_writeq(mask[1], hd->irq_mask[1]); 70 } 71 72 static unsigned int startup_bridge_irq(struct irq_data *d) 73 { 74 struct hub_irq_data *hd = irq_data_get_irq_chip_data(d); 75 struct bridge_controller *bc; 76 nasid_t nasid; 77 u32 device; 78 int pin; 79 80 if (!hd) 81 return -EINVAL; 82 83 pin = hd->pin; 84 bc = hd->bc; 85 86 nasid = COMPACT_TO_NASID_NODEID(cpu_to_node(hd->cpu)); 87 bridge_write(bc, b_int_addr[pin].addr, 88 (0x20000 | hd->bit | (nasid << 8))); 89 bridge_set(bc, b_int_enable, (1 << pin)); 90 bridge_set(bc, b_int_enable, 0x7ffffe00); /* more stuff in int_enable */ 91 92 /* 93 * Enable sending of an interrupt clear packt to the hub on a high to 94 * low transition of the interrupt pin. 95 * 96 * IRIX sets additional bits in the address which are documented as 97 * reserved in the bridge docs. 98 */ 99 bridge_set(bc, b_int_mode, (1UL << pin)); 100 101 /* 102 * We assume the bridge to have a 1:1 mapping between devices 103 * (slots) and intr pins. 104 */ 105 device = bridge_read(bc, b_int_device); 106 device &= ~(7 << (pin*3)); 107 device |= (pin << (pin*3)); 108 bridge_write(bc, b_int_device, device); 109 110 bridge_read(bc, b_wid_tflush); 111 112 enable_hub_irq(d); 113 114 return 0; /* Never anything pending. */ 115 } 116 117 static void shutdown_bridge_irq(struct irq_data *d) 118 { 119 struct hub_irq_data *hd = irq_data_get_irq_chip_data(d); 120 struct bridge_controller *bc; 121 int pin = hd->pin; 122 123 if (!hd) 124 return; 125 126 disable_hub_irq(d); 127 128 bc = hd->bc; 129 bridge_clr(bc, b_int_enable, (1 << pin)); 130 bridge_read(bc, b_wid_tflush); 131 } 132 133 static void setup_hub_mask(struct hub_irq_data *hd, const struct cpumask *mask) 134 { 135 nasid_t nasid; 136 int cpu; 137 138 cpu = cpumask_first_and(mask, cpu_online_mask); 139 nasid = COMPACT_TO_NASID_NODEID(cpu_to_node(cpu)); 140 hd->cpu = cpu; 141 if (!cputoslice(cpu)) { 142 hd->irq_mask[0] = REMOTE_HUB_PTR(nasid, PI_INT_MASK0_A); 143 hd->irq_mask[1] = REMOTE_HUB_PTR(nasid, PI_INT_MASK1_A); 144 } else { 145 hd->irq_mask[0] = REMOTE_HUB_PTR(nasid, PI_INT_MASK0_B); 146 hd->irq_mask[1] = REMOTE_HUB_PTR(nasid, PI_INT_MASK1_B); 147 } 148 149 /* Make sure it's not already pending when we connect it. */ 150 REMOTE_HUB_CLR_INTR(nasid, hd->bit); 151 } 152 153 static int set_affinity_hub_irq(struct irq_data *d, const struct cpumask *mask, 154 bool force) 155 { 156 struct hub_irq_data *hd = irq_data_get_irq_chip_data(d); 157 158 if (!hd) 159 return -EINVAL; 160 161 if (irqd_is_started(d)) 162 disable_hub_irq(d); 163 164 setup_hub_mask(hd, mask); 165 166 if (irqd_is_started(d)) 167 startup_bridge_irq(d); 168 169 irq_data_update_effective_affinity(d, cpumask_of(hd->cpu)); 170 171 return 0; 172 } 173 174 static struct irq_chip hub_irq_type = { 175 .name = "HUB", 176 .irq_startup = startup_bridge_irq, 177 .irq_shutdown = shutdown_bridge_irq, 178 .irq_mask = disable_hub_irq, 179 .irq_unmask = enable_hub_irq, 180 .irq_set_affinity = set_affinity_hub_irq, 181 }; 182 183 int request_bridge_irq(struct bridge_controller *bc, int pin) 184 { 185 struct hub_irq_data *hd; 186 struct hub_data *hub; 187 struct irq_desc *desc; 188 int swlevel; 189 int irq; 190 191 hd = kzalloc(sizeof(*hd), GFP_KERNEL); 192 if (!hd) 193 return -ENOMEM; 194 195 swlevel = alloc_level(); 196 if (unlikely(swlevel < 0)) { 197 kfree(hd); 198 return -EAGAIN; 199 } 200 irq = swlevel + IP27_HUB_IRQ_BASE; 201 202 hd->bc = bc; 203 hd->bit = swlevel; 204 hd->pin = pin; 205 irq_set_chip_data(irq, hd); 206 207 /* use CPU connected to nearest hub */ 208 hub = hub_data(NASID_TO_COMPACT_NODEID(bc->nasid)); 209 setup_hub_mask(hd, &hub->h_cpus); 210 211 desc = irq_to_desc(irq); 212 desc->irq_common_data.node = bc->nasid; 213 cpumask_copy(desc->irq_common_data.affinity, &hub->h_cpus); 214 215 return irq; 216 } 217 218 void ip27_hub_irq_init(void) 219 { 220 int i; 221 222 for (i = IP27_HUB_IRQ_BASE; 223 i < (IP27_HUB_IRQ_BASE + IP27_HUB_IRQ_COUNT); i++) 224 irq_set_chip_and_handler(i, &hub_irq_type, handle_level_irq); 225 226 /* 227 * Some interrupts are reserved by hardware or by software convention. 228 * Mark these as reserved right away so they won't be used accidentally 229 * later. 230 */ 231 for (i = 0; i <= BASE_PCI_IRQ; i++) 232 set_bit(i, hub_irq_map); 233 234 set_bit(IP_PEND0_6_63, hub_irq_map); 235 236 for (i = NI_BRDCAST_ERR_A; i <= MSC_PANIC_INTR; i++) 237 set_bit(i, hub_irq_map); 238 } 239 240 /* 241 * This code is unnecessarily complex, because we do 242 * intr enabling. Basically, once we grab the set of intrs we need 243 * to service, we must mask _all_ these interrupts; firstly, to make 244 * sure the same intr does not intr again, causing recursion that 245 * can lead to stack overflow. Secondly, we can not just mask the 246 * one intr we are do_IRQing, because the non-masked intrs in the 247 * first set might intr again, causing multiple servicings of the 248 * same intr. This effect is mostly seen for intercpu intrs. 249 * Kanoj 05.13.00 250 */ 251 252 static void ip27_do_irq_mask0(struct irq_desc *desc) 253 { 254 cpuid_t cpu = smp_processor_id(); 255 unsigned long *mask = per_cpu(irq_enable_mask, cpu); 256 u64 pend0; 257 258 /* copied from Irix intpend0() */ 259 pend0 = LOCAL_HUB_L(PI_INT_PEND0); 260 261 pend0 &= mask[0]; /* Pick intrs we should look at */ 262 if (!pend0) 263 return; 264 265 #ifdef CONFIG_SMP 266 if (pend0 & (1UL << CPU_RESCHED_A_IRQ)) { 267 LOCAL_HUB_CLR_INTR(CPU_RESCHED_A_IRQ); 268 scheduler_ipi(); 269 } else if (pend0 & (1UL << CPU_RESCHED_B_IRQ)) { 270 LOCAL_HUB_CLR_INTR(CPU_RESCHED_B_IRQ); 271 scheduler_ipi(); 272 } else if (pend0 & (1UL << CPU_CALL_A_IRQ)) { 273 LOCAL_HUB_CLR_INTR(CPU_CALL_A_IRQ); 274 generic_smp_call_function_interrupt(); 275 } else if (pend0 & (1UL << CPU_CALL_B_IRQ)) { 276 LOCAL_HUB_CLR_INTR(CPU_CALL_B_IRQ); 277 generic_smp_call_function_interrupt(); 278 } else 279 #endif 280 generic_handle_irq(__ffs(pend0) + IP27_HUB_IRQ_BASE); 281 282 LOCAL_HUB_L(PI_INT_PEND0); 283 } 284 285 static void ip27_do_irq_mask1(struct irq_desc *desc) 286 { 287 cpuid_t cpu = smp_processor_id(); 288 unsigned long *mask = per_cpu(irq_enable_mask, cpu); 289 u64 pend1; 290 291 /* copied from Irix intpend0() */ 292 pend1 = LOCAL_HUB_L(PI_INT_PEND1); 293 294 pend1 &= mask[1]; /* Pick intrs we should look at */ 295 if (!pend1) 296 return; 297 298 generic_handle_irq(__ffs(pend1) + IP27_HUB_IRQ_BASE + 64); 299 300 LOCAL_HUB_L(PI_INT_PEND1); 301 } 302 303 void install_ipi(void) 304 { 305 int cpu = smp_processor_id(); 306 unsigned long *mask = per_cpu(irq_enable_mask, cpu); 307 int slice = LOCAL_HUB_L(PI_CPU_NUM); 308 int resched, call; 309 310 resched = CPU_RESCHED_A_IRQ + slice; 311 set_bit(resched, mask); 312 LOCAL_HUB_CLR_INTR(resched); 313 314 call = CPU_CALL_A_IRQ + slice; 315 set_bit(call, mask); 316 LOCAL_HUB_CLR_INTR(call); 317 318 if (slice == 0) { 319 LOCAL_HUB_S(PI_INT_MASK0_A, mask[0]); 320 LOCAL_HUB_S(PI_INT_MASK1_A, mask[1]); 321 } else { 322 LOCAL_HUB_S(PI_INT_MASK0_B, mask[0]); 323 LOCAL_HUB_S(PI_INT_MASK1_B, mask[1]); 324 } 325 } 326 327 void __init arch_init_irq(void) 328 { 329 mips_cpu_irq_init(); 330 ip27_hub_irq_init(); 331 332 irq_set_percpu_devid(IP27_HUB_PEND0_IRQ); 333 irq_set_chained_handler(IP27_HUB_PEND0_IRQ, ip27_do_irq_mask0); 334 irq_set_percpu_devid(IP27_HUB_PEND1_IRQ); 335 irq_set_chained_handler(IP27_HUB_PEND1_IRQ, ip27_do_irq_mask1); 336 } 337