1 /* 2 * ip27-irq.c: Highlevel interrupt handling for IP27 architecture. 3 * 4 * Copyright (C) 1999, 2000 Ralf Baechle (ralf@gnu.org) 5 * Copyright (C) 1999, 2000 Silicon Graphics, Inc. 6 * Copyright (C) 1999 - 2001 Kanoj Sarcar 7 */ 8 9 #undef DEBUG 10 11 #include <linux/init.h> 12 #include <linux/irq.h> 13 #include <linux/errno.h> 14 #include <linux/signal.h> 15 #include <linux/sched.h> 16 #include <linux/types.h> 17 #include <linux/interrupt.h> 18 #include <linux/ioport.h> 19 #include <linux/timex.h> 20 #include <linux/smp.h> 21 #include <linux/random.h> 22 #include <linux/kernel.h> 23 #include <linux/kernel_stat.h> 24 #include <linux/delay.h> 25 #include <linux/bitops.h> 26 27 #include <asm/bootinfo.h> 28 #include <asm/io.h> 29 #include <asm/mipsregs.h> 30 #include <asm/system.h> 31 32 #include <asm/processor.h> 33 #include <asm/pci/bridge.h> 34 #include <asm/sn/addrs.h> 35 #include <asm/sn/agent.h> 36 #include <asm/sn/arch.h> 37 #include <asm/sn/hub.h> 38 #include <asm/sn/intr.h> 39 40 /* 41 * Linux has a controller-independent x86 interrupt architecture. 42 * every controller has a 'controller-template', that is used 43 * by the main code to do the right thing. Each driver-visible 44 * interrupt source is transparently wired to the appropriate 45 * controller. Thus drivers need not be aware of the 46 * interrupt-controller. 47 * 48 * Various interrupt controllers we handle: 8259 PIC, SMP IO-APIC, 49 * PIIX4's internal 8259 PIC and SGI's Visual Workstation Cobalt (IO-)APIC. 50 * (IO-APICs assumed to be messaging to Pentium local-APICs) 51 * 52 * the code is designed to be easily extended with new/different 53 * interrupt controllers, without having to do assembly magic. 54 */ 55 56 extern asmlinkage void ip27_irq(void); 57 58 extern struct bridge_controller *irq_to_bridge[]; 59 extern int irq_to_slot[]; 60 61 /* 62 * use these macros to get the encoded nasid and widget id 63 * from the irq value 64 */ 65 #define IRQ_TO_BRIDGE(i) irq_to_bridge[(i)] 66 #define SLOT_FROM_PCI_IRQ(i) irq_to_slot[i] 67 68 static inline int alloc_level(int cpu, int irq) 69 { 70 struct hub_data *hub = hub_data(cpu_to_node(cpu)); 71 struct slice_data *si = cpu_data[cpu].data; 72 int level; 73 74 level = find_first_zero_bit(hub->irq_alloc_mask, LEVELS_PER_SLICE); 75 if (level >= LEVELS_PER_SLICE) 76 panic("Cpu %d flooded with devices", cpu); 77 78 __set_bit(level, hub->irq_alloc_mask); 79 si->level_to_irq[level] = irq; 80 81 return level; 82 } 83 84 static inline int find_level(cpuid_t *cpunum, int irq) 85 { 86 int cpu, i; 87 88 for_each_online_cpu(cpu) { 89 struct slice_data *si = cpu_data[cpu].data; 90 91 for (i = BASE_PCI_IRQ; i < LEVELS_PER_SLICE; i++) 92 if (si->level_to_irq[i] == irq) { 93 *cpunum = cpu; 94 95 return i; 96 } 97 } 98 99 panic("Could not identify cpu/level for irq %d", irq); 100 } 101 102 /* 103 * Find first bit set 104 */ 105 static int ms1bit(unsigned long x) 106 { 107 int b = 0, s; 108 109 s = 16; if (x >> 16 == 0) s = 0; b += s; x >>= s; 110 s = 8; if (x >> 8 == 0) s = 0; b += s; x >>= s; 111 s = 4; if (x >> 4 == 0) s = 0; b += s; x >>= s; 112 s = 2; if (x >> 2 == 0) s = 0; b += s; x >>= s; 113 s = 1; if (x >> 1 == 0) s = 0; b += s; 114 115 return b; 116 } 117 118 /* 119 * This code is unnecessarily complex, because we do 120 * intr enabling. Basically, once we grab the set of intrs we need 121 * to service, we must mask _all_ these interrupts; firstly, to make 122 * sure the same intr does not intr again, causing recursion that 123 * can lead to stack overflow. Secondly, we can not just mask the 124 * one intr we are do_IRQing, because the non-masked intrs in the 125 * first set might intr again, causing multiple servicings of the 126 * same intr. This effect is mostly seen for intercpu intrs. 127 * Kanoj 05.13.00 128 */ 129 130 static void ip27_do_irq_mask0(void) 131 { 132 int irq, swlevel; 133 hubreg_t pend0, mask0; 134 cpuid_t cpu = smp_processor_id(); 135 int pi_int_mask0 = 136 (cputoslice(cpu) == 0) ? PI_INT_MASK0_A : PI_INT_MASK0_B; 137 138 /* copied from Irix intpend0() */ 139 pend0 = LOCAL_HUB_L(PI_INT_PEND0); 140 mask0 = LOCAL_HUB_L(pi_int_mask0); 141 142 pend0 &= mask0; /* Pick intrs we should look at */ 143 if (!pend0) 144 return; 145 146 swlevel = ms1bit(pend0); 147 #ifdef CONFIG_SMP 148 if (pend0 & (1UL << CPU_RESCHED_A_IRQ)) { 149 LOCAL_HUB_CLR_INTR(CPU_RESCHED_A_IRQ); 150 scheduler_ipi(); 151 } else if (pend0 & (1UL << CPU_RESCHED_B_IRQ)) { 152 LOCAL_HUB_CLR_INTR(CPU_RESCHED_B_IRQ); 153 scheduler_ipi(); 154 } else if (pend0 & (1UL << CPU_CALL_A_IRQ)) { 155 LOCAL_HUB_CLR_INTR(CPU_CALL_A_IRQ); 156 smp_call_function_interrupt(); 157 } else if (pend0 & (1UL << CPU_CALL_B_IRQ)) { 158 LOCAL_HUB_CLR_INTR(CPU_CALL_B_IRQ); 159 smp_call_function_interrupt(); 160 } else 161 #endif 162 { 163 /* "map" swlevel to irq */ 164 struct slice_data *si = cpu_data[cpu].data; 165 166 irq = si->level_to_irq[swlevel]; 167 do_IRQ(irq); 168 } 169 170 LOCAL_HUB_L(PI_INT_PEND0); 171 } 172 173 static void ip27_do_irq_mask1(void) 174 { 175 int irq, swlevel; 176 hubreg_t pend1, mask1; 177 cpuid_t cpu = smp_processor_id(); 178 int pi_int_mask1 = (cputoslice(cpu) == 0) ? PI_INT_MASK1_A : PI_INT_MASK1_B; 179 struct slice_data *si = cpu_data[cpu].data; 180 181 /* copied from Irix intpend0() */ 182 pend1 = LOCAL_HUB_L(PI_INT_PEND1); 183 mask1 = LOCAL_HUB_L(pi_int_mask1); 184 185 pend1 &= mask1; /* Pick intrs we should look at */ 186 if (!pend1) 187 return; 188 189 swlevel = ms1bit(pend1); 190 /* "map" swlevel to irq */ 191 irq = si->level_to_irq[swlevel]; 192 LOCAL_HUB_CLR_INTR(swlevel); 193 do_IRQ(irq); 194 195 LOCAL_HUB_L(PI_INT_PEND1); 196 } 197 198 static void ip27_prof_timer(void) 199 { 200 panic("CPU %d got a profiling interrupt", smp_processor_id()); 201 } 202 203 static void ip27_hub_error(void) 204 { 205 panic("CPU %d got a hub error interrupt", smp_processor_id()); 206 } 207 208 static int intr_connect_level(int cpu, int bit) 209 { 210 nasid_t nasid = COMPACT_TO_NASID_NODEID(cpu_to_node(cpu)); 211 struct slice_data *si = cpu_data[cpu].data; 212 213 set_bit(bit, si->irq_enable_mask); 214 215 if (!cputoslice(cpu)) { 216 REMOTE_HUB_S(nasid, PI_INT_MASK0_A, si->irq_enable_mask[0]); 217 REMOTE_HUB_S(nasid, PI_INT_MASK1_A, si->irq_enable_mask[1]); 218 } else { 219 REMOTE_HUB_S(nasid, PI_INT_MASK0_B, si->irq_enable_mask[0]); 220 REMOTE_HUB_S(nasid, PI_INT_MASK1_B, si->irq_enable_mask[1]); 221 } 222 223 return 0; 224 } 225 226 static int intr_disconnect_level(int cpu, int bit) 227 { 228 nasid_t nasid = COMPACT_TO_NASID_NODEID(cpu_to_node(cpu)); 229 struct slice_data *si = cpu_data[cpu].data; 230 231 clear_bit(bit, si->irq_enable_mask); 232 233 if (!cputoslice(cpu)) { 234 REMOTE_HUB_S(nasid, PI_INT_MASK0_A, si->irq_enable_mask[0]); 235 REMOTE_HUB_S(nasid, PI_INT_MASK1_A, si->irq_enable_mask[1]); 236 } else { 237 REMOTE_HUB_S(nasid, PI_INT_MASK0_B, si->irq_enable_mask[0]); 238 REMOTE_HUB_S(nasid, PI_INT_MASK1_B, si->irq_enable_mask[1]); 239 } 240 241 return 0; 242 } 243 244 /* Startup one of the (PCI ...) IRQs routes over a bridge. */ 245 static unsigned int startup_bridge_irq(struct irq_data *d) 246 { 247 struct bridge_controller *bc; 248 bridgereg_t device; 249 bridge_t *bridge; 250 int pin, swlevel; 251 cpuid_t cpu; 252 253 pin = SLOT_FROM_PCI_IRQ(d->irq); 254 bc = IRQ_TO_BRIDGE(d->irq); 255 bridge = bc->base; 256 257 pr_debug("bridge_startup(): irq= 0x%x pin=%d\n", d->irq, pin); 258 /* 259 * "map" irq to a swlevel greater than 6 since the first 6 bits 260 * of INT_PEND0 are taken 261 */ 262 swlevel = find_level(&cpu, d->irq); 263 bridge->b_int_addr[pin].addr = (0x20000 | swlevel | (bc->nasid << 8)); 264 bridge->b_int_enable |= (1 << pin); 265 bridge->b_int_enable |= 0x7ffffe00; /* more stuff in int_enable */ 266 267 /* 268 * Enable sending of an interrupt clear packt to the hub on a high to 269 * low transition of the interrupt pin. 270 * 271 * IRIX sets additional bits in the address which are documented as 272 * reserved in the bridge docs. 273 */ 274 bridge->b_int_mode |= (1UL << pin); 275 276 /* 277 * We assume the bridge to have a 1:1 mapping between devices 278 * (slots) and intr pins. 279 */ 280 device = bridge->b_int_device; 281 device &= ~(7 << (pin*3)); 282 device |= (pin << (pin*3)); 283 bridge->b_int_device = device; 284 285 bridge->b_wid_tflush; 286 287 intr_connect_level(cpu, swlevel); 288 289 return 0; /* Never anything pending. */ 290 } 291 292 /* Shutdown one of the (PCI ...) IRQs routes over a bridge. */ 293 static void shutdown_bridge_irq(struct irq_data *d) 294 { 295 struct bridge_controller *bc = IRQ_TO_BRIDGE(d->irq); 296 bridge_t *bridge = bc->base; 297 int pin, swlevel; 298 cpuid_t cpu; 299 300 pr_debug("bridge_shutdown: irq 0x%x\n", d->irq); 301 pin = SLOT_FROM_PCI_IRQ(d->irq); 302 303 /* 304 * map irq to a swlevel greater than 6 since the first 6 bits 305 * of INT_PEND0 are taken 306 */ 307 swlevel = find_level(&cpu, d->irq); 308 intr_disconnect_level(cpu, swlevel); 309 310 bridge->b_int_enable &= ~(1 << pin); 311 bridge->b_wid_tflush; 312 } 313 314 static inline void enable_bridge_irq(struct irq_data *d) 315 { 316 cpuid_t cpu; 317 int swlevel; 318 319 swlevel = find_level(&cpu, d->irq); /* Criminal offence */ 320 intr_connect_level(cpu, swlevel); 321 } 322 323 static inline void disable_bridge_irq(struct irq_data *d) 324 { 325 cpuid_t cpu; 326 int swlevel; 327 328 swlevel = find_level(&cpu, d->irq); /* Criminal offence */ 329 intr_disconnect_level(cpu, swlevel); 330 } 331 332 static struct irq_chip bridge_irq_type = { 333 .name = "bridge", 334 .irq_startup = startup_bridge_irq, 335 .irq_shutdown = shutdown_bridge_irq, 336 .irq_mask = disable_bridge_irq, 337 .irq_unmask = enable_bridge_irq, 338 }; 339 340 void register_bridge_irq(unsigned int irq) 341 { 342 irq_set_chip_and_handler(irq, &bridge_irq_type, handle_level_irq); 343 } 344 345 int request_bridge_irq(struct bridge_controller *bc) 346 { 347 int irq = allocate_irqno(); 348 int swlevel, cpu; 349 nasid_t nasid; 350 351 if (irq < 0) 352 return irq; 353 354 /* 355 * "map" irq to a swlevel greater than 6 since the first 6 bits 356 * of INT_PEND0 are taken 357 */ 358 cpu = bc->irq_cpu; 359 swlevel = alloc_level(cpu, irq); 360 if (unlikely(swlevel < 0)) { 361 free_irqno(irq); 362 363 return -EAGAIN; 364 } 365 366 /* Make sure it's not already pending when we connect it. */ 367 nasid = COMPACT_TO_NASID_NODEID(cpu_to_node(cpu)); 368 REMOTE_HUB_CLR_INTR(nasid, swlevel); 369 370 intr_connect_level(cpu, swlevel); 371 372 register_bridge_irq(irq); 373 374 return irq; 375 } 376 377 asmlinkage void plat_irq_dispatch(void) 378 { 379 unsigned long pending = read_c0_cause() & read_c0_status(); 380 extern unsigned int rt_timer_irq; 381 382 if (pending & CAUSEF_IP4) 383 do_IRQ(rt_timer_irq); 384 else if (pending & CAUSEF_IP2) /* PI_INT_PEND_0 or CC_PEND_{A|B} */ 385 ip27_do_irq_mask0(); 386 else if (pending & CAUSEF_IP3) /* PI_INT_PEND_1 */ 387 ip27_do_irq_mask1(); 388 else if (pending & CAUSEF_IP5) 389 ip27_prof_timer(); 390 else if (pending & CAUSEF_IP6) 391 ip27_hub_error(); 392 } 393 394 void __init arch_init_irq(void) 395 { 396 } 397 398 void install_ipi(void) 399 { 400 int slice = LOCAL_HUB_L(PI_CPU_NUM); 401 int cpu = smp_processor_id(); 402 struct slice_data *si = cpu_data[cpu].data; 403 struct hub_data *hub = hub_data(cpu_to_node(cpu)); 404 int resched, call; 405 406 resched = CPU_RESCHED_A_IRQ + slice; 407 __set_bit(resched, hub->irq_alloc_mask); 408 __set_bit(resched, si->irq_enable_mask); 409 LOCAL_HUB_CLR_INTR(resched); 410 411 call = CPU_CALL_A_IRQ + slice; 412 __set_bit(call, hub->irq_alloc_mask); 413 __set_bit(call, si->irq_enable_mask); 414 LOCAL_HUB_CLR_INTR(call); 415 416 if (slice == 0) { 417 LOCAL_HUB_S(PI_INT_MASK0_A, si->irq_enable_mask[0]); 418 LOCAL_HUB_S(PI_INT_MASK1_A, si->irq_enable_mask[1]); 419 } else { 420 LOCAL_HUB_S(PI_INT_MASK0_B, si->irq_enable_mask[0]); 421 LOCAL_HUB_S(PI_INT_MASK1_B, si->irq_enable_mask[1]); 422 } 423 } 424