1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * ip27-irq.c: Highlevel interrupt handling for IP27 architecture. 4 * 5 * Copyright (C) 1999, 2000 Ralf Baechle (ralf@gnu.org) 6 * Copyright (C) 1999, 2000 Silicon Graphics, Inc. 7 * Copyright (C) 1999 - 2001 Kanoj Sarcar 8 */ 9 10 #include <linux/interrupt.h> 11 #include <linux/irq.h> 12 #include <linux/ioport.h> 13 #include <linux/kernel.h> 14 #include <linux/bitops.h> 15 16 #include <asm/io.h> 17 #include <asm/irq_cpu.h> 18 #include <asm/pci/bridge.h> 19 #include <asm/sn/addrs.h> 20 #include <asm/sn/agent.h> 21 #include <asm/sn/arch.h> 22 #include <asm/sn/hub.h> 23 #include <asm/sn/intr.h> 24 25 struct hub_irq_data { 26 struct bridge_controller *bc; 27 u64 *irq_mask[2]; 28 cpuid_t cpu; 29 int bit; 30 int pin; 31 }; 32 33 static DECLARE_BITMAP(hub_irq_map, IP27_HUB_IRQ_COUNT); 34 35 static DEFINE_PER_CPU(unsigned long [2], irq_enable_mask); 36 37 static inline int alloc_level(void) 38 { 39 int level; 40 41 again: 42 level = find_first_zero_bit(hub_irq_map, IP27_HUB_IRQ_COUNT); 43 if (level >= IP27_HUB_IRQ_COUNT) 44 return -ENOSPC; 45 46 if (test_and_set_bit(level, hub_irq_map)) 47 goto again; 48 49 return level; 50 } 51 52 static void enable_hub_irq(struct irq_data *d) 53 { 54 struct hub_irq_data *hd = irq_data_get_irq_chip_data(d); 55 unsigned long *mask = per_cpu(irq_enable_mask, hd->cpu); 56 57 set_bit(hd->bit, mask); 58 __raw_writeq(mask[0], hd->irq_mask[0]); 59 __raw_writeq(mask[1], hd->irq_mask[1]); 60 } 61 62 static void disable_hub_irq(struct irq_data *d) 63 { 64 struct hub_irq_data *hd = irq_data_get_irq_chip_data(d); 65 unsigned long *mask = per_cpu(irq_enable_mask, hd->cpu); 66 67 clear_bit(hd->bit, mask); 68 __raw_writeq(mask[0], hd->irq_mask[0]); 69 __raw_writeq(mask[1], hd->irq_mask[1]); 70 } 71 72 static unsigned int startup_bridge_irq(struct irq_data *d) 73 { 74 struct hub_irq_data *hd = irq_data_get_irq_chip_data(d); 75 struct bridge_controller *bc; 76 nasid_t nasid; 77 u32 device; 78 int pin; 79 80 if (!hd) 81 return -EINVAL; 82 83 pin = hd->pin; 84 bc = hd->bc; 85 86 nasid = COMPACT_TO_NASID_NODEID(cpu_to_node(hd->cpu)); 87 bridge_write(bc, b_int_addr[pin].addr, 88 (0x20000 | hd->bit | (nasid << 8))); 89 bridge_set(bc, b_int_enable, (1 << pin)); 90 bridge_set(bc, b_int_enable, 0x7ffffe00); /* more stuff in int_enable */ 91 92 /* 93 * Enable sending of an interrupt clear packt to the hub on a high to 94 * low transition of the interrupt pin. 95 * 96 * IRIX sets additional bits in the address which are documented as 97 * reserved in the bridge docs. 98 */ 99 bridge_set(bc, b_int_mode, (1UL << pin)); 100 101 /* 102 * We assume the bridge to have a 1:1 mapping between devices 103 * (slots) and intr pins. 104 */ 105 device = bridge_read(bc, b_int_device); 106 device &= ~(7 << (pin*3)); 107 device |= (pin << (pin*3)); 108 bridge_write(bc, b_int_device, device); 109 110 bridge_read(bc, b_wid_tflush); 111 112 enable_hub_irq(d); 113 114 return 0; /* Never anything pending. */ 115 } 116 117 static void shutdown_bridge_irq(struct irq_data *d) 118 { 119 struct hub_irq_data *hd = irq_data_get_irq_chip_data(d); 120 struct bridge_controller *bc; 121 122 if (!hd) 123 return; 124 125 disable_hub_irq(d); 126 127 bc = hd->bc; 128 bridge_clr(bc, b_int_enable, (1 << hd->pin)); 129 bridge_read(bc, b_wid_tflush); 130 } 131 132 static void setup_hub_mask(struct hub_irq_data *hd, const struct cpumask *mask) 133 { 134 nasid_t nasid; 135 int cpu; 136 137 cpu = cpumask_first_and(mask, cpu_online_mask); 138 nasid = COMPACT_TO_NASID_NODEID(cpu_to_node(cpu)); 139 hd->cpu = cpu; 140 if (!cputoslice(cpu)) { 141 hd->irq_mask[0] = REMOTE_HUB_PTR(nasid, PI_INT_MASK0_A); 142 hd->irq_mask[1] = REMOTE_HUB_PTR(nasid, PI_INT_MASK1_A); 143 } else { 144 hd->irq_mask[0] = REMOTE_HUB_PTR(nasid, PI_INT_MASK0_B); 145 hd->irq_mask[1] = REMOTE_HUB_PTR(nasid, PI_INT_MASK1_B); 146 } 147 148 /* Make sure it's not already pending when we connect it. */ 149 REMOTE_HUB_CLR_INTR(nasid, hd->bit); 150 } 151 152 static int set_affinity_hub_irq(struct irq_data *d, const struct cpumask *mask, 153 bool force) 154 { 155 struct hub_irq_data *hd = irq_data_get_irq_chip_data(d); 156 157 if (!hd) 158 return -EINVAL; 159 160 if (irqd_is_started(d)) 161 disable_hub_irq(d); 162 163 setup_hub_mask(hd, mask); 164 165 if (irqd_is_started(d)) 166 startup_bridge_irq(d); 167 168 irq_data_update_effective_affinity(d, cpumask_of(hd->cpu)); 169 170 return 0; 171 } 172 173 static struct irq_chip hub_irq_type = { 174 .name = "HUB", 175 .irq_startup = startup_bridge_irq, 176 .irq_shutdown = shutdown_bridge_irq, 177 .irq_mask = disable_hub_irq, 178 .irq_unmask = enable_hub_irq, 179 .irq_set_affinity = set_affinity_hub_irq, 180 }; 181 182 int request_bridge_irq(struct bridge_controller *bc, int pin) 183 { 184 struct hub_irq_data *hd; 185 struct hub_data *hub; 186 struct irq_desc *desc; 187 int swlevel; 188 int irq; 189 190 hd = kzalloc(sizeof(*hd), GFP_KERNEL); 191 if (!hd) 192 return -ENOMEM; 193 194 swlevel = alloc_level(); 195 if (unlikely(swlevel < 0)) { 196 kfree(hd); 197 return -EAGAIN; 198 } 199 irq = swlevel + IP27_HUB_IRQ_BASE; 200 201 hd->bc = bc; 202 hd->bit = swlevel; 203 hd->pin = pin; 204 irq_set_chip_data(irq, hd); 205 206 /* use CPU connected to nearest hub */ 207 hub = hub_data(NASID_TO_COMPACT_NODEID(bc->nasid)); 208 setup_hub_mask(hd, &hub->h_cpus); 209 210 desc = irq_to_desc(irq); 211 desc->irq_common_data.node = bc->nasid; 212 cpumask_copy(desc->irq_common_data.affinity, &hub->h_cpus); 213 214 return irq; 215 } 216 217 void ip27_hub_irq_init(void) 218 { 219 int i; 220 221 for (i = IP27_HUB_IRQ_BASE; 222 i < (IP27_HUB_IRQ_BASE + IP27_HUB_IRQ_COUNT); i++) 223 irq_set_chip_and_handler(i, &hub_irq_type, handle_level_irq); 224 225 /* 226 * Some interrupts are reserved by hardware or by software convention. 227 * Mark these as reserved right away so they won't be used accidentally 228 * later. 229 */ 230 for (i = 0; i <= BASE_PCI_IRQ; i++) 231 set_bit(i, hub_irq_map); 232 233 set_bit(IP_PEND0_6_63, hub_irq_map); 234 235 for (i = NI_BRDCAST_ERR_A; i <= MSC_PANIC_INTR; i++) 236 set_bit(i, hub_irq_map); 237 } 238 239 /* 240 * This code is unnecessarily complex, because we do 241 * intr enabling. Basically, once we grab the set of intrs we need 242 * to service, we must mask _all_ these interrupts; firstly, to make 243 * sure the same intr does not intr again, causing recursion that 244 * can lead to stack overflow. Secondly, we can not just mask the 245 * one intr we are do_IRQing, because the non-masked intrs in the 246 * first set might intr again, causing multiple servicings of the 247 * same intr. This effect is mostly seen for intercpu intrs. 248 * Kanoj 05.13.00 249 */ 250 251 static void ip27_do_irq_mask0(struct irq_desc *desc) 252 { 253 cpuid_t cpu = smp_processor_id(); 254 unsigned long *mask = per_cpu(irq_enable_mask, cpu); 255 u64 pend0; 256 257 /* copied from Irix intpend0() */ 258 pend0 = LOCAL_HUB_L(PI_INT_PEND0); 259 260 pend0 &= mask[0]; /* Pick intrs we should look at */ 261 if (!pend0) 262 return; 263 264 #ifdef CONFIG_SMP 265 if (pend0 & (1UL << CPU_RESCHED_A_IRQ)) { 266 LOCAL_HUB_CLR_INTR(CPU_RESCHED_A_IRQ); 267 scheduler_ipi(); 268 } else if (pend0 & (1UL << CPU_RESCHED_B_IRQ)) { 269 LOCAL_HUB_CLR_INTR(CPU_RESCHED_B_IRQ); 270 scheduler_ipi(); 271 } else if (pend0 & (1UL << CPU_CALL_A_IRQ)) { 272 LOCAL_HUB_CLR_INTR(CPU_CALL_A_IRQ); 273 generic_smp_call_function_interrupt(); 274 } else if (pend0 & (1UL << CPU_CALL_B_IRQ)) { 275 LOCAL_HUB_CLR_INTR(CPU_CALL_B_IRQ); 276 generic_smp_call_function_interrupt(); 277 } else 278 #endif 279 generic_handle_irq(__ffs(pend0) + IP27_HUB_IRQ_BASE); 280 281 LOCAL_HUB_L(PI_INT_PEND0); 282 } 283 284 static void ip27_do_irq_mask1(struct irq_desc *desc) 285 { 286 cpuid_t cpu = smp_processor_id(); 287 unsigned long *mask = per_cpu(irq_enable_mask, cpu); 288 u64 pend1; 289 290 /* copied from Irix intpend0() */ 291 pend1 = LOCAL_HUB_L(PI_INT_PEND1); 292 293 pend1 &= mask[1]; /* Pick intrs we should look at */ 294 if (!pend1) 295 return; 296 297 generic_handle_irq(__ffs(pend1) + IP27_HUB_IRQ_BASE + 64); 298 299 LOCAL_HUB_L(PI_INT_PEND1); 300 } 301 302 void install_ipi(void) 303 { 304 int cpu = smp_processor_id(); 305 unsigned long *mask = per_cpu(irq_enable_mask, cpu); 306 int slice = LOCAL_HUB_L(PI_CPU_NUM); 307 int resched, call; 308 309 resched = CPU_RESCHED_A_IRQ + slice; 310 set_bit(resched, mask); 311 LOCAL_HUB_CLR_INTR(resched); 312 313 call = CPU_CALL_A_IRQ + slice; 314 set_bit(call, mask); 315 LOCAL_HUB_CLR_INTR(call); 316 317 if (slice == 0) { 318 LOCAL_HUB_S(PI_INT_MASK0_A, mask[0]); 319 LOCAL_HUB_S(PI_INT_MASK1_A, mask[1]); 320 } else { 321 LOCAL_HUB_S(PI_INT_MASK0_B, mask[0]); 322 LOCAL_HUB_S(PI_INT_MASK1_B, mask[1]); 323 } 324 } 325 326 void __init arch_init_irq(void) 327 { 328 mips_cpu_irq_init(); 329 ip27_hub_irq_init(); 330 331 irq_set_percpu_devid(IP27_HUB_PEND0_IRQ); 332 irq_set_chained_handler(IP27_HUB_PEND0_IRQ, ip27_do_irq_mask0); 333 irq_set_percpu_devid(IP27_HUB_PEND1_IRQ); 334 irq_set_chained_handler(IP27_HUB_PEND1_IRQ, ip27_do_irq_mask1); 335 } 336