1 /* 2 * Miscellaneous functions for IDT EB434 board 3 * 4 * Copyright 2004 IDT Inc. (rischelp@idt.com) 5 * Copyright 2006 Phil Sutter <n0-1@freewrt.org> 6 * Copyright 2007 Florian Fainelli <florian@openwrt.org> 7 * 8 * This program is free software; you can redistribute it and/or modify it 9 * under the terms of the GNU General Public License as published by the 10 * Free Software Foundation; either version 2 of the License, or (at your 11 * option) any later version. 12 * 13 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED 14 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 15 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN 16 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 17 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 18 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF 19 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON 20 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 21 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 22 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 23 * 24 * You should have received a copy of the GNU General Public License along 25 * with this program; if not, write to the Free Software Foundation, Inc., 26 * 675 Mass Ave, Cambridge, MA 02139, USA. 27 */ 28 29 #include <linux/kernel.h> 30 #include <linux/init.h> 31 #include <linux/types.h> 32 #include <linux/spinlock.h> 33 #include <linux/platform_device.h> 34 #include <linux/gpio.h> 35 36 #include <asm/mach-rc32434/rb.h> 37 #include <asm/mach-rc32434/gpio.h> 38 39 struct rb532_gpio_chip { 40 struct gpio_chip chip; 41 void __iomem *regbase; 42 }; 43 44 struct mpmc_device dev3; 45 46 static struct resource rb532_gpio_reg0_res[] = { 47 { 48 .name = "gpio_reg0", 49 .start = REGBASE + GPIOBASE, 50 .end = REGBASE + GPIOBASE + sizeof(struct rb532_gpio_reg) - 1, 51 .flags = IORESOURCE_MEM, 52 } 53 }; 54 55 static struct resource rb532_dev3_ctl_res[] = { 56 { 57 .name = "dev3_ctl", 58 .start = REGBASE + DEV3BASE, 59 .end = REGBASE + DEV3BASE + sizeof(struct dev_reg) - 1, 60 .flags = IORESOURCE_MEM, 61 } 62 }; 63 64 void set_434_reg(unsigned reg_offs, unsigned bit, unsigned len, unsigned val) 65 { 66 unsigned long flags; 67 unsigned data; 68 unsigned i = 0; 69 70 spin_lock_irqsave(&dev3.lock, flags); 71 72 data = readl(IDT434_REG_BASE + reg_offs); 73 for (i = 0; i != len; ++i) { 74 if (val & (1 << i)) 75 data |= (1 << (i + bit)); 76 else 77 data &= ~(1 << (i + bit)); 78 } 79 writel(data, (IDT434_REG_BASE + reg_offs)); 80 81 spin_unlock_irqrestore(&dev3.lock, flags); 82 } 83 EXPORT_SYMBOL(set_434_reg); 84 85 unsigned get_434_reg(unsigned reg_offs) 86 { 87 return readl(IDT434_REG_BASE + reg_offs); 88 } 89 EXPORT_SYMBOL(get_434_reg); 90 91 void set_latch_u5(unsigned char or_mask, unsigned char nand_mask) 92 { 93 unsigned long flags; 94 95 spin_lock_irqsave(&dev3.lock, flags); 96 97 dev3.state = (dev3.state | or_mask) & ~nand_mask; 98 writel(dev3.state, &dev3.base); 99 100 spin_unlock_irqrestore(&dev3.lock, flags); 101 } 102 EXPORT_SYMBOL(set_latch_u5); 103 104 unsigned char get_latch_u5(void) 105 { 106 return dev3.state; 107 } 108 EXPORT_SYMBOL(get_latch_u5); 109 110 /* rb532_set_bit - sanely set a bit 111 * 112 * bitval: new value for the bit 113 * offset: bit index in the 4 byte address range 114 * ioaddr: 4 byte aligned address being altered 115 */ 116 static inline void rb532_set_bit(unsigned bitval, 117 unsigned offset, void __iomem *ioaddr) 118 { 119 unsigned long flags; 120 u32 val; 121 122 bitval = !!bitval; /* map parameter to {0,1} */ 123 124 local_irq_save(flags); 125 126 val = readl(ioaddr); 127 val &= ~( ~bitval << offset ); /* unset bit if bitval == 0 */ 128 val |= ( bitval << offset ); /* set bit if bitval == 1 */ 129 writel(val, ioaddr); 130 131 local_irq_restore(flags); 132 } 133 134 /* rb532_get_bit - read a bit 135 * 136 * returns the boolean state of the bit, which may be > 1 137 */ 138 static inline int rb532_get_bit(unsigned offset, void __iomem *ioaddr) 139 { 140 return (readl(ioaddr) & (1 << offset)); 141 } 142 143 /* 144 * Return GPIO level */ 145 static int rb532_gpio_get(struct gpio_chip *chip, unsigned offset) 146 { 147 struct rb532_gpio_chip *gpch; 148 149 gpch = container_of(chip, struct rb532_gpio_chip, chip); 150 return rb532_get_bit(offset, gpch->regbase + GPIOD); 151 } 152 153 /* 154 * Set output GPIO level 155 */ 156 static void rb532_gpio_set(struct gpio_chip *chip, 157 unsigned offset, int value) 158 { 159 struct rb532_gpio_chip *gpch; 160 161 gpch = container_of(chip, struct rb532_gpio_chip, chip); 162 rb532_set_bit(value, offset, gpch->regbase + GPIOD); 163 } 164 165 /* 166 * Set GPIO direction to input 167 */ 168 static int rb532_gpio_direction_input(struct gpio_chip *chip, unsigned offset) 169 { 170 struct rb532_gpio_chip *gpch; 171 172 gpch = container_of(chip, struct rb532_gpio_chip, chip); 173 174 if (rb532_get_bit(offset, gpch->regbase + GPIOFUNC)) 175 return 1; /* alternate function, GPIOCFG is ignored */ 176 177 rb532_set_bit(0, offset, gpch->regbase + GPIOCFG); 178 return 0; 179 } 180 181 /* 182 * Set GPIO direction to output 183 */ 184 static int rb532_gpio_direction_output(struct gpio_chip *chip, 185 unsigned offset, int value) 186 { 187 struct rb532_gpio_chip *gpch; 188 189 gpch = container_of(chip, struct rb532_gpio_chip, chip); 190 191 if (rb532_get_bit(offset, gpch->regbase + GPIOFUNC)) 192 return 1; /* alternate function, GPIOCFG is ignored */ 193 194 /* set the initial output value */ 195 rb532_set_bit(value, offset, gpch->regbase + GPIOD); 196 197 rb532_set_bit(1, offset, gpch->regbase + GPIOCFG); 198 return 0; 199 } 200 201 static struct rb532_gpio_chip rb532_gpio_chip[] = { 202 [0] = { 203 .chip = { 204 .label = "gpio0", 205 .direction_input = rb532_gpio_direction_input, 206 .direction_output = rb532_gpio_direction_output, 207 .get = rb532_gpio_get, 208 .set = rb532_gpio_set, 209 .base = 0, 210 .ngpio = 32, 211 }, 212 }, 213 }; 214 215 /* 216 * Set GPIO interrupt level 217 */ 218 void rb532_gpio_set_ilevel(int bit, unsigned gpio) 219 { 220 rb532_set_bit(bit, gpio, rb532_gpio_chip->regbase + GPIOILEVEL); 221 } 222 EXPORT_SYMBOL(rb532_gpio_set_ilevel); 223 224 /* 225 * Set GPIO interrupt status 226 */ 227 void rb532_gpio_set_istat(int bit, unsigned gpio) 228 { 229 rb532_set_bit(bit, gpio, rb532_gpio_chip->regbase + GPIOISTAT); 230 } 231 EXPORT_SYMBOL(rb532_gpio_set_istat); 232 233 /* 234 * Configure GPIO alternate function 235 */ 236 static void rb532_gpio_set_func(int bit, unsigned gpio) 237 { 238 rb532_set_bit(bit, gpio, rb532_gpio_chip->regbase + GPIOFUNC); 239 } 240 241 int __init rb532_gpio_init(void) 242 { 243 struct resource *r; 244 245 r = rb532_gpio_reg0_res; 246 rb532_gpio_chip->regbase = ioremap_nocache(r->start, r->end - r->start); 247 248 if (!rb532_gpio_chip->regbase) { 249 printk(KERN_ERR "rb532: cannot remap GPIO register 0\n"); 250 return -ENXIO; 251 } 252 253 /* Register our GPIO chip */ 254 gpiochip_add(&rb532_gpio_chip->chip); 255 256 r = rb532_dev3_ctl_res; 257 dev3.base = ioremap_nocache(r->start, r->end - r->start); 258 259 if (!dev3.base) { 260 printk(KERN_ERR "rb532: cannot remap device controller 3\n"); 261 return -ENXIO; 262 } 263 264 /* configure CF_GPIO_NUM as CFRDY IRQ source */ 265 rb532_gpio_set_func(0, CF_GPIO_NUM); 266 rb532_gpio_direction_input(&rb532_gpio_chip->chip, CF_GPIO_NUM); 267 rb532_gpio_set_ilevel(1, CF_GPIO_NUM); 268 rb532_gpio_set_istat(0, CF_GPIO_NUM); 269 270 return 0; 271 } 272 arch_initcall(rb532_gpio_init); 273