1 /* 2 * This program is free software; you can redistribute it and/or modify it 3 * under the terms of the GNU General Public License version 2 as published 4 * by the Free Software Foundation. 5 * 6 * Parts of this file are based on Ralink's 2.6.21 BSP 7 * 8 * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org> 9 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org> 10 * Copyright (C) 2013 John Crispin <john@phrozen.org> 11 */ 12 13 #include <linux/kernel.h> 14 #include <linux/init.h> 15 #include <linux/bug.h> 16 17 #include <asm/io.h> 18 #include <asm/mipsregs.h> 19 #include <asm/mach-ralink/ralink_regs.h> 20 #include <asm/mach-ralink/rt305x.h> 21 #include <asm/mach-ralink/pinmux.h> 22 23 #include "common.h" 24 25 static struct rt2880_pmx_func i2c_func[] = { FUNC("i2c", 0, 1, 2) }; 26 static struct rt2880_pmx_func spi_func[] = { FUNC("spi", 0, 3, 4) }; 27 static struct rt2880_pmx_func uartf_func[] = { 28 FUNC("uartf", RT305X_GPIO_MODE_UARTF, 7, 8), 29 FUNC("pcm uartf", RT305X_GPIO_MODE_PCM_UARTF, 7, 8), 30 FUNC("pcm i2s", RT305X_GPIO_MODE_PCM_I2S, 7, 8), 31 FUNC("i2s uartf", RT305X_GPIO_MODE_I2S_UARTF, 7, 8), 32 FUNC("pcm gpio", RT305X_GPIO_MODE_PCM_GPIO, 11, 4), 33 FUNC("gpio uartf", RT305X_GPIO_MODE_GPIO_UARTF, 7, 4), 34 FUNC("gpio i2s", RT305X_GPIO_MODE_GPIO_I2S, 7, 4), 35 }; 36 static struct rt2880_pmx_func uartlite_func[] = { FUNC("uartlite", 0, 15, 2) }; 37 static struct rt2880_pmx_func jtag_func[] = { FUNC("jtag", 0, 17, 5) }; 38 static struct rt2880_pmx_func mdio_func[] = { FUNC("mdio", 0, 22, 2) }; 39 static struct rt2880_pmx_func rt5350_led_func[] = { FUNC("led", 0, 22, 5) }; 40 static struct rt2880_pmx_func rt5350_cs1_func[] = { 41 FUNC("spi_cs1", 0, 27, 1), 42 FUNC("wdg_cs1", 1, 27, 1), 43 }; 44 static struct rt2880_pmx_func sdram_func[] = { FUNC("sdram", 0, 24, 16) }; 45 static struct rt2880_pmx_func rt3352_rgmii_func[] = { 46 FUNC("rgmii", 0, 24, 12) 47 }; 48 static struct rt2880_pmx_func rgmii_func[] = { FUNC("rgmii", 0, 40, 12) }; 49 static struct rt2880_pmx_func rt3352_lna_func[] = { FUNC("lna", 0, 36, 2) }; 50 static struct rt2880_pmx_func rt3352_pa_func[] = { FUNC("pa", 0, 38, 2) }; 51 static struct rt2880_pmx_func rt3352_led_func[] = { FUNC("led", 0, 40, 5) }; 52 static struct rt2880_pmx_func rt3352_cs1_func[] = { 53 FUNC("spi_cs1", 0, 45, 1), 54 FUNC("wdg_cs1", 1, 45, 1), 55 }; 56 57 static struct rt2880_pmx_group rt3050_pinmux_data[] = { 58 GRP("i2c", i2c_func, 1, RT305X_GPIO_MODE_I2C), 59 GRP("spi", spi_func, 1, RT305X_GPIO_MODE_SPI), 60 GRP("uartf", uartf_func, RT305X_GPIO_MODE_UART0_MASK, 61 RT305X_GPIO_MODE_UART0_SHIFT), 62 GRP("uartlite", uartlite_func, 1, RT305X_GPIO_MODE_UART1), 63 GRP("jtag", jtag_func, 1, RT305X_GPIO_MODE_JTAG), 64 GRP("mdio", mdio_func, 1, RT305X_GPIO_MODE_MDIO), 65 GRP("rgmii", rgmii_func, 1, RT305X_GPIO_MODE_RGMII), 66 GRP("sdram", sdram_func, 1, RT305X_GPIO_MODE_SDRAM), 67 { 0 } 68 }; 69 70 static struct rt2880_pmx_group rt3352_pinmux_data[] = { 71 GRP("i2c", i2c_func, 1, RT305X_GPIO_MODE_I2C), 72 GRP("spi", spi_func, 1, RT305X_GPIO_MODE_SPI), 73 GRP("uartf", uartf_func, RT305X_GPIO_MODE_UART0_MASK, 74 RT305X_GPIO_MODE_UART0_SHIFT), 75 GRP("uartlite", uartlite_func, 1, RT305X_GPIO_MODE_UART1), 76 GRP("jtag", jtag_func, 1, RT305X_GPIO_MODE_JTAG), 77 GRP("mdio", mdio_func, 1, RT305X_GPIO_MODE_MDIO), 78 GRP("rgmii", rt3352_rgmii_func, 1, RT305X_GPIO_MODE_RGMII), 79 GRP("lna", rt3352_lna_func, 1, RT3352_GPIO_MODE_LNA), 80 GRP("pa", rt3352_pa_func, 1, RT3352_GPIO_MODE_PA), 81 GRP("led", rt3352_led_func, 1, RT5350_GPIO_MODE_PHY_LED), 82 GRP("spi_cs1", rt3352_cs1_func, 2, RT5350_GPIO_MODE_SPI_CS1), 83 { 0 } 84 }; 85 86 static struct rt2880_pmx_group rt5350_pinmux_data[] = { 87 GRP("i2c", i2c_func, 1, RT305X_GPIO_MODE_I2C), 88 GRP("spi", spi_func, 1, RT305X_GPIO_MODE_SPI), 89 GRP("uartf", uartf_func, RT305X_GPIO_MODE_UART0_MASK, 90 RT305X_GPIO_MODE_UART0_SHIFT), 91 GRP("uartlite", uartlite_func, 1, RT305X_GPIO_MODE_UART1), 92 GRP("jtag", jtag_func, 1, RT305X_GPIO_MODE_JTAG), 93 GRP("led", rt5350_led_func, 1, RT5350_GPIO_MODE_PHY_LED), 94 GRP("spi_cs1", rt5350_cs1_func, 2, RT5350_GPIO_MODE_SPI_CS1), 95 { 0 } 96 }; 97 98 static unsigned long rt5350_get_mem_size(void) 99 { 100 void __iomem *sysc = (void __iomem *) KSEG1ADDR(RT305X_SYSC_BASE); 101 unsigned long ret; 102 u32 t; 103 104 t = __raw_readl(sysc + SYSC_REG_SYSTEM_CONFIG); 105 t = (t >> RT5350_SYSCFG0_DRAM_SIZE_SHIFT) & 106 RT5350_SYSCFG0_DRAM_SIZE_MASK; 107 108 switch (t) { 109 case RT5350_SYSCFG0_DRAM_SIZE_2M: 110 ret = 2; 111 break; 112 case RT5350_SYSCFG0_DRAM_SIZE_8M: 113 ret = 8; 114 break; 115 case RT5350_SYSCFG0_DRAM_SIZE_16M: 116 ret = 16; 117 break; 118 case RT5350_SYSCFG0_DRAM_SIZE_32M: 119 ret = 32; 120 break; 121 case RT5350_SYSCFG0_DRAM_SIZE_64M: 122 ret = 64; 123 break; 124 default: 125 panic("rt5350: invalid DRAM size: %u", t); 126 break; 127 } 128 129 return ret; 130 } 131 132 void __init ralink_clk_init(void) 133 { 134 unsigned long cpu_rate, sys_rate, wdt_rate, uart_rate; 135 unsigned long wmac_rate = 40000000; 136 137 u32 t = rt_sysc_r32(SYSC_REG_SYSTEM_CONFIG); 138 139 if (soc_is_rt305x() || soc_is_rt3350()) { 140 t = (t >> RT305X_SYSCFG_CPUCLK_SHIFT) & 141 RT305X_SYSCFG_CPUCLK_MASK; 142 switch (t) { 143 case RT305X_SYSCFG_CPUCLK_LOW: 144 cpu_rate = 320000000; 145 break; 146 case RT305X_SYSCFG_CPUCLK_HIGH: 147 cpu_rate = 384000000; 148 break; 149 } 150 sys_rate = uart_rate = wdt_rate = cpu_rate / 3; 151 } else if (soc_is_rt3352()) { 152 t = (t >> RT3352_SYSCFG0_CPUCLK_SHIFT) & 153 RT3352_SYSCFG0_CPUCLK_MASK; 154 switch (t) { 155 case RT3352_SYSCFG0_CPUCLK_LOW: 156 cpu_rate = 384000000; 157 break; 158 case RT3352_SYSCFG0_CPUCLK_HIGH: 159 cpu_rate = 400000000; 160 break; 161 } 162 sys_rate = wdt_rate = cpu_rate / 3; 163 uart_rate = 40000000; 164 } else if (soc_is_rt5350()) { 165 t = (t >> RT5350_SYSCFG0_CPUCLK_SHIFT) & 166 RT5350_SYSCFG0_CPUCLK_MASK; 167 switch (t) { 168 case RT5350_SYSCFG0_CPUCLK_360: 169 cpu_rate = 360000000; 170 sys_rate = cpu_rate / 3; 171 break; 172 case RT5350_SYSCFG0_CPUCLK_320: 173 cpu_rate = 320000000; 174 sys_rate = cpu_rate / 4; 175 break; 176 case RT5350_SYSCFG0_CPUCLK_300: 177 cpu_rate = 300000000; 178 sys_rate = cpu_rate / 3; 179 break; 180 default: 181 BUG(); 182 } 183 uart_rate = 40000000; 184 wdt_rate = sys_rate; 185 } else { 186 BUG(); 187 } 188 189 if (soc_is_rt3352() || soc_is_rt5350()) { 190 u32 val = rt_sysc_r32(RT3352_SYSC_REG_SYSCFG0); 191 192 if (!(val & RT3352_CLKCFG0_XTAL_SEL)) 193 wmac_rate = 20000000; 194 } 195 196 ralink_clk_add("cpu", cpu_rate); 197 ralink_clk_add("sys", sys_rate); 198 ralink_clk_add("10000900.i2c", uart_rate); 199 ralink_clk_add("10000a00.i2s", uart_rate); 200 ralink_clk_add("10000b00.spi", sys_rate); 201 ralink_clk_add("10000b40.spi", sys_rate); 202 ralink_clk_add("10000100.timer", wdt_rate); 203 ralink_clk_add("10000120.watchdog", wdt_rate); 204 ralink_clk_add("10000500.uart", uart_rate); 205 ralink_clk_add("10000c00.uartlite", uart_rate); 206 ralink_clk_add("10100000.ethernet", sys_rate); 207 ralink_clk_add("10180000.wmac", wmac_rate); 208 } 209 210 void __init ralink_of_remap(void) 211 { 212 rt_sysc_membase = plat_of_remap_node("ralink,rt3050-sysc"); 213 rt_memc_membase = plat_of_remap_node("ralink,rt3050-memc"); 214 215 if (!rt_sysc_membase || !rt_memc_membase) 216 panic("Failed to remap core resources"); 217 } 218 219 void prom_soc_init(struct ralink_soc_info *soc_info) 220 { 221 void __iomem *sysc = (void __iomem *) KSEG1ADDR(RT305X_SYSC_BASE); 222 unsigned char *name; 223 u32 n0; 224 u32 n1; 225 u32 id; 226 227 n0 = __raw_readl(sysc + SYSC_REG_CHIP_NAME0); 228 n1 = __raw_readl(sysc + SYSC_REG_CHIP_NAME1); 229 230 if (n0 == RT3052_CHIP_NAME0 && n1 == RT3052_CHIP_NAME1) { 231 unsigned long icache_sets; 232 233 icache_sets = (read_c0_config1() >> 22) & 7; 234 if (icache_sets == 1) { 235 ralink_soc = RT305X_SOC_RT3050; 236 name = "RT3050"; 237 soc_info->compatible = "ralink,rt3050-soc"; 238 } else { 239 ralink_soc = RT305X_SOC_RT3052; 240 name = "RT3052"; 241 soc_info->compatible = "ralink,rt3052-soc"; 242 } 243 } else if (n0 == RT3350_CHIP_NAME0 && n1 == RT3350_CHIP_NAME1) { 244 ralink_soc = RT305X_SOC_RT3350; 245 name = "RT3350"; 246 soc_info->compatible = "ralink,rt3350-soc"; 247 } else if (n0 == RT3352_CHIP_NAME0 && n1 == RT3352_CHIP_NAME1) { 248 ralink_soc = RT305X_SOC_RT3352; 249 name = "RT3352"; 250 soc_info->compatible = "ralink,rt3352-soc"; 251 } else if (n0 == RT5350_CHIP_NAME0 && n1 == RT5350_CHIP_NAME1) { 252 ralink_soc = RT305X_SOC_RT5350; 253 name = "RT5350"; 254 soc_info->compatible = "ralink,rt5350-soc"; 255 } else { 256 panic("rt305x: unknown SoC, n0:%08x n1:%08x", n0, n1); 257 } 258 259 id = __raw_readl(sysc + SYSC_REG_CHIP_ID); 260 261 snprintf(soc_info->sys_type, RAMIPS_SYS_TYPE_LEN, 262 "Ralink %s id:%u rev:%u", 263 name, 264 (id >> CHIP_ID_ID_SHIFT) & CHIP_ID_ID_MASK, 265 (id & CHIP_ID_REV_MASK)); 266 267 soc_info->mem_base = RT305X_SDRAM_BASE; 268 if (soc_is_rt5350()) { 269 soc_info->mem_size = rt5350_get_mem_size(); 270 rt2880_pinmux_data = rt5350_pinmux_data; 271 } else if (soc_is_rt305x() || soc_is_rt3350()) { 272 soc_info->mem_size_min = RT305X_MEM_SIZE_MIN; 273 soc_info->mem_size_max = RT305X_MEM_SIZE_MAX; 274 rt2880_pinmux_data = rt3050_pinmux_data; 275 } else if (soc_is_rt3352()) { 276 soc_info->mem_size_min = RT3352_MEM_SIZE_MIN; 277 soc_info->mem_size_max = RT3352_MEM_SIZE_MAX; 278 rt2880_pinmux_data = rt3352_pinmux_data; 279 } 280 } 281