1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * 4 * Parts of this file are based on Ralink's 2.6.21 BSP 5 * 6 * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org> 7 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org> 8 * Copyright (C) 2013 John Crispin <john@phrozen.org> 9 */ 10 11 #include <linux/kernel.h> 12 #include <linux/init.h> 13 #include <linux/slab.h> 14 #include <linux/sys_soc.h> 15 16 #include <asm/mipsregs.h> 17 #include <asm/mach-ralink/ralink_regs.h> 18 #include <asm/mach-ralink/rt288x.h> 19 20 #include "common.h" 21 22 static struct ralink_soc_info *soc_info_ptr; 23 24 void __init ralink_clk_init(void) 25 { 26 unsigned long cpu_rate, wmac_rate = 40000000; 27 u32 t = rt_sysc_r32(SYSC_REG_SYSTEM_CONFIG); 28 t = ((t >> SYSTEM_CONFIG_CPUCLK_SHIFT) & SYSTEM_CONFIG_CPUCLK_MASK); 29 30 switch (t) { 31 case SYSTEM_CONFIG_CPUCLK_250: 32 cpu_rate = 250000000; 33 break; 34 case SYSTEM_CONFIG_CPUCLK_266: 35 cpu_rate = 266666667; 36 break; 37 case SYSTEM_CONFIG_CPUCLK_280: 38 cpu_rate = 280000000; 39 break; 40 case SYSTEM_CONFIG_CPUCLK_300: 41 cpu_rate = 300000000; 42 break; 43 } 44 45 ralink_clk_add("cpu", cpu_rate); 46 ralink_clk_add("300100.timer", cpu_rate / 2); 47 ralink_clk_add("300120.watchdog", cpu_rate / 2); 48 ralink_clk_add("300500.uart", cpu_rate / 2); 49 ralink_clk_add("300900.i2c", cpu_rate / 2); 50 ralink_clk_add("300c00.uartlite", cpu_rate / 2); 51 ralink_clk_add("400000.ethernet", cpu_rate / 2); 52 ralink_clk_add("480000.wmac", wmac_rate); 53 } 54 55 void __init ralink_of_remap(void) 56 { 57 rt_sysc_membase = plat_of_remap_node("ralink,rt2880-sysc"); 58 rt_memc_membase = plat_of_remap_node("ralink,rt2880-memc"); 59 60 if (!rt_sysc_membase || !rt_memc_membase) 61 panic("Failed to remap core resources"); 62 } 63 64 static unsigned int __init rt2880_get_soc_name0(void) 65 { 66 return __raw_readl(RT2880_SYSC_BASE + SYSC_REG_CHIP_NAME0); 67 } 68 69 static unsigned int __init rt2880_get_soc_name1(void) 70 { 71 return __raw_readl(RT2880_SYSC_BASE + SYSC_REG_CHIP_NAME1); 72 } 73 74 static bool __init rt2880_soc_valid(void) 75 { 76 if (rt2880_get_soc_name0() == RT2880_CHIP_NAME0 && 77 rt2880_get_soc_name1() == RT2880_CHIP_NAME1) 78 return true; 79 else 80 return false; 81 } 82 83 static const char __init *rt2880_get_soc_name(void) 84 { 85 if (rt2880_soc_valid()) 86 return "RT2880"; 87 else 88 return "invalid"; 89 } 90 91 static unsigned int __init rt2880_get_soc_id(void) 92 { 93 return __raw_readl(RT2880_SYSC_BASE + SYSC_REG_CHIP_ID); 94 } 95 96 static unsigned int __init rt2880_get_soc_ver(void) 97 { 98 return (rt2880_get_soc_id() >> CHIP_ID_ID_SHIFT) & CHIP_ID_ID_MASK; 99 } 100 101 static unsigned int __init rt2880_get_soc_rev(void) 102 { 103 return (rt2880_get_soc_id() & CHIP_ID_REV_MASK); 104 } 105 106 static int __init rt2880_soc_dev_init(void) 107 { 108 struct soc_device *soc_dev; 109 struct soc_device_attribute *soc_dev_attr; 110 111 soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL); 112 if (!soc_dev_attr) 113 return -ENOMEM; 114 115 soc_dev_attr->family = "Ralink"; 116 soc_dev_attr->soc_id = rt2880_get_soc_name(); 117 118 soc_dev_attr->data = soc_info_ptr; 119 120 soc_dev = soc_device_register(soc_dev_attr); 121 if (IS_ERR(soc_dev)) { 122 kfree(soc_dev_attr); 123 return PTR_ERR(soc_dev); 124 } 125 126 return 0; 127 } 128 device_initcall(rt2880_soc_dev_init); 129 130 void __init prom_soc_init(struct ralink_soc_info *soc_info) 131 { 132 if (rt2880_soc_valid()) 133 soc_info->compatible = "ralink,r2880-soc"; 134 else 135 panic("rt288x: unknown SoC, n0:%08x n1:%08x", 136 rt2880_get_soc_name0(), rt2880_get_soc_name1()); 137 138 snprintf(soc_info->sys_type, RAMIPS_SYS_TYPE_LEN, 139 "Ralink %s id:%u rev:%u", 140 rt2880_get_soc_name(), 141 rt2880_get_soc_ver(), 142 rt2880_get_soc_rev()); 143 144 soc_info->mem_base = RT2880_SDRAM_BASE; 145 soc_info->mem_size_min = RT2880_MEM_SIZE_MIN; 146 soc_info->mem_size_max = RT2880_MEM_SIZE_MAX; 147 148 ralink_soc = RT2880_SOC; 149 soc_info_ptr = soc_info; 150 } 151