1 /* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * Copyright (C) 2007, 2008 Cavium Networks 7 */ 8 #include <linux/kernel.h> 9 #include <linux/init.h> 10 #include <linux/pci.h> 11 #include <linux/interrupt.h> 12 #include <linux/time.h> 13 #include <linux/delay.h> 14 15 #include <asm/octeon/octeon.h> 16 #include <asm/octeon/cvmx-npei-defs.h> 17 #include <asm/octeon/cvmx-pciercx-defs.h> 18 #include <asm/octeon/cvmx-pescx-defs.h> 19 #include <asm/octeon/cvmx-pexp-defs.h> 20 #include <asm/octeon/cvmx-helper-errata.h> 21 #include <asm/octeon/pci-octeon.h> 22 23 union cvmx_pcie_address { 24 uint64_t u64; 25 struct { 26 uint64_t upper:2; /* Normally 2 for XKPHYS */ 27 uint64_t reserved_49_61:13; /* Must be zero */ 28 uint64_t io:1; /* 1 for IO space access */ 29 uint64_t did:5; /* PCIe DID = 3 */ 30 uint64_t subdid:3; /* PCIe SubDID = 1 */ 31 uint64_t reserved_36_39:4; /* Must be zero */ 32 uint64_t es:2; /* Endian swap = 1 */ 33 uint64_t port:2; /* PCIe port 0,1 */ 34 uint64_t reserved_29_31:3; /* Must be zero */ 35 /* 36 * Selects the type of the configuration request (0 = type 0, 37 * 1 = type 1). 38 */ 39 uint64_t ty:1; 40 /* Target bus number sent in the ID in the request. */ 41 uint64_t bus:8; 42 /* 43 * Target device number sent in the ID in the 44 * request. Note that Dev must be zero for type 0 45 * configuration requests. 46 */ 47 uint64_t dev:5; 48 /* Target function number sent in the ID in the request. */ 49 uint64_t func:3; 50 /* 51 * Selects a register in the configuration space of 52 * the target. 53 */ 54 uint64_t reg:12; 55 } config; 56 struct { 57 uint64_t upper:2; /* Normally 2 for XKPHYS */ 58 uint64_t reserved_49_61:13; /* Must be zero */ 59 uint64_t io:1; /* 1 for IO space access */ 60 uint64_t did:5; /* PCIe DID = 3 */ 61 uint64_t subdid:3; /* PCIe SubDID = 2 */ 62 uint64_t reserved_36_39:4; /* Must be zero */ 63 uint64_t es:2; /* Endian swap = 1 */ 64 uint64_t port:2; /* PCIe port 0,1 */ 65 uint64_t address:32; /* PCIe IO address */ 66 } io; 67 struct { 68 uint64_t upper:2; /* Normally 2 for XKPHYS */ 69 uint64_t reserved_49_61:13; /* Must be zero */ 70 uint64_t io:1; /* 1 for IO space access */ 71 uint64_t did:5; /* PCIe DID = 3 */ 72 uint64_t subdid:3; /* PCIe SubDID = 3-6 */ 73 uint64_t reserved_36_39:4; /* Must be zero */ 74 uint64_t address:36; /* PCIe Mem address */ 75 } mem; 76 }; 77 78 /** 79 * Return the Core virtual base address for PCIe IO access. IOs are 80 * read/written as an offset from this address. 81 * 82 * @pcie_port: PCIe port the IO is for 83 * 84 * Returns 64bit Octeon IO base address for read/write 85 */ 86 static inline uint64_t cvmx_pcie_get_io_base_address(int pcie_port) 87 { 88 union cvmx_pcie_address pcie_addr; 89 pcie_addr.u64 = 0; 90 pcie_addr.io.upper = 0; 91 pcie_addr.io.io = 1; 92 pcie_addr.io.did = 3; 93 pcie_addr.io.subdid = 2; 94 pcie_addr.io.es = 1; 95 pcie_addr.io.port = pcie_port; 96 return pcie_addr.u64; 97 } 98 99 /** 100 * Size of the IO address region returned at address 101 * cvmx_pcie_get_io_base_address() 102 * 103 * @pcie_port: PCIe port the IO is for 104 * 105 * Returns Size of the IO window 106 */ 107 static inline uint64_t cvmx_pcie_get_io_size(int pcie_port) 108 { 109 return 1ull << 32; 110 } 111 112 /** 113 * Return the Core virtual base address for PCIe MEM access. Memory is 114 * read/written as an offset from this address. 115 * 116 * @pcie_port: PCIe port the IO is for 117 * 118 * Returns 64bit Octeon IO base address for read/write 119 */ 120 static inline uint64_t cvmx_pcie_get_mem_base_address(int pcie_port) 121 { 122 union cvmx_pcie_address pcie_addr; 123 pcie_addr.u64 = 0; 124 pcie_addr.mem.upper = 0; 125 pcie_addr.mem.io = 1; 126 pcie_addr.mem.did = 3; 127 pcie_addr.mem.subdid = 3 + pcie_port; 128 return pcie_addr.u64; 129 } 130 131 /** 132 * Size of the Mem address region returned at address 133 * cvmx_pcie_get_mem_base_address() 134 * 135 * @pcie_port: PCIe port the IO is for 136 * 137 * Returns Size of the Mem window 138 */ 139 static inline uint64_t cvmx_pcie_get_mem_size(int pcie_port) 140 { 141 return 1ull << 36; 142 } 143 144 /** 145 * Read a PCIe config space register indirectly. This is used for 146 * registers of the form PCIEEP_CFG??? and PCIERC?_CFG???. 147 * 148 * @pcie_port: PCIe port to read from 149 * @cfg_offset: Address to read 150 * 151 * Returns Value read 152 */ 153 static uint32_t cvmx_pcie_cfgx_read(int pcie_port, uint32_t cfg_offset) 154 { 155 union cvmx_pescx_cfg_rd pescx_cfg_rd; 156 pescx_cfg_rd.u64 = 0; 157 pescx_cfg_rd.s.addr = cfg_offset; 158 cvmx_write_csr(CVMX_PESCX_CFG_RD(pcie_port), pescx_cfg_rd.u64); 159 pescx_cfg_rd.u64 = cvmx_read_csr(CVMX_PESCX_CFG_RD(pcie_port)); 160 return pescx_cfg_rd.s.data; 161 } 162 163 /** 164 * Write a PCIe config space register indirectly. This is used for 165 * registers of the form PCIEEP_CFG??? and PCIERC?_CFG???. 166 * 167 * @pcie_port: PCIe port to write to 168 * @cfg_offset: Address to write 169 * @val: Value to write 170 */ 171 static void cvmx_pcie_cfgx_write(int pcie_port, uint32_t cfg_offset, 172 uint32_t val) 173 { 174 union cvmx_pescx_cfg_wr pescx_cfg_wr; 175 pescx_cfg_wr.u64 = 0; 176 pescx_cfg_wr.s.addr = cfg_offset; 177 pescx_cfg_wr.s.data = val; 178 cvmx_write_csr(CVMX_PESCX_CFG_WR(pcie_port), pescx_cfg_wr.u64); 179 } 180 181 /** 182 * Build a PCIe config space request address for a device 183 * 184 * @pcie_port: PCIe port to access 185 * @bus: Sub bus 186 * @dev: Device ID 187 * @fn: Device sub function 188 * @reg: Register to access 189 * 190 * Returns 64bit Octeon IO address 191 */ 192 static inline uint64_t __cvmx_pcie_build_config_addr(int pcie_port, int bus, 193 int dev, int fn, int reg) 194 { 195 union cvmx_pcie_address pcie_addr; 196 union cvmx_pciercx_cfg006 pciercx_cfg006; 197 198 pciercx_cfg006.u32 = 199 cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG006(pcie_port)); 200 if ((bus <= pciercx_cfg006.s.pbnum) && (dev != 0)) 201 return 0; 202 203 pcie_addr.u64 = 0; 204 pcie_addr.config.upper = 2; 205 pcie_addr.config.io = 1; 206 pcie_addr.config.did = 3; 207 pcie_addr.config.subdid = 1; 208 pcie_addr.config.es = 1; 209 pcie_addr.config.port = pcie_port; 210 pcie_addr.config.ty = (bus > pciercx_cfg006.s.pbnum); 211 pcie_addr.config.bus = bus; 212 pcie_addr.config.dev = dev; 213 pcie_addr.config.func = fn; 214 pcie_addr.config.reg = reg; 215 return pcie_addr.u64; 216 } 217 218 /** 219 * Read 8bits from a Device's config space 220 * 221 * @pcie_port: PCIe port the device is on 222 * @bus: Sub bus 223 * @dev: Device ID 224 * @fn: Device sub function 225 * @reg: Register to access 226 * 227 * Returns Result of the read 228 */ 229 static uint8_t cvmx_pcie_config_read8(int pcie_port, int bus, int dev, 230 int fn, int reg) 231 { 232 uint64_t address = 233 __cvmx_pcie_build_config_addr(pcie_port, bus, dev, fn, reg); 234 if (address) 235 return cvmx_read64_uint8(address); 236 else 237 return 0xff; 238 } 239 240 /** 241 * Read 16bits from a Device's config space 242 * 243 * @pcie_port: PCIe port the device is on 244 * @bus: Sub bus 245 * @dev: Device ID 246 * @fn: Device sub function 247 * @reg: Register to access 248 * 249 * Returns Result of the read 250 */ 251 static uint16_t cvmx_pcie_config_read16(int pcie_port, int bus, int dev, 252 int fn, int reg) 253 { 254 uint64_t address = 255 __cvmx_pcie_build_config_addr(pcie_port, bus, dev, fn, reg); 256 if (address) 257 return le16_to_cpu(cvmx_read64_uint16(address)); 258 else 259 return 0xffff; 260 } 261 262 /** 263 * Read 32bits from a Device's config space 264 * 265 * @pcie_port: PCIe port the device is on 266 * @bus: Sub bus 267 * @dev: Device ID 268 * @fn: Device sub function 269 * @reg: Register to access 270 * 271 * Returns Result of the read 272 */ 273 static uint32_t cvmx_pcie_config_read32(int pcie_port, int bus, int dev, 274 int fn, int reg) 275 { 276 uint64_t address = 277 __cvmx_pcie_build_config_addr(pcie_port, bus, dev, fn, reg); 278 if (address) 279 return le32_to_cpu(cvmx_read64_uint32(address)); 280 else 281 return 0xffffffff; 282 } 283 284 /** 285 * Write 8bits to a Device's config space 286 * 287 * @pcie_port: PCIe port the device is on 288 * @bus: Sub bus 289 * @dev: Device ID 290 * @fn: Device sub function 291 * @reg: Register to access 292 * @val: Value to write 293 */ 294 static void cvmx_pcie_config_write8(int pcie_port, int bus, int dev, int fn, 295 int reg, uint8_t val) 296 { 297 uint64_t address = 298 __cvmx_pcie_build_config_addr(pcie_port, bus, dev, fn, reg); 299 if (address) 300 cvmx_write64_uint8(address, val); 301 } 302 303 /** 304 * Write 16bits to a Device's config space 305 * 306 * @pcie_port: PCIe port the device is on 307 * @bus: Sub bus 308 * @dev: Device ID 309 * @fn: Device sub function 310 * @reg: Register to access 311 * @val: Value to write 312 */ 313 static void cvmx_pcie_config_write16(int pcie_port, int bus, int dev, int fn, 314 int reg, uint16_t val) 315 { 316 uint64_t address = 317 __cvmx_pcie_build_config_addr(pcie_port, bus, dev, fn, reg); 318 if (address) 319 cvmx_write64_uint16(address, cpu_to_le16(val)); 320 } 321 322 /** 323 * Write 32bits to a Device's config space 324 * 325 * @pcie_port: PCIe port the device is on 326 * @bus: Sub bus 327 * @dev: Device ID 328 * @fn: Device sub function 329 * @reg: Register to access 330 * @val: Value to write 331 */ 332 static void cvmx_pcie_config_write32(int pcie_port, int bus, int dev, int fn, 333 int reg, uint32_t val) 334 { 335 uint64_t address = 336 __cvmx_pcie_build_config_addr(pcie_port, bus, dev, fn, reg); 337 if (address) 338 cvmx_write64_uint32(address, cpu_to_le32(val)); 339 } 340 341 /** 342 * Initialize the RC config space CSRs 343 * 344 * @pcie_port: PCIe port to initialize 345 */ 346 static void __cvmx_pcie_rc_initialize_config_space(int pcie_port) 347 { 348 union cvmx_pciercx_cfg030 pciercx_cfg030; 349 union cvmx_npei_ctl_status2 npei_ctl_status2; 350 union cvmx_pciercx_cfg070 pciercx_cfg070; 351 union cvmx_pciercx_cfg001 pciercx_cfg001; 352 union cvmx_pciercx_cfg032 pciercx_cfg032; 353 union cvmx_pciercx_cfg006 pciercx_cfg006; 354 union cvmx_pciercx_cfg008 pciercx_cfg008; 355 union cvmx_pciercx_cfg009 pciercx_cfg009; 356 union cvmx_pciercx_cfg010 pciercx_cfg010; 357 union cvmx_pciercx_cfg011 pciercx_cfg011; 358 union cvmx_pciercx_cfg035 pciercx_cfg035; 359 union cvmx_pciercx_cfg075 pciercx_cfg075; 360 union cvmx_pciercx_cfg034 pciercx_cfg034; 361 362 /* Max Payload Size (PCIE*_CFG030[MPS]) */ 363 /* Max Read Request Size (PCIE*_CFG030[MRRS]) */ 364 /* Relaxed-order, no-snoop enables (PCIE*_CFG030[RO_EN,NS_EN] */ 365 /* Error Message Enables (PCIE*_CFG030[CE_EN,NFE_EN,FE_EN,UR_EN]) */ 366 pciercx_cfg030.u32 = 367 cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG030(pcie_port)); 368 /* 369 * Max payload size = 128 bytes for best Octeon DMA 370 * performance. 371 */ 372 pciercx_cfg030.s.mps = 0; 373 /* 374 * Max read request size = 128 bytes for best Octeon DMA 375 * performance. 376 */ 377 pciercx_cfg030.s.mrrs = 0; 378 /* Enable relaxed ordering. */ 379 pciercx_cfg030.s.ro_en = 1; 380 /* Enable no snoop. */ 381 pciercx_cfg030.s.ns_en = 1; 382 /* Correctable error reporting enable. */ 383 pciercx_cfg030.s.ce_en = 1; 384 /* Non-fatal error reporting enable. */ 385 pciercx_cfg030.s.nfe_en = 1; 386 /* Fatal error reporting enable. */ 387 pciercx_cfg030.s.fe_en = 1; 388 /* Unsupported request reporting enable. */ 389 pciercx_cfg030.s.ur_en = 1; 390 cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG030(pcie_port), 391 pciercx_cfg030.u32); 392 393 /* 394 * Max Payload Size (NPEI_CTL_STATUS2[MPS]) must match 395 * PCIE*_CFG030[MPS] 396 * 397 * Max Read Request Size (NPEI_CTL_STATUS2[MRRS]) must not 398 * exceed PCIE*_CFG030[MRRS]. 399 */ 400 npei_ctl_status2.u64 = cvmx_read_csr(CVMX_PEXP_NPEI_CTL_STATUS2); 401 /* Max payload size = 128 bytes for best Octeon DMA performance */ 402 npei_ctl_status2.s.mps = 0; 403 /* Max read request size = 128 bytes for best Octeon DMA performance */ 404 npei_ctl_status2.s.mrrs = 0; 405 if (pcie_port) 406 npei_ctl_status2.s.c1_b1_s = 3; /* Port1 BAR1 Size 256MB */ 407 else 408 npei_ctl_status2.s.c0_b1_s = 3; /* Port0 BAR1 Size 256MB */ 409 cvmx_write_csr(CVMX_PEXP_NPEI_CTL_STATUS2, npei_ctl_status2.u64); 410 411 /* ECRC Generation (PCIE*_CFG070[GE,CE]) */ 412 pciercx_cfg070.u32 = 413 cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG070(pcie_port)); 414 pciercx_cfg070.s.ge = 1; /* ECRC generation enable. */ 415 pciercx_cfg070.s.ce = 1; /* ECRC check enable. */ 416 cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG070(pcie_port), 417 pciercx_cfg070.u32); 418 419 /* 420 * Access Enables (PCIE*_CFG001[MSAE,ME]) ME and MSAE should 421 * always be set. 422 * 423 * Interrupt Disable (PCIE*_CFG001[I_DIS]) System Error 424 * Message Enable (PCIE*_CFG001[SEE]) 425 */ 426 pciercx_cfg001.u32 = 427 cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG001(pcie_port)); 428 pciercx_cfg001.s.msae = 1; /* Memory space enable. */ 429 pciercx_cfg001.s.me = 1; /* Bus master enable. */ 430 pciercx_cfg001.s.i_dis = 1; /* INTx assertion disable. */ 431 pciercx_cfg001.s.see = 1; /* SERR# enable */ 432 cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG001(pcie_port), 433 pciercx_cfg001.u32); 434 435 /* Advanced Error Recovery Message Enables */ 436 /* (PCIE*_CFG066,PCIE*_CFG067,PCIE*_CFG069) */ 437 cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG066(pcie_port), 0); 438 /* Use CVMX_PCIERCX_CFG067 hardware default */ 439 cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG069(pcie_port), 0); 440 441 /* Active State Power Management (PCIE*_CFG032[ASLPC]) */ 442 pciercx_cfg032.u32 = 443 cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG032(pcie_port)); 444 pciercx_cfg032.s.aslpc = 0; /* Active state Link PM control. */ 445 cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG032(pcie_port), 446 pciercx_cfg032.u32); 447 448 /* Entrance Latencies (PCIE*_CFG451[L0EL,L1EL]) */ 449 450 /* 451 * Link Width Mode (PCIERCn_CFG452[LME]) - Set during 452 * cvmx_pcie_rc_initialize_link() 453 * 454 * Primary Bus Number (PCIERCn_CFG006[PBNUM]) 455 * 456 * We set the primary bus number to 1 so IDT bridges are 457 * happy. They don't like zero. 458 */ 459 pciercx_cfg006.u32 = 0; 460 pciercx_cfg006.s.pbnum = 1; 461 pciercx_cfg006.s.sbnum = 1; 462 pciercx_cfg006.s.subbnum = 1; 463 cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG006(pcie_port), 464 pciercx_cfg006.u32); 465 466 /* 467 * Memory-mapped I/O BAR (PCIERCn_CFG008) 468 * Most applications should disable the memory-mapped I/O BAR by 469 * setting PCIERCn_CFG008[ML_ADDR] < PCIERCn_CFG008[MB_ADDR] 470 */ 471 pciercx_cfg008.u32 = 0; 472 pciercx_cfg008.s.mb_addr = 0x100; 473 pciercx_cfg008.s.ml_addr = 0; 474 cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG008(pcie_port), 475 pciercx_cfg008.u32); 476 477 /* 478 * Prefetchable BAR (PCIERCn_CFG009,PCIERCn_CFG010,PCIERCn_CFG011) 479 * Most applications should disable the prefetchable BAR by setting 480 * PCIERCn_CFG011[UMEM_LIMIT],PCIERCn_CFG009[LMEM_LIMIT] < 481 * PCIERCn_CFG010[UMEM_BASE],PCIERCn_CFG009[LMEM_BASE] 482 */ 483 pciercx_cfg009.u32 = 484 cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG009(pcie_port)); 485 pciercx_cfg010.u32 = 486 cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG010(pcie_port)); 487 pciercx_cfg011.u32 = 488 cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG011(pcie_port)); 489 pciercx_cfg009.s.lmem_base = 0x100; 490 pciercx_cfg009.s.lmem_limit = 0; 491 pciercx_cfg010.s.umem_base = 0x100; 492 pciercx_cfg011.s.umem_limit = 0; 493 cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG009(pcie_port), 494 pciercx_cfg009.u32); 495 cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG010(pcie_port), 496 pciercx_cfg010.u32); 497 cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG011(pcie_port), 498 pciercx_cfg011.u32); 499 500 /* 501 * System Error Interrupt Enables (PCIERCn_CFG035[SECEE,SEFEE,SENFEE]) 502 * PME Interrupt Enables (PCIERCn_CFG035[PMEIE]) 503 */ 504 pciercx_cfg035.u32 = 505 cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG035(pcie_port)); 506 /* System error on correctable error enable. */ 507 pciercx_cfg035.s.secee = 1; 508 /* System error on fatal error enable. */ 509 pciercx_cfg035.s.sefee = 1; 510 /* System error on non-fatal error enable. */ 511 pciercx_cfg035.s.senfee = 1; 512 /* PME interrupt enable. */ 513 pciercx_cfg035.s.pmeie = 1; 514 cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG035(pcie_port), 515 pciercx_cfg035.u32); 516 517 /* 518 * Advanced Error Recovery Interrupt Enables 519 * (PCIERCn_CFG075[CERE,NFERE,FERE]) 520 */ 521 pciercx_cfg075.u32 = 522 cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG075(pcie_port)); 523 /* Correctable error reporting enable. */ 524 pciercx_cfg075.s.cere = 1; 525 /* Non-fatal error reporting enable. */ 526 pciercx_cfg075.s.nfere = 1; 527 /* Fatal error reporting enable. */ 528 pciercx_cfg075.s.fere = 1; 529 cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG075(pcie_port), 530 pciercx_cfg075.u32); 531 532 /* HP Interrupt Enables (PCIERCn_CFG034[HPINT_EN], 533 * PCIERCn_CFG034[DLLS_EN,CCINT_EN]) 534 */ 535 pciercx_cfg034.u32 = 536 cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG034(pcie_port)); 537 /* Hot-plug interrupt enable. */ 538 pciercx_cfg034.s.hpint_en = 1; 539 /* Data Link Layer state changed enable */ 540 pciercx_cfg034.s.dlls_en = 1; 541 /* Command completed interrupt enable. */ 542 pciercx_cfg034.s.ccint_en = 1; 543 cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG034(pcie_port), 544 pciercx_cfg034.u32); 545 } 546 547 /** 548 * Initialize a host mode PCIe link. This function takes a PCIe 549 * port from reset to a link up state. Software can then begin 550 * configuring the rest of the link. 551 * 552 * @pcie_port: PCIe port to initialize 553 * 554 * Returns Zero on success 555 */ 556 static int __cvmx_pcie_rc_initialize_link(int pcie_port) 557 { 558 uint64_t start_cycle; 559 union cvmx_pescx_ctl_status pescx_ctl_status; 560 union cvmx_pciercx_cfg452 pciercx_cfg452; 561 union cvmx_pciercx_cfg032 pciercx_cfg032; 562 union cvmx_pciercx_cfg448 pciercx_cfg448; 563 564 /* Set the lane width */ 565 pciercx_cfg452.u32 = 566 cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG452(pcie_port)); 567 pescx_ctl_status.u64 = cvmx_read_csr(CVMX_PESCX_CTL_STATUS(pcie_port)); 568 if (pescx_ctl_status.s.qlm_cfg == 0) { 569 /* We're in 8 lane (56XX) or 4 lane (54XX) mode */ 570 pciercx_cfg452.s.lme = 0xf; 571 } else { 572 /* We're in 4 lane (56XX) or 2 lane (52XX) mode */ 573 pciercx_cfg452.s.lme = 0x7; 574 } 575 cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG452(pcie_port), 576 pciercx_cfg452.u32); 577 578 /* 579 * CN52XX pass 1.x has an errata where length mismatches on UR 580 * responses can cause bus errors on 64bit memory 581 * reads. Turning off length error checking fixes this. 582 */ 583 if (OCTEON_IS_MODEL(OCTEON_CN52XX_PASS1_X)) { 584 union cvmx_pciercx_cfg455 pciercx_cfg455; 585 pciercx_cfg455.u32 = 586 cvmx_pcie_cfgx_read(pcie_port, 587 CVMX_PCIERCX_CFG455(pcie_port)); 588 pciercx_cfg455.s.m_cpl_len_err = 1; 589 cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG455(pcie_port), 590 pciercx_cfg455.u32); 591 } 592 593 /* Lane swap needs to be manually enabled for CN52XX */ 594 if (OCTEON_IS_MODEL(OCTEON_CN52XX) && (pcie_port == 1)) { 595 pescx_ctl_status.s.lane_swp = 1; 596 cvmx_write_csr(CVMX_PESCX_CTL_STATUS(pcie_port), 597 pescx_ctl_status.u64); 598 } 599 600 /* Bring up the link */ 601 pescx_ctl_status.u64 = cvmx_read_csr(CVMX_PESCX_CTL_STATUS(pcie_port)); 602 pescx_ctl_status.s.lnk_enb = 1; 603 cvmx_write_csr(CVMX_PESCX_CTL_STATUS(pcie_port), pescx_ctl_status.u64); 604 605 /* 606 * CN52XX pass 1.0: Due to a bug in 2nd order CDR, it needs to 607 * be disabled. 608 */ 609 if (OCTEON_IS_MODEL(OCTEON_CN52XX_PASS1_0)) 610 __cvmx_helper_errata_qlm_disable_2nd_order_cdr(0); 611 612 /* Wait for the link to come up */ 613 cvmx_dprintf("PCIe: Waiting for port %d link\n", pcie_port); 614 start_cycle = cvmx_get_cycle(); 615 do { 616 if (cvmx_get_cycle() - start_cycle > 617 2 * cvmx_sysinfo_get()->cpu_clock_hz) { 618 cvmx_dprintf("PCIe: Port %d link timeout\n", 619 pcie_port); 620 return -1; 621 } 622 cvmx_wait(10000); 623 pciercx_cfg032.u32 = 624 cvmx_pcie_cfgx_read(pcie_port, 625 CVMX_PCIERCX_CFG032(pcie_port)); 626 } while (pciercx_cfg032.s.dlla == 0); 627 628 /* Display the link status */ 629 cvmx_dprintf("PCIe: Port %d link active, %d lanes\n", pcie_port, 630 pciercx_cfg032.s.nlw); 631 632 /* 633 * Update the Replay Time Limit. Empirically, some PCIe 634 * devices take a little longer to respond than expected under 635 * load. As a workaround for this we configure the Replay Time 636 * Limit to the value expected for a 512 byte MPS instead of 637 * our actual 256 byte MPS. The numbers below are directly 638 * from the PCIe spec table 3-4. 639 */ 640 pciercx_cfg448.u32 = 641 cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG448(pcie_port)); 642 switch (pciercx_cfg032.s.nlw) { 643 case 1: /* 1 lane */ 644 pciercx_cfg448.s.rtl = 1677; 645 break; 646 case 2: /* 2 lanes */ 647 pciercx_cfg448.s.rtl = 867; 648 break; 649 case 4: /* 4 lanes */ 650 pciercx_cfg448.s.rtl = 462; 651 break; 652 case 8: /* 8 lanes */ 653 pciercx_cfg448.s.rtl = 258; 654 break; 655 } 656 cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG448(pcie_port), 657 pciercx_cfg448.u32); 658 659 return 0; 660 } 661 662 /** 663 * Initialize a PCIe port for use in host(RC) mode. It doesn't 664 * enumerate the bus. 665 * 666 * @pcie_port: PCIe port to initialize 667 * 668 * Returns Zero on success 669 */ 670 static int cvmx_pcie_rc_initialize(int pcie_port) 671 { 672 int i; 673 int base; 674 u64 addr_swizzle; 675 union cvmx_ciu_soft_prst ciu_soft_prst; 676 union cvmx_pescx_bist_status pescx_bist_status; 677 union cvmx_pescx_bist_status2 pescx_bist_status2; 678 union cvmx_npei_ctl_status npei_ctl_status; 679 union cvmx_npei_mem_access_ctl npei_mem_access_ctl; 680 union cvmx_npei_mem_access_subidx mem_access_subid; 681 union cvmx_npei_dbg_data npei_dbg_data; 682 union cvmx_pescx_ctl_status2 pescx_ctl_status2; 683 union cvmx_npei_bar1_indexx bar1_index; 684 685 /* 686 * Make sure we aren't trying to setup a target mode interface 687 * in host mode. 688 */ 689 npei_ctl_status.u64 = cvmx_read_csr(CVMX_PEXP_NPEI_CTL_STATUS); 690 if ((pcie_port == 0) && !npei_ctl_status.s.host_mode) { 691 cvmx_dprintf("PCIe: ERROR: cvmx_pcie_rc_initialize() called " 692 "on port0, but port0 is not in host mode\n"); 693 return -1; 694 } 695 696 /* 697 * Make sure a CN52XX isn't trying to bring up port 1 when it 698 * is disabled. 699 */ 700 if (OCTEON_IS_MODEL(OCTEON_CN52XX)) { 701 npei_dbg_data.u64 = cvmx_read_csr(CVMX_PEXP_NPEI_DBG_DATA); 702 if ((pcie_port == 1) && npei_dbg_data.cn52xx.qlm0_link_width) { 703 cvmx_dprintf("PCIe: ERROR: cvmx_pcie_rc_initialize() " 704 "called on port1, but port1 is " 705 "disabled\n"); 706 return -1; 707 } 708 } 709 710 /* 711 * PCIe switch arbitration mode. '0' == fixed priority NPEI, 712 * PCIe0, then PCIe1. '1' == round robin. 713 */ 714 npei_ctl_status.s.arb = 1; 715 /* Allow up to 0x20 config retries */ 716 npei_ctl_status.s.cfg_rtry = 0x20; 717 /* 718 * CN52XX pass1.x has an errata where P0_NTAGS and P1_NTAGS 719 * don't reset. 720 */ 721 if (OCTEON_IS_MODEL(OCTEON_CN52XX_PASS1_X)) { 722 npei_ctl_status.s.p0_ntags = 0x20; 723 npei_ctl_status.s.p1_ntags = 0x20; 724 } 725 cvmx_write_csr(CVMX_PEXP_NPEI_CTL_STATUS, npei_ctl_status.u64); 726 727 /* Bring the PCIe out of reset */ 728 if (cvmx_sysinfo_get()->board_type == CVMX_BOARD_TYPE_EBH5200) { 729 /* 730 * The EBH5200 board swapped the PCIe reset lines on 731 * the board. As a workaround for this bug, we bring 732 * both PCIe ports out of reset at the same time 733 * instead of on separate calls. So for port 0, we 734 * bring both out of reset and do nothing on port 1. 735 */ 736 if (pcie_port == 0) { 737 ciu_soft_prst.u64 = cvmx_read_csr(CVMX_CIU_SOFT_PRST); 738 /* 739 * After a chip reset the PCIe will also be in 740 * reset. If it isn't, most likely someone is 741 * trying to init it again without a proper 742 * PCIe reset. 743 */ 744 if (ciu_soft_prst.s.soft_prst == 0) { 745 /* Reset the ports */ 746 ciu_soft_prst.s.soft_prst = 1; 747 cvmx_write_csr(CVMX_CIU_SOFT_PRST, 748 ciu_soft_prst.u64); 749 ciu_soft_prst.u64 = 750 cvmx_read_csr(CVMX_CIU_SOFT_PRST1); 751 ciu_soft_prst.s.soft_prst = 1; 752 cvmx_write_csr(CVMX_CIU_SOFT_PRST1, 753 ciu_soft_prst.u64); 754 /* Wait until pcie resets the ports. */ 755 udelay(2000); 756 } 757 ciu_soft_prst.u64 = cvmx_read_csr(CVMX_CIU_SOFT_PRST1); 758 ciu_soft_prst.s.soft_prst = 0; 759 cvmx_write_csr(CVMX_CIU_SOFT_PRST1, ciu_soft_prst.u64); 760 ciu_soft_prst.u64 = cvmx_read_csr(CVMX_CIU_SOFT_PRST); 761 ciu_soft_prst.s.soft_prst = 0; 762 cvmx_write_csr(CVMX_CIU_SOFT_PRST, ciu_soft_prst.u64); 763 } 764 } else { 765 /* 766 * The normal case: The PCIe ports are completely 767 * separate and can be brought out of reset 768 * independently. 769 */ 770 if (pcie_port) 771 ciu_soft_prst.u64 = cvmx_read_csr(CVMX_CIU_SOFT_PRST1); 772 else 773 ciu_soft_prst.u64 = cvmx_read_csr(CVMX_CIU_SOFT_PRST); 774 /* 775 * After a chip reset the PCIe will also be in 776 * reset. If it isn't, most likely someone is trying 777 * to init it again without a proper PCIe reset. 778 */ 779 if (ciu_soft_prst.s.soft_prst == 0) { 780 /* Reset the port */ 781 ciu_soft_prst.s.soft_prst = 1; 782 if (pcie_port) 783 cvmx_write_csr(CVMX_CIU_SOFT_PRST1, 784 ciu_soft_prst.u64); 785 else 786 cvmx_write_csr(CVMX_CIU_SOFT_PRST, 787 ciu_soft_prst.u64); 788 /* Wait until pcie resets the ports. */ 789 udelay(2000); 790 } 791 if (pcie_port) { 792 ciu_soft_prst.u64 = cvmx_read_csr(CVMX_CIU_SOFT_PRST1); 793 ciu_soft_prst.s.soft_prst = 0; 794 cvmx_write_csr(CVMX_CIU_SOFT_PRST1, ciu_soft_prst.u64); 795 } else { 796 ciu_soft_prst.u64 = cvmx_read_csr(CVMX_CIU_SOFT_PRST); 797 ciu_soft_prst.s.soft_prst = 0; 798 cvmx_write_csr(CVMX_CIU_SOFT_PRST, ciu_soft_prst.u64); 799 } 800 } 801 802 /* 803 * Wait for PCIe reset to complete. Due to errata PCIE-700, we 804 * don't poll PESCX_CTL_STATUS2[PCIERST], but simply wait a 805 * fixed number of cycles. 806 */ 807 cvmx_wait(400000); 808 809 /* PESCX_BIST_STATUS2[PCLK_RUN] was missing on pass 1 of CN56XX and 810 CN52XX, so we only probe it on newer chips */ 811 if (!OCTEON_IS_MODEL(OCTEON_CN56XX_PASS1_X) 812 && !OCTEON_IS_MODEL(OCTEON_CN52XX_PASS1_X)) { 813 /* Clear PCLK_RUN so we can check if the clock is running */ 814 pescx_ctl_status2.u64 = 815 cvmx_read_csr(CVMX_PESCX_CTL_STATUS2(pcie_port)); 816 pescx_ctl_status2.s.pclk_run = 1; 817 cvmx_write_csr(CVMX_PESCX_CTL_STATUS2(pcie_port), 818 pescx_ctl_status2.u64); 819 /* 820 * Now that we cleared PCLK_RUN, wait for it to be set 821 * again telling us the clock is running. 822 */ 823 if (CVMX_WAIT_FOR_FIELD64(CVMX_PESCX_CTL_STATUS2(pcie_port), 824 union cvmx_pescx_ctl_status2, 825 pclk_run, ==, 1, 10000)) { 826 cvmx_dprintf("PCIe: Port %d isn't clocked, skipping.\n", 827 pcie_port); 828 return -1; 829 } 830 } 831 832 /* 833 * Check and make sure PCIe came out of reset. If it doesn't 834 * the board probably hasn't wired the clocks up and the 835 * interface should be skipped. 836 */ 837 pescx_ctl_status2.u64 = 838 cvmx_read_csr(CVMX_PESCX_CTL_STATUS2(pcie_port)); 839 if (pescx_ctl_status2.s.pcierst) { 840 cvmx_dprintf("PCIe: Port %d stuck in reset, skipping.\n", 841 pcie_port); 842 return -1; 843 } 844 845 /* 846 * Check BIST2 status. If any bits are set skip this interface. This 847 * is an attempt to catch PCIE-813 on pass 1 parts. 848 */ 849 pescx_bist_status2.u64 = 850 cvmx_read_csr(CVMX_PESCX_BIST_STATUS2(pcie_port)); 851 if (pescx_bist_status2.u64) { 852 cvmx_dprintf("PCIe: Port %d BIST2 failed. Most likely this " 853 "port isn't hooked up, skipping.\n", 854 pcie_port); 855 return -1; 856 } 857 858 /* Check BIST status */ 859 pescx_bist_status.u64 = 860 cvmx_read_csr(CVMX_PESCX_BIST_STATUS(pcie_port)); 861 if (pescx_bist_status.u64) 862 cvmx_dprintf("PCIe: BIST FAILED for port %d (0x%016llx)\n", 863 pcie_port, CAST64(pescx_bist_status.u64)); 864 865 /* Initialize the config space CSRs */ 866 __cvmx_pcie_rc_initialize_config_space(pcie_port); 867 868 /* Bring the link up */ 869 if (__cvmx_pcie_rc_initialize_link(pcie_port)) { 870 cvmx_dprintf 871 ("PCIe: ERROR: cvmx_pcie_rc_initialize_link() failed\n"); 872 return -1; 873 } 874 875 /* Store merge control (NPEI_MEM_ACCESS_CTL[TIMER,MAX_WORD]) */ 876 npei_mem_access_ctl.u64 = cvmx_read_csr(CVMX_PEXP_NPEI_MEM_ACCESS_CTL); 877 /* Allow 16 words to combine */ 878 npei_mem_access_ctl.s.max_word = 0; 879 /* Wait up to 127 cycles for more data */ 880 npei_mem_access_ctl.s.timer = 127; 881 cvmx_write_csr(CVMX_PEXP_NPEI_MEM_ACCESS_CTL, npei_mem_access_ctl.u64); 882 883 /* Setup Mem access SubDIDs */ 884 mem_access_subid.u64 = 0; 885 /* Port the request is sent to. */ 886 mem_access_subid.s.port = pcie_port; 887 /* Due to an errata on pass 1 chips, no merging is allowed. */ 888 mem_access_subid.s.nmerge = 1; 889 /* Endian-swap for Reads. */ 890 mem_access_subid.s.esr = 1; 891 /* Endian-swap for Writes. */ 892 mem_access_subid.s.esw = 1; 893 /* No Snoop for Reads. */ 894 mem_access_subid.s.nsr = 1; 895 /* No Snoop for Writes. */ 896 mem_access_subid.s.nsw = 1; 897 /* Disable Relaxed Ordering for Reads. */ 898 mem_access_subid.s.ror = 0; 899 /* Disable Relaxed Ordering for Writes. */ 900 mem_access_subid.s.row = 0; 901 /* PCIe Adddress Bits <63:34>. */ 902 mem_access_subid.s.ba = 0; 903 904 /* 905 * Setup mem access 12-15 for port 0, 16-19 for port 1, 906 * supplying 36 bits of address space. 907 */ 908 for (i = 12 + pcie_port * 4; i < 16 + pcie_port * 4; i++) { 909 cvmx_write_csr(CVMX_PEXP_NPEI_MEM_ACCESS_SUBIDX(i), 910 mem_access_subid.u64); 911 /* Set each SUBID to extend the addressable range */ 912 mem_access_subid.s.ba += 1; 913 } 914 915 /* 916 * Disable the peer to peer forwarding register. This must be 917 * setup by the OS after it enumerates the bus and assigns 918 * addresses to the PCIe busses. 919 */ 920 for (i = 0; i < 4; i++) { 921 cvmx_write_csr(CVMX_PESCX_P2P_BARX_START(i, pcie_port), -1); 922 cvmx_write_csr(CVMX_PESCX_P2P_BARX_END(i, pcie_port), -1); 923 } 924 925 /* Set Octeon's BAR0 to decode 0-16KB. It overlaps with Bar2 */ 926 cvmx_write_csr(CVMX_PESCX_P2N_BAR0_START(pcie_port), 0); 927 928 /* BAR1 follows BAR2 with a gap. */ 929 cvmx_write_csr(CVMX_PESCX_P2N_BAR1_START(pcie_port), CVMX_PCIE_BAR1_RC_BASE); 930 931 bar1_index.u32 = 0; 932 bar1_index.s.addr_idx = (CVMX_PCIE_BAR1_PHYS_BASE >> 22); 933 bar1_index.s.ca = 1; /* Not Cached */ 934 bar1_index.s.end_swp = 1; /* Endian Swap mode */ 935 bar1_index.s.addr_v = 1; /* Valid entry */ 936 937 base = pcie_port ? 16 : 0; 938 939 /* Big endian swizzle for 32-bit PEXP_NCB register. */ 940 #ifdef __MIPSEB__ 941 addr_swizzle = 4; 942 #else 943 addr_swizzle = 0; 944 #endif 945 for (i = 0; i < 16; i++) { 946 cvmx_write64_uint32((CVMX_PEXP_NPEI_BAR1_INDEXX(base) ^ addr_swizzle), 947 bar1_index.u32); 948 base++; 949 /* 256MB / 16 >> 22 == 4 */ 950 bar1_index.s.addr_idx += (((1ull << 28) / 16ull) >> 22); 951 } 952 953 /* 954 * Set Octeon's BAR2 to decode 0-2^39. Bar0 and Bar1 take 955 * precedence where they overlap. It also overlaps with the 956 * device addresses, so make sure the peer to peer forwarding 957 * is set right. 958 */ 959 cvmx_write_csr(CVMX_PESCX_P2N_BAR2_START(pcie_port), 0); 960 961 /* 962 * Setup BAR2 attributes 963 * 964 * Relaxed Ordering (NPEI_CTL_PORTn[PTLP_RO,CTLP_RO, WAIT_COM]) 965 * - PTLP_RO,CTLP_RO should normally be set (except for debug). 966 * - WAIT_COM=0 will likely work for all applications. 967 * 968 * Load completion relaxed ordering (NPEI_CTL_PORTn[WAITL_COM]). 969 */ 970 if (pcie_port) { 971 union cvmx_npei_ctl_port1 npei_ctl_port; 972 npei_ctl_port.u64 = cvmx_read_csr(CVMX_PEXP_NPEI_CTL_PORT1); 973 npei_ctl_port.s.bar2_enb = 1; 974 npei_ctl_port.s.bar2_esx = 1; 975 npei_ctl_port.s.bar2_cax = 0; 976 npei_ctl_port.s.ptlp_ro = 1; 977 npei_ctl_port.s.ctlp_ro = 1; 978 npei_ctl_port.s.wait_com = 0; 979 npei_ctl_port.s.waitl_com = 0; 980 cvmx_write_csr(CVMX_PEXP_NPEI_CTL_PORT1, npei_ctl_port.u64); 981 } else { 982 union cvmx_npei_ctl_port0 npei_ctl_port; 983 npei_ctl_port.u64 = cvmx_read_csr(CVMX_PEXP_NPEI_CTL_PORT0); 984 npei_ctl_port.s.bar2_enb = 1; 985 npei_ctl_port.s.bar2_esx = 1; 986 npei_ctl_port.s.bar2_cax = 0; 987 npei_ctl_port.s.ptlp_ro = 1; 988 npei_ctl_port.s.ctlp_ro = 1; 989 npei_ctl_port.s.wait_com = 0; 990 npei_ctl_port.s.waitl_com = 0; 991 cvmx_write_csr(CVMX_PEXP_NPEI_CTL_PORT0, npei_ctl_port.u64); 992 } 993 return 0; 994 } 995 996 997 /* Above was cvmx-pcie.c, below original pcie.c */ 998 999 1000 /** 1001 * Map a PCI device to the appropriate interrupt line 1002 * 1003 * @dev: The Linux PCI device structure for the device to map 1004 * @slot: The slot number for this device on __BUS 0__. Linux 1005 * enumerates through all the bridges and figures out the 1006 * slot on Bus 0 where this device eventually hooks to. 1007 * @pin: The PCI interrupt pin read from the device, then swizzled 1008 * as it goes through each bridge. 1009 * Returns Interrupt number for the device 1010 */ 1011 int __init octeon_pcie_pcibios_map_irq(const struct pci_dev *dev, 1012 u8 slot, u8 pin) 1013 { 1014 /* 1015 * The EBH5600 board with the PCI to PCIe bridge mistakenly 1016 * wires the first slot for both device id 2 and interrupt 1017 * A. According to the PCI spec, device id 2 should be C. The 1018 * following kludge attempts to fix this. 1019 */ 1020 if (strstr(octeon_board_type_string(), "EBH5600") && 1021 dev->bus && dev->bus->parent) { 1022 /* 1023 * Iterate all the way up the device chain and find 1024 * the root bus. 1025 */ 1026 while (dev->bus && dev->bus->parent) 1027 dev = to_pci_dev(dev->bus->bridge); 1028 /* If the root bus is number 0 and the PEX 8114 is the 1029 * root, assume we are behind the miswired bus. We 1030 * need to correct the swizzle level by two. Yuck. 1031 */ 1032 if ((dev->bus->number == 0) && 1033 (dev->vendor == 0x10b5) && (dev->device == 0x8114)) { 1034 /* 1035 * The pin field is one based, not zero. We 1036 * need to swizzle it by minus two. 1037 */ 1038 pin = ((pin - 3) & 3) + 1; 1039 } 1040 } 1041 /* 1042 * The -1 is because pin starts with one, not zero. It might 1043 * be that this equation needs to include the slot number, but 1044 * I don't have hardware to check that against. 1045 */ 1046 return pin - 1 + OCTEON_IRQ_PCI_INT0; 1047 } 1048 1049 /** 1050 * Read a value from configuration space 1051 * 1052 * @bus: 1053 * @devfn: 1054 * @reg: 1055 * @size: 1056 * @val: 1057 * Returns 1058 */ 1059 static inline int octeon_pcie_read_config(int pcie_port, struct pci_bus *bus, 1060 unsigned int devfn, int reg, int size, 1061 u32 *val) 1062 { 1063 union octeon_cvmemctl cvmmemctl; 1064 union octeon_cvmemctl cvmmemctl_save; 1065 int bus_number = bus->number; 1066 1067 /* 1068 * For the top level bus make sure our hardware bus number 1069 * matches the software one. 1070 */ 1071 if (bus->parent == NULL) { 1072 union cvmx_pciercx_cfg006 pciercx_cfg006; 1073 pciercx_cfg006.u32 = cvmx_pcie_cfgx_read(pcie_port, 1074 CVMX_PCIERCX_CFG006(pcie_port)); 1075 if (pciercx_cfg006.s.pbnum != bus_number) { 1076 pciercx_cfg006.s.pbnum = bus_number; 1077 pciercx_cfg006.s.sbnum = bus_number; 1078 pciercx_cfg006.s.subbnum = bus_number; 1079 cvmx_pcie_cfgx_write(pcie_port, 1080 CVMX_PCIERCX_CFG006(pcie_port), 1081 pciercx_cfg006.u32); 1082 } 1083 } 1084 1085 /* 1086 * PCIe only has a single device connected to Octeon. It is 1087 * always device ID 0. Don't bother doing reads for other 1088 * device IDs on the first segment. 1089 */ 1090 if ((bus->parent == NULL) && (devfn >> 3 != 0)) 1091 return PCIBIOS_FUNC_NOT_SUPPORTED; 1092 1093 /* 1094 * The following is a workaround for the CN57XX, CN56XX, 1095 * CN55XX, and CN54XX errata with PCIe config reads from non 1096 * existent devices. These chips will hang the PCIe link if a 1097 * config read is performed that causes a UR response. 1098 */ 1099 if (OCTEON_IS_MODEL(OCTEON_CN56XX_PASS1) || 1100 OCTEON_IS_MODEL(OCTEON_CN56XX_PASS1_1)) { 1101 /* 1102 * For our EBH5600 board, port 0 has a bridge with two 1103 * PCI-X slots. We need a new special checks to make 1104 * sure we only probe valid stuff. The PCIe->PCI-X 1105 * bridge only respondes to device ID 0, function 1106 * 0-1 1107 */ 1108 if ((bus->parent == NULL) && (devfn >= 2)) 1109 return PCIBIOS_FUNC_NOT_SUPPORTED; 1110 /* 1111 * The PCI-X slots are device ID 2,3. Choose one of 1112 * the below "if" blocks based on what is plugged into 1113 * the board. 1114 */ 1115 #if 1 1116 /* Use this option if you aren't using either slot */ 1117 if (bus_number == 1) 1118 return PCIBIOS_FUNC_NOT_SUPPORTED; 1119 #elif 0 1120 /* 1121 * Use this option if you are using the first slot but 1122 * not the second. 1123 */ 1124 if ((bus_number == 1) && (devfn >> 3 != 2)) 1125 return PCIBIOS_FUNC_NOT_SUPPORTED; 1126 #elif 0 1127 /* 1128 * Use this option if you are using the second slot 1129 * but not the first. 1130 */ 1131 if ((bus_number == 1) && (devfn >> 3 != 3)) 1132 return PCIBIOS_FUNC_NOT_SUPPORTED; 1133 #elif 0 1134 /* Use this opion if you are using both slots */ 1135 if ((bus_number == 1) && 1136 !((devfn == (2 << 3)) || (devfn == (3 << 3)))) 1137 return PCIBIOS_FUNC_NOT_SUPPORTED; 1138 #endif 1139 1140 /* 1141 * Shorten the DID timeout so bus errors for PCIe 1142 * config reads from non existent devices happen 1143 * faster. This allows us to continue booting even if 1144 * the above "if" checks are wrong. Once one of these 1145 * errors happens, the PCIe port is dead. 1146 */ 1147 cvmmemctl_save.u64 = __read_64bit_c0_register($11, 7); 1148 cvmmemctl.u64 = cvmmemctl_save.u64; 1149 cvmmemctl.s.didtto = 2; 1150 __write_64bit_c0_register($11, 7, cvmmemctl.u64); 1151 } 1152 1153 switch (size) { 1154 case 4: 1155 *val = cvmx_pcie_config_read32(pcie_port, bus_number, 1156 devfn >> 3, devfn & 0x7, reg); 1157 break; 1158 case 2: 1159 *val = cvmx_pcie_config_read16(pcie_port, bus_number, 1160 devfn >> 3, devfn & 0x7, reg); 1161 break; 1162 case 1: 1163 *val = cvmx_pcie_config_read8(pcie_port, bus_number, devfn >> 3, 1164 devfn & 0x7, reg); 1165 break; 1166 default: 1167 return PCIBIOS_FUNC_NOT_SUPPORTED; 1168 } 1169 1170 if (OCTEON_IS_MODEL(OCTEON_CN56XX_PASS1) || 1171 OCTEON_IS_MODEL(OCTEON_CN56XX_PASS1_1)) 1172 __write_64bit_c0_register($11, 7, cvmmemctl_save.u64); 1173 return PCIBIOS_SUCCESSFUL; 1174 } 1175 1176 static int octeon_pcie0_read_config(struct pci_bus *bus, unsigned int devfn, 1177 int reg, int size, u32 *val) 1178 { 1179 return octeon_pcie_read_config(0, bus, devfn, reg, size, val); 1180 } 1181 1182 static int octeon_pcie1_read_config(struct pci_bus *bus, unsigned int devfn, 1183 int reg, int size, u32 *val) 1184 { 1185 return octeon_pcie_read_config(1, bus, devfn, reg, size, val); 1186 } 1187 1188 1189 1190 /** 1191 * Write a value to PCI configuration space 1192 * 1193 * @bus: 1194 * @devfn: 1195 * @reg: 1196 * @size: 1197 * @val: 1198 * Returns 1199 */ 1200 static inline int octeon_pcie_write_config(int pcie_port, struct pci_bus *bus, 1201 unsigned int devfn, int reg, 1202 int size, u32 val) 1203 { 1204 int bus_number = bus->number; 1205 1206 switch (size) { 1207 case 4: 1208 cvmx_pcie_config_write32(pcie_port, bus_number, devfn >> 3, 1209 devfn & 0x7, reg, val); 1210 return PCIBIOS_SUCCESSFUL; 1211 case 2: 1212 cvmx_pcie_config_write16(pcie_port, bus_number, devfn >> 3, 1213 devfn & 0x7, reg, val); 1214 return PCIBIOS_SUCCESSFUL; 1215 case 1: 1216 cvmx_pcie_config_write8(pcie_port, bus_number, devfn >> 3, 1217 devfn & 0x7, reg, val); 1218 return PCIBIOS_SUCCESSFUL; 1219 } 1220 #if PCI_CONFIG_SPACE_DELAY 1221 udelay(PCI_CONFIG_SPACE_DELAY); 1222 #endif 1223 return PCIBIOS_FUNC_NOT_SUPPORTED; 1224 } 1225 1226 static int octeon_pcie0_write_config(struct pci_bus *bus, unsigned int devfn, 1227 int reg, int size, u32 val) 1228 { 1229 return octeon_pcie_write_config(0, bus, devfn, reg, size, val); 1230 } 1231 1232 static int octeon_pcie1_write_config(struct pci_bus *bus, unsigned int devfn, 1233 int reg, int size, u32 val) 1234 { 1235 return octeon_pcie_write_config(1, bus, devfn, reg, size, val); 1236 } 1237 1238 static struct pci_ops octeon_pcie0_ops = { 1239 octeon_pcie0_read_config, 1240 octeon_pcie0_write_config, 1241 }; 1242 1243 static struct resource octeon_pcie0_mem_resource = { 1244 .name = "Octeon PCIe0 MEM", 1245 .flags = IORESOURCE_MEM, 1246 }; 1247 1248 static struct resource octeon_pcie0_io_resource = { 1249 .name = "Octeon PCIe0 IO", 1250 .flags = IORESOURCE_IO, 1251 }; 1252 1253 static struct pci_controller octeon_pcie0_controller = { 1254 .pci_ops = &octeon_pcie0_ops, 1255 .mem_resource = &octeon_pcie0_mem_resource, 1256 .io_resource = &octeon_pcie0_io_resource, 1257 }; 1258 1259 static struct pci_ops octeon_pcie1_ops = { 1260 octeon_pcie1_read_config, 1261 octeon_pcie1_write_config, 1262 }; 1263 1264 static struct resource octeon_pcie1_mem_resource = { 1265 .name = "Octeon PCIe1 MEM", 1266 .flags = IORESOURCE_MEM, 1267 }; 1268 1269 static struct resource octeon_pcie1_io_resource = { 1270 .name = "Octeon PCIe1 IO", 1271 .flags = IORESOURCE_IO, 1272 }; 1273 1274 static struct pci_controller octeon_pcie1_controller = { 1275 .pci_ops = &octeon_pcie1_ops, 1276 .mem_resource = &octeon_pcie1_mem_resource, 1277 .io_resource = &octeon_pcie1_io_resource, 1278 }; 1279 1280 1281 /** 1282 * Initialize the Octeon PCIe controllers 1283 * 1284 * Returns 1285 */ 1286 static int __init octeon_pcie_setup(void) 1287 { 1288 union cvmx_npei_ctl_status npei_ctl_status; 1289 int result; 1290 1291 /* These chips don't have PCIe */ 1292 if (!octeon_has_feature(OCTEON_FEATURE_PCIE)) 1293 return 0; 1294 1295 /* Point pcibios_map_irq() to the PCIe version of it */ 1296 octeon_pcibios_map_irq = octeon_pcie_pcibios_map_irq; 1297 1298 /* Use the PCIe based DMA mappings */ 1299 octeon_dma_bar_type = OCTEON_DMA_BAR_TYPE_PCIE; 1300 1301 /* 1302 * PCIe I/O range. It is based on port 0 but includes up until 1303 * port 1's end. 1304 */ 1305 set_io_port_base(CVMX_ADD_IO_SEG(cvmx_pcie_get_io_base_address(0))); 1306 ioport_resource.start = 0; 1307 ioport_resource.end = 1308 cvmx_pcie_get_io_base_address(1) - 1309 cvmx_pcie_get_io_base_address(0) + cvmx_pcie_get_io_size(1) - 1; 1310 1311 npei_ctl_status.u64 = cvmx_read_csr(CVMX_PEXP_NPEI_CTL_STATUS); 1312 if (npei_ctl_status.s.host_mode) { 1313 pr_notice("PCIe: Initializing port 0\n"); 1314 result = cvmx_pcie_rc_initialize(0); 1315 if (result == 0) { 1316 /* Memory offsets are physical addresses */ 1317 octeon_pcie0_controller.mem_offset = 1318 cvmx_pcie_get_mem_base_address(0); 1319 /* IO offsets are Mips virtual addresses */ 1320 octeon_pcie0_controller.io_map_base = 1321 CVMX_ADD_IO_SEG(cvmx_pcie_get_io_base_address 1322 (0)); 1323 octeon_pcie0_controller.io_offset = 0; 1324 /* 1325 * To keep things similar to PCI, we start 1326 * device addresses at the same place as PCI 1327 * uisng big bar support. This normally 1328 * translates to 4GB-256MB, which is the same 1329 * as most x86 PCs. 1330 */ 1331 octeon_pcie0_controller.mem_resource->start = 1332 cvmx_pcie_get_mem_base_address(0) + 1333 (4ul << 30) - (OCTEON_PCI_BAR1_HOLE_SIZE << 20); 1334 octeon_pcie0_controller.mem_resource->end = 1335 cvmx_pcie_get_mem_base_address(0) + 1336 cvmx_pcie_get_mem_size(0) - 1; 1337 /* 1338 * Ports must be above 16KB for the ISA bus 1339 * filtering in the PCI-X to PCI bridge. 1340 */ 1341 octeon_pcie0_controller.io_resource->start = 4 << 10; 1342 octeon_pcie0_controller.io_resource->end = 1343 cvmx_pcie_get_io_size(0) - 1; 1344 register_pci_controller(&octeon_pcie0_controller); 1345 } 1346 } else { 1347 pr_notice("PCIe: Port 0 in endpoint mode, skipping.\n"); 1348 } 1349 1350 /* Skip the 2nd port on CN52XX if port 0 is in 4 lane mode */ 1351 if (OCTEON_IS_MODEL(OCTEON_CN52XX)) { 1352 union cvmx_npei_dbg_data npei_dbg_data; 1353 npei_dbg_data.u64 = cvmx_read_csr(CVMX_PEXP_NPEI_DBG_DATA); 1354 if (npei_dbg_data.cn52xx.qlm0_link_width) 1355 return 0; 1356 } 1357 1358 pr_notice("PCIe: Initializing port 1\n"); 1359 result = cvmx_pcie_rc_initialize(1); 1360 if (result == 0) { 1361 /* Memory offsets are physical addresses */ 1362 octeon_pcie1_controller.mem_offset = 1363 cvmx_pcie_get_mem_base_address(1); 1364 /* IO offsets are Mips virtual addresses */ 1365 octeon_pcie1_controller.io_map_base = 1366 CVMX_ADD_IO_SEG(cvmx_pcie_get_io_base_address(1)); 1367 octeon_pcie1_controller.io_offset = 1368 cvmx_pcie_get_io_base_address(1) - 1369 cvmx_pcie_get_io_base_address(0); 1370 /* 1371 * To keep things similar to PCI, we start device 1372 * addresses at the same place as PCI uisng big bar 1373 * support. This normally translates to 4GB-256MB, 1374 * which is the same as most x86 PCs. 1375 */ 1376 octeon_pcie1_controller.mem_resource->start = 1377 cvmx_pcie_get_mem_base_address(1) + (4ul << 30) - 1378 (OCTEON_PCI_BAR1_HOLE_SIZE << 20); 1379 octeon_pcie1_controller.mem_resource->end = 1380 cvmx_pcie_get_mem_base_address(1) + 1381 cvmx_pcie_get_mem_size(1) - 1; 1382 /* 1383 * Ports must be above 16KB for the ISA bus filtering 1384 * in the PCI-X to PCI bridge. 1385 */ 1386 octeon_pcie1_controller.io_resource->start = 1387 cvmx_pcie_get_io_base_address(1) - 1388 cvmx_pcie_get_io_base_address(0); 1389 octeon_pcie1_controller.io_resource->end = 1390 octeon_pcie1_controller.io_resource->start + 1391 cvmx_pcie_get_io_size(1) - 1; 1392 register_pci_controller(&octeon_pcie1_controller); 1393 } 1394 return 0; 1395 } 1396 1397 arch_initcall(octeon_pcie_setup); 1398