1 /* 2 * This program is free software; you can redistribute it and/or modify it 3 * under the terms of the GNU General Public License as published by the 4 * Free Software Foundation; either version 2 of the License, or (at your 5 * option) any later version. 6 * 7 * Copyright (C) 2003, 04, 11 Ralf Baechle (ralf@linux-mips.org) 8 * Copyright (C) 2011 Wind River Systems, 9 * written by Ralf Baechle (ralf@linux-mips.org) 10 */ 11 #include <linux/bug.h> 12 #include <linux/kernel.h> 13 #include <linux/mm.h> 14 #include <linux/bootmem.h> 15 #include <linux/export.h> 16 #include <linux/init.h> 17 #include <linux/types.h> 18 #include <linux/pci.h> 19 #include <linux/of_address.h> 20 21 #include <asm/cpu-info.h> 22 23 /* 24 * If PCI_PROBE_ONLY in pci_flags is set, we don't change any PCI resource 25 * assignments. 26 */ 27 28 /* 29 * The PCI controller list. 30 */ 31 32 static struct pci_controller *hose_head, **hose_tail = &hose_head; 33 34 unsigned long PCIBIOS_MIN_IO; 35 unsigned long PCIBIOS_MIN_MEM; 36 37 static int pci_initialized; 38 39 /* 40 * We need to avoid collisions with `mirrored' VGA ports 41 * and other strange ISA hardware, so we always want the 42 * addresses to be allocated in the 0x000-0x0ff region 43 * modulo 0x400. 44 * 45 * Why? Because some silly external IO cards only decode 46 * the low 10 bits of the IO address. The 0x00-0xff region 47 * is reserved for motherboard devices that decode all 16 48 * bits, so it's ok to allocate at, say, 0x2800-0x28ff, 49 * but we want to try to avoid allocating at 0x2900-0x2bff 50 * which might have be mirrored at 0x0100-0x03ff.. 51 */ 52 resource_size_t 53 pcibios_align_resource(void *data, const struct resource *res, 54 resource_size_t size, resource_size_t align) 55 { 56 struct pci_dev *dev = data; 57 struct pci_controller *hose = dev->sysdata; 58 resource_size_t start = res->start; 59 60 if (res->flags & IORESOURCE_IO) { 61 /* Make sure we start at our min on all hoses */ 62 if (start < PCIBIOS_MIN_IO + hose->io_resource->start) 63 start = PCIBIOS_MIN_IO + hose->io_resource->start; 64 65 /* 66 * Put everything into 0x00-0xff region modulo 0x400 67 */ 68 if (start & 0x300) 69 start = (start + 0x3ff) & ~0x3ff; 70 } else if (res->flags & IORESOURCE_MEM) { 71 /* Make sure we start at our min on all hoses */ 72 if (start < PCIBIOS_MIN_MEM + hose->mem_resource->start) 73 start = PCIBIOS_MIN_MEM + hose->mem_resource->start; 74 } 75 76 return start; 77 } 78 79 static void pcibios_scanbus(struct pci_controller *hose) 80 { 81 static int next_busno; 82 static int need_domain_info; 83 LIST_HEAD(resources); 84 struct pci_bus *bus; 85 86 if (!hose->iommu) 87 PCI_DMA_BUS_IS_PHYS = 1; 88 89 if (hose->get_busno && pci_has_flag(PCI_PROBE_ONLY)) 90 next_busno = (*hose->get_busno)(); 91 92 pci_add_resource_offset(&resources, 93 hose->mem_resource, hose->mem_offset); 94 pci_add_resource_offset(&resources, hose->io_resource, hose->io_offset); 95 bus = pci_scan_root_bus(NULL, next_busno, hose->pci_ops, hose, 96 &resources); 97 if (!bus) 98 pci_free_resource_list(&resources); 99 100 hose->bus = bus; 101 102 need_domain_info = need_domain_info || hose->index; 103 hose->need_domain_info = need_domain_info; 104 if (bus) { 105 next_busno = bus->busn_res.end + 1; 106 /* Don't allow 8-bit bus number overflow inside the hose - 107 reserve some space for bridges. */ 108 if (next_busno > 224) { 109 next_busno = 0; 110 need_domain_info = 1; 111 } 112 113 if (!pci_has_flag(PCI_PROBE_ONLY)) { 114 pci_bus_size_bridges(bus); 115 pci_bus_assign_resources(bus); 116 pci_enable_bridges(bus); 117 } 118 bus->dev.of_node = hose->of_node; 119 } 120 } 121 122 #ifdef CONFIG_OF 123 void pci_load_of_ranges(struct pci_controller *hose, struct device_node *node) 124 { 125 const __be32 *ranges; 126 int rlen; 127 int pna = of_n_addr_cells(node); 128 int np = pna + 5; 129 130 pr_info("PCI host bridge %s ranges:\n", node->full_name); 131 ranges = of_get_property(node, "ranges", &rlen); 132 if (ranges == NULL) 133 return; 134 hose->of_node = node; 135 136 while ((rlen -= np * 4) >= 0) { 137 u32 pci_space; 138 struct resource *res = NULL; 139 u64 addr, size; 140 141 pci_space = be32_to_cpup(&ranges[0]); 142 addr = of_translate_address(node, ranges + 3); 143 size = of_read_number(ranges + pna + 3, 2); 144 ranges += np; 145 switch ((pci_space >> 24) & 0x3) { 146 case 1: /* PCI IO space */ 147 pr_info(" IO 0x%016llx..0x%016llx\n", 148 addr, addr + size - 1); 149 hose->io_map_base = 150 (unsigned long)ioremap(addr, size); 151 res = hose->io_resource; 152 res->flags = IORESOURCE_IO; 153 break; 154 case 2: /* PCI Memory space */ 155 case 3: /* PCI 64 bits Memory space */ 156 pr_info(" MEM 0x%016llx..0x%016llx\n", 157 addr, addr + size - 1); 158 res = hose->mem_resource; 159 res->flags = IORESOURCE_MEM; 160 break; 161 } 162 if (res != NULL) { 163 res->start = addr; 164 res->name = node->full_name; 165 res->end = res->start + size - 1; 166 res->parent = NULL; 167 res->sibling = NULL; 168 res->child = NULL; 169 } 170 } 171 } 172 #endif 173 174 static DEFINE_MUTEX(pci_scan_mutex); 175 176 void register_pci_controller(struct pci_controller *hose) 177 { 178 if (request_resource(&iomem_resource, hose->mem_resource) < 0) 179 goto out; 180 if (request_resource(&ioport_resource, hose->io_resource) < 0) { 181 release_resource(hose->mem_resource); 182 goto out; 183 } 184 185 *hose_tail = hose; 186 hose_tail = &hose->next; 187 188 /* 189 * Do not panic here but later - this might happen before console init. 190 */ 191 if (!hose->io_map_base) { 192 printk(KERN_WARNING 193 "registering PCI controller with io_map_base unset\n"); 194 } 195 196 /* 197 * Scan the bus if it is register after the PCI subsystem 198 * initialization. 199 */ 200 if (pci_initialized) { 201 mutex_lock(&pci_scan_mutex); 202 pcibios_scanbus(hose); 203 mutex_unlock(&pci_scan_mutex); 204 } 205 206 return; 207 208 out: 209 printk(KERN_WARNING 210 "Skipping PCI bus scan due to resource conflict\n"); 211 } 212 213 static void __init pcibios_set_cache_line_size(void) 214 { 215 struct cpuinfo_mips *c = ¤t_cpu_data; 216 unsigned int lsize; 217 218 /* 219 * Set PCI cacheline size to that of the highest level in the 220 * cache hierarchy. 221 */ 222 lsize = c->dcache.linesz; 223 lsize = c->scache.linesz ? : lsize; 224 lsize = c->tcache.linesz ? : lsize; 225 226 BUG_ON(!lsize); 227 228 pci_dfl_cache_line_size = lsize >> 2; 229 230 pr_debug("PCI: pci_cache_line_size set to %d bytes\n", lsize); 231 } 232 233 static int __init pcibios_init(void) 234 { 235 struct pci_controller *hose; 236 237 pcibios_set_cache_line_size(); 238 239 /* Scan all of the recorded PCI controllers. */ 240 for (hose = hose_head; hose; hose = hose->next) 241 pcibios_scanbus(hose); 242 243 pci_fixup_irqs(pci_common_swizzle, pcibios_map_irq); 244 245 pci_initialized = 1; 246 247 return 0; 248 } 249 250 subsys_initcall(pcibios_init); 251 252 static int pcibios_enable_resources(struct pci_dev *dev, int mask) 253 { 254 u16 cmd, old_cmd; 255 int idx; 256 struct resource *r; 257 258 pci_read_config_word(dev, PCI_COMMAND, &cmd); 259 old_cmd = cmd; 260 for (idx=0; idx < PCI_NUM_RESOURCES; idx++) { 261 /* Only set up the requested stuff */ 262 if (!(mask & (1<<idx))) 263 continue; 264 265 r = &dev->resource[idx]; 266 if (!(r->flags & (IORESOURCE_IO | IORESOURCE_MEM))) 267 continue; 268 if ((idx == PCI_ROM_RESOURCE) && 269 (!(r->flags & IORESOURCE_ROM_ENABLE))) 270 continue; 271 if (!r->start && r->end) { 272 printk(KERN_ERR "PCI: Device %s not available " 273 "because of resource collisions\n", 274 pci_name(dev)); 275 return -EINVAL; 276 } 277 if (r->flags & IORESOURCE_IO) 278 cmd |= PCI_COMMAND_IO; 279 if (r->flags & IORESOURCE_MEM) 280 cmd |= PCI_COMMAND_MEMORY; 281 } 282 if (cmd != old_cmd) { 283 printk("PCI: Enabling device %s (%04x -> %04x)\n", 284 pci_name(dev), old_cmd, cmd); 285 pci_write_config_word(dev, PCI_COMMAND, cmd); 286 } 287 return 0; 288 } 289 290 unsigned int pcibios_assign_all_busses(void) 291 { 292 return 1; 293 } 294 295 int pcibios_enable_device(struct pci_dev *dev, int mask) 296 { 297 int err; 298 299 if ((err = pcibios_enable_resources(dev, mask)) < 0) 300 return err; 301 302 return pcibios_plat_dev_init(dev); 303 } 304 305 void pcibios_fixup_bus(struct pci_bus *bus) 306 { 307 struct pci_dev *dev = bus->self; 308 309 if (pci_has_flag(PCI_PROBE_ONLY) && dev && 310 (dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) { 311 pci_read_bridge_bases(bus); 312 } 313 } 314 315 EXPORT_SYMBOL(PCIBIOS_MIN_IO); 316 EXPORT_SYMBOL(PCIBIOS_MIN_MEM); 317 318 int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma, 319 enum pci_mmap_state mmap_state, int write_combine) 320 { 321 unsigned long prot; 322 323 /* 324 * I/O space can be accessed via normal processor loads and stores on 325 * this platform but for now we elect not to do this and portable 326 * drivers should not do this anyway. 327 */ 328 if (mmap_state == pci_mmap_io) 329 return -EINVAL; 330 331 /* 332 * Ignore write-combine; for now only return uncached mappings. 333 */ 334 prot = pgprot_val(vma->vm_page_prot); 335 prot = (prot & ~_CACHE_MASK) | _CACHE_UNCACHED; 336 vma->vm_page_prot = __pgprot(prot); 337 338 return remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff, 339 vma->vm_end - vma->vm_start, vma->vm_page_prot); 340 } 341 342 char * (*pcibios_plat_setup)(char *str) __initdata; 343 344 char *__init pcibios_setup(char *str) 345 { 346 if (pcibios_plat_setup) 347 return pcibios_plat_setup(str); 348 return str; 349 } 350