1 /* 2 * This program is free software; you can redistribute it and/or modify it 3 * under the terms of the GNU General Public License as published by the 4 * Free Software Foundation; either version 2 of the License, or (at your 5 * option) any later version. 6 * 7 * Copyright (C) 2003, 04 Ralf Baechle (ralf@linux-mips.org) 8 */ 9 #include <linux/config.h> 10 #include <linux/kernel.h> 11 #include <linux/mm.h> 12 #include <linux/bootmem.h> 13 #include <linux/init.h> 14 #include <linux/types.h> 15 #include <linux/pci.h> 16 17 /* 18 * Indicate whether we respect the PCI setup left by the firmware. 19 * 20 * Make this long-lived so that we know when shutting down 21 * whether we probed only or not. 22 */ 23 int pci_probe_only; 24 25 #define PCI_ASSIGN_ALL_BUSSES 1 26 27 unsigned int pci_probe = PCI_ASSIGN_ALL_BUSSES; 28 29 /* 30 * The PCI controller list. 31 */ 32 33 struct pci_controller *hose_head, **hose_tail = &hose_head; 34 struct pci_controller *pci_isa_hose; 35 36 unsigned long PCIBIOS_MIN_IO = 0x0000; 37 unsigned long PCIBIOS_MIN_MEM = 0; 38 39 /* 40 * We need to avoid collisions with `mirrored' VGA ports 41 * and other strange ISA hardware, so we always want the 42 * addresses to be allocated in the 0x000-0x0ff region 43 * modulo 0x400. 44 * 45 * Why? Because some silly external IO cards only decode 46 * the low 10 bits of the IO address. The 0x00-0xff region 47 * is reserved for motherboard devices that decode all 16 48 * bits, so it's ok to allocate at, say, 0x2800-0x28ff, 49 * but we want to try to avoid allocating at 0x2900-0x2bff 50 * which might have be mirrored at 0x0100-0x03ff.. 51 */ 52 void 53 pcibios_align_resource(void *data, struct resource *res, 54 unsigned long size, unsigned long align) 55 { 56 struct pci_dev *dev = data; 57 struct pci_controller *hose = dev->sysdata; 58 unsigned long start = res->start; 59 60 if (res->flags & IORESOURCE_IO) { 61 /* Make sure we start at our min on all hoses */ 62 if (start < PCIBIOS_MIN_IO + hose->io_resource->start) 63 start = PCIBIOS_MIN_IO + hose->io_resource->start; 64 65 /* 66 * Put everything into 0x00-0xff region modulo 0x400 67 */ 68 if (start & 0x300) 69 start = (start + 0x3ff) & ~0x3ff; 70 } else if (res->flags & IORESOURCE_MEM) { 71 /* Make sure we start at our min on all hoses */ 72 if (start < PCIBIOS_MIN_MEM + hose->mem_resource->start) 73 start = PCIBIOS_MIN_MEM + hose->mem_resource->start; 74 } 75 76 res->start = start; 77 } 78 79 struct pci_controller * __init alloc_pci_controller(void) 80 { 81 return alloc_bootmem(sizeof(struct pci_controller)); 82 } 83 84 void __init register_pci_controller(struct pci_controller *hose) 85 { 86 *hose_tail = hose; 87 hose_tail = &hose->next; 88 } 89 90 /* Most MIPS systems have straight-forward swizzling needs. */ 91 92 static inline u8 bridge_swizzle(u8 pin, u8 slot) 93 { 94 return (((pin - 1) + slot) % 4) + 1; 95 } 96 97 static u8 __init common_swizzle(struct pci_dev *dev, u8 *pinp) 98 { 99 u8 pin = *pinp; 100 101 while (dev->bus->parent) { 102 pin = bridge_swizzle(pin, PCI_SLOT(dev->devfn)); 103 /* Move up the chain of bridges. */ 104 dev = dev->bus->self; 105 } 106 *pinp = pin; 107 108 /* The slot is the slot of the last bridge. */ 109 return PCI_SLOT(dev->devfn); 110 } 111 112 static int __init pcibios_init(void) 113 { 114 struct pci_controller *hose; 115 struct pci_bus *bus; 116 int next_busno; 117 int need_domain_info = 0; 118 119 /* Scan all of the recorded PCI controllers. */ 120 for (next_busno = 0, hose = hose_head; hose; hose = hose->next) { 121 122 if (request_resource(&iomem_resource, hose->mem_resource) < 0) 123 goto out; 124 if (request_resource(&ioport_resource, hose->io_resource) < 0) 125 goto out_free_mem_resource; 126 127 if (!hose->iommu) 128 PCI_DMA_BUS_IS_PHYS = 1; 129 130 if (hose->get_busno && pci_probe_only) 131 next_busno = (*hose->get_busno)(); 132 133 bus = pci_scan_bus(next_busno, hose->pci_ops, hose); 134 hose->bus = bus; 135 hose->need_domain_info = need_domain_info; 136 if (bus) { 137 next_busno = bus->subordinate + 1; 138 /* Don't allow 8-bit bus number overflow inside the hose - 139 reserve some space for bridges. */ 140 if (next_busno > 224) { 141 next_busno = 0; 142 need_domain_info = 1; 143 } 144 } 145 continue; 146 147 out_free_mem_resource: 148 release_resource(hose->mem_resource); 149 150 out: 151 printk(KERN_WARNING 152 "Skipping PCI bus scan due to resource conflict\n"); 153 } 154 155 if (!pci_probe_only) 156 pci_assign_unassigned_resources(); 157 pci_fixup_irqs(common_swizzle, pcibios_map_irq); 158 159 return 0; 160 } 161 162 subsys_initcall(pcibios_init); 163 164 static int pcibios_enable_resources(struct pci_dev *dev, int mask) 165 { 166 u16 cmd, old_cmd; 167 int idx; 168 struct resource *r; 169 170 pci_read_config_word(dev, PCI_COMMAND, &cmd); 171 old_cmd = cmd; 172 for (idx=0; idx < PCI_NUM_RESOURCES; idx++) { 173 /* Only set up the requested stuff */ 174 if (!(mask & (1<<idx))) 175 continue; 176 177 r = &dev->resource[idx]; 178 if (!r->start && r->end) { 179 printk(KERN_ERR "PCI: Device %s not available because of resource collisions\n", pci_name(dev)); 180 return -EINVAL; 181 } 182 if (r->flags & IORESOURCE_IO) 183 cmd |= PCI_COMMAND_IO; 184 if (r->flags & IORESOURCE_MEM) 185 cmd |= PCI_COMMAND_MEMORY; 186 } 187 if (dev->resource[PCI_ROM_RESOURCE].start) 188 cmd |= PCI_COMMAND_MEMORY; 189 if (cmd != old_cmd) { 190 printk("PCI: Enabling device %s (%04x -> %04x)\n", pci_name(dev), old_cmd, cmd); 191 pci_write_config_word(dev, PCI_COMMAND, cmd); 192 } 193 return 0; 194 } 195 196 /* 197 * If we set up a device for bus mastering, we need to check the latency 198 * timer as certain crappy BIOSes forget to set it properly. 199 */ 200 unsigned int pcibios_max_latency = 255; 201 202 void pcibios_set_master(struct pci_dev *dev) 203 { 204 u8 lat; 205 pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat); 206 if (lat < 16) 207 lat = (64 <= pcibios_max_latency) ? 64 : pcibios_max_latency; 208 else if (lat > pcibios_max_latency) 209 lat = pcibios_max_latency; 210 else 211 return; 212 printk(KERN_DEBUG "PCI: Setting latency timer of device %s to %d\n", 213 pci_name(dev), lat); 214 pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat); 215 } 216 217 unsigned int pcibios_assign_all_busses(void) 218 { 219 return (pci_probe & PCI_ASSIGN_ALL_BUSSES) ? 1 : 0; 220 } 221 222 int pcibios_enable_device(struct pci_dev *dev, int mask) 223 { 224 int err; 225 226 if ((err = pcibios_enable_resources(dev, mask)) < 0) 227 return err; 228 229 return pcibios_plat_dev_init(dev); 230 } 231 232 static void __init pcibios_fixup_device_resources(struct pci_dev *dev, 233 struct pci_bus *bus) 234 { 235 /* Update device resources. */ 236 struct pci_controller *hose = (struct pci_controller *)bus->sysdata; 237 unsigned long offset = 0; 238 int i; 239 240 for (i = 0; i < PCI_NUM_RESOURCES; i++) { 241 if (!dev->resource[i].start) 242 continue; 243 if (dev->resource[i].flags & IORESOURCE_IO) 244 offset = hose->io_offset; 245 else if (dev->resource[i].flags & IORESOURCE_MEM) 246 offset = hose->mem_offset; 247 248 dev->resource[i].start += offset; 249 dev->resource[i].end += offset; 250 } 251 } 252 253 void __devinit pcibios_fixup_bus(struct pci_bus *bus) 254 { 255 /* Propagate hose info into the subordinate devices. */ 256 257 struct pci_controller *hose = bus->sysdata; 258 struct list_head *ln; 259 struct pci_dev *dev = bus->self; 260 261 if (!dev) { 262 bus->resource[0] = hose->io_resource; 263 bus->resource[1] = hose->mem_resource; 264 } else if (pci_probe_only && 265 (dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) { 266 pci_read_bridge_bases(bus); 267 pcibios_fixup_device_resources(dev, bus); 268 } 269 270 for (ln = bus->devices.next; ln != &bus->devices; ln = ln->next) { 271 struct pci_dev *dev = pci_dev_b(ln); 272 273 if ((dev->class >> 8) != PCI_CLASS_BRIDGE_PCI) 274 pcibios_fixup_device_resources(dev, bus); 275 } 276 } 277 278 void __init 279 pcibios_update_irq(struct pci_dev *dev, int irq) 280 { 281 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq); 282 } 283 284 void __devinit 285 pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region, 286 struct resource *res) 287 { 288 struct pci_controller *hose = (struct pci_controller *)dev->sysdata; 289 unsigned long offset = 0; 290 291 if (res->flags & IORESOURCE_IO) 292 offset = hose->io_offset; 293 else if (res->flags & IORESOURCE_MEM) 294 offset = hose->mem_offset; 295 296 region->start = res->start - offset; 297 region->end = res->end - offset; 298 } 299 300 void __devinit 301 pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res, 302 struct pci_bus_region *region) 303 { 304 struct pci_controller *hose = (struct pci_controller *)dev->sysdata; 305 unsigned long offset = 0; 306 307 if (res->flags & IORESOURCE_IO) 308 offset = hose->io_offset; 309 else if (res->flags & IORESOURCE_MEM) 310 offset = hose->mem_offset; 311 312 res->start = region->start + offset; 313 res->end = region->end + offset; 314 } 315 316 #ifdef CONFIG_HOTPLUG 317 EXPORT_SYMBOL(pcibios_resource_to_bus); 318 EXPORT_SYMBOL(pcibios_bus_to_resource); 319 EXPORT_SYMBOL(PCIBIOS_MIN_IO); 320 EXPORT_SYMBOL(PCIBIOS_MIN_MEM); 321 #endif 322 323 char *pcibios_setup(char *str) 324 { 325 return str; 326 } 327