1 /* 2 * This program is free software; you can redistribute it and/or modify it 3 * under the terms of the GNU General Public License as published by the 4 * Free Software Foundation; either version 2 of the License, or (at your 5 * option) any later version. 6 * 7 * Copyright (C) 2003, 04 Ralf Baechle (ralf@linux-mips.org) 8 */ 9 #include <linux/kernel.h> 10 #include <linux/mm.h> 11 #include <linux/bootmem.h> 12 #include <linux/init.h> 13 #include <linux/types.h> 14 #include <linux/pci.h> 15 16 /* 17 * Indicate whether we respect the PCI setup left by the firmware. 18 * 19 * Make this long-lived so that we know when shutting down 20 * whether we probed only or not. 21 */ 22 int pci_probe_only; 23 24 #define PCI_ASSIGN_ALL_BUSSES 1 25 26 unsigned int pci_probe = PCI_ASSIGN_ALL_BUSSES; 27 28 /* 29 * The PCI controller list. 30 */ 31 32 static struct pci_controller *hose_head, **hose_tail = &hose_head; 33 34 unsigned long PCIBIOS_MIN_IO = 0x0000; 35 unsigned long PCIBIOS_MIN_MEM = 0; 36 37 static int pci_initialized; 38 39 /* 40 * We need to avoid collisions with `mirrored' VGA ports 41 * and other strange ISA hardware, so we always want the 42 * addresses to be allocated in the 0x000-0x0ff region 43 * modulo 0x400. 44 * 45 * Why? Because some silly external IO cards only decode 46 * the low 10 bits of the IO address. The 0x00-0xff region 47 * is reserved for motherboard devices that decode all 16 48 * bits, so it's ok to allocate at, say, 0x2800-0x28ff, 49 * but we want to try to avoid allocating at 0x2900-0x2bff 50 * which might have be mirrored at 0x0100-0x03ff.. 51 */ 52 void 53 pcibios_align_resource(void *data, struct resource *res, 54 resource_size_t size, resource_size_t align) 55 { 56 struct pci_dev *dev = data; 57 struct pci_controller *hose = dev->sysdata; 58 resource_size_t start = res->start; 59 60 if (res->flags & IORESOURCE_IO) { 61 /* Make sure we start at our min on all hoses */ 62 if (start < PCIBIOS_MIN_IO + hose->io_resource->start) 63 start = PCIBIOS_MIN_IO + hose->io_resource->start; 64 65 /* 66 * Put everything into 0x00-0xff region modulo 0x400 67 */ 68 if (start & 0x300) 69 start = (start + 0x3ff) & ~0x3ff; 70 } else if (res->flags & IORESOURCE_MEM) { 71 /* Make sure we start at our min on all hoses */ 72 if (start < PCIBIOS_MIN_MEM + hose->mem_resource->start) 73 start = PCIBIOS_MIN_MEM + hose->mem_resource->start; 74 } 75 76 res->start = start; 77 } 78 79 static void __devinit pcibios_scanbus(struct pci_controller *hose) 80 { 81 static int next_busno; 82 static int need_domain_info; 83 struct pci_bus *bus; 84 85 if (!hose->iommu) 86 PCI_DMA_BUS_IS_PHYS = 1; 87 88 if (hose->get_busno && pci_probe_only) 89 next_busno = (*hose->get_busno)(); 90 91 bus = pci_scan_bus(next_busno, hose->pci_ops, hose); 92 hose->bus = bus; 93 94 need_domain_info = need_domain_info || hose->index; 95 hose->need_domain_info = need_domain_info; 96 if (bus) { 97 next_busno = bus->subordinate + 1; 98 /* Don't allow 8-bit bus number overflow inside the hose - 99 reserve some space for bridges. */ 100 if (next_busno > 224) { 101 next_busno = 0; 102 need_domain_info = 1; 103 } 104 105 if (!pci_probe_only) { 106 pci_bus_size_bridges(bus); 107 pci_bus_assign_resources(bus); 108 pci_enable_bridges(bus); 109 } 110 } 111 } 112 113 static DEFINE_MUTEX(pci_scan_mutex); 114 115 void __devinit register_pci_controller(struct pci_controller *hose) 116 { 117 if (request_resource(&iomem_resource, hose->mem_resource) < 0) 118 goto out; 119 if (request_resource(&ioport_resource, hose->io_resource) < 0) { 120 release_resource(hose->mem_resource); 121 goto out; 122 } 123 124 *hose_tail = hose; 125 hose_tail = &hose->next; 126 127 /* 128 * Do not panic here but later - this might hapen before console init. 129 */ 130 if (!hose->io_map_base) { 131 printk(KERN_WARNING 132 "registering PCI controller with io_map_base unset\n"); 133 } 134 135 /* 136 * Scan the bus if it is register after the PCI subsystem 137 * initialization. 138 */ 139 if (pci_initialized) { 140 mutex_lock(&pci_scan_mutex); 141 pcibios_scanbus(hose); 142 mutex_unlock(&pci_scan_mutex); 143 } 144 145 return; 146 147 out: 148 printk(KERN_WARNING 149 "Skipping PCI bus scan due to resource conflict\n"); 150 } 151 152 /* Most MIPS systems have straight-forward swizzling needs. */ 153 154 static inline u8 bridge_swizzle(u8 pin, u8 slot) 155 { 156 return (((pin - 1) + slot) % 4) + 1; 157 } 158 159 static u8 __init common_swizzle(struct pci_dev *dev, u8 *pinp) 160 { 161 u8 pin = *pinp; 162 163 while (dev->bus->parent) { 164 pin = bridge_swizzle(pin, PCI_SLOT(dev->devfn)); 165 /* Move up the chain of bridges. */ 166 dev = dev->bus->self; 167 } 168 *pinp = pin; 169 170 /* The slot is the slot of the last bridge. */ 171 return PCI_SLOT(dev->devfn); 172 } 173 174 static int __init pcibios_init(void) 175 { 176 struct pci_controller *hose; 177 178 /* Scan all of the recorded PCI controllers. */ 179 for (hose = hose_head; hose; hose = hose->next) 180 pcibios_scanbus(hose); 181 182 pci_fixup_irqs(common_swizzle, pcibios_map_irq); 183 184 pci_initialized = 1; 185 186 return 0; 187 } 188 189 subsys_initcall(pcibios_init); 190 191 static int pcibios_enable_resources(struct pci_dev *dev, int mask) 192 { 193 u16 cmd, old_cmd; 194 int idx; 195 struct resource *r; 196 197 pci_read_config_word(dev, PCI_COMMAND, &cmd); 198 old_cmd = cmd; 199 for (idx=0; idx < PCI_NUM_RESOURCES; idx++) { 200 /* Only set up the requested stuff */ 201 if (!(mask & (1<<idx))) 202 continue; 203 204 r = &dev->resource[idx]; 205 if (!(r->flags & (IORESOURCE_IO | IORESOURCE_MEM))) 206 continue; 207 if ((idx == PCI_ROM_RESOURCE) && 208 (!(r->flags & IORESOURCE_ROM_ENABLE))) 209 continue; 210 if (!r->start && r->end) { 211 printk(KERN_ERR "PCI: Device %s not available " 212 "because of resource collisions\n", 213 pci_name(dev)); 214 return -EINVAL; 215 } 216 if (r->flags & IORESOURCE_IO) 217 cmd |= PCI_COMMAND_IO; 218 if (r->flags & IORESOURCE_MEM) 219 cmd |= PCI_COMMAND_MEMORY; 220 } 221 if (cmd != old_cmd) { 222 printk("PCI: Enabling device %s (%04x -> %04x)\n", 223 pci_name(dev), old_cmd, cmd); 224 pci_write_config_word(dev, PCI_COMMAND, cmd); 225 } 226 return 0; 227 } 228 229 /* 230 * If we set up a device for bus mastering, we need to check the latency 231 * timer as certain crappy BIOSes forget to set it properly. 232 */ 233 static unsigned int pcibios_max_latency = 255; 234 235 void pcibios_set_master(struct pci_dev *dev) 236 { 237 u8 lat; 238 pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat); 239 if (lat < 16) 240 lat = (64 <= pcibios_max_latency) ? 64 : pcibios_max_latency; 241 else if (lat > pcibios_max_latency) 242 lat = pcibios_max_latency; 243 else 244 return; 245 printk(KERN_DEBUG "PCI: Setting latency timer of device %s to %d\n", 246 pci_name(dev), lat); 247 pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat); 248 } 249 250 unsigned int pcibios_assign_all_busses(void) 251 { 252 return (pci_probe & PCI_ASSIGN_ALL_BUSSES) ? 1 : 0; 253 } 254 255 int pcibios_enable_device(struct pci_dev *dev, int mask) 256 { 257 int err; 258 259 if ((err = pcibios_enable_resources(dev, mask)) < 0) 260 return err; 261 262 return pcibios_plat_dev_init(dev); 263 } 264 265 static void pcibios_fixup_device_resources(struct pci_dev *dev, 266 struct pci_bus *bus) 267 { 268 /* Update device resources. */ 269 struct pci_controller *hose = (struct pci_controller *)bus->sysdata; 270 unsigned long offset = 0; 271 int i; 272 273 for (i = 0; i < PCI_NUM_RESOURCES; i++) { 274 if (!dev->resource[i].start) 275 continue; 276 if (dev->resource[i].flags & IORESOURCE_PCI_FIXED) 277 continue; 278 if (dev->resource[i].flags & IORESOURCE_IO) 279 offset = hose->io_offset; 280 else if (dev->resource[i].flags & IORESOURCE_MEM) 281 offset = hose->mem_offset; 282 283 dev->resource[i].start += offset; 284 dev->resource[i].end += offset; 285 } 286 } 287 288 void __devinit pcibios_fixup_bus(struct pci_bus *bus) 289 { 290 /* Propagate hose info into the subordinate devices. */ 291 292 struct pci_controller *hose = bus->sysdata; 293 struct list_head *ln; 294 struct pci_dev *dev = bus->self; 295 296 if (!dev) { 297 bus->resource[0] = hose->io_resource; 298 bus->resource[1] = hose->mem_resource; 299 } else if (pci_probe_only && 300 (dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) { 301 pci_read_bridge_bases(bus); 302 pcibios_fixup_device_resources(dev, bus); 303 } 304 305 for (ln = bus->devices.next; ln != &bus->devices; ln = ln->next) { 306 dev = pci_dev_b(ln); 307 308 if ((dev->class >> 8) != PCI_CLASS_BRIDGE_PCI) 309 pcibios_fixup_device_resources(dev, bus); 310 } 311 } 312 313 void __init 314 pcibios_update_irq(struct pci_dev *dev, int irq) 315 { 316 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq); 317 } 318 319 void pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region, 320 struct resource *res) 321 { 322 struct pci_controller *hose = (struct pci_controller *)dev->sysdata; 323 unsigned long offset = 0; 324 325 if (res->flags & IORESOURCE_IO) 326 offset = hose->io_offset; 327 else if (res->flags & IORESOURCE_MEM) 328 offset = hose->mem_offset; 329 330 region->start = res->start - offset; 331 region->end = res->end - offset; 332 } 333 334 void __devinit 335 pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res, 336 struct pci_bus_region *region) 337 { 338 struct pci_controller *hose = (struct pci_controller *)dev->sysdata; 339 unsigned long offset = 0; 340 341 if (res->flags & IORESOURCE_IO) 342 offset = hose->io_offset; 343 else if (res->flags & IORESOURCE_MEM) 344 offset = hose->mem_offset; 345 346 res->start = region->start + offset; 347 res->end = region->end + offset; 348 } 349 350 #ifdef CONFIG_HOTPLUG 351 EXPORT_SYMBOL(pcibios_resource_to_bus); 352 EXPORT_SYMBOL(pcibios_bus_to_resource); 353 EXPORT_SYMBOL(PCIBIOS_MIN_IO); 354 EXPORT_SYMBOL(PCIBIOS_MIN_MEM); 355 #endif 356 357 char * (*pcibios_plat_setup)(char *str) __devinitdata; 358 359 char *__devinit pcibios_setup(char *str) 360 { 361 if (pcibios_plat_setup) 362 return pcibios_plat_setup(str); 363 return str; 364 } 365