1*12d14e0eSGabor Juhos /* 2*12d14e0eSGabor Juhos * Ralink RT3662/RT3883 SoC PCI support 3*12d14e0eSGabor Juhos * 4*12d14e0eSGabor Juhos * Copyright (C) 2011-2013 Gabor Juhos <juhosg@openwrt.org> 5*12d14e0eSGabor Juhos * 6*12d14e0eSGabor Juhos * Parts of this file are based on Ralink's 2.6.21 BSP 7*12d14e0eSGabor Juhos * 8*12d14e0eSGabor Juhos * This program is free software; you can redistribute it and/or modify it 9*12d14e0eSGabor Juhos * under the terms of the GNU General Public License version 2 as published 10*12d14e0eSGabor Juhos * by the Free Software Foundation. 11*12d14e0eSGabor Juhos */ 12*12d14e0eSGabor Juhos 13*12d14e0eSGabor Juhos #include <linux/types.h> 14*12d14e0eSGabor Juhos #include <linux/pci.h> 15*12d14e0eSGabor Juhos #include <linux/io.h> 16*12d14e0eSGabor Juhos #include <linux/init.h> 17*12d14e0eSGabor Juhos #include <linux/delay.h> 18*12d14e0eSGabor Juhos #include <linux/interrupt.h> 19*12d14e0eSGabor Juhos #include <linux/module.h> 20*12d14e0eSGabor Juhos #include <linux/of.h> 21*12d14e0eSGabor Juhos #include <linux/of_irq.h> 22*12d14e0eSGabor Juhos #include <linux/of_pci.h> 23*12d14e0eSGabor Juhos #include <linux/platform_device.h> 24*12d14e0eSGabor Juhos 25*12d14e0eSGabor Juhos #include <asm/mach-ralink/rt3883.h> 26*12d14e0eSGabor Juhos #include <asm/mach-ralink/ralink_regs.h> 27*12d14e0eSGabor Juhos 28*12d14e0eSGabor Juhos #define RT3883_MEMORY_BASE 0x00000000 29*12d14e0eSGabor Juhos #define RT3883_MEMORY_SIZE 0x02000000 30*12d14e0eSGabor Juhos 31*12d14e0eSGabor Juhos #define RT3883_PCI_REG_PCICFG 0x00 32*12d14e0eSGabor Juhos #define RT3883_PCICFG_P2P_BR_DEVNUM_M 0xf 33*12d14e0eSGabor Juhos #define RT3883_PCICFG_P2P_BR_DEVNUM_S 16 34*12d14e0eSGabor Juhos #define RT3883_PCICFG_PCIRST BIT(1) 35*12d14e0eSGabor Juhos #define RT3883_PCI_REG_PCIRAW 0x04 36*12d14e0eSGabor Juhos #define RT3883_PCI_REG_PCIINT 0x08 37*12d14e0eSGabor Juhos #define RT3883_PCI_REG_PCIENA 0x0c 38*12d14e0eSGabor Juhos 39*12d14e0eSGabor Juhos #define RT3883_PCI_REG_CFGADDR 0x20 40*12d14e0eSGabor Juhos #define RT3883_PCI_REG_CFGDATA 0x24 41*12d14e0eSGabor Juhos #define RT3883_PCI_REG_MEMBASE 0x28 42*12d14e0eSGabor Juhos #define RT3883_PCI_REG_IOBASE 0x2c 43*12d14e0eSGabor Juhos #define RT3883_PCI_REG_ARBCTL 0x80 44*12d14e0eSGabor Juhos 45*12d14e0eSGabor Juhos #define RT3883_PCI_REG_BASE(_x) (0x1000 + (_x) * 0x1000) 46*12d14e0eSGabor Juhos #define RT3883_PCI_REG_BAR0SETUP(_x) (RT3883_PCI_REG_BASE((_x)) + 0x10) 47*12d14e0eSGabor Juhos #define RT3883_PCI_REG_IMBASEBAR0(_x) (RT3883_PCI_REG_BASE((_x)) + 0x18) 48*12d14e0eSGabor Juhos #define RT3883_PCI_REG_ID(_x) (RT3883_PCI_REG_BASE((_x)) + 0x30) 49*12d14e0eSGabor Juhos #define RT3883_PCI_REG_CLASS(_x) (RT3883_PCI_REG_BASE((_x)) + 0x34) 50*12d14e0eSGabor Juhos #define RT3883_PCI_REG_SUBID(_x) (RT3883_PCI_REG_BASE((_x)) + 0x38) 51*12d14e0eSGabor Juhos #define RT3883_PCI_REG_STATUS(_x) (RT3883_PCI_REG_BASE((_x)) + 0x50) 52*12d14e0eSGabor Juhos 53*12d14e0eSGabor Juhos #define RT3883_PCI_MODE_NONE 0 54*12d14e0eSGabor Juhos #define RT3883_PCI_MODE_PCI BIT(0) 55*12d14e0eSGabor Juhos #define RT3883_PCI_MODE_PCIE BIT(1) 56*12d14e0eSGabor Juhos #define RT3883_PCI_MODE_BOTH (RT3883_PCI_MODE_PCI | RT3883_PCI_MODE_PCIE) 57*12d14e0eSGabor Juhos 58*12d14e0eSGabor Juhos #define RT3883_PCI_IRQ_COUNT 32 59*12d14e0eSGabor Juhos 60*12d14e0eSGabor Juhos #define RT3883_P2P_BR_DEVNUM 1 61*12d14e0eSGabor Juhos 62*12d14e0eSGabor Juhos struct rt3883_pci_controller { 63*12d14e0eSGabor Juhos void __iomem *base; 64*12d14e0eSGabor Juhos spinlock_t lock; 65*12d14e0eSGabor Juhos 66*12d14e0eSGabor Juhos struct device_node *intc_of_node; 67*12d14e0eSGabor Juhos struct irq_domain *irq_domain; 68*12d14e0eSGabor Juhos 69*12d14e0eSGabor Juhos struct pci_controller pci_controller; 70*12d14e0eSGabor Juhos struct resource io_res; 71*12d14e0eSGabor Juhos struct resource mem_res; 72*12d14e0eSGabor Juhos 73*12d14e0eSGabor Juhos bool pcie_ready; 74*12d14e0eSGabor Juhos }; 75*12d14e0eSGabor Juhos 76*12d14e0eSGabor Juhos static inline struct rt3883_pci_controller * 77*12d14e0eSGabor Juhos pci_bus_to_rt3883_controller(struct pci_bus *bus) 78*12d14e0eSGabor Juhos { 79*12d14e0eSGabor Juhos struct pci_controller *hose; 80*12d14e0eSGabor Juhos 81*12d14e0eSGabor Juhos hose = (struct pci_controller *) bus->sysdata; 82*12d14e0eSGabor Juhos return container_of(hose, struct rt3883_pci_controller, pci_controller); 83*12d14e0eSGabor Juhos } 84*12d14e0eSGabor Juhos 85*12d14e0eSGabor Juhos static inline u32 rt3883_pci_r32(struct rt3883_pci_controller *rpc, 86*12d14e0eSGabor Juhos unsigned reg) 87*12d14e0eSGabor Juhos { 88*12d14e0eSGabor Juhos return ioread32(rpc->base + reg); 89*12d14e0eSGabor Juhos } 90*12d14e0eSGabor Juhos 91*12d14e0eSGabor Juhos static inline void rt3883_pci_w32(struct rt3883_pci_controller *rpc, 92*12d14e0eSGabor Juhos u32 val, unsigned reg) 93*12d14e0eSGabor Juhos { 94*12d14e0eSGabor Juhos iowrite32(val, rpc->base + reg); 95*12d14e0eSGabor Juhos } 96*12d14e0eSGabor Juhos 97*12d14e0eSGabor Juhos static inline u32 rt3883_pci_get_cfgaddr(unsigned int bus, unsigned int slot, 98*12d14e0eSGabor Juhos unsigned int func, unsigned int where) 99*12d14e0eSGabor Juhos { 100*12d14e0eSGabor Juhos return (bus << 16) | (slot << 11) | (func << 8) | (where & 0xfc) | 101*12d14e0eSGabor Juhos 0x80000000; 102*12d14e0eSGabor Juhos } 103*12d14e0eSGabor Juhos 104*12d14e0eSGabor Juhos static u32 rt3883_pci_read_cfg32(struct rt3883_pci_controller *rpc, 105*12d14e0eSGabor Juhos unsigned bus, unsigned slot, 106*12d14e0eSGabor Juhos unsigned func, unsigned reg) 107*12d14e0eSGabor Juhos { 108*12d14e0eSGabor Juhos unsigned long flags; 109*12d14e0eSGabor Juhos u32 address; 110*12d14e0eSGabor Juhos u32 ret; 111*12d14e0eSGabor Juhos 112*12d14e0eSGabor Juhos address = rt3883_pci_get_cfgaddr(bus, slot, func, reg); 113*12d14e0eSGabor Juhos 114*12d14e0eSGabor Juhos spin_lock_irqsave(&rpc->lock, flags); 115*12d14e0eSGabor Juhos rt3883_pci_w32(rpc, address, RT3883_PCI_REG_CFGADDR); 116*12d14e0eSGabor Juhos ret = rt3883_pci_r32(rpc, RT3883_PCI_REG_CFGDATA); 117*12d14e0eSGabor Juhos spin_unlock_irqrestore(&rpc->lock, flags); 118*12d14e0eSGabor Juhos 119*12d14e0eSGabor Juhos return ret; 120*12d14e0eSGabor Juhos } 121*12d14e0eSGabor Juhos 122*12d14e0eSGabor Juhos static void rt3883_pci_write_cfg32(struct rt3883_pci_controller *rpc, 123*12d14e0eSGabor Juhos unsigned bus, unsigned slot, 124*12d14e0eSGabor Juhos unsigned func, unsigned reg, u32 val) 125*12d14e0eSGabor Juhos { 126*12d14e0eSGabor Juhos unsigned long flags; 127*12d14e0eSGabor Juhos u32 address; 128*12d14e0eSGabor Juhos 129*12d14e0eSGabor Juhos address = rt3883_pci_get_cfgaddr(bus, slot, func, reg); 130*12d14e0eSGabor Juhos 131*12d14e0eSGabor Juhos spin_lock_irqsave(&rpc->lock, flags); 132*12d14e0eSGabor Juhos rt3883_pci_w32(rpc, address, RT3883_PCI_REG_CFGADDR); 133*12d14e0eSGabor Juhos rt3883_pci_w32(rpc, val, RT3883_PCI_REG_CFGDATA); 134*12d14e0eSGabor Juhos spin_unlock_irqrestore(&rpc->lock, flags); 135*12d14e0eSGabor Juhos } 136*12d14e0eSGabor Juhos 137*12d14e0eSGabor Juhos static void rt3883_pci_irq_handler(unsigned int irq, struct irq_desc *desc) 138*12d14e0eSGabor Juhos { 139*12d14e0eSGabor Juhos struct rt3883_pci_controller *rpc; 140*12d14e0eSGabor Juhos u32 pending; 141*12d14e0eSGabor Juhos 142*12d14e0eSGabor Juhos rpc = irq_get_handler_data(irq); 143*12d14e0eSGabor Juhos 144*12d14e0eSGabor Juhos pending = rt3883_pci_r32(rpc, RT3883_PCI_REG_PCIINT) & 145*12d14e0eSGabor Juhos rt3883_pci_r32(rpc, RT3883_PCI_REG_PCIENA); 146*12d14e0eSGabor Juhos 147*12d14e0eSGabor Juhos if (!pending) { 148*12d14e0eSGabor Juhos spurious_interrupt(); 149*12d14e0eSGabor Juhos return; 150*12d14e0eSGabor Juhos } 151*12d14e0eSGabor Juhos 152*12d14e0eSGabor Juhos while (pending) { 153*12d14e0eSGabor Juhos unsigned bit = __ffs(pending); 154*12d14e0eSGabor Juhos 155*12d14e0eSGabor Juhos irq = irq_find_mapping(rpc->irq_domain, bit); 156*12d14e0eSGabor Juhos generic_handle_irq(irq); 157*12d14e0eSGabor Juhos 158*12d14e0eSGabor Juhos pending &= ~BIT(bit); 159*12d14e0eSGabor Juhos } 160*12d14e0eSGabor Juhos } 161*12d14e0eSGabor Juhos 162*12d14e0eSGabor Juhos static void rt3883_pci_irq_unmask(struct irq_data *d) 163*12d14e0eSGabor Juhos { 164*12d14e0eSGabor Juhos struct rt3883_pci_controller *rpc; 165*12d14e0eSGabor Juhos u32 t; 166*12d14e0eSGabor Juhos 167*12d14e0eSGabor Juhos rpc = irq_data_get_irq_chip_data(d); 168*12d14e0eSGabor Juhos 169*12d14e0eSGabor Juhos t = rt3883_pci_r32(rpc, RT3883_PCI_REG_PCIENA); 170*12d14e0eSGabor Juhos rt3883_pci_w32(rpc, t | BIT(d->hwirq), RT3883_PCI_REG_PCIENA); 171*12d14e0eSGabor Juhos /* flush write */ 172*12d14e0eSGabor Juhos rt3883_pci_r32(rpc, RT3883_PCI_REG_PCIENA); 173*12d14e0eSGabor Juhos } 174*12d14e0eSGabor Juhos 175*12d14e0eSGabor Juhos static void rt3883_pci_irq_mask(struct irq_data *d) 176*12d14e0eSGabor Juhos { 177*12d14e0eSGabor Juhos struct rt3883_pci_controller *rpc; 178*12d14e0eSGabor Juhos u32 t; 179*12d14e0eSGabor Juhos 180*12d14e0eSGabor Juhos rpc = irq_data_get_irq_chip_data(d); 181*12d14e0eSGabor Juhos 182*12d14e0eSGabor Juhos t = rt3883_pci_r32(rpc, RT3883_PCI_REG_PCIENA); 183*12d14e0eSGabor Juhos rt3883_pci_w32(rpc, t & ~BIT(d->hwirq), RT3883_PCI_REG_PCIENA); 184*12d14e0eSGabor Juhos /* flush write */ 185*12d14e0eSGabor Juhos rt3883_pci_r32(rpc, RT3883_PCI_REG_PCIENA); 186*12d14e0eSGabor Juhos } 187*12d14e0eSGabor Juhos 188*12d14e0eSGabor Juhos static struct irq_chip rt3883_pci_irq_chip = { 189*12d14e0eSGabor Juhos .name = "RT3883 PCI", 190*12d14e0eSGabor Juhos .irq_mask = rt3883_pci_irq_mask, 191*12d14e0eSGabor Juhos .irq_unmask = rt3883_pci_irq_unmask, 192*12d14e0eSGabor Juhos .irq_mask_ack = rt3883_pci_irq_mask, 193*12d14e0eSGabor Juhos }; 194*12d14e0eSGabor Juhos 195*12d14e0eSGabor Juhos static int rt3883_pci_irq_map(struct irq_domain *d, unsigned int irq, 196*12d14e0eSGabor Juhos irq_hw_number_t hw) 197*12d14e0eSGabor Juhos { 198*12d14e0eSGabor Juhos irq_set_chip_and_handler(irq, &rt3883_pci_irq_chip, handle_level_irq); 199*12d14e0eSGabor Juhos irq_set_chip_data(irq, d->host_data); 200*12d14e0eSGabor Juhos 201*12d14e0eSGabor Juhos return 0; 202*12d14e0eSGabor Juhos } 203*12d14e0eSGabor Juhos 204*12d14e0eSGabor Juhos static const struct irq_domain_ops rt3883_pci_irq_domain_ops = { 205*12d14e0eSGabor Juhos .map = rt3883_pci_irq_map, 206*12d14e0eSGabor Juhos .xlate = irq_domain_xlate_onecell, 207*12d14e0eSGabor Juhos }; 208*12d14e0eSGabor Juhos 209*12d14e0eSGabor Juhos static int rt3883_pci_irq_init(struct device *dev, 210*12d14e0eSGabor Juhos struct rt3883_pci_controller *rpc) 211*12d14e0eSGabor Juhos { 212*12d14e0eSGabor Juhos int irq; 213*12d14e0eSGabor Juhos 214*12d14e0eSGabor Juhos irq = irq_of_parse_and_map(rpc->intc_of_node, 0); 215*12d14e0eSGabor Juhos if (irq == 0) { 216*12d14e0eSGabor Juhos dev_err(dev, "%s has no IRQ", 217*12d14e0eSGabor Juhos of_node_full_name(rpc->intc_of_node)); 218*12d14e0eSGabor Juhos return -EINVAL; 219*12d14e0eSGabor Juhos } 220*12d14e0eSGabor Juhos 221*12d14e0eSGabor Juhos /* disable all interrupts */ 222*12d14e0eSGabor Juhos rt3883_pci_w32(rpc, 0, RT3883_PCI_REG_PCIENA); 223*12d14e0eSGabor Juhos 224*12d14e0eSGabor Juhos rpc->irq_domain = 225*12d14e0eSGabor Juhos irq_domain_add_linear(rpc->intc_of_node, RT3883_PCI_IRQ_COUNT, 226*12d14e0eSGabor Juhos &rt3883_pci_irq_domain_ops, 227*12d14e0eSGabor Juhos rpc); 228*12d14e0eSGabor Juhos if (!rpc->irq_domain) { 229*12d14e0eSGabor Juhos dev_err(dev, "unable to add IRQ domain\n"); 230*12d14e0eSGabor Juhos return -ENODEV; 231*12d14e0eSGabor Juhos } 232*12d14e0eSGabor Juhos 233*12d14e0eSGabor Juhos irq_set_handler_data(irq, rpc); 234*12d14e0eSGabor Juhos irq_set_chained_handler(irq, rt3883_pci_irq_handler); 235*12d14e0eSGabor Juhos 236*12d14e0eSGabor Juhos return 0; 237*12d14e0eSGabor Juhos } 238*12d14e0eSGabor Juhos 239*12d14e0eSGabor Juhos static int rt3883_pci_config_read(struct pci_bus *bus, unsigned int devfn, 240*12d14e0eSGabor Juhos int where, int size, u32 *val) 241*12d14e0eSGabor Juhos { 242*12d14e0eSGabor Juhos struct rt3883_pci_controller *rpc; 243*12d14e0eSGabor Juhos unsigned long flags; 244*12d14e0eSGabor Juhos u32 address; 245*12d14e0eSGabor Juhos u32 data; 246*12d14e0eSGabor Juhos 247*12d14e0eSGabor Juhos rpc = pci_bus_to_rt3883_controller(bus); 248*12d14e0eSGabor Juhos 249*12d14e0eSGabor Juhos if (!rpc->pcie_ready && bus->number == 1) 250*12d14e0eSGabor Juhos return PCIBIOS_DEVICE_NOT_FOUND; 251*12d14e0eSGabor Juhos 252*12d14e0eSGabor Juhos address = rt3883_pci_get_cfgaddr(bus->number, PCI_SLOT(devfn), 253*12d14e0eSGabor Juhos PCI_FUNC(devfn), where); 254*12d14e0eSGabor Juhos 255*12d14e0eSGabor Juhos spin_lock_irqsave(&rpc->lock, flags); 256*12d14e0eSGabor Juhos rt3883_pci_w32(rpc, address, RT3883_PCI_REG_CFGADDR); 257*12d14e0eSGabor Juhos data = rt3883_pci_r32(rpc, RT3883_PCI_REG_CFGDATA); 258*12d14e0eSGabor Juhos spin_unlock_irqrestore(&rpc->lock, flags); 259*12d14e0eSGabor Juhos 260*12d14e0eSGabor Juhos switch (size) { 261*12d14e0eSGabor Juhos case 1: 262*12d14e0eSGabor Juhos *val = (data >> ((where & 3) << 3)) & 0xff; 263*12d14e0eSGabor Juhos break; 264*12d14e0eSGabor Juhos case 2: 265*12d14e0eSGabor Juhos *val = (data >> ((where & 3) << 3)) & 0xffff; 266*12d14e0eSGabor Juhos break; 267*12d14e0eSGabor Juhos case 4: 268*12d14e0eSGabor Juhos *val = data; 269*12d14e0eSGabor Juhos break; 270*12d14e0eSGabor Juhos } 271*12d14e0eSGabor Juhos 272*12d14e0eSGabor Juhos return PCIBIOS_SUCCESSFUL; 273*12d14e0eSGabor Juhos } 274*12d14e0eSGabor Juhos 275*12d14e0eSGabor Juhos static int rt3883_pci_config_write(struct pci_bus *bus, unsigned int devfn, 276*12d14e0eSGabor Juhos int where, int size, u32 val) 277*12d14e0eSGabor Juhos { 278*12d14e0eSGabor Juhos struct rt3883_pci_controller *rpc; 279*12d14e0eSGabor Juhos unsigned long flags; 280*12d14e0eSGabor Juhos u32 address; 281*12d14e0eSGabor Juhos u32 data; 282*12d14e0eSGabor Juhos 283*12d14e0eSGabor Juhos rpc = pci_bus_to_rt3883_controller(bus); 284*12d14e0eSGabor Juhos 285*12d14e0eSGabor Juhos if (!rpc->pcie_ready && bus->number == 1) 286*12d14e0eSGabor Juhos return PCIBIOS_DEVICE_NOT_FOUND; 287*12d14e0eSGabor Juhos 288*12d14e0eSGabor Juhos address = rt3883_pci_get_cfgaddr(bus->number, PCI_SLOT(devfn), 289*12d14e0eSGabor Juhos PCI_FUNC(devfn), where); 290*12d14e0eSGabor Juhos 291*12d14e0eSGabor Juhos spin_lock_irqsave(&rpc->lock, flags); 292*12d14e0eSGabor Juhos rt3883_pci_w32(rpc, address, RT3883_PCI_REG_CFGADDR); 293*12d14e0eSGabor Juhos data = rt3883_pci_r32(rpc, RT3883_PCI_REG_CFGDATA); 294*12d14e0eSGabor Juhos 295*12d14e0eSGabor Juhos switch (size) { 296*12d14e0eSGabor Juhos case 1: 297*12d14e0eSGabor Juhos data = (data & ~(0xff << ((where & 3) << 3))) | 298*12d14e0eSGabor Juhos (val << ((where & 3) << 3)); 299*12d14e0eSGabor Juhos break; 300*12d14e0eSGabor Juhos case 2: 301*12d14e0eSGabor Juhos data = (data & ~(0xffff << ((where & 3) << 3))) | 302*12d14e0eSGabor Juhos (val << ((where & 3) << 3)); 303*12d14e0eSGabor Juhos break; 304*12d14e0eSGabor Juhos case 4: 305*12d14e0eSGabor Juhos data = val; 306*12d14e0eSGabor Juhos break; 307*12d14e0eSGabor Juhos } 308*12d14e0eSGabor Juhos 309*12d14e0eSGabor Juhos rt3883_pci_w32(rpc, data, RT3883_PCI_REG_CFGDATA); 310*12d14e0eSGabor Juhos spin_unlock_irqrestore(&rpc->lock, flags); 311*12d14e0eSGabor Juhos 312*12d14e0eSGabor Juhos return PCIBIOS_SUCCESSFUL; 313*12d14e0eSGabor Juhos } 314*12d14e0eSGabor Juhos 315*12d14e0eSGabor Juhos static struct pci_ops rt3883_pci_ops = { 316*12d14e0eSGabor Juhos .read = rt3883_pci_config_read, 317*12d14e0eSGabor Juhos .write = rt3883_pci_config_write, 318*12d14e0eSGabor Juhos }; 319*12d14e0eSGabor Juhos 320*12d14e0eSGabor Juhos static void rt3883_pci_preinit(struct rt3883_pci_controller *rpc, unsigned mode) 321*12d14e0eSGabor Juhos { 322*12d14e0eSGabor Juhos u32 syscfg1; 323*12d14e0eSGabor Juhos u32 rstctrl; 324*12d14e0eSGabor Juhos u32 clkcfg1; 325*12d14e0eSGabor Juhos u32 t; 326*12d14e0eSGabor Juhos 327*12d14e0eSGabor Juhos rstctrl = rt_sysc_r32(RT3883_SYSC_REG_RSTCTRL); 328*12d14e0eSGabor Juhos syscfg1 = rt_sysc_r32(RT3883_SYSC_REG_SYSCFG1); 329*12d14e0eSGabor Juhos clkcfg1 = rt_sysc_r32(RT3883_SYSC_REG_CLKCFG1); 330*12d14e0eSGabor Juhos 331*12d14e0eSGabor Juhos if (mode & RT3883_PCI_MODE_PCIE) { 332*12d14e0eSGabor Juhos rstctrl |= RT3883_RSTCTRL_PCIE; 333*12d14e0eSGabor Juhos rt_sysc_w32(rstctrl, RT3883_SYSC_REG_RSTCTRL); 334*12d14e0eSGabor Juhos 335*12d14e0eSGabor Juhos /* setup PCI PAD drive mode */ 336*12d14e0eSGabor Juhos syscfg1 &= ~(0x30); 337*12d14e0eSGabor Juhos syscfg1 |= (2 << 4); 338*12d14e0eSGabor Juhos rt_sysc_w32(syscfg1, RT3883_SYSC_REG_SYSCFG1); 339*12d14e0eSGabor Juhos 340*12d14e0eSGabor Juhos t = rt_sysc_r32(RT3883_SYSC_REG_PCIE_CLK_GEN0); 341*12d14e0eSGabor Juhos t &= ~BIT(31); 342*12d14e0eSGabor Juhos rt_sysc_w32(t, RT3883_SYSC_REG_PCIE_CLK_GEN0); 343*12d14e0eSGabor Juhos 344*12d14e0eSGabor Juhos t = rt_sysc_r32(RT3883_SYSC_REG_PCIE_CLK_GEN1); 345*12d14e0eSGabor Juhos t &= 0x80ffffff; 346*12d14e0eSGabor Juhos rt_sysc_w32(t, RT3883_SYSC_REG_PCIE_CLK_GEN1); 347*12d14e0eSGabor Juhos 348*12d14e0eSGabor Juhos t = rt_sysc_r32(RT3883_SYSC_REG_PCIE_CLK_GEN1); 349*12d14e0eSGabor Juhos t |= 0xa << 24; 350*12d14e0eSGabor Juhos rt_sysc_w32(t, RT3883_SYSC_REG_PCIE_CLK_GEN1); 351*12d14e0eSGabor Juhos 352*12d14e0eSGabor Juhos t = rt_sysc_r32(RT3883_SYSC_REG_PCIE_CLK_GEN0); 353*12d14e0eSGabor Juhos t |= BIT(31); 354*12d14e0eSGabor Juhos rt_sysc_w32(t, RT3883_SYSC_REG_PCIE_CLK_GEN0); 355*12d14e0eSGabor Juhos 356*12d14e0eSGabor Juhos msleep(50); 357*12d14e0eSGabor Juhos 358*12d14e0eSGabor Juhos rstctrl &= ~RT3883_RSTCTRL_PCIE; 359*12d14e0eSGabor Juhos rt_sysc_w32(rstctrl, RT3883_SYSC_REG_RSTCTRL); 360*12d14e0eSGabor Juhos } 361*12d14e0eSGabor Juhos 362*12d14e0eSGabor Juhos syscfg1 |= (RT3883_SYSCFG1_PCIE_RC_MODE | RT3883_SYSCFG1_PCI_HOST_MODE); 363*12d14e0eSGabor Juhos 364*12d14e0eSGabor Juhos clkcfg1 &= ~(RT3883_CLKCFG1_PCI_CLK_EN | RT3883_CLKCFG1_PCIE_CLK_EN); 365*12d14e0eSGabor Juhos 366*12d14e0eSGabor Juhos if (mode & RT3883_PCI_MODE_PCI) { 367*12d14e0eSGabor Juhos clkcfg1 |= RT3883_CLKCFG1_PCI_CLK_EN; 368*12d14e0eSGabor Juhos rstctrl &= ~RT3883_RSTCTRL_PCI; 369*12d14e0eSGabor Juhos } 370*12d14e0eSGabor Juhos 371*12d14e0eSGabor Juhos if (mode & RT3883_PCI_MODE_PCIE) { 372*12d14e0eSGabor Juhos clkcfg1 |= RT3883_CLKCFG1_PCIE_CLK_EN; 373*12d14e0eSGabor Juhos rstctrl &= ~RT3883_RSTCTRL_PCIE; 374*12d14e0eSGabor Juhos } 375*12d14e0eSGabor Juhos 376*12d14e0eSGabor Juhos rt_sysc_w32(syscfg1, RT3883_SYSC_REG_SYSCFG1); 377*12d14e0eSGabor Juhos rt_sysc_w32(rstctrl, RT3883_SYSC_REG_RSTCTRL); 378*12d14e0eSGabor Juhos rt_sysc_w32(clkcfg1, RT3883_SYSC_REG_CLKCFG1); 379*12d14e0eSGabor Juhos 380*12d14e0eSGabor Juhos msleep(500); 381*12d14e0eSGabor Juhos 382*12d14e0eSGabor Juhos /* 383*12d14e0eSGabor Juhos * setup the device number of the P2P bridge 384*12d14e0eSGabor Juhos * and de-assert the reset line 385*12d14e0eSGabor Juhos */ 386*12d14e0eSGabor Juhos t = (RT3883_P2P_BR_DEVNUM << RT3883_PCICFG_P2P_BR_DEVNUM_S); 387*12d14e0eSGabor Juhos rt3883_pci_w32(rpc, t, RT3883_PCI_REG_PCICFG); 388*12d14e0eSGabor Juhos 389*12d14e0eSGabor Juhos /* flush write */ 390*12d14e0eSGabor Juhos rt3883_pci_r32(rpc, RT3883_PCI_REG_PCICFG); 391*12d14e0eSGabor Juhos msleep(500); 392*12d14e0eSGabor Juhos 393*12d14e0eSGabor Juhos if (mode & RT3883_PCI_MODE_PCIE) { 394*12d14e0eSGabor Juhos msleep(500); 395*12d14e0eSGabor Juhos 396*12d14e0eSGabor Juhos t = rt3883_pci_r32(rpc, RT3883_PCI_REG_STATUS(1)); 397*12d14e0eSGabor Juhos 398*12d14e0eSGabor Juhos rpc->pcie_ready = t & BIT(0); 399*12d14e0eSGabor Juhos 400*12d14e0eSGabor Juhos if (!rpc->pcie_ready) { 401*12d14e0eSGabor Juhos /* reset the PCIe block */ 402*12d14e0eSGabor Juhos t = rt_sysc_r32(RT3883_SYSC_REG_RSTCTRL); 403*12d14e0eSGabor Juhos t |= RT3883_RSTCTRL_PCIE; 404*12d14e0eSGabor Juhos rt_sysc_w32(t, RT3883_SYSC_REG_RSTCTRL); 405*12d14e0eSGabor Juhos t &= ~RT3883_RSTCTRL_PCIE; 406*12d14e0eSGabor Juhos rt_sysc_w32(t, RT3883_SYSC_REG_RSTCTRL); 407*12d14e0eSGabor Juhos 408*12d14e0eSGabor Juhos /* turn off PCIe clock */ 409*12d14e0eSGabor Juhos t = rt_sysc_r32(RT3883_SYSC_REG_CLKCFG1); 410*12d14e0eSGabor Juhos t &= ~RT3883_CLKCFG1_PCIE_CLK_EN; 411*12d14e0eSGabor Juhos rt_sysc_w32(t, RT3883_SYSC_REG_CLKCFG1); 412*12d14e0eSGabor Juhos 413*12d14e0eSGabor Juhos t = rt_sysc_r32(RT3883_SYSC_REG_PCIE_CLK_GEN0); 414*12d14e0eSGabor Juhos t &= ~0xf000c080; 415*12d14e0eSGabor Juhos rt_sysc_w32(t, RT3883_SYSC_REG_PCIE_CLK_GEN0); 416*12d14e0eSGabor Juhos } 417*12d14e0eSGabor Juhos } 418*12d14e0eSGabor Juhos 419*12d14e0eSGabor Juhos /* enable PCI arbiter */ 420*12d14e0eSGabor Juhos rt3883_pci_w32(rpc, 0x79, RT3883_PCI_REG_ARBCTL); 421*12d14e0eSGabor Juhos } 422*12d14e0eSGabor Juhos 423*12d14e0eSGabor Juhos static int rt3883_pci_probe(struct platform_device *pdev) 424*12d14e0eSGabor Juhos { 425*12d14e0eSGabor Juhos struct rt3883_pci_controller *rpc; 426*12d14e0eSGabor Juhos struct device *dev = &pdev->dev; 427*12d14e0eSGabor Juhos struct device_node *np = dev->of_node; 428*12d14e0eSGabor Juhos struct resource *res; 429*12d14e0eSGabor Juhos struct device_node *child; 430*12d14e0eSGabor Juhos u32 val; 431*12d14e0eSGabor Juhos int err; 432*12d14e0eSGabor Juhos int mode; 433*12d14e0eSGabor Juhos 434*12d14e0eSGabor Juhos rpc = devm_kzalloc(dev, sizeof(*rpc), GFP_KERNEL); 435*12d14e0eSGabor Juhos if (!rpc) 436*12d14e0eSGabor Juhos return -ENOMEM; 437*12d14e0eSGabor Juhos 438*12d14e0eSGabor Juhos res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 439*12d14e0eSGabor Juhos if (!res) 440*12d14e0eSGabor Juhos return -EINVAL; 441*12d14e0eSGabor Juhos 442*12d14e0eSGabor Juhos rpc->base = devm_ioremap_resource(dev, res); 443*12d14e0eSGabor Juhos if (IS_ERR(rpc->base)) 444*12d14e0eSGabor Juhos return PTR_ERR(rpc->base); 445*12d14e0eSGabor Juhos 446*12d14e0eSGabor Juhos /* find the interrupt controller child node */ 447*12d14e0eSGabor Juhos for_each_child_of_node(np, child) { 448*12d14e0eSGabor Juhos if (of_get_property(child, "interrupt-controller", NULL) && 449*12d14e0eSGabor Juhos of_node_get(child)) { 450*12d14e0eSGabor Juhos rpc->intc_of_node = child; 451*12d14e0eSGabor Juhos break; 452*12d14e0eSGabor Juhos } 453*12d14e0eSGabor Juhos } 454*12d14e0eSGabor Juhos 455*12d14e0eSGabor Juhos if (!rpc->intc_of_node) { 456*12d14e0eSGabor Juhos dev_err(dev, "%s has no %s child node", 457*12d14e0eSGabor Juhos of_node_full_name(rpc->intc_of_node), 458*12d14e0eSGabor Juhos "interrupt controller"); 459*12d14e0eSGabor Juhos return -EINVAL; 460*12d14e0eSGabor Juhos } 461*12d14e0eSGabor Juhos 462*12d14e0eSGabor Juhos /* find the PCI host bridge child node */ 463*12d14e0eSGabor Juhos for_each_child_of_node(np, child) { 464*12d14e0eSGabor Juhos if (child->type && 465*12d14e0eSGabor Juhos of_node_cmp(child->type, "pci") == 0 && 466*12d14e0eSGabor Juhos of_node_get(child)) { 467*12d14e0eSGabor Juhos rpc->pci_controller.of_node = child; 468*12d14e0eSGabor Juhos break; 469*12d14e0eSGabor Juhos } 470*12d14e0eSGabor Juhos } 471*12d14e0eSGabor Juhos 472*12d14e0eSGabor Juhos if (!rpc->pci_controller.of_node) { 473*12d14e0eSGabor Juhos dev_err(dev, "%s has no %s child node", 474*12d14e0eSGabor Juhos of_node_full_name(rpc->intc_of_node), 475*12d14e0eSGabor Juhos "PCI host bridge"); 476*12d14e0eSGabor Juhos err = -EINVAL; 477*12d14e0eSGabor Juhos goto err_put_intc_node; 478*12d14e0eSGabor Juhos } 479*12d14e0eSGabor Juhos 480*12d14e0eSGabor Juhos mode = RT3883_PCI_MODE_NONE; 481*12d14e0eSGabor Juhos for_each_available_child_of_node(rpc->pci_controller.of_node, child) { 482*12d14e0eSGabor Juhos int devfn; 483*12d14e0eSGabor Juhos 484*12d14e0eSGabor Juhos if (!child->type || 485*12d14e0eSGabor Juhos of_node_cmp(child->type, "pci") != 0) 486*12d14e0eSGabor Juhos continue; 487*12d14e0eSGabor Juhos 488*12d14e0eSGabor Juhos devfn = of_pci_get_devfn(child); 489*12d14e0eSGabor Juhos if (devfn < 0) 490*12d14e0eSGabor Juhos continue; 491*12d14e0eSGabor Juhos 492*12d14e0eSGabor Juhos switch (PCI_SLOT(devfn)) { 493*12d14e0eSGabor Juhos case 1: 494*12d14e0eSGabor Juhos mode |= RT3883_PCI_MODE_PCIE; 495*12d14e0eSGabor Juhos break; 496*12d14e0eSGabor Juhos 497*12d14e0eSGabor Juhos case 17: 498*12d14e0eSGabor Juhos case 18: 499*12d14e0eSGabor Juhos mode |= RT3883_PCI_MODE_PCI; 500*12d14e0eSGabor Juhos break; 501*12d14e0eSGabor Juhos } 502*12d14e0eSGabor Juhos } 503*12d14e0eSGabor Juhos 504*12d14e0eSGabor Juhos if (mode == RT3883_PCI_MODE_NONE) { 505*12d14e0eSGabor Juhos dev_err(dev, "unable to determine PCI mode\n"); 506*12d14e0eSGabor Juhos err = -EINVAL; 507*12d14e0eSGabor Juhos goto err_put_hb_node; 508*12d14e0eSGabor Juhos } 509*12d14e0eSGabor Juhos 510*12d14e0eSGabor Juhos dev_info(dev, "mode:%s%s\n", 511*12d14e0eSGabor Juhos (mode & RT3883_PCI_MODE_PCI) ? " PCI" : "", 512*12d14e0eSGabor Juhos (mode & RT3883_PCI_MODE_PCIE) ? " PCIe" : ""); 513*12d14e0eSGabor Juhos 514*12d14e0eSGabor Juhos rt3883_pci_preinit(rpc, mode); 515*12d14e0eSGabor Juhos 516*12d14e0eSGabor Juhos rpc->pci_controller.pci_ops = &rt3883_pci_ops; 517*12d14e0eSGabor Juhos rpc->pci_controller.io_resource = &rpc->io_res; 518*12d14e0eSGabor Juhos rpc->pci_controller.mem_resource = &rpc->mem_res; 519*12d14e0eSGabor Juhos 520*12d14e0eSGabor Juhos /* Load PCI I/O and memory resources from DT */ 521*12d14e0eSGabor Juhos pci_load_of_ranges(&rpc->pci_controller, 522*12d14e0eSGabor Juhos rpc->pci_controller.of_node); 523*12d14e0eSGabor Juhos 524*12d14e0eSGabor Juhos rt3883_pci_w32(rpc, rpc->mem_res.start, RT3883_PCI_REG_MEMBASE); 525*12d14e0eSGabor Juhos rt3883_pci_w32(rpc, rpc->io_res.start, RT3883_PCI_REG_IOBASE); 526*12d14e0eSGabor Juhos 527*12d14e0eSGabor Juhos ioport_resource.start = rpc->io_res.start; 528*12d14e0eSGabor Juhos ioport_resource.end = rpc->io_res.end; 529*12d14e0eSGabor Juhos 530*12d14e0eSGabor Juhos /* PCI */ 531*12d14e0eSGabor Juhos rt3883_pci_w32(rpc, 0x03ff0000, RT3883_PCI_REG_BAR0SETUP(0)); 532*12d14e0eSGabor Juhos rt3883_pci_w32(rpc, RT3883_MEMORY_BASE, RT3883_PCI_REG_IMBASEBAR0(0)); 533*12d14e0eSGabor Juhos rt3883_pci_w32(rpc, 0x08021814, RT3883_PCI_REG_ID(0)); 534*12d14e0eSGabor Juhos rt3883_pci_w32(rpc, 0x00800001, RT3883_PCI_REG_CLASS(0)); 535*12d14e0eSGabor Juhos rt3883_pci_w32(rpc, 0x28801814, RT3883_PCI_REG_SUBID(0)); 536*12d14e0eSGabor Juhos 537*12d14e0eSGabor Juhos /* PCIe */ 538*12d14e0eSGabor Juhos rt3883_pci_w32(rpc, 0x03ff0000, RT3883_PCI_REG_BAR0SETUP(1)); 539*12d14e0eSGabor Juhos rt3883_pci_w32(rpc, RT3883_MEMORY_BASE, RT3883_PCI_REG_IMBASEBAR0(1)); 540*12d14e0eSGabor Juhos rt3883_pci_w32(rpc, 0x08021814, RT3883_PCI_REG_ID(1)); 541*12d14e0eSGabor Juhos rt3883_pci_w32(rpc, 0x06040001, RT3883_PCI_REG_CLASS(1)); 542*12d14e0eSGabor Juhos rt3883_pci_w32(rpc, 0x28801814, RT3883_PCI_REG_SUBID(1)); 543*12d14e0eSGabor Juhos 544*12d14e0eSGabor Juhos err = rt3883_pci_irq_init(dev, rpc); 545*12d14e0eSGabor Juhos if (err) 546*12d14e0eSGabor Juhos goto err_put_hb_node; 547*12d14e0eSGabor Juhos 548*12d14e0eSGabor Juhos /* PCIe */ 549*12d14e0eSGabor Juhos val = rt3883_pci_read_cfg32(rpc, 0, 0x01, 0, PCI_COMMAND); 550*12d14e0eSGabor Juhos val |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER; 551*12d14e0eSGabor Juhos rt3883_pci_write_cfg32(rpc, 0, 0x01, 0, PCI_COMMAND, val); 552*12d14e0eSGabor Juhos 553*12d14e0eSGabor Juhos /* PCI */ 554*12d14e0eSGabor Juhos val = rt3883_pci_read_cfg32(rpc, 0, 0x00, 0, PCI_COMMAND); 555*12d14e0eSGabor Juhos val |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER; 556*12d14e0eSGabor Juhos rt3883_pci_write_cfg32(rpc, 0, 0x00, 0, PCI_COMMAND, val); 557*12d14e0eSGabor Juhos 558*12d14e0eSGabor Juhos if (mode == RT3883_PCI_MODE_PCIE) { 559*12d14e0eSGabor Juhos rt3883_pci_w32(rpc, 0x03ff0001, RT3883_PCI_REG_BAR0SETUP(0)); 560*12d14e0eSGabor Juhos rt3883_pci_w32(rpc, 0x03ff0001, RT3883_PCI_REG_BAR0SETUP(1)); 561*12d14e0eSGabor Juhos 562*12d14e0eSGabor Juhos rt3883_pci_write_cfg32(rpc, 0, RT3883_P2P_BR_DEVNUM, 0, 563*12d14e0eSGabor Juhos PCI_BASE_ADDRESS_0, 564*12d14e0eSGabor Juhos RT3883_MEMORY_BASE); 565*12d14e0eSGabor Juhos /* flush write */ 566*12d14e0eSGabor Juhos rt3883_pci_read_cfg32(rpc, 0, RT3883_P2P_BR_DEVNUM, 0, 567*12d14e0eSGabor Juhos PCI_BASE_ADDRESS_0); 568*12d14e0eSGabor Juhos } else { 569*12d14e0eSGabor Juhos rt3883_pci_write_cfg32(rpc, 0, RT3883_P2P_BR_DEVNUM, 0, 570*12d14e0eSGabor Juhos PCI_IO_BASE, 0x00000101); 571*12d14e0eSGabor Juhos } 572*12d14e0eSGabor Juhos 573*12d14e0eSGabor Juhos register_pci_controller(&rpc->pci_controller); 574*12d14e0eSGabor Juhos 575*12d14e0eSGabor Juhos return 0; 576*12d14e0eSGabor Juhos 577*12d14e0eSGabor Juhos err_put_hb_node: 578*12d14e0eSGabor Juhos of_node_put(rpc->pci_controller.of_node); 579*12d14e0eSGabor Juhos err_put_intc_node: 580*12d14e0eSGabor Juhos of_node_put(rpc->intc_of_node); 581*12d14e0eSGabor Juhos return err; 582*12d14e0eSGabor Juhos } 583*12d14e0eSGabor Juhos 584*12d14e0eSGabor Juhos int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) 585*12d14e0eSGabor Juhos { 586*12d14e0eSGabor Juhos struct of_irq dev_irq; 587*12d14e0eSGabor Juhos int err; 588*12d14e0eSGabor Juhos int irq; 589*12d14e0eSGabor Juhos 590*12d14e0eSGabor Juhos err = of_irq_map_pci(dev, &dev_irq); 591*12d14e0eSGabor Juhos if (err) { 592*12d14e0eSGabor Juhos pr_err("pci %s: unable to get irq map, err=%d\n", 593*12d14e0eSGabor Juhos pci_name((struct pci_dev *) dev), err); 594*12d14e0eSGabor Juhos return 0; 595*12d14e0eSGabor Juhos } 596*12d14e0eSGabor Juhos 597*12d14e0eSGabor Juhos irq = irq_create_of_mapping(dev_irq.controller, 598*12d14e0eSGabor Juhos dev_irq.specifier, 599*12d14e0eSGabor Juhos dev_irq.size); 600*12d14e0eSGabor Juhos 601*12d14e0eSGabor Juhos if (irq == 0) 602*12d14e0eSGabor Juhos pr_crit("pci %s: no irq found for pin %u\n", 603*12d14e0eSGabor Juhos pci_name((struct pci_dev *) dev), pin); 604*12d14e0eSGabor Juhos else 605*12d14e0eSGabor Juhos pr_info("pci %s: using irq %d for pin %u\n", 606*12d14e0eSGabor Juhos pci_name((struct pci_dev *) dev), irq, pin); 607*12d14e0eSGabor Juhos 608*12d14e0eSGabor Juhos return irq; 609*12d14e0eSGabor Juhos } 610*12d14e0eSGabor Juhos 611*12d14e0eSGabor Juhos int pcibios_plat_dev_init(struct pci_dev *dev) 612*12d14e0eSGabor Juhos { 613*12d14e0eSGabor Juhos return 0; 614*12d14e0eSGabor Juhos } 615*12d14e0eSGabor Juhos 616*12d14e0eSGabor Juhos static const struct of_device_id rt3883_pci_ids[] = { 617*12d14e0eSGabor Juhos { .compatible = "ralink,rt3883-pci" }, 618*12d14e0eSGabor Juhos {}, 619*12d14e0eSGabor Juhos }; 620*12d14e0eSGabor Juhos MODULE_DEVICE_TABLE(of, rt3883_pci_ids); 621*12d14e0eSGabor Juhos 622*12d14e0eSGabor Juhos static struct platform_driver rt3883_pci_driver = { 623*12d14e0eSGabor Juhos .probe = rt3883_pci_probe, 624*12d14e0eSGabor Juhos .driver = { 625*12d14e0eSGabor Juhos .name = "rt3883-pci", 626*12d14e0eSGabor Juhos .owner = THIS_MODULE, 627*12d14e0eSGabor Juhos .of_match_table = of_match_ptr(rt3883_pci_ids), 628*12d14e0eSGabor Juhos }, 629*12d14e0eSGabor Juhos }; 630*12d14e0eSGabor Juhos 631*12d14e0eSGabor Juhos static int __init rt3883_pci_init(void) 632*12d14e0eSGabor Juhos { 633*12d14e0eSGabor Juhos return platform_driver_register(&rt3883_pci_driver); 634*12d14e0eSGabor Juhos } 635*12d14e0eSGabor Juhos 636*12d14e0eSGabor Juhos postcore_initcall(rt3883_pci_init); 637