1d2912cb1SThomas Gleixner // SPDX-License-Identifier: GPL-2.0-only
212d14e0eSGabor Juhos /*
312d14e0eSGabor Juhos * Ralink RT3662/RT3883 SoC PCI support
412d14e0eSGabor Juhos *
512d14e0eSGabor Juhos * Copyright (C) 2011-2013 Gabor Juhos <juhosg@openwrt.org>
612d14e0eSGabor Juhos *
712d14e0eSGabor Juhos * Parts of this file are based on Ralink's 2.6.21 BSP
812d14e0eSGabor Juhos */
912d14e0eSGabor Juhos
1012d14e0eSGabor Juhos #include <linux/types.h>
1112d14e0eSGabor Juhos #include <linux/pci.h>
1212d14e0eSGabor Juhos #include <linux/io.h>
1312d14e0eSGabor Juhos #include <linux/init.h>
1412d14e0eSGabor Juhos #include <linux/delay.h>
1512d14e0eSGabor Juhos #include <linux/interrupt.h>
1618ca45f5SMarc Zyngier #include <linux/irqdomain.h>
1712d14e0eSGabor Juhos #include <linux/of.h>
1812d14e0eSGabor Juhos #include <linux/of_irq.h>
1912d14e0eSGabor Juhos #include <linux/of_pci.h>
2012d14e0eSGabor Juhos #include <linux/platform_device.h>
2112d14e0eSGabor Juhos
2212d14e0eSGabor Juhos #include <asm/mach-ralink/rt3883.h>
2312d14e0eSGabor Juhos #include <asm/mach-ralink/ralink_regs.h>
2412d14e0eSGabor Juhos
2512d14e0eSGabor Juhos #define RT3883_MEMORY_BASE 0x00000000
2612d14e0eSGabor Juhos #define RT3883_MEMORY_SIZE 0x02000000
2712d14e0eSGabor Juhos
2812d14e0eSGabor Juhos #define RT3883_PCI_REG_PCICFG 0x00
2912d14e0eSGabor Juhos #define RT3883_PCICFG_P2P_BR_DEVNUM_M 0xf
3012d14e0eSGabor Juhos #define RT3883_PCICFG_P2P_BR_DEVNUM_S 16
3112d14e0eSGabor Juhos #define RT3883_PCICFG_PCIRST BIT(1)
3212d14e0eSGabor Juhos #define RT3883_PCI_REG_PCIRAW 0x04
3312d14e0eSGabor Juhos #define RT3883_PCI_REG_PCIINT 0x08
3412d14e0eSGabor Juhos #define RT3883_PCI_REG_PCIENA 0x0c
3512d14e0eSGabor Juhos
3612d14e0eSGabor Juhos #define RT3883_PCI_REG_CFGADDR 0x20
3712d14e0eSGabor Juhos #define RT3883_PCI_REG_CFGDATA 0x24
3812d14e0eSGabor Juhos #define RT3883_PCI_REG_MEMBASE 0x28
3912d14e0eSGabor Juhos #define RT3883_PCI_REG_IOBASE 0x2c
4012d14e0eSGabor Juhos #define RT3883_PCI_REG_ARBCTL 0x80
4112d14e0eSGabor Juhos
4212d14e0eSGabor Juhos #define RT3883_PCI_REG_BASE(_x) (0x1000 + (_x) * 0x1000)
4312d14e0eSGabor Juhos #define RT3883_PCI_REG_BAR0SETUP(_x) (RT3883_PCI_REG_BASE((_x)) + 0x10)
4412d14e0eSGabor Juhos #define RT3883_PCI_REG_IMBASEBAR0(_x) (RT3883_PCI_REG_BASE((_x)) + 0x18)
4512d14e0eSGabor Juhos #define RT3883_PCI_REG_ID(_x) (RT3883_PCI_REG_BASE((_x)) + 0x30)
4612d14e0eSGabor Juhos #define RT3883_PCI_REG_CLASS(_x) (RT3883_PCI_REG_BASE((_x)) + 0x34)
4712d14e0eSGabor Juhos #define RT3883_PCI_REG_SUBID(_x) (RT3883_PCI_REG_BASE((_x)) + 0x38)
4812d14e0eSGabor Juhos #define RT3883_PCI_REG_STATUS(_x) (RT3883_PCI_REG_BASE((_x)) + 0x50)
4912d14e0eSGabor Juhos
5012d14e0eSGabor Juhos #define RT3883_PCI_MODE_NONE 0
5112d14e0eSGabor Juhos #define RT3883_PCI_MODE_PCI BIT(0)
5212d14e0eSGabor Juhos #define RT3883_PCI_MODE_PCIE BIT(1)
5312d14e0eSGabor Juhos #define RT3883_PCI_MODE_BOTH (RT3883_PCI_MODE_PCI | RT3883_PCI_MODE_PCIE)
5412d14e0eSGabor Juhos
5512d14e0eSGabor Juhos #define RT3883_PCI_IRQ_COUNT 32
5612d14e0eSGabor Juhos
5712d14e0eSGabor Juhos #define RT3883_P2P_BR_DEVNUM 1
5812d14e0eSGabor Juhos
5912d14e0eSGabor Juhos struct rt3883_pci_controller {
6012d14e0eSGabor Juhos void __iomem *base;
6112d14e0eSGabor Juhos
6212d14e0eSGabor Juhos struct device_node *intc_of_node;
6312d14e0eSGabor Juhos struct irq_domain *irq_domain;
6412d14e0eSGabor Juhos
6512d14e0eSGabor Juhos struct pci_controller pci_controller;
6612d14e0eSGabor Juhos struct resource io_res;
6712d14e0eSGabor Juhos struct resource mem_res;
6812d14e0eSGabor Juhos
6912d14e0eSGabor Juhos bool pcie_ready;
7012d14e0eSGabor Juhos };
7112d14e0eSGabor Juhos
7212d14e0eSGabor Juhos static inline struct rt3883_pci_controller *
pci_bus_to_rt3883_controller(struct pci_bus * bus)7312d14e0eSGabor Juhos pci_bus_to_rt3883_controller(struct pci_bus *bus)
7412d14e0eSGabor Juhos {
7512d14e0eSGabor Juhos struct pci_controller *hose;
7612d14e0eSGabor Juhos
7712d14e0eSGabor Juhos hose = (struct pci_controller *) bus->sysdata;
7812d14e0eSGabor Juhos return container_of(hose, struct rt3883_pci_controller, pci_controller);
7912d14e0eSGabor Juhos }
8012d14e0eSGabor Juhos
rt3883_pci_r32(struct rt3883_pci_controller * rpc,unsigned reg)8112d14e0eSGabor Juhos static inline u32 rt3883_pci_r32(struct rt3883_pci_controller *rpc,
8212d14e0eSGabor Juhos unsigned reg)
8312d14e0eSGabor Juhos {
8412d14e0eSGabor Juhos return ioread32(rpc->base + reg);
8512d14e0eSGabor Juhos }
8612d14e0eSGabor Juhos
rt3883_pci_w32(struct rt3883_pci_controller * rpc,u32 val,unsigned reg)8712d14e0eSGabor Juhos static inline void rt3883_pci_w32(struct rt3883_pci_controller *rpc,
8812d14e0eSGabor Juhos u32 val, unsigned reg)
8912d14e0eSGabor Juhos {
9012d14e0eSGabor Juhos iowrite32(val, rpc->base + reg);
9112d14e0eSGabor Juhos }
9212d14e0eSGabor Juhos
rt3883_pci_get_cfgaddr(unsigned int bus,unsigned int slot,unsigned int func,unsigned int where)9312d14e0eSGabor Juhos static inline u32 rt3883_pci_get_cfgaddr(unsigned int bus, unsigned int slot,
9412d14e0eSGabor Juhos unsigned int func, unsigned int where)
9512d14e0eSGabor Juhos {
9612d14e0eSGabor Juhos return (bus << 16) | (slot << 11) | (func << 8) | (where & 0xfc) |
9712d14e0eSGabor Juhos 0x80000000;
9812d14e0eSGabor Juhos }
9912d14e0eSGabor Juhos
rt3883_pci_read_cfg32(struct rt3883_pci_controller * rpc,unsigned bus,unsigned slot,unsigned func,unsigned reg)10012d14e0eSGabor Juhos static u32 rt3883_pci_read_cfg32(struct rt3883_pci_controller *rpc,
10112d14e0eSGabor Juhos unsigned bus, unsigned slot,
10212d14e0eSGabor Juhos unsigned func, unsigned reg)
10312d14e0eSGabor Juhos {
10412d14e0eSGabor Juhos u32 address;
10512d14e0eSGabor Juhos
10612d14e0eSGabor Juhos address = rt3883_pci_get_cfgaddr(bus, slot, func, reg);
10712d14e0eSGabor Juhos
10812d14e0eSGabor Juhos rt3883_pci_w32(rpc, address, RT3883_PCI_REG_CFGADDR);
10912d14e0eSGabor Juhos
1106bcfdc49SMinghao Chi return rt3883_pci_r32(rpc, RT3883_PCI_REG_CFGDATA);
11112d14e0eSGabor Juhos }
11212d14e0eSGabor Juhos
rt3883_pci_write_cfg32(struct rt3883_pci_controller * rpc,unsigned bus,unsigned slot,unsigned func,unsigned reg,u32 val)11312d14e0eSGabor Juhos static void rt3883_pci_write_cfg32(struct rt3883_pci_controller *rpc,
11412d14e0eSGabor Juhos unsigned bus, unsigned slot,
11512d14e0eSGabor Juhos unsigned func, unsigned reg, u32 val)
11612d14e0eSGabor Juhos {
11712d14e0eSGabor Juhos u32 address;
11812d14e0eSGabor Juhos
11912d14e0eSGabor Juhos address = rt3883_pci_get_cfgaddr(bus, slot, func, reg);
12012d14e0eSGabor Juhos
12112d14e0eSGabor Juhos rt3883_pci_w32(rpc, address, RT3883_PCI_REG_CFGADDR);
12212d14e0eSGabor Juhos rt3883_pci_w32(rpc, val, RT3883_PCI_REG_CFGDATA);
12312d14e0eSGabor Juhos }
12412d14e0eSGabor Juhos
rt3883_pci_irq_handler(struct irq_desc * desc)125bd0b9ac4SThomas Gleixner static void rt3883_pci_irq_handler(struct irq_desc *desc)
12612d14e0eSGabor Juhos {
12712d14e0eSGabor Juhos struct rt3883_pci_controller *rpc;
12812d14e0eSGabor Juhos u32 pending;
12912d14e0eSGabor Juhos
13025aae561SJiang Liu rpc = irq_desc_get_handler_data(desc);
13112d14e0eSGabor Juhos
13212d14e0eSGabor Juhos pending = rt3883_pci_r32(rpc, RT3883_PCI_REG_PCIINT) &
13312d14e0eSGabor Juhos rt3883_pci_r32(rpc, RT3883_PCI_REG_PCIENA);
13412d14e0eSGabor Juhos
13512d14e0eSGabor Juhos if (!pending) {
13612d14e0eSGabor Juhos spurious_interrupt();
13712d14e0eSGabor Juhos return;
13812d14e0eSGabor Juhos }
13912d14e0eSGabor Juhos
14012d14e0eSGabor Juhos while (pending) {
1410661cb2aSMarc Zyngier unsigned bit = __ffs(pending);
14212d14e0eSGabor Juhos
1430661cb2aSMarc Zyngier generic_handle_domain_irq(rpc->irq_domain, bit);
14412d14e0eSGabor Juhos
14512d14e0eSGabor Juhos pending &= ~BIT(bit);
14612d14e0eSGabor Juhos }
14712d14e0eSGabor Juhos }
14812d14e0eSGabor Juhos
rt3883_pci_irq_unmask(struct irq_data * d)14912d14e0eSGabor Juhos static void rt3883_pci_irq_unmask(struct irq_data *d)
15012d14e0eSGabor Juhos {
15112d14e0eSGabor Juhos struct rt3883_pci_controller *rpc;
15212d14e0eSGabor Juhos u32 t;
15312d14e0eSGabor Juhos
15412d14e0eSGabor Juhos rpc = irq_data_get_irq_chip_data(d);
15512d14e0eSGabor Juhos
15612d14e0eSGabor Juhos t = rt3883_pci_r32(rpc, RT3883_PCI_REG_PCIENA);
15712d14e0eSGabor Juhos rt3883_pci_w32(rpc, t | BIT(d->hwirq), RT3883_PCI_REG_PCIENA);
15812d14e0eSGabor Juhos /* flush write */
15912d14e0eSGabor Juhos rt3883_pci_r32(rpc, RT3883_PCI_REG_PCIENA);
16012d14e0eSGabor Juhos }
16112d14e0eSGabor Juhos
rt3883_pci_irq_mask(struct irq_data * d)16212d14e0eSGabor Juhos static void rt3883_pci_irq_mask(struct irq_data *d)
16312d14e0eSGabor Juhos {
16412d14e0eSGabor Juhos struct rt3883_pci_controller *rpc;
16512d14e0eSGabor Juhos u32 t;
16612d14e0eSGabor Juhos
16712d14e0eSGabor Juhos rpc = irq_data_get_irq_chip_data(d);
16812d14e0eSGabor Juhos
16912d14e0eSGabor Juhos t = rt3883_pci_r32(rpc, RT3883_PCI_REG_PCIENA);
17012d14e0eSGabor Juhos rt3883_pci_w32(rpc, t & ~BIT(d->hwirq), RT3883_PCI_REG_PCIENA);
17112d14e0eSGabor Juhos /* flush write */
17212d14e0eSGabor Juhos rt3883_pci_r32(rpc, RT3883_PCI_REG_PCIENA);
17312d14e0eSGabor Juhos }
17412d14e0eSGabor Juhos
17512d14e0eSGabor Juhos static struct irq_chip rt3883_pci_irq_chip = {
17612d14e0eSGabor Juhos .name = "RT3883 PCI",
17712d14e0eSGabor Juhos .irq_mask = rt3883_pci_irq_mask,
17812d14e0eSGabor Juhos .irq_unmask = rt3883_pci_irq_unmask,
17912d14e0eSGabor Juhos .irq_mask_ack = rt3883_pci_irq_mask,
18012d14e0eSGabor Juhos };
18112d14e0eSGabor Juhos
rt3883_pci_irq_map(struct irq_domain * d,unsigned int irq,irq_hw_number_t hw)18212d14e0eSGabor Juhos static int rt3883_pci_irq_map(struct irq_domain *d, unsigned int irq,
18312d14e0eSGabor Juhos irq_hw_number_t hw)
18412d14e0eSGabor Juhos {
18512d14e0eSGabor Juhos irq_set_chip_and_handler(irq, &rt3883_pci_irq_chip, handle_level_irq);
18612d14e0eSGabor Juhos irq_set_chip_data(irq, d->host_data);
18712d14e0eSGabor Juhos
18812d14e0eSGabor Juhos return 0;
18912d14e0eSGabor Juhos }
19012d14e0eSGabor Juhos
19112d14e0eSGabor Juhos static const struct irq_domain_ops rt3883_pci_irq_domain_ops = {
19212d14e0eSGabor Juhos .map = rt3883_pci_irq_map,
19312d14e0eSGabor Juhos .xlate = irq_domain_xlate_onecell,
19412d14e0eSGabor Juhos };
19512d14e0eSGabor Juhos
rt3883_pci_irq_init(struct device * dev,struct rt3883_pci_controller * rpc)19612d14e0eSGabor Juhos static int rt3883_pci_irq_init(struct device *dev,
19712d14e0eSGabor Juhos struct rt3883_pci_controller *rpc)
19812d14e0eSGabor Juhos {
19912d14e0eSGabor Juhos int irq;
20012d14e0eSGabor Juhos
20112d14e0eSGabor Juhos irq = irq_of_parse_and_map(rpc->intc_of_node, 0);
20212d14e0eSGabor Juhos if (irq == 0) {
2037f27b5b8SRob Herring dev_err(dev, "%pOF has no IRQ", rpc->intc_of_node);
20412d14e0eSGabor Juhos return -EINVAL;
20512d14e0eSGabor Juhos }
20612d14e0eSGabor Juhos
20712d14e0eSGabor Juhos /* disable all interrupts */
20812d14e0eSGabor Juhos rt3883_pci_w32(rpc, 0, RT3883_PCI_REG_PCIENA);
20912d14e0eSGabor Juhos
21012d14e0eSGabor Juhos rpc->irq_domain =
21112d14e0eSGabor Juhos irq_domain_add_linear(rpc->intc_of_node, RT3883_PCI_IRQ_COUNT,
21212d14e0eSGabor Juhos &rt3883_pci_irq_domain_ops,
21312d14e0eSGabor Juhos rpc);
21412d14e0eSGabor Juhos if (!rpc->irq_domain) {
21512d14e0eSGabor Juhos dev_err(dev, "unable to add IRQ domain\n");
21612d14e0eSGabor Juhos return -ENODEV;
21712d14e0eSGabor Juhos }
21812d14e0eSGabor Juhos
219586134a8SThomas Gleixner irq_set_chained_handler_and_data(irq, rt3883_pci_irq_handler, rpc);
22012d14e0eSGabor Juhos
22112d14e0eSGabor Juhos return 0;
22212d14e0eSGabor Juhos }
22312d14e0eSGabor Juhos
rt3883_pci_config_read(struct pci_bus * bus,unsigned int devfn,int where,int size,u32 * val)22412d14e0eSGabor Juhos static int rt3883_pci_config_read(struct pci_bus *bus, unsigned int devfn,
22512d14e0eSGabor Juhos int where, int size, u32 *val)
22612d14e0eSGabor Juhos {
22712d14e0eSGabor Juhos struct rt3883_pci_controller *rpc;
22812d14e0eSGabor Juhos u32 address;
22912d14e0eSGabor Juhos u32 data;
23012d14e0eSGabor Juhos
23112d14e0eSGabor Juhos rpc = pci_bus_to_rt3883_controller(bus);
23212d14e0eSGabor Juhos
23312d14e0eSGabor Juhos if (!rpc->pcie_ready && bus->number == 1)
23412d14e0eSGabor Juhos return PCIBIOS_DEVICE_NOT_FOUND;
23512d14e0eSGabor Juhos
23612d14e0eSGabor Juhos address = rt3883_pci_get_cfgaddr(bus->number, PCI_SLOT(devfn),
23712d14e0eSGabor Juhos PCI_FUNC(devfn), where);
23812d14e0eSGabor Juhos
23912d14e0eSGabor Juhos rt3883_pci_w32(rpc, address, RT3883_PCI_REG_CFGADDR);
24012d14e0eSGabor Juhos data = rt3883_pci_r32(rpc, RT3883_PCI_REG_CFGDATA);
24112d14e0eSGabor Juhos
24212d14e0eSGabor Juhos switch (size) {
24312d14e0eSGabor Juhos case 1:
24412d14e0eSGabor Juhos *val = (data >> ((where & 3) << 3)) & 0xff;
24512d14e0eSGabor Juhos break;
24612d14e0eSGabor Juhos case 2:
24712d14e0eSGabor Juhos *val = (data >> ((where & 3) << 3)) & 0xffff;
24812d14e0eSGabor Juhos break;
24912d14e0eSGabor Juhos case 4:
25012d14e0eSGabor Juhos *val = data;
25112d14e0eSGabor Juhos break;
25212d14e0eSGabor Juhos }
25312d14e0eSGabor Juhos
25412d14e0eSGabor Juhos return PCIBIOS_SUCCESSFUL;
25512d14e0eSGabor Juhos }
25612d14e0eSGabor Juhos
rt3883_pci_config_write(struct pci_bus * bus,unsigned int devfn,int where,int size,u32 val)25712d14e0eSGabor Juhos static int rt3883_pci_config_write(struct pci_bus *bus, unsigned int devfn,
25812d14e0eSGabor Juhos int where, int size, u32 val)
25912d14e0eSGabor Juhos {
26012d14e0eSGabor Juhos struct rt3883_pci_controller *rpc;
26112d14e0eSGabor Juhos u32 address;
26212d14e0eSGabor Juhos u32 data;
26312d14e0eSGabor Juhos
26412d14e0eSGabor Juhos rpc = pci_bus_to_rt3883_controller(bus);
26512d14e0eSGabor Juhos
26612d14e0eSGabor Juhos if (!rpc->pcie_ready && bus->number == 1)
26712d14e0eSGabor Juhos return PCIBIOS_DEVICE_NOT_FOUND;
26812d14e0eSGabor Juhos
26912d14e0eSGabor Juhos address = rt3883_pci_get_cfgaddr(bus->number, PCI_SLOT(devfn),
27012d14e0eSGabor Juhos PCI_FUNC(devfn), where);
27112d14e0eSGabor Juhos
27212d14e0eSGabor Juhos rt3883_pci_w32(rpc, address, RT3883_PCI_REG_CFGADDR);
27312d14e0eSGabor Juhos data = rt3883_pci_r32(rpc, RT3883_PCI_REG_CFGDATA);
27412d14e0eSGabor Juhos
27512d14e0eSGabor Juhos switch (size) {
27612d14e0eSGabor Juhos case 1:
27712d14e0eSGabor Juhos data = (data & ~(0xff << ((where & 3) << 3))) |
27812d14e0eSGabor Juhos (val << ((where & 3) << 3));
27912d14e0eSGabor Juhos break;
28012d14e0eSGabor Juhos case 2:
28112d14e0eSGabor Juhos data = (data & ~(0xffff << ((where & 3) << 3))) |
28212d14e0eSGabor Juhos (val << ((where & 3) << 3));
28312d14e0eSGabor Juhos break;
28412d14e0eSGabor Juhos case 4:
28512d14e0eSGabor Juhos data = val;
28612d14e0eSGabor Juhos break;
28712d14e0eSGabor Juhos }
28812d14e0eSGabor Juhos
28912d14e0eSGabor Juhos rt3883_pci_w32(rpc, data, RT3883_PCI_REG_CFGDATA);
29012d14e0eSGabor Juhos
29112d14e0eSGabor Juhos return PCIBIOS_SUCCESSFUL;
29212d14e0eSGabor Juhos }
29312d14e0eSGabor Juhos
29412d14e0eSGabor Juhos static struct pci_ops rt3883_pci_ops = {
29512d14e0eSGabor Juhos .read = rt3883_pci_config_read,
29612d14e0eSGabor Juhos .write = rt3883_pci_config_write,
29712d14e0eSGabor Juhos };
29812d14e0eSGabor Juhos
rt3883_pci_preinit(struct rt3883_pci_controller * rpc,unsigned mode)29912d14e0eSGabor Juhos static void rt3883_pci_preinit(struct rt3883_pci_controller *rpc, unsigned mode)
30012d14e0eSGabor Juhos {
30112d14e0eSGabor Juhos u32 syscfg1;
30212d14e0eSGabor Juhos u32 rstctrl;
30312d14e0eSGabor Juhos u32 clkcfg1;
30412d14e0eSGabor Juhos u32 t;
30512d14e0eSGabor Juhos
30612d14e0eSGabor Juhos rstctrl = rt_sysc_r32(RT3883_SYSC_REG_RSTCTRL);
30712d14e0eSGabor Juhos syscfg1 = rt_sysc_r32(RT3883_SYSC_REG_SYSCFG1);
30812d14e0eSGabor Juhos clkcfg1 = rt_sysc_r32(RT3883_SYSC_REG_CLKCFG1);
30912d14e0eSGabor Juhos
31012d14e0eSGabor Juhos if (mode & RT3883_PCI_MODE_PCIE) {
31112d14e0eSGabor Juhos rstctrl |= RT3883_RSTCTRL_PCIE;
31212d14e0eSGabor Juhos rt_sysc_w32(rstctrl, RT3883_SYSC_REG_RSTCTRL);
31312d14e0eSGabor Juhos
31412d14e0eSGabor Juhos /* setup PCI PAD drive mode */
31512d14e0eSGabor Juhos syscfg1 &= ~(0x30);
31612d14e0eSGabor Juhos syscfg1 |= (2 << 4);
31712d14e0eSGabor Juhos rt_sysc_w32(syscfg1, RT3883_SYSC_REG_SYSCFG1);
31812d14e0eSGabor Juhos
31912d14e0eSGabor Juhos t = rt_sysc_r32(RT3883_SYSC_REG_PCIE_CLK_GEN0);
32012d14e0eSGabor Juhos t &= ~BIT(31);
32112d14e0eSGabor Juhos rt_sysc_w32(t, RT3883_SYSC_REG_PCIE_CLK_GEN0);
32212d14e0eSGabor Juhos
32312d14e0eSGabor Juhos t = rt_sysc_r32(RT3883_SYSC_REG_PCIE_CLK_GEN1);
32412d14e0eSGabor Juhos t &= 0x80ffffff;
32512d14e0eSGabor Juhos rt_sysc_w32(t, RT3883_SYSC_REG_PCIE_CLK_GEN1);
32612d14e0eSGabor Juhos
32712d14e0eSGabor Juhos t = rt_sysc_r32(RT3883_SYSC_REG_PCIE_CLK_GEN1);
32812d14e0eSGabor Juhos t |= 0xa << 24;
32912d14e0eSGabor Juhos rt_sysc_w32(t, RT3883_SYSC_REG_PCIE_CLK_GEN1);
33012d14e0eSGabor Juhos
33112d14e0eSGabor Juhos t = rt_sysc_r32(RT3883_SYSC_REG_PCIE_CLK_GEN0);
33212d14e0eSGabor Juhos t |= BIT(31);
33312d14e0eSGabor Juhos rt_sysc_w32(t, RT3883_SYSC_REG_PCIE_CLK_GEN0);
33412d14e0eSGabor Juhos
33512d14e0eSGabor Juhos msleep(50);
33612d14e0eSGabor Juhos
33712d14e0eSGabor Juhos rstctrl &= ~RT3883_RSTCTRL_PCIE;
33812d14e0eSGabor Juhos rt_sysc_w32(rstctrl, RT3883_SYSC_REG_RSTCTRL);
33912d14e0eSGabor Juhos }
34012d14e0eSGabor Juhos
34112d14e0eSGabor Juhos syscfg1 |= (RT3883_SYSCFG1_PCIE_RC_MODE | RT3883_SYSCFG1_PCI_HOST_MODE);
34212d14e0eSGabor Juhos
34312d14e0eSGabor Juhos clkcfg1 &= ~(RT3883_CLKCFG1_PCI_CLK_EN | RT3883_CLKCFG1_PCIE_CLK_EN);
34412d14e0eSGabor Juhos
34512d14e0eSGabor Juhos if (mode & RT3883_PCI_MODE_PCI) {
34612d14e0eSGabor Juhos clkcfg1 |= RT3883_CLKCFG1_PCI_CLK_EN;
34712d14e0eSGabor Juhos rstctrl &= ~RT3883_RSTCTRL_PCI;
34812d14e0eSGabor Juhos }
34912d14e0eSGabor Juhos
35012d14e0eSGabor Juhos if (mode & RT3883_PCI_MODE_PCIE) {
35112d14e0eSGabor Juhos clkcfg1 |= RT3883_CLKCFG1_PCIE_CLK_EN;
35212d14e0eSGabor Juhos rstctrl &= ~RT3883_RSTCTRL_PCIE;
35312d14e0eSGabor Juhos }
35412d14e0eSGabor Juhos
35512d14e0eSGabor Juhos rt_sysc_w32(syscfg1, RT3883_SYSC_REG_SYSCFG1);
35612d14e0eSGabor Juhos rt_sysc_w32(rstctrl, RT3883_SYSC_REG_RSTCTRL);
35712d14e0eSGabor Juhos rt_sysc_w32(clkcfg1, RT3883_SYSC_REG_CLKCFG1);
35812d14e0eSGabor Juhos
35912d14e0eSGabor Juhos msleep(500);
36012d14e0eSGabor Juhos
36112d14e0eSGabor Juhos /*
36212d14e0eSGabor Juhos * setup the device number of the P2P bridge
36312d14e0eSGabor Juhos * and de-assert the reset line
36412d14e0eSGabor Juhos */
36512d14e0eSGabor Juhos t = (RT3883_P2P_BR_DEVNUM << RT3883_PCICFG_P2P_BR_DEVNUM_S);
36612d14e0eSGabor Juhos rt3883_pci_w32(rpc, t, RT3883_PCI_REG_PCICFG);
36712d14e0eSGabor Juhos
36812d14e0eSGabor Juhos /* flush write */
36912d14e0eSGabor Juhos rt3883_pci_r32(rpc, RT3883_PCI_REG_PCICFG);
37012d14e0eSGabor Juhos msleep(500);
37112d14e0eSGabor Juhos
37212d14e0eSGabor Juhos if (mode & RT3883_PCI_MODE_PCIE) {
37312d14e0eSGabor Juhos msleep(500);
37412d14e0eSGabor Juhos
37512d14e0eSGabor Juhos t = rt3883_pci_r32(rpc, RT3883_PCI_REG_STATUS(1));
37612d14e0eSGabor Juhos
37712d14e0eSGabor Juhos rpc->pcie_ready = t & BIT(0);
37812d14e0eSGabor Juhos
37912d14e0eSGabor Juhos if (!rpc->pcie_ready) {
38012d14e0eSGabor Juhos /* reset the PCIe block */
38112d14e0eSGabor Juhos t = rt_sysc_r32(RT3883_SYSC_REG_RSTCTRL);
38212d14e0eSGabor Juhos t |= RT3883_RSTCTRL_PCIE;
38312d14e0eSGabor Juhos rt_sysc_w32(t, RT3883_SYSC_REG_RSTCTRL);
38412d14e0eSGabor Juhos t &= ~RT3883_RSTCTRL_PCIE;
38512d14e0eSGabor Juhos rt_sysc_w32(t, RT3883_SYSC_REG_RSTCTRL);
38612d14e0eSGabor Juhos
38712d14e0eSGabor Juhos /* turn off PCIe clock */
38812d14e0eSGabor Juhos t = rt_sysc_r32(RT3883_SYSC_REG_CLKCFG1);
38912d14e0eSGabor Juhos t &= ~RT3883_CLKCFG1_PCIE_CLK_EN;
39012d14e0eSGabor Juhos rt_sysc_w32(t, RT3883_SYSC_REG_CLKCFG1);
39112d14e0eSGabor Juhos
39212d14e0eSGabor Juhos t = rt_sysc_r32(RT3883_SYSC_REG_PCIE_CLK_GEN0);
39312d14e0eSGabor Juhos t &= ~0xf000c080;
39412d14e0eSGabor Juhos rt_sysc_w32(t, RT3883_SYSC_REG_PCIE_CLK_GEN0);
39512d14e0eSGabor Juhos }
39612d14e0eSGabor Juhos }
39712d14e0eSGabor Juhos
39812d14e0eSGabor Juhos /* enable PCI arbiter */
39912d14e0eSGabor Juhos rt3883_pci_w32(rpc, 0x79, RT3883_PCI_REG_ARBCTL);
40012d14e0eSGabor Juhos }
40112d14e0eSGabor Juhos
rt3883_pci_probe(struct platform_device * pdev)40212d14e0eSGabor Juhos static int rt3883_pci_probe(struct platform_device *pdev)
40312d14e0eSGabor Juhos {
40412d14e0eSGabor Juhos struct rt3883_pci_controller *rpc;
40512d14e0eSGabor Juhos struct device *dev = &pdev->dev;
40612d14e0eSGabor Juhos struct device_node *np = dev->of_node;
40712d14e0eSGabor Juhos struct device_node *child;
40812d14e0eSGabor Juhos u32 val;
40912d14e0eSGabor Juhos int err;
41012d14e0eSGabor Juhos int mode;
41112d14e0eSGabor Juhos
41212d14e0eSGabor Juhos rpc = devm_kzalloc(dev, sizeof(*rpc), GFP_KERNEL);
41312d14e0eSGabor Juhos if (!rpc)
41412d14e0eSGabor Juhos return -ENOMEM;
41512d14e0eSGabor Juhos
416b43340ddSzhang songyi rpc->base = devm_platform_ioremap_resource(pdev, 0);
41712d14e0eSGabor Juhos if (IS_ERR(rpc->base))
41812d14e0eSGabor Juhos return PTR_ERR(rpc->base);
41912d14e0eSGabor Juhos
42012d14e0eSGabor Juhos /* find the interrupt controller child node */
42112d14e0eSGabor Juhos for_each_child_of_node(np, child) {
422*9c99b488SRob Herring if (of_property_read_bool(child, "interrupt-controller")) {
42312d14e0eSGabor Juhos rpc->intc_of_node = child;
42412d14e0eSGabor Juhos break;
42512d14e0eSGabor Juhos }
42612d14e0eSGabor Juhos }
42712d14e0eSGabor Juhos
42812d14e0eSGabor Juhos if (!rpc->intc_of_node) {
4297f27b5b8SRob Herring dev_err(dev, "%pOF has no %s child node",
4302f802e17SIlya Lipnitskiy np, "interrupt controller");
43112d14e0eSGabor Juhos return -EINVAL;
43212d14e0eSGabor Juhos }
43312d14e0eSGabor Juhos
43412d14e0eSGabor Juhos /* find the PCI host bridge child node */
43512d14e0eSGabor Juhos for_each_child_of_node(np, child) {
43649e510ddSRob Herring if (of_node_is_type(child, "pci")) {
43712d14e0eSGabor Juhos rpc->pci_controller.of_node = child;
43812d14e0eSGabor Juhos break;
43912d14e0eSGabor Juhos }
44012d14e0eSGabor Juhos }
44112d14e0eSGabor Juhos
44212d14e0eSGabor Juhos if (!rpc->pci_controller.of_node) {
4437f27b5b8SRob Herring dev_err(dev, "%pOF has no %s child node",
4442f802e17SIlya Lipnitskiy np, "PCI host bridge");
44512d14e0eSGabor Juhos err = -EINVAL;
44612d14e0eSGabor Juhos goto err_put_intc_node;
44712d14e0eSGabor Juhos }
44812d14e0eSGabor Juhos
44912d14e0eSGabor Juhos mode = RT3883_PCI_MODE_NONE;
45012d14e0eSGabor Juhos for_each_available_child_of_node(rpc->pci_controller.of_node, child) {
45112d14e0eSGabor Juhos int devfn;
45212d14e0eSGabor Juhos
45349e510ddSRob Herring if (!of_node_is_type(child, "pci"))
45412d14e0eSGabor Juhos continue;
45512d14e0eSGabor Juhos
45612d14e0eSGabor Juhos devfn = of_pci_get_devfn(child);
45712d14e0eSGabor Juhos if (devfn < 0)
45812d14e0eSGabor Juhos continue;
45912d14e0eSGabor Juhos
46012d14e0eSGabor Juhos switch (PCI_SLOT(devfn)) {
46112d14e0eSGabor Juhos case 1:
46212d14e0eSGabor Juhos mode |= RT3883_PCI_MODE_PCIE;
46312d14e0eSGabor Juhos break;
46412d14e0eSGabor Juhos
46512d14e0eSGabor Juhos case 17:
46612d14e0eSGabor Juhos case 18:
46712d14e0eSGabor Juhos mode |= RT3883_PCI_MODE_PCI;
46812d14e0eSGabor Juhos break;
46912d14e0eSGabor Juhos }
47012d14e0eSGabor Juhos }
47112d14e0eSGabor Juhos
47212d14e0eSGabor Juhos if (mode == RT3883_PCI_MODE_NONE) {
47312d14e0eSGabor Juhos dev_err(dev, "unable to determine PCI mode\n");
47412d14e0eSGabor Juhos err = -EINVAL;
47512d14e0eSGabor Juhos goto err_put_hb_node;
47612d14e0eSGabor Juhos }
47712d14e0eSGabor Juhos
47812d14e0eSGabor Juhos dev_info(dev, "mode:%s%s\n",
47912d14e0eSGabor Juhos (mode & RT3883_PCI_MODE_PCI) ? " PCI" : "",
48012d14e0eSGabor Juhos (mode & RT3883_PCI_MODE_PCIE) ? " PCIe" : "");
48112d14e0eSGabor Juhos
48212d14e0eSGabor Juhos rt3883_pci_preinit(rpc, mode);
48312d14e0eSGabor Juhos
48412d14e0eSGabor Juhos rpc->pci_controller.pci_ops = &rt3883_pci_ops;
48512d14e0eSGabor Juhos rpc->pci_controller.io_resource = &rpc->io_res;
48612d14e0eSGabor Juhos rpc->pci_controller.mem_resource = &rpc->mem_res;
48712d14e0eSGabor Juhos
48812d14e0eSGabor Juhos /* Load PCI I/O and memory resources from DT */
48912d14e0eSGabor Juhos pci_load_of_ranges(&rpc->pci_controller,
49012d14e0eSGabor Juhos rpc->pci_controller.of_node);
49112d14e0eSGabor Juhos
49212d14e0eSGabor Juhos rt3883_pci_w32(rpc, rpc->mem_res.start, RT3883_PCI_REG_MEMBASE);
49312d14e0eSGabor Juhos rt3883_pci_w32(rpc, rpc->io_res.start, RT3883_PCI_REG_IOBASE);
49412d14e0eSGabor Juhos
49512d14e0eSGabor Juhos ioport_resource.start = rpc->io_res.start;
49612d14e0eSGabor Juhos ioport_resource.end = rpc->io_res.end;
49712d14e0eSGabor Juhos
49812d14e0eSGabor Juhos /* PCI */
49912d14e0eSGabor Juhos rt3883_pci_w32(rpc, 0x03ff0000, RT3883_PCI_REG_BAR0SETUP(0));
50012d14e0eSGabor Juhos rt3883_pci_w32(rpc, RT3883_MEMORY_BASE, RT3883_PCI_REG_IMBASEBAR0(0));
50112d14e0eSGabor Juhos rt3883_pci_w32(rpc, 0x08021814, RT3883_PCI_REG_ID(0));
50212d14e0eSGabor Juhos rt3883_pci_w32(rpc, 0x00800001, RT3883_PCI_REG_CLASS(0));
50312d14e0eSGabor Juhos rt3883_pci_w32(rpc, 0x28801814, RT3883_PCI_REG_SUBID(0));
50412d14e0eSGabor Juhos
50512d14e0eSGabor Juhos /* PCIe */
50612d14e0eSGabor Juhos rt3883_pci_w32(rpc, 0x03ff0000, RT3883_PCI_REG_BAR0SETUP(1));
50712d14e0eSGabor Juhos rt3883_pci_w32(rpc, RT3883_MEMORY_BASE, RT3883_PCI_REG_IMBASEBAR0(1));
50812d14e0eSGabor Juhos rt3883_pci_w32(rpc, 0x08021814, RT3883_PCI_REG_ID(1));
50912d14e0eSGabor Juhos rt3883_pci_w32(rpc, 0x06040001, RT3883_PCI_REG_CLASS(1));
51012d14e0eSGabor Juhos rt3883_pci_w32(rpc, 0x28801814, RT3883_PCI_REG_SUBID(1));
51112d14e0eSGabor Juhos
51212d14e0eSGabor Juhos err = rt3883_pci_irq_init(dev, rpc);
51312d14e0eSGabor Juhos if (err)
51412d14e0eSGabor Juhos goto err_put_hb_node;
51512d14e0eSGabor Juhos
51612d14e0eSGabor Juhos /* PCIe */
51712d14e0eSGabor Juhos val = rt3883_pci_read_cfg32(rpc, 0, 0x01, 0, PCI_COMMAND);
51812d14e0eSGabor Juhos val |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
51912d14e0eSGabor Juhos rt3883_pci_write_cfg32(rpc, 0, 0x01, 0, PCI_COMMAND, val);
52012d14e0eSGabor Juhos
52112d14e0eSGabor Juhos /* PCI */
52212d14e0eSGabor Juhos val = rt3883_pci_read_cfg32(rpc, 0, 0x00, 0, PCI_COMMAND);
52312d14e0eSGabor Juhos val |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
52412d14e0eSGabor Juhos rt3883_pci_write_cfg32(rpc, 0, 0x00, 0, PCI_COMMAND, val);
52512d14e0eSGabor Juhos
52612d14e0eSGabor Juhos if (mode == RT3883_PCI_MODE_PCIE) {
52712d14e0eSGabor Juhos rt3883_pci_w32(rpc, 0x03ff0001, RT3883_PCI_REG_BAR0SETUP(0));
52812d14e0eSGabor Juhos rt3883_pci_w32(rpc, 0x03ff0001, RT3883_PCI_REG_BAR0SETUP(1));
52912d14e0eSGabor Juhos
53012d14e0eSGabor Juhos rt3883_pci_write_cfg32(rpc, 0, RT3883_P2P_BR_DEVNUM, 0,
53112d14e0eSGabor Juhos PCI_BASE_ADDRESS_0,
53212d14e0eSGabor Juhos RT3883_MEMORY_BASE);
53312d14e0eSGabor Juhos /* flush write */
53412d14e0eSGabor Juhos rt3883_pci_read_cfg32(rpc, 0, RT3883_P2P_BR_DEVNUM, 0,
53512d14e0eSGabor Juhos PCI_BASE_ADDRESS_0);
53612d14e0eSGabor Juhos } else {
53712d14e0eSGabor Juhos rt3883_pci_write_cfg32(rpc, 0, RT3883_P2P_BR_DEVNUM, 0,
53812d14e0eSGabor Juhos PCI_IO_BASE, 0x00000101);
53912d14e0eSGabor Juhos }
54012d14e0eSGabor Juhos
54112d14e0eSGabor Juhos register_pci_controller(&rpc->pci_controller);
54212d14e0eSGabor Juhos
54312d14e0eSGabor Juhos return 0;
54412d14e0eSGabor Juhos
54512d14e0eSGabor Juhos err_put_hb_node:
54612d14e0eSGabor Juhos of_node_put(rpc->pci_controller.of_node);
54712d14e0eSGabor Juhos err_put_intc_node:
54812d14e0eSGabor Juhos of_node_put(rpc->intc_of_node);
54912d14e0eSGabor Juhos return err;
55012d14e0eSGabor Juhos }
55112d14e0eSGabor Juhos
pcibios_map_irq(const struct pci_dev * dev,u8 slot,u8 pin)5528eba3651SManuel Lauss int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
55312d14e0eSGabor Juhos {
55416b84e5aSGrant Likely return of_irq_parse_and_map_pci(dev, slot, pin);
55512d14e0eSGabor Juhos }
55612d14e0eSGabor Juhos
pcibios_plat_dev_init(struct pci_dev * dev)55712d14e0eSGabor Juhos int pcibios_plat_dev_init(struct pci_dev *dev)
55812d14e0eSGabor Juhos {
55912d14e0eSGabor Juhos return 0;
56012d14e0eSGabor Juhos }
56112d14e0eSGabor Juhos
56212d14e0eSGabor Juhos static const struct of_device_id rt3883_pci_ids[] = {
56312d14e0eSGabor Juhos { .compatible = "ralink,rt3883-pci" },
56412d14e0eSGabor Juhos {},
56512d14e0eSGabor Juhos };
56612d14e0eSGabor Juhos
56712d14e0eSGabor Juhos static struct platform_driver rt3883_pci_driver = {
56812d14e0eSGabor Juhos .probe = rt3883_pci_probe,
56912d14e0eSGabor Juhos .driver = {
57012d14e0eSGabor Juhos .name = "rt3883-pci",
57112d14e0eSGabor Juhos .of_match_table = of_match_ptr(rt3883_pci_ids),
57212d14e0eSGabor Juhos },
57312d14e0eSGabor Juhos };
57412d14e0eSGabor Juhos
rt3883_pci_init(void)57512d14e0eSGabor Juhos static int __init rt3883_pci_init(void)
57612d14e0eSGabor Juhos {
57712d14e0eSGabor Juhos return platform_driver_register(&rt3883_pci_driver);
57812d14e0eSGabor Juhos }
57912d14e0eSGabor Juhos
58012d14e0eSGabor Juhos postcore_initcall(rt3883_pci_init);
581