1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Ralink RT288x SoC PCI register definitions 4 * 5 * Copyright (C) 2009 John Crispin <john@phrozen.org> 6 * Copyright (C) 2009 Gabor Juhos <juhosg@openwrt.org> 7 * 8 * Parts of this file are based on Ralink's 2.6.21 BSP 9 */ 10 11 #include <linux/delay.h> 12 #include <linux/types.h> 13 #include <linux/pci.h> 14 #include <linux/io.h> 15 #include <linux/init.h> 16 #include <linux/of_platform.h> 17 #include <linux/of_irq.h> 18 #include <linux/of_pci.h> 19 20 #include <asm/mach-ralink/rt288x.h> 21 22 #define RT2880_PCI_BASE 0x00440000 23 #define RT288X_CPU_IRQ_PCI 4 24 25 #define RT2880_PCI_MEM_BASE 0x20000000 26 #define RT2880_PCI_MEM_SIZE 0x10000000 27 #define RT2880_PCI_IO_BASE 0x00460000 28 #define RT2880_PCI_IO_SIZE 0x00010000 29 30 #define RT2880_PCI_REG_PCICFG_ADDR 0x00 31 #define RT2880_PCI_REG_PCIMSK_ADDR 0x0c 32 #define RT2880_PCI_REG_BAR0SETUP_ADDR 0x10 33 #define RT2880_PCI_REG_IMBASEBAR0_ADDR 0x18 34 #define RT2880_PCI_REG_CONFIG_ADDR 0x20 35 #define RT2880_PCI_REG_CONFIG_DATA 0x24 36 #define RT2880_PCI_REG_MEMBASE 0x28 37 #define RT2880_PCI_REG_IOBASE 0x2c 38 #define RT2880_PCI_REG_ID 0x30 39 #define RT2880_PCI_REG_CLASS 0x34 40 #define RT2880_PCI_REG_SUBID 0x38 41 #define RT2880_PCI_REG_ARBCTL 0x80 42 43 static void __iomem *rt2880_pci_base; 44 45 static u32 rt2880_pci_reg_read(u32 reg) 46 { 47 return readl(rt2880_pci_base + reg); 48 } 49 50 static void rt2880_pci_reg_write(u32 val, u32 reg) 51 { 52 writel(val, rt2880_pci_base + reg); 53 } 54 55 static inline u32 rt2880_pci_get_cfgaddr(unsigned int bus, unsigned int slot, 56 unsigned int func, unsigned int where) 57 { 58 return ((bus << 16) | (slot << 11) | (func << 8) | (where & 0xfc) | 59 0x80000000); 60 } 61 62 static int rt2880_pci_config_read(struct pci_bus *bus, unsigned int devfn, 63 int where, int size, u32 *val) 64 { 65 u32 address; 66 u32 data; 67 68 address = rt2880_pci_get_cfgaddr(bus->number, PCI_SLOT(devfn), 69 PCI_FUNC(devfn), where); 70 71 rt2880_pci_reg_write(address, RT2880_PCI_REG_CONFIG_ADDR); 72 data = rt2880_pci_reg_read(RT2880_PCI_REG_CONFIG_DATA); 73 74 switch (size) { 75 case 1: 76 *val = (data >> ((where & 3) << 3)) & 0xff; 77 break; 78 case 2: 79 *val = (data >> ((where & 3) << 3)) & 0xffff; 80 break; 81 case 4: 82 *val = data; 83 break; 84 } 85 86 return PCIBIOS_SUCCESSFUL; 87 } 88 89 static int rt2880_pci_config_write(struct pci_bus *bus, unsigned int devfn, 90 int where, int size, u32 val) 91 { 92 u32 address; 93 u32 data; 94 95 address = rt2880_pci_get_cfgaddr(bus->number, PCI_SLOT(devfn), 96 PCI_FUNC(devfn), where); 97 98 rt2880_pci_reg_write(address, RT2880_PCI_REG_CONFIG_ADDR); 99 data = rt2880_pci_reg_read(RT2880_PCI_REG_CONFIG_DATA); 100 101 switch (size) { 102 case 1: 103 data = (data & ~(0xff << ((where & 3) << 3))) | 104 (val << ((where & 3) << 3)); 105 break; 106 case 2: 107 data = (data & ~(0xffff << ((where & 3) << 3))) | 108 (val << ((where & 3) << 3)); 109 break; 110 case 4: 111 data = val; 112 break; 113 } 114 115 rt2880_pci_reg_write(data, RT2880_PCI_REG_CONFIG_DATA); 116 117 return PCIBIOS_SUCCESSFUL; 118 } 119 120 static struct pci_ops rt2880_pci_ops = { 121 .read = rt2880_pci_config_read, 122 .write = rt2880_pci_config_write, 123 }; 124 125 static struct resource rt2880_pci_mem_resource = { 126 .name = "PCI MEM space", 127 .start = RT2880_PCI_MEM_BASE, 128 .end = RT2880_PCI_MEM_BASE + RT2880_PCI_MEM_SIZE - 1, 129 .flags = IORESOURCE_MEM, 130 }; 131 132 static struct resource rt2880_pci_io_resource = { 133 .name = "PCI IO space", 134 .start = RT2880_PCI_IO_BASE, 135 .end = RT2880_PCI_IO_BASE + RT2880_PCI_IO_SIZE - 1, 136 .flags = IORESOURCE_IO, 137 }; 138 139 static struct pci_controller rt2880_pci_controller = { 140 .pci_ops = &rt2880_pci_ops, 141 .mem_resource = &rt2880_pci_mem_resource, 142 .io_resource = &rt2880_pci_io_resource, 143 }; 144 145 static inline u32 rt2880_pci_read_u32(unsigned long reg) 146 { 147 u32 address; 148 u32 ret; 149 150 address = rt2880_pci_get_cfgaddr(0, 0, 0, reg); 151 152 rt2880_pci_reg_write(address, RT2880_PCI_REG_CONFIG_ADDR); 153 ret = rt2880_pci_reg_read(RT2880_PCI_REG_CONFIG_DATA); 154 155 return ret; 156 } 157 158 static inline void rt2880_pci_write_u32(unsigned long reg, u32 val) 159 { 160 u32 address; 161 162 address = rt2880_pci_get_cfgaddr(0, 0, 0, reg); 163 164 rt2880_pci_reg_write(address, RT2880_PCI_REG_CONFIG_ADDR); 165 rt2880_pci_reg_write(val, RT2880_PCI_REG_CONFIG_DATA); 166 } 167 168 int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) 169 { 170 int irq = -1; 171 172 if (dev->bus->number != 0) 173 return irq; 174 175 switch (PCI_SLOT(dev->devfn)) { 176 case 0x00: 177 break; 178 case 0x11: 179 irq = RT288X_CPU_IRQ_PCI; 180 break; 181 default: 182 pr_err("%s:%s[%d] trying to alloc unknown pci irq\n", 183 __FILE__, __func__, __LINE__); 184 BUG(); 185 break; 186 } 187 188 return irq; 189 } 190 191 static int rt288x_pci_probe(struct platform_device *pdev) 192 { 193 void __iomem *io_map_base; 194 195 rt2880_pci_base = ioremap(RT2880_PCI_BASE, PAGE_SIZE); 196 197 io_map_base = ioremap(RT2880_PCI_IO_BASE, RT2880_PCI_IO_SIZE); 198 rt2880_pci_controller.io_map_base = (unsigned long) io_map_base; 199 set_io_port_base((unsigned long) io_map_base); 200 201 ioport_resource.start = RT2880_PCI_IO_BASE; 202 ioport_resource.end = RT2880_PCI_IO_BASE + RT2880_PCI_IO_SIZE - 1; 203 204 rt2880_pci_reg_write(0, RT2880_PCI_REG_PCICFG_ADDR); 205 udelay(1); 206 207 rt2880_pci_reg_write(0x79, RT2880_PCI_REG_ARBCTL); 208 rt2880_pci_reg_write(0x07FF0001, RT2880_PCI_REG_BAR0SETUP_ADDR); 209 rt2880_pci_reg_write(RT2880_PCI_MEM_BASE, RT2880_PCI_REG_MEMBASE); 210 rt2880_pci_reg_write(RT2880_PCI_IO_BASE, RT2880_PCI_REG_IOBASE); 211 rt2880_pci_reg_write(0x08000000, RT2880_PCI_REG_IMBASEBAR0_ADDR); 212 rt2880_pci_reg_write(0x08021814, RT2880_PCI_REG_ID); 213 rt2880_pci_reg_write(0x00800001, RT2880_PCI_REG_CLASS); 214 rt2880_pci_reg_write(0x28801814, RT2880_PCI_REG_SUBID); 215 rt2880_pci_reg_write(0x000c0000, RT2880_PCI_REG_PCIMSK_ADDR); 216 217 rt2880_pci_write_u32(PCI_BASE_ADDRESS_0, 0x08000000); 218 (void) rt2880_pci_read_u32(PCI_BASE_ADDRESS_0); 219 220 rt2880_pci_controller.of_node = pdev->dev.of_node; 221 222 register_pci_controller(&rt2880_pci_controller); 223 return 0; 224 } 225 226 int pcibios_plat_dev_init(struct pci_dev *dev) 227 { 228 static bool slot0_init; 229 230 /* 231 * Nobody seems to initialize slot 0, but this platform requires it, so 232 * do it once when some other slot is being enabled. The PCI subsystem 233 * should configure other slots properly, so no need to do anything 234 * special for those. 235 */ 236 if (!slot0_init && dev->bus->number == 0) { 237 u16 cmd; 238 u32 bar0; 239 240 slot0_init = true; 241 242 pci_bus_write_config_dword(dev->bus, 0, PCI_BASE_ADDRESS_0, 243 0x08000000); 244 pci_bus_read_config_dword(dev->bus, 0, PCI_BASE_ADDRESS_0, 245 &bar0); 246 247 pci_bus_read_config_word(dev->bus, 0, PCI_COMMAND, &cmd); 248 cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_IO | PCI_COMMAND_MEMORY; 249 pci_bus_write_config_word(dev->bus, 0, PCI_COMMAND, cmd); 250 } 251 252 return 0; 253 } 254 255 static const struct of_device_id rt288x_pci_match[] = { 256 { .compatible = "ralink,rt288x-pci" }, 257 {}, 258 }; 259 260 static struct platform_driver rt288x_pci_driver = { 261 .probe = rt288x_pci_probe, 262 .driver = { 263 .name = "rt288x-pci", 264 .of_match_table = rt288x_pci_match, 265 }, 266 }; 267 268 int __init pcibios_init(void) 269 { 270 int ret = platform_driver_register(&rt288x_pci_driver); 271 272 if (ret) 273 pr_info("rt288x-pci: Error registering platform driver!"); 274 275 return ret; 276 } 277 278 arch_initcall(pcibios_init); 279