1 /* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * Copyright (C) 2005-2009 Cavium Networks 7 */ 8 #include <linux/kernel.h> 9 #include <linux/init.h> 10 #include <linux/pci.h> 11 #include <linux/interrupt.h> 12 #include <linux/time.h> 13 #include <linux/delay.h> 14 #include <linux/platform_device.h> 15 #include <linux/swiotlb.h> 16 17 #include <asm/time.h> 18 19 #include <asm/octeon/octeon.h> 20 #include <asm/octeon/cvmx-npi-defs.h> 21 #include <asm/octeon/cvmx-pci-defs.h> 22 #include <asm/octeon/pci-octeon.h> 23 24 #include <dma-coherence.h> 25 26 #define USE_OCTEON_INTERNAL_ARBITER 27 28 /* 29 * Octeon's PCI controller uses did=3, subdid=2 for PCI IO 30 * addresses. Use PCI endian swapping 1 so no address swapping is 31 * necessary. The Linux io routines will endian swap the data. 32 */ 33 #define OCTEON_PCI_IOSPACE_BASE 0x80011a0400000000ull 34 #define OCTEON_PCI_IOSPACE_SIZE (1ull<<32) 35 36 /* Octeon't PCI controller uses did=3, subdid=3 for PCI memory. */ 37 #define OCTEON_PCI_MEMSPACE_OFFSET (0x00011b0000000000ull) 38 39 u64 octeon_bar1_pci_phys; 40 41 /** 42 * This is the bit decoding used for the Octeon PCI controller addresses 43 */ 44 union octeon_pci_address { 45 uint64_t u64; 46 struct { 47 uint64_t upper:2; 48 uint64_t reserved:13; 49 uint64_t io:1; 50 uint64_t did:5; 51 uint64_t subdid:3; 52 uint64_t reserved2:4; 53 uint64_t endian_swap:2; 54 uint64_t reserved3:10; 55 uint64_t bus:8; 56 uint64_t dev:5; 57 uint64_t func:3; 58 uint64_t reg:8; 59 } s; 60 }; 61 62 int (*octeon_pcibios_map_irq)(const struct pci_dev *dev, u8 slot, u8 pin); 63 enum octeon_dma_bar_type octeon_dma_bar_type = OCTEON_DMA_BAR_TYPE_INVALID; 64 65 /** 66 * Map a PCI device to the appropriate interrupt line 67 * 68 * @dev: The Linux PCI device structure for the device to map 69 * @slot: The slot number for this device on __BUS 0__. Linux 70 * enumerates through all the bridges and figures out the 71 * slot on Bus 0 where this device eventually hooks to. 72 * @pin: The PCI interrupt pin read from the device, then swizzled 73 * as it goes through each bridge. 74 * Returns Interrupt number for the device 75 */ 76 int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) 77 { 78 if (octeon_pcibios_map_irq) 79 return octeon_pcibios_map_irq(dev, slot, pin); 80 else 81 panic("octeon_pcibios_map_irq not set."); 82 } 83 84 85 /* 86 * Called to perform platform specific PCI setup 87 */ 88 int pcibios_plat_dev_init(struct pci_dev *dev) 89 { 90 uint16_t config; 91 uint32_t dconfig; 92 int pos; 93 /* 94 * Force the Cache line setting to 64 bytes. The standard 95 * Linux bus scan doesn't seem to set it. Octeon really has 96 * 128 byte lines, but Intel bridges get really upset if you 97 * try and set values above 64 bytes. Value is specified in 98 * 32bit words. 99 */ 100 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 64 / 4); 101 /* Set latency timers for all devices */ 102 pci_write_config_byte(dev, PCI_LATENCY_TIMER, 64); 103 104 /* Enable reporting System errors and parity errors on all devices */ 105 /* Enable parity checking and error reporting */ 106 pci_read_config_word(dev, PCI_COMMAND, &config); 107 config |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR; 108 pci_write_config_word(dev, PCI_COMMAND, config); 109 110 if (dev->subordinate) { 111 /* Set latency timers on sub bridges */ 112 pci_write_config_byte(dev, PCI_SEC_LATENCY_TIMER, 64); 113 /* More bridge error detection */ 114 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &config); 115 config |= PCI_BRIDGE_CTL_PARITY | PCI_BRIDGE_CTL_SERR; 116 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, config); 117 } 118 119 /* Enable the PCIe normal error reporting */ 120 config = PCI_EXP_DEVCTL_CERE; /* Correctable Error Reporting */ 121 config |= PCI_EXP_DEVCTL_NFERE; /* Non-Fatal Error Reporting */ 122 config |= PCI_EXP_DEVCTL_FERE; /* Fatal Error Reporting */ 123 config |= PCI_EXP_DEVCTL_URRE; /* Unsupported Request */ 124 pcie_capability_set_word(dev, PCI_EXP_DEVCTL, config); 125 126 /* Find the Advanced Error Reporting capability */ 127 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR); 128 if (pos) { 129 /* Clear Uncorrectable Error Status */ 130 pci_read_config_dword(dev, pos + PCI_ERR_UNCOR_STATUS, 131 &dconfig); 132 pci_write_config_dword(dev, pos + PCI_ERR_UNCOR_STATUS, 133 dconfig); 134 /* Enable reporting of all uncorrectable errors */ 135 /* Uncorrectable Error Mask - turned on bits disable errors */ 136 pci_write_config_dword(dev, pos + PCI_ERR_UNCOR_MASK, 0); 137 /* 138 * Leave severity at HW default. This only controls if 139 * errors are reported as uncorrectable or 140 * correctable, not if the error is reported. 141 */ 142 /* PCI_ERR_UNCOR_SEVER - Uncorrectable Error Severity */ 143 /* Clear Correctable Error Status */ 144 pci_read_config_dword(dev, pos + PCI_ERR_COR_STATUS, &dconfig); 145 pci_write_config_dword(dev, pos + PCI_ERR_COR_STATUS, dconfig); 146 /* Enable reporting of all correctable errors */ 147 /* Correctable Error Mask - turned on bits disable errors */ 148 pci_write_config_dword(dev, pos + PCI_ERR_COR_MASK, 0); 149 /* Advanced Error Capabilities */ 150 pci_read_config_dword(dev, pos + PCI_ERR_CAP, &dconfig); 151 /* ECRC Generation Enable */ 152 if (config & PCI_ERR_CAP_ECRC_GENC) 153 config |= PCI_ERR_CAP_ECRC_GENE; 154 /* ECRC Check Enable */ 155 if (config & PCI_ERR_CAP_ECRC_CHKC) 156 config |= PCI_ERR_CAP_ECRC_CHKE; 157 pci_write_config_dword(dev, pos + PCI_ERR_CAP, dconfig); 158 /* PCI_ERR_HEADER_LOG - Header Log Register (16 bytes) */ 159 /* Report all errors to the root complex */ 160 pci_write_config_dword(dev, pos + PCI_ERR_ROOT_COMMAND, 161 PCI_ERR_ROOT_CMD_COR_EN | 162 PCI_ERR_ROOT_CMD_NONFATAL_EN | 163 PCI_ERR_ROOT_CMD_FATAL_EN); 164 /* Clear the Root status register */ 165 pci_read_config_dword(dev, pos + PCI_ERR_ROOT_STATUS, &dconfig); 166 pci_write_config_dword(dev, pos + PCI_ERR_ROOT_STATUS, dconfig); 167 } 168 169 return 0; 170 } 171 172 /** 173 * Return the mapping of PCI device number to IRQ line. Each 174 * character in the return string represents the interrupt 175 * line for the device at that position. Device 1 maps to the 176 * first character, etc. The characters A-D are used for PCI 177 * interrupts. 178 * 179 * Returns PCI interrupt mapping 180 */ 181 const char *octeon_get_pci_interrupts(void) 182 { 183 /* 184 * Returning an empty string causes the interrupts to be 185 * routed based on the PCI specification. From the PCI spec: 186 * 187 * INTA# of Device Number 0 is connected to IRQW on the system 188 * board. (Device Number has no significance regarding being 189 * located on the system board or in a connector.) INTA# of 190 * Device Number 1 is connected to IRQX on the system 191 * board. INTA# of Device Number 2 is connected to IRQY on the 192 * system board. INTA# of Device Number 3 is connected to IRQZ 193 * on the system board. The table below describes how each 194 * agent's INTx# lines are connected to the system board 195 * interrupt lines. The following equation can be used to 196 * determine to which INTx# signal on the system board a given 197 * device's INTx# line(s) is connected. 198 * 199 * MB = (D + I) MOD 4 MB = System board Interrupt (IRQW = 0, 200 * IRQX = 1, IRQY = 2, and IRQZ = 3) D = Device Number I = 201 * Interrupt Number (INTA# = 0, INTB# = 1, INTC# = 2, and 202 * INTD# = 3) 203 */ 204 if (of_machine_is_compatible("dlink,dsr-500n")) 205 return "CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC"; 206 switch (octeon_bootinfo->board_type) { 207 case CVMX_BOARD_TYPE_NAO38: 208 /* This is really the NAC38 */ 209 return "AAAAADABAAAAAAAAAAAAAAAAAAAAAAAA"; 210 case CVMX_BOARD_TYPE_EBH3100: 211 case CVMX_BOARD_TYPE_CN3010_EVB_HS5: 212 case CVMX_BOARD_TYPE_CN3005_EVB_HS5: 213 return "AAABAAAAAAAAAAAAAAAAAAAAAAAAAAAA"; 214 case CVMX_BOARD_TYPE_BBGW_REF: 215 return "AABCD"; 216 case CVMX_BOARD_TYPE_CUST_DSR1000N: 217 return "CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC"; 218 case CVMX_BOARD_TYPE_THUNDER: 219 case CVMX_BOARD_TYPE_EBH3000: 220 default: 221 return ""; 222 } 223 } 224 225 /** 226 * Map a PCI device to the appropriate interrupt line 227 * 228 * @dev: The Linux PCI device structure for the device to map 229 * @slot: The slot number for this device on __BUS 0__. Linux 230 * enumerates through all the bridges and figures out the 231 * slot on Bus 0 where this device eventually hooks to. 232 * @pin: The PCI interrupt pin read from the device, then swizzled 233 * as it goes through each bridge. 234 * Returns Interrupt number for the device 235 */ 236 int __init octeon_pci_pcibios_map_irq(const struct pci_dev *dev, 237 u8 slot, u8 pin) 238 { 239 int irq_num; 240 const char *interrupts; 241 int dev_num; 242 243 /* Get the board specific interrupt mapping */ 244 interrupts = octeon_get_pci_interrupts(); 245 246 dev_num = dev->devfn >> 3; 247 if (dev_num < strlen(interrupts)) 248 irq_num = ((interrupts[dev_num] - 'A' + pin - 1) & 3) + 249 OCTEON_IRQ_PCI_INT0; 250 else 251 irq_num = ((slot + pin - 3) & 3) + OCTEON_IRQ_PCI_INT0; 252 return irq_num; 253 } 254 255 256 /* 257 * Read a value from configuration space 258 */ 259 static int octeon_read_config(struct pci_bus *bus, unsigned int devfn, 260 int reg, int size, u32 *val) 261 { 262 union octeon_pci_address pci_addr; 263 264 pci_addr.u64 = 0; 265 pci_addr.s.upper = 2; 266 pci_addr.s.io = 1; 267 pci_addr.s.did = 3; 268 pci_addr.s.subdid = 1; 269 pci_addr.s.endian_swap = 1; 270 pci_addr.s.bus = bus->number; 271 pci_addr.s.dev = devfn >> 3; 272 pci_addr.s.func = devfn & 0x7; 273 pci_addr.s.reg = reg; 274 275 switch (size) { 276 case 4: 277 *val = le32_to_cpu(cvmx_read64_uint32(pci_addr.u64)); 278 return PCIBIOS_SUCCESSFUL; 279 case 2: 280 *val = le16_to_cpu(cvmx_read64_uint16(pci_addr.u64)); 281 return PCIBIOS_SUCCESSFUL; 282 case 1: 283 *val = cvmx_read64_uint8(pci_addr.u64); 284 return PCIBIOS_SUCCESSFUL; 285 } 286 return PCIBIOS_FUNC_NOT_SUPPORTED; 287 } 288 289 290 /* 291 * Write a value to PCI configuration space 292 */ 293 static int octeon_write_config(struct pci_bus *bus, unsigned int devfn, 294 int reg, int size, u32 val) 295 { 296 union octeon_pci_address pci_addr; 297 298 pci_addr.u64 = 0; 299 pci_addr.s.upper = 2; 300 pci_addr.s.io = 1; 301 pci_addr.s.did = 3; 302 pci_addr.s.subdid = 1; 303 pci_addr.s.endian_swap = 1; 304 pci_addr.s.bus = bus->number; 305 pci_addr.s.dev = devfn >> 3; 306 pci_addr.s.func = devfn & 0x7; 307 pci_addr.s.reg = reg; 308 309 switch (size) { 310 case 4: 311 cvmx_write64_uint32(pci_addr.u64, cpu_to_le32(val)); 312 return PCIBIOS_SUCCESSFUL; 313 case 2: 314 cvmx_write64_uint16(pci_addr.u64, cpu_to_le16(val)); 315 return PCIBIOS_SUCCESSFUL; 316 case 1: 317 cvmx_write64_uint8(pci_addr.u64, val); 318 return PCIBIOS_SUCCESSFUL; 319 } 320 return PCIBIOS_FUNC_NOT_SUPPORTED; 321 } 322 323 324 static struct pci_ops octeon_pci_ops = { 325 .read = octeon_read_config, 326 .write = octeon_write_config, 327 }; 328 329 static struct resource octeon_pci_mem_resource = { 330 .start = 0, 331 .end = 0, 332 .name = "Octeon PCI MEM", 333 .flags = IORESOURCE_MEM, 334 }; 335 336 /* 337 * PCI ports must be above 16KB so the ISA bus filtering in the PCI-X to PCI 338 * bridge 339 */ 340 static struct resource octeon_pci_io_resource = { 341 .start = 0x4000, 342 .end = OCTEON_PCI_IOSPACE_SIZE - 1, 343 .name = "Octeon PCI IO", 344 .flags = IORESOURCE_IO, 345 }; 346 347 static struct pci_controller octeon_pci_controller = { 348 .pci_ops = &octeon_pci_ops, 349 .mem_resource = &octeon_pci_mem_resource, 350 .mem_offset = OCTEON_PCI_MEMSPACE_OFFSET, 351 .io_resource = &octeon_pci_io_resource, 352 .io_offset = 0, 353 .io_map_base = OCTEON_PCI_IOSPACE_BASE, 354 }; 355 356 357 /* 358 * Low level initialize the Octeon PCI controller 359 */ 360 static void octeon_pci_initialize(void) 361 { 362 union cvmx_pci_cfg01 cfg01; 363 union cvmx_npi_ctl_status ctl_status; 364 union cvmx_pci_ctl_status_2 ctl_status_2; 365 union cvmx_pci_cfg19 cfg19; 366 union cvmx_pci_cfg16 cfg16; 367 union cvmx_pci_cfg22 cfg22; 368 union cvmx_pci_cfg56 cfg56; 369 370 /* Reset the PCI Bus */ 371 cvmx_write_csr(CVMX_CIU_SOFT_PRST, 0x1); 372 cvmx_read_csr(CVMX_CIU_SOFT_PRST); 373 374 udelay(2000); /* Hold PCI reset for 2 ms */ 375 376 ctl_status.u64 = 0; /* cvmx_read_csr(CVMX_NPI_CTL_STATUS); */ 377 ctl_status.s.max_word = 1; 378 ctl_status.s.timer = 1; 379 cvmx_write_csr(CVMX_NPI_CTL_STATUS, ctl_status.u64); 380 381 /* Deassert PCI reset and advertize PCX Host Mode Device Capability 382 (64b) */ 383 cvmx_write_csr(CVMX_CIU_SOFT_PRST, 0x4); 384 cvmx_read_csr(CVMX_CIU_SOFT_PRST); 385 386 udelay(2000); /* Wait 2 ms after deasserting PCI reset */ 387 388 ctl_status_2.u32 = 0; 389 ctl_status_2.s.tsr_hwm = 1; /* Initializes to 0. Must be set 390 before any PCI reads. */ 391 ctl_status_2.s.bar2pres = 1; /* Enable BAR2 */ 392 ctl_status_2.s.bar2_enb = 1; 393 ctl_status_2.s.bar2_cax = 1; /* Don't use L2 */ 394 ctl_status_2.s.bar2_esx = 1; 395 ctl_status_2.s.pmo_amod = 1; /* Round robin priority */ 396 if (octeon_dma_bar_type == OCTEON_DMA_BAR_TYPE_BIG) { 397 /* BAR1 hole */ 398 ctl_status_2.s.bb1_hole = OCTEON_PCI_BAR1_HOLE_BITS; 399 ctl_status_2.s.bb1_siz = 1; /* BAR1 is 2GB */ 400 ctl_status_2.s.bb_ca = 1; /* Don't use L2 with big bars */ 401 ctl_status_2.s.bb_es = 1; /* Big bar in byte swap mode */ 402 ctl_status_2.s.bb1 = 1; /* BAR1 is big */ 403 ctl_status_2.s.bb0 = 1; /* BAR0 is big */ 404 } 405 406 octeon_npi_write32(CVMX_NPI_PCI_CTL_STATUS_2, ctl_status_2.u32); 407 udelay(2000); /* Wait 2 ms before doing PCI reads */ 408 409 ctl_status_2.u32 = octeon_npi_read32(CVMX_NPI_PCI_CTL_STATUS_2); 410 pr_notice("PCI Status: %s %s-bit\n", 411 ctl_status_2.s.ap_pcix ? "PCI-X" : "PCI", 412 ctl_status_2.s.ap_64ad ? "64" : "32"); 413 414 if (OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN50XX)) { 415 union cvmx_pci_cnt_reg cnt_reg_start; 416 union cvmx_pci_cnt_reg cnt_reg_end; 417 unsigned long cycles, pci_clock; 418 419 cnt_reg_start.u64 = cvmx_read_csr(CVMX_NPI_PCI_CNT_REG); 420 cycles = read_c0_cvmcount(); 421 udelay(1000); 422 cnt_reg_end.u64 = cvmx_read_csr(CVMX_NPI_PCI_CNT_REG); 423 cycles = read_c0_cvmcount() - cycles; 424 pci_clock = (cnt_reg_end.s.pcicnt - cnt_reg_start.s.pcicnt) / 425 (cycles / (mips_hpt_frequency / 1000000)); 426 pr_notice("PCI Clock: %lu MHz\n", pci_clock); 427 } 428 429 /* 430 * TDOMC must be set to one in PCI mode. TDOMC should be set to 4 431 * in PCI-X mode to allow four outstanding splits. Otherwise, 432 * should not change from its reset value. Don't write PCI_CFG19 433 * in PCI mode (0x82000001 reset value), write it to 0x82000004 434 * after PCI-X mode is known. MRBCI,MDWE,MDRE -> must be zero. 435 * MRBCM -> must be one. 436 */ 437 if (ctl_status_2.s.ap_pcix) { 438 cfg19.u32 = 0; 439 /* 440 * Target Delayed/Split request outstanding maximum 441 * count. [1..31] and 0=32. NOTE: If the user 442 * programs these bits beyond the Designed Maximum 443 * outstanding count, then the designed maximum table 444 * depth will be used instead. No additional 445 * Deferred/Split transactions will be accepted if 446 * this outstanding maximum count is 447 * reached. Furthermore, no additional deferred/split 448 * transactions will be accepted if the I/O delay/ I/O 449 * Split Request outstanding maximum is reached. 450 */ 451 cfg19.s.tdomc = 4; 452 /* 453 * Master Deferred Read Request Outstanding Max Count 454 * (PCI only). CR4C[26:24] Max SAC cycles MAX DAC 455 * cycles 000 8 4 001 1 0 010 2 1 011 3 1 100 4 2 101 456 * 5 2 110 6 3 111 7 3 For example, if these bits are 457 * programmed to 100, the core can support 2 DAC 458 * cycles, 4 SAC cycles or a combination of 1 DAC and 459 * 2 SAC cycles. NOTE: For the PCI-X maximum 460 * outstanding split transactions, refer to 461 * CRE0[22:20]. 462 */ 463 cfg19.s.mdrrmc = 2; 464 /* 465 * Master Request (Memory Read) Byte Count/Byte Enable 466 * select. 0 = Byte Enables valid. In PCI mode, a 467 * burst transaction cannot be performed using Memory 468 * Read command=4?h6. 1 = DWORD Byte Count valid 469 * (default). In PCI Mode, the memory read byte 470 * enables are automatically generated by the 471 * core. Note: N3 Master Request transaction sizes are 472 * always determined through the 473 * am_attr[<35:32>|<7:0>] field. 474 */ 475 cfg19.s.mrbcm = 1; 476 octeon_npi_write32(CVMX_NPI_PCI_CFG19, cfg19.u32); 477 } 478 479 480 cfg01.u32 = 0; 481 cfg01.s.msae = 1; /* Memory Space Access Enable */ 482 cfg01.s.me = 1; /* Master Enable */ 483 cfg01.s.pee = 1; /* PERR# Enable */ 484 cfg01.s.see = 1; /* System Error Enable */ 485 cfg01.s.fbbe = 1; /* Fast Back to Back Transaction Enable */ 486 487 octeon_npi_write32(CVMX_NPI_PCI_CFG01, cfg01.u32); 488 489 #ifdef USE_OCTEON_INTERNAL_ARBITER 490 /* 491 * When OCTEON is a PCI host, most systems will use OCTEON's 492 * internal arbiter, so must enable it before any PCI/PCI-X 493 * traffic can occur. 494 */ 495 { 496 union cvmx_npi_pci_int_arb_cfg pci_int_arb_cfg; 497 498 pci_int_arb_cfg.u64 = 0; 499 pci_int_arb_cfg.s.en = 1; /* Internal arbiter enable */ 500 cvmx_write_csr(CVMX_NPI_PCI_INT_ARB_CFG, pci_int_arb_cfg.u64); 501 } 502 #endif /* USE_OCTEON_INTERNAL_ARBITER */ 503 504 /* 505 * Preferably written to 1 to set MLTD. [RDSATI,TRTAE, 506 * TWTAE,TMAE,DPPMR -> must be zero. TILT -> must not be set to 507 * 1..7. 508 */ 509 cfg16.u32 = 0; 510 cfg16.s.mltd = 1; /* Master Latency Timer Disable */ 511 octeon_npi_write32(CVMX_NPI_PCI_CFG16, cfg16.u32); 512 513 /* 514 * Should be written to 0x4ff00. MTTV -> must be zero. 515 * FLUSH -> must be 1. MRV -> should be 0xFF. 516 */ 517 cfg22.u32 = 0; 518 /* Master Retry Value [1..255] and 0=infinite */ 519 cfg22.s.mrv = 0xff; 520 /* 521 * AM_DO_FLUSH_I control NOTE: This bit MUST BE ONE for proper 522 * N3K operation. 523 */ 524 cfg22.s.flush = 1; 525 octeon_npi_write32(CVMX_NPI_PCI_CFG22, cfg22.u32); 526 527 /* 528 * MOST Indicates the maximum number of outstanding splits (in -1 529 * notation) when OCTEON is in PCI-X mode. PCI-X performance is 530 * affected by the MOST selection. Should generally be written 531 * with one of 0x3be807, 0x2be807, 0x1be807, or 0x0be807, 532 * depending on the desired MOST of 3, 2, 1, or 0, respectively. 533 */ 534 cfg56.u32 = 0; 535 cfg56.s.pxcid = 7; /* RO - PCI-X Capability ID */ 536 cfg56.s.ncp = 0xe8; /* RO - Next Capability Pointer */ 537 cfg56.s.dpere = 1; /* Data Parity Error Recovery Enable */ 538 cfg56.s.roe = 1; /* Relaxed Ordering Enable */ 539 cfg56.s.mmbc = 1; /* Maximum Memory Byte Count 540 [0=512B,1=1024B,2=2048B,3=4096B] */ 541 cfg56.s.most = 3; /* Maximum outstanding Split transactions [0=1 542 .. 7=32] */ 543 544 octeon_npi_write32(CVMX_NPI_PCI_CFG56, cfg56.u32); 545 546 /* 547 * Affects PCI performance when OCTEON services reads to its 548 * BAR1/BAR2. Refer to Section 10.6.1. The recommended values are 549 * 0x22, 0x33, and 0x33 for PCI_READ_CMD_6, PCI_READ_CMD_C, and 550 * PCI_READ_CMD_E, respectively. Unfortunately due to errata DDR-700, 551 * these values need to be changed so they won't possibly prefetch off 552 * of the end of memory if PCI is DMAing a buffer at the end of 553 * memory. Note that these values differ from their reset values. 554 */ 555 octeon_npi_write32(CVMX_NPI_PCI_READ_CMD_6, 0x21); 556 octeon_npi_write32(CVMX_NPI_PCI_READ_CMD_C, 0x31); 557 octeon_npi_write32(CVMX_NPI_PCI_READ_CMD_E, 0x31); 558 } 559 560 561 /* 562 * Initialize the Octeon PCI controller 563 */ 564 static int __init octeon_pci_setup(void) 565 { 566 union cvmx_npi_mem_access_subidx mem_access; 567 int index; 568 569 /* Only these chips have PCI */ 570 if (octeon_has_feature(OCTEON_FEATURE_PCIE)) 571 return 0; 572 573 /* Point pcibios_map_irq() to the PCI version of it */ 574 octeon_pcibios_map_irq = octeon_pci_pcibios_map_irq; 575 576 /* Only use the big bars on chips that support it */ 577 if (OCTEON_IS_MODEL(OCTEON_CN31XX) || 578 OCTEON_IS_MODEL(OCTEON_CN38XX_PASS2) || 579 OCTEON_IS_MODEL(OCTEON_CN38XX_PASS1)) 580 octeon_dma_bar_type = OCTEON_DMA_BAR_TYPE_SMALL; 581 else 582 octeon_dma_bar_type = OCTEON_DMA_BAR_TYPE_BIG; 583 584 if (!octeon_is_pci_host()) { 585 pr_notice("Not in host mode, PCI Controller not initialized\n"); 586 return 0; 587 } 588 589 /* PCI I/O and PCI MEM values */ 590 set_io_port_base(OCTEON_PCI_IOSPACE_BASE); 591 ioport_resource.start = 0; 592 ioport_resource.end = OCTEON_PCI_IOSPACE_SIZE - 1; 593 594 pr_notice("%s Octeon big bar support\n", 595 (octeon_dma_bar_type == 596 OCTEON_DMA_BAR_TYPE_BIG) ? "Enabling" : "Disabling"); 597 598 octeon_pci_initialize(); 599 600 mem_access.u64 = 0; 601 mem_access.s.esr = 1; /* Endian-Swap on read. */ 602 mem_access.s.esw = 1; /* Endian-Swap on write. */ 603 mem_access.s.nsr = 0; /* No-Snoop on read. */ 604 mem_access.s.nsw = 0; /* No-Snoop on write. */ 605 mem_access.s.ror = 0; /* Relax Read on read. */ 606 mem_access.s.row = 0; /* Relax Order on write. */ 607 mem_access.s.ba = 0; /* PCI Address bits [63:36]. */ 608 cvmx_write_csr(CVMX_NPI_MEM_ACCESS_SUBID3, mem_access.u64); 609 610 /* 611 * Remap the Octeon BAR 2 above all 32 bit devices 612 * (0x8000000000ul). This is done here so it is remapped 613 * before the readl()'s below. We don't want BAR2 overlapping 614 * with BAR0/BAR1 during these reads. 615 */ 616 octeon_npi_write32(CVMX_NPI_PCI_CFG08, 617 (u32)(OCTEON_BAR2_PCI_ADDRESS & 0xffffffffull)); 618 octeon_npi_write32(CVMX_NPI_PCI_CFG09, 619 (u32)(OCTEON_BAR2_PCI_ADDRESS >> 32)); 620 621 if (octeon_dma_bar_type == OCTEON_DMA_BAR_TYPE_BIG) { 622 /* Remap the Octeon BAR 0 to 0-2GB */ 623 octeon_npi_write32(CVMX_NPI_PCI_CFG04, 0); 624 octeon_npi_write32(CVMX_NPI_PCI_CFG05, 0); 625 626 /* 627 * Remap the Octeon BAR 1 to map 2GB-4GB (minus the 628 * BAR 1 hole). 629 */ 630 octeon_npi_write32(CVMX_NPI_PCI_CFG06, 2ul << 30); 631 octeon_npi_write32(CVMX_NPI_PCI_CFG07, 0); 632 633 /* BAR1 movable mappings set for identity mapping */ 634 octeon_bar1_pci_phys = 0x80000000ull; 635 for (index = 0; index < 32; index++) { 636 union cvmx_pci_bar1_indexx bar1_index; 637 638 bar1_index.u32 = 0; 639 /* Address bits[35:22] sent to L2C */ 640 bar1_index.s.addr_idx = 641 (octeon_bar1_pci_phys >> 22) + index; 642 /* Don't put PCI accesses in L2. */ 643 bar1_index.s.ca = 1; 644 /* Endian Swap Mode */ 645 bar1_index.s.end_swp = 1; 646 /* Set '1' when the selected address range is valid. */ 647 bar1_index.s.addr_v = 1; 648 octeon_npi_write32(CVMX_NPI_PCI_BAR1_INDEXX(index), 649 bar1_index.u32); 650 } 651 652 /* Devices go after BAR1 */ 653 octeon_pci_mem_resource.start = 654 OCTEON_PCI_MEMSPACE_OFFSET + (4ul << 30) - 655 (OCTEON_PCI_BAR1_HOLE_SIZE << 20); 656 octeon_pci_mem_resource.end = 657 octeon_pci_mem_resource.start + (1ul << 30); 658 } else { 659 /* Remap the Octeon BAR 0 to map 128MB-(128MB+4KB) */ 660 octeon_npi_write32(CVMX_NPI_PCI_CFG04, 128ul << 20); 661 octeon_npi_write32(CVMX_NPI_PCI_CFG05, 0); 662 663 /* Remap the Octeon BAR 1 to map 0-128MB */ 664 octeon_npi_write32(CVMX_NPI_PCI_CFG06, 0); 665 octeon_npi_write32(CVMX_NPI_PCI_CFG07, 0); 666 667 /* BAR1 movable regions contiguous to cover the swiotlb */ 668 octeon_bar1_pci_phys = 669 virt_to_phys(octeon_swiotlb) & ~((1ull << 22) - 1); 670 671 for (index = 0; index < 32; index++) { 672 union cvmx_pci_bar1_indexx bar1_index; 673 674 bar1_index.u32 = 0; 675 /* Address bits[35:22] sent to L2C */ 676 bar1_index.s.addr_idx = 677 (octeon_bar1_pci_phys >> 22) + index; 678 /* Don't put PCI accesses in L2. */ 679 bar1_index.s.ca = 1; 680 /* Endian Swap Mode */ 681 bar1_index.s.end_swp = 1; 682 /* Set '1' when the selected address range is valid. */ 683 bar1_index.s.addr_v = 1; 684 octeon_npi_write32(CVMX_NPI_PCI_BAR1_INDEXX(index), 685 bar1_index.u32); 686 } 687 688 /* Devices go after BAR0 */ 689 octeon_pci_mem_resource.start = 690 OCTEON_PCI_MEMSPACE_OFFSET + (128ul << 20) + 691 (4ul << 10); 692 octeon_pci_mem_resource.end = 693 octeon_pci_mem_resource.start + (1ul << 30); 694 } 695 696 register_pci_controller(&octeon_pci_controller); 697 698 /* 699 * Clear any errors that might be pending from before the bus 700 * was setup properly. 701 */ 702 cvmx_write_csr(CVMX_NPI_PCI_INT_SUM2, -1); 703 704 if (IS_ERR(platform_device_register_simple("octeon_pci_edac", 705 -1, NULL, 0))) 706 pr_err("Registration of co_pci_edac failed!\n"); 707 708 octeon_pci_dma_init(); 709 710 return 0; 711 } 712 713 arch_initcall(octeon_pci_setup); 714