1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Ralink MT7620A SoC PCI support 4 * 5 * Copyright (C) 2007-2013 Bruce Chang (Mediatek) 6 * Copyright (C) 2013-2016 John Crispin <john@phrozen.org> 7 */ 8 9 #include <linux/types.h> 10 #include <linux/pci.h> 11 #include <linux/io.h> 12 #include <linux/init.h> 13 #include <linux/delay.h> 14 #include <linux/interrupt.h> 15 #include <linux/of.h> 16 #include <linux/of_irq.h> 17 #include <linux/of_pci.h> 18 #include <linux/reset.h> 19 #include <linux/platform_device.h> 20 21 #include <asm/mach-ralink/ralink_regs.h> 22 #include <asm/mach-ralink/mt7620.h> 23 24 #define RALINK_PCI_IO_MAP_BASE 0x10160000 25 #define RALINK_PCI_MEMORY_BASE 0x0 26 27 #define RALINK_INT_PCIE0 4 28 29 #define RALINK_SYSCFG0 0x10 30 #define RALINK_SYSCFG0_XTAL40 BIT(6) 31 #define RALINK_CLKCFG1 0x30 32 33 #define PPLL_CFG1 0x9c 34 #define PPLL_LD BIT(23) 35 36 #define PPLL_DRV 0xa0 37 #define PDRV_SW_SET BIT(31) 38 #define LC_CKDRVPD BIT(19) 39 #define LC_CKDRVOHZ BIT(18) 40 #define LC_CKDRVHZ BIT(17) 41 #define LC_CKTEST BIT(16) 42 43 /* PCI Bridge registers */ 44 #define RALINK_PCI_PCICFG_ADDR 0x00 45 #define PCIRST BIT(1) 46 47 #define RALINK_PCI_PCIENA 0x0C 48 #define PCIINT2 BIT(20) 49 50 #define RALINK_PCI_CONFIG_ADDR 0x20 51 #define RALINK_PCI_CONFIG_DATA_VIRT_REG 0x24 52 #define RALINK_PCI_MEMBASE 0x28 53 #define RALINK_PCI_IOBASE 0x2C 54 55 /* PCI RC registers */ 56 #define RALINK_PCI0_BAR0SETUP_ADDR 0x10 57 #define RALINK_PCI0_IMBASEBAR0_ADDR 0x18 58 #define RALINK_PCI0_ID 0x30 59 #define RALINK_PCI0_CLASS 0x34 60 #define RALINK_PCI0_SUBID 0x38 61 #define RALINK_PCI0_STATUS 0x50 62 #define PCIE_LINK_UP_ST BIT(0) 63 64 #define PCIEPHY0_CFG 0x90 65 66 #define RALINK_PCIEPHY_P0_CTL_OFFSET 0x7000 67 #define RALINK_PCIE0_CLK_EN BIT(26) 68 69 #define BUSY 0x80000000 70 #define WAITRETRY_MAX 10 71 #define WRITE_MODE (1UL << 23) 72 #define DATA_SHIFT 0 73 #define ADDR_SHIFT 8 74 75 76 static void __iomem *bridge_base; 77 static void __iomem *pcie_base; 78 79 static struct reset_control *rstpcie0; 80 81 static inline void bridge_w32(u32 val, unsigned reg) 82 { 83 iowrite32(val, bridge_base + reg); 84 } 85 86 static inline u32 bridge_r32(unsigned reg) 87 { 88 return ioread32(bridge_base + reg); 89 } 90 91 static inline void bridge_m32(u32 clr, u32 set, unsigned reg) 92 { 93 u32 val = bridge_r32(reg); 94 95 val &= ~clr; 96 val |= set; 97 bridge_w32(val, reg); 98 } 99 100 static inline void pcie_w32(u32 val, unsigned reg) 101 { 102 iowrite32(val, pcie_base + reg); 103 } 104 105 static inline u32 pcie_r32(unsigned reg) 106 { 107 return ioread32(pcie_base + reg); 108 } 109 110 static inline void pcie_m32(u32 clr, u32 set, unsigned reg) 111 { 112 u32 val = pcie_r32(reg); 113 114 val &= ~clr; 115 val |= set; 116 pcie_w32(val, reg); 117 } 118 119 static inline void 120 pcie_phyctrl_set(unsigned offset, u32 b_start, u32 bits, u32 val) 121 { 122 pcie_m32(GENMASK(b_start + bits - 1, b_start), 123 val << b_start, 124 RALINK_PCIEPHY_P0_CTL_OFFSET + offset); 125 } 126 127 static int wait_pciephy_busy(void) 128 { 129 unsigned long reg_value = 0x0, retry = 0; 130 131 while (1) { 132 reg_value = pcie_r32(PCIEPHY0_CFG); 133 134 if (reg_value & BUSY) 135 mdelay(100); 136 else 137 break; 138 if (retry++ > WAITRETRY_MAX) { 139 pr_warn("PCIE-PHY retry failed.\n"); 140 return -1; 141 } 142 } 143 return 0; 144 } 145 146 static void pcie_phy(unsigned long addr, unsigned long val) 147 { 148 wait_pciephy_busy(); 149 pcie_w32(WRITE_MODE | (val << DATA_SHIFT) | (addr << ADDR_SHIFT), 150 PCIEPHY0_CFG); 151 mdelay(1); 152 wait_pciephy_busy(); 153 } 154 155 static int pci_config_read(struct pci_bus *bus, unsigned int devfn, int where, 156 int size, u32 *val) 157 { 158 unsigned int slot = PCI_SLOT(devfn); 159 u8 func = PCI_FUNC(devfn); 160 u32 address; 161 u32 data; 162 u32 num = 0; 163 164 if (bus) 165 num = bus->number; 166 167 address = (((where & 0xF00) >> 8) << 24) | (num << 16) | (slot << 11) | 168 (func << 8) | (where & 0xfc) | 0x80000000; 169 bridge_w32(address, RALINK_PCI_CONFIG_ADDR); 170 data = bridge_r32(RALINK_PCI_CONFIG_DATA_VIRT_REG); 171 172 switch (size) { 173 case 1: 174 *val = (data >> ((where & 3) << 3)) & 0xff; 175 break; 176 case 2: 177 *val = (data >> ((where & 3) << 3)) & 0xffff; 178 break; 179 case 4: 180 *val = data; 181 break; 182 } 183 184 return PCIBIOS_SUCCESSFUL; 185 } 186 187 static int pci_config_write(struct pci_bus *bus, unsigned int devfn, int where, 188 int size, u32 val) 189 { 190 unsigned int slot = PCI_SLOT(devfn); 191 u8 func = PCI_FUNC(devfn); 192 u32 address; 193 u32 data; 194 u32 num = 0; 195 196 if (bus) 197 num = bus->number; 198 199 address = (((where & 0xF00) >> 8) << 24) | (num << 16) | (slot << 11) | 200 (func << 8) | (where & 0xfc) | 0x80000000; 201 bridge_w32(address, RALINK_PCI_CONFIG_ADDR); 202 data = bridge_r32(RALINK_PCI_CONFIG_DATA_VIRT_REG); 203 204 switch (size) { 205 case 1: 206 data = (data & ~(0xff << ((where & 3) << 3))) | 207 (val << ((where & 3) << 3)); 208 break; 209 case 2: 210 data = (data & ~(0xffff << ((where & 3) << 3))) | 211 (val << ((where & 3) << 3)); 212 break; 213 case 4: 214 data = val; 215 break; 216 } 217 218 bridge_w32(data, RALINK_PCI_CONFIG_DATA_VIRT_REG); 219 220 return PCIBIOS_SUCCESSFUL; 221 } 222 223 struct pci_ops mt7620_pci_ops = { 224 .read = pci_config_read, 225 .write = pci_config_write, 226 }; 227 228 static struct resource mt7620_res_pci_mem1; 229 static struct resource mt7620_res_pci_io1; 230 struct pci_controller mt7620_controller = { 231 .pci_ops = &mt7620_pci_ops, 232 .mem_resource = &mt7620_res_pci_mem1, 233 .mem_offset = 0x00000000UL, 234 .io_resource = &mt7620_res_pci_io1, 235 .io_offset = 0x00000000UL, 236 .io_map_base = 0xa0000000, 237 }; 238 239 static int mt7620_pci_hw_init(struct platform_device *pdev) 240 { 241 /* bypass PCIe DLL */ 242 pcie_phy(0x0, 0x80); 243 pcie_phy(0x1, 0x04); 244 245 /* Elastic buffer control */ 246 pcie_phy(0x68, 0xB4); 247 248 if (!(rt_sysc_r32(PPLL_CFG1) & PPLL_LD)) { 249 dev_err(&pdev->dev, "pcie PLL not locked, aborting init\n"); 250 reset_control_assert(rstpcie0); 251 rt_sysc_m32(RALINK_PCIE0_CLK_EN, 0, RALINK_CLKCFG1); 252 return -1; 253 } 254 255 /* power up the bus */ 256 rt_sysc_m32(LC_CKDRVHZ | LC_CKDRVOHZ, LC_CKDRVPD | PDRV_SW_SET, 257 PPLL_DRV); 258 259 return 0; 260 } 261 262 static void mt7628_pci_hw_init(struct platform_device *pdev) 263 { 264 /* voodoo from the SDK driver */ 265 pcie_phyctrl_set(0x400, 8, 1, 0x1); 266 pcie_phyctrl_set(0x400, 9, 2, 0x0); 267 pcie_phyctrl_set(0x000, 4, 1, 0x1); 268 pcie_phyctrl_set(0x000, 5, 1, 0x0); 269 pcie_phyctrl_set(0x4ac, 16, 3, 0x3); 270 271 if (rt_sysc_r32(RALINK_SYSCFG0) & RALINK_SYSCFG0_XTAL40) { 272 pcie_phyctrl_set(0x4bc, 24, 8, 0x7d); 273 pcie_phyctrl_set(0x490, 12, 4, 0x08); 274 pcie_phyctrl_set(0x490, 6, 2, 0x01); 275 pcie_phyctrl_set(0x4c0, 0, 32, 0x1f400000); 276 pcie_phyctrl_set(0x4a4, 0, 16, 0x013d); 277 pcie_phyctrl_set(0x4a8, 16, 16, 0x74); 278 pcie_phyctrl_set(0x4a8, 0, 16, 0x74); 279 } else { 280 pcie_phyctrl_set(0x4bc, 24, 8, 0x64); 281 pcie_phyctrl_set(0x490, 12, 4, 0x0a); 282 pcie_phyctrl_set(0x490, 6, 2, 0x00); 283 pcie_phyctrl_set(0x4c0, 0, 32, 0x19000000); 284 pcie_phyctrl_set(0x4a4, 0, 16, 0x018d); 285 pcie_phyctrl_set(0x4a8, 16, 16, 0x4a); 286 pcie_phyctrl_set(0x4a8, 0, 16, 0x4a); 287 } 288 289 pcie_phyctrl_set(0x498, 0, 8, 0x5); 290 pcie_phyctrl_set(0x000, 5, 1, 0x1); 291 pcie_phyctrl_set(0x000, 4, 1, 0x0); 292 } 293 294 static int mt7620_pci_probe(struct platform_device *pdev) 295 { 296 u32 val = 0; 297 298 rstpcie0 = devm_reset_control_get_exclusive(&pdev->dev, "pcie0"); 299 if (IS_ERR(rstpcie0)) 300 return PTR_ERR(rstpcie0); 301 302 bridge_base = devm_platform_get_and_ioremap_resource(pdev, 0, NULL); 303 if (IS_ERR(bridge_base)) 304 return PTR_ERR(bridge_base); 305 306 pcie_base = devm_platform_get_and_ioremap_resource(pdev, 1, NULL); 307 if (IS_ERR(pcie_base)) 308 return PTR_ERR(pcie_base); 309 310 iomem_resource.start = 0; 311 iomem_resource.end = ~0; 312 ioport_resource.start = 0; 313 ioport_resource.end = ~0; 314 315 /* reset PCIe controller */ 316 reset_control_assert(rstpcie0); 317 msleep(100); 318 reset_control_deassert(rstpcie0); 319 rt_sysc_m32(0, RALINK_PCIE0_CLK_EN, RALINK_CLKCFG1); 320 msleep(100); 321 322 /* assert PERST_N pin */ 323 bridge_m32(PCIRST, PCIRST, RALINK_PCI_PCICFG_ADDR); 324 325 /* bring up the pci core */ 326 switch (ralink_soc) { 327 case MT762X_SOC_MT7620A: 328 if (mt7620_pci_hw_init(pdev)) 329 return -1; 330 break; 331 332 case MT762X_SOC_MT7628AN: 333 case MT762X_SOC_MT7688: 334 mt7628_pci_hw_init(pdev); 335 break; 336 337 default: 338 dev_err(&pdev->dev, "pcie is not supported on this hardware\n"); 339 return -1; 340 } 341 msleep(500); 342 343 /* deassert PERST_N pin and wait PCIe peripheral init */ 344 bridge_m32(PCIRST, 0, RALINK_PCI_PCICFG_ADDR); 345 msleep(1000); 346 347 /* check if there is a card present */ 348 if ((pcie_r32(RALINK_PCI0_STATUS) & PCIE_LINK_UP_ST) == 0) { 349 reset_control_assert(rstpcie0); 350 rt_sysc_m32(RALINK_PCIE0_CLK_EN, 0, RALINK_CLKCFG1); 351 if (ralink_soc == MT762X_SOC_MT7620A) 352 rt_sysc_m32(LC_CKDRVPD, PDRV_SW_SET, PPLL_DRV); 353 else 354 pcie_phyctrl_set(0x000, 0, 32, 0x10); 355 dev_info(&pdev->dev, "PCIE0 no card, disable it(RST&CLK)\n"); 356 return -1; 357 } 358 359 /* setup ranges */ 360 bridge_w32(0xffffffff, RALINK_PCI_MEMBASE); 361 bridge_w32(RALINK_PCI_IO_MAP_BASE, RALINK_PCI_IOBASE); 362 363 pcie_w32(0x7FFF0001, RALINK_PCI0_BAR0SETUP_ADDR); 364 pcie_w32(RALINK_PCI_MEMORY_BASE, RALINK_PCI0_IMBASEBAR0_ADDR); 365 pcie_w32(0x06040001, RALINK_PCI0_CLASS); 366 367 /* enable interrupts */ 368 bridge_m32(PCIINT2, PCIINT2, RALINK_PCI_PCIENA); 369 370 /* voodoo from the SDK driver */ 371 pci_config_read(NULL, 0, 4, 4, &val); 372 pci_config_write(NULL, 0, 4, 4, val | 0x7); 373 374 pci_config_read(NULL, 0, 0x70c, 4, &val); 375 val &= ~(0xff) << 8; 376 val |= 0x50 << 8; 377 pci_config_write(NULL, 0, 0x70c, 4, val); 378 379 pci_load_of_ranges(&mt7620_controller, pdev->dev.of_node); 380 register_pci_controller(&mt7620_controller); 381 382 return 0; 383 } 384 385 int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) 386 { 387 u16 cmd; 388 u32 val; 389 int irq = 0; 390 391 if ((dev->bus->number == 0) && (slot == 0)) { 392 pcie_w32(0x7FFF0001, RALINK_PCI0_BAR0SETUP_ADDR); 393 pci_config_write(dev->bus, 0, PCI_BASE_ADDRESS_0, 4, 394 RALINK_PCI_MEMORY_BASE); 395 pci_config_read(dev->bus, 0, PCI_BASE_ADDRESS_0, 4, &val); 396 } else if ((dev->bus->number == 1) && (slot == 0x0)) { 397 irq = RALINK_INT_PCIE0; 398 } else { 399 dev_err(&dev->dev, "no irq found - bus=0x%x, slot = 0x%x\n", 400 dev->bus->number, slot); 401 return 0; 402 } 403 dev_info(&dev->dev, "card - bus=0x%x, slot = 0x%x irq=%d\n", 404 dev->bus->number, slot, irq); 405 406 /* configure the cache line size to 0x14 */ 407 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 0x14); 408 409 /* configure latency timer to 0xff */ 410 pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0xff); 411 pci_read_config_word(dev, PCI_COMMAND, &cmd); 412 413 /* setup the slot */ 414 cmd = cmd | PCI_COMMAND_MASTER | PCI_COMMAND_IO | PCI_COMMAND_MEMORY; 415 pci_write_config_word(dev, PCI_COMMAND, cmd); 416 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq); 417 418 return irq; 419 } 420 421 int pcibios_plat_dev_init(struct pci_dev *dev) 422 { 423 return 0; 424 } 425 426 static const struct of_device_id mt7620_pci_ids[] = { 427 { .compatible = "mediatek,mt7620-pci" }, 428 {}, 429 }; 430 431 static struct platform_driver mt7620_pci_driver = { 432 .probe = mt7620_pci_probe, 433 .driver = { 434 .name = "mt7620-pci", 435 .of_match_table = of_match_ptr(mt7620_pci_ids), 436 }, 437 }; 438 439 static int __init mt7620_pci_init(void) 440 { 441 return platform_driver_register(&mt7620_pci_driver); 442 } 443 444 arch_initcall(mt7620_pci_init); 445