1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * 4 * Copyright (C) 2003, 04, 11 Ralf Baechle (ralf@linux-mips.org) 5 * Copyright (C) 2011 Wind River Systems, 6 * written by Ralf Baechle (ralf@linux-mips.org) 7 */ 8 #include <linux/bug.h> 9 #include <linux/kernel.h> 10 #include <linux/mm.h> 11 #include <linux/memblock.h> 12 #include <linux/export.h> 13 #include <linux/init.h> 14 #include <linux/types.h> 15 #include <linux/pci.h> 16 #include <linux/of_address.h> 17 18 #include <asm/cpu-info.h> 19 20 /* 21 * If PCI_PROBE_ONLY in pci_flags is set, we don't change any PCI resource 22 * assignments. 23 */ 24 25 /* 26 * The PCI controller list. 27 */ 28 static LIST_HEAD(controllers); 29 30 static int pci_initialized; 31 32 unsigned long pci_address_to_pio(phys_addr_t address) 33 { 34 if (address > IO_SPACE_LIMIT) 35 return (unsigned long)-1; 36 37 return (unsigned long) address; 38 } 39 40 /* 41 * We need to avoid collisions with `mirrored' VGA ports 42 * and other strange ISA hardware, so we always want the 43 * addresses to be allocated in the 0x000-0x0ff region 44 * modulo 0x400. 45 * 46 * Why? Because some silly external IO cards only decode 47 * the low 10 bits of the IO address. The 0x00-0xff region 48 * is reserved for motherboard devices that decode all 16 49 * bits, so it's ok to allocate at, say, 0x2800-0x28ff, 50 * but we want to try to avoid allocating at 0x2900-0x2bff 51 * which might have be mirrored at 0x0100-0x03ff.. 52 */ 53 resource_size_t 54 pcibios_align_resource(void *data, const struct resource *res, 55 const struct resource *empty_res, 56 resource_size_t size, resource_size_t align) 57 { 58 struct pci_dev *dev = data; 59 struct pci_controller *hose = dev->sysdata; 60 resource_size_t start = res->start; 61 62 if (res->flags & IORESOURCE_IO) { 63 /* Make sure we start at our min on all hoses */ 64 if (start < PCIBIOS_MIN_IO + hose->io_resource->start) 65 start = PCIBIOS_MIN_IO + hose->io_resource->start; 66 67 /* 68 * Put everything into 0x00-0xff region modulo 0x400 69 */ 70 if (start & 0x300) 71 start = (start + 0x3ff) & ~0x3ff; 72 } else if (res->flags & IORESOURCE_MEM) { 73 start = pci_align_resource(dev, res, empty_res, size, align); 74 75 /* Make sure we start at our min on all hoses */ 76 if (start < PCIBIOS_MIN_MEM + hose->mem_resource->start) 77 start = PCIBIOS_MIN_MEM + hose->mem_resource->start; 78 } 79 80 return start; 81 } 82 83 static void pcibios_scanbus(struct pci_controller *hose) 84 { 85 static int next_busno; 86 static int need_domain_info; 87 LIST_HEAD(resources); 88 struct pci_bus *bus; 89 struct pci_host_bridge *bridge; 90 int ret; 91 92 bridge = pci_alloc_host_bridge(0); 93 if (!bridge) 94 return; 95 96 if (hose->get_busno && pci_has_flag(PCI_PROBE_ONLY)) 97 next_busno = (*hose->get_busno)(); 98 99 pci_add_resource_offset(&resources, 100 hose->mem_resource, hose->mem_offset); 101 pci_add_resource_offset(&resources, 102 hose->io_resource, hose->io_offset); 103 list_splice_init(&resources, &bridge->windows); 104 bridge->dev.parent = NULL; 105 bridge->sysdata = hose; 106 bridge->busnr = next_busno; 107 bridge->ops = hose->pci_ops; 108 bridge->swizzle_irq = pci_common_swizzle; 109 bridge->map_irq = pcibios_map_irq; 110 ret = pci_scan_root_bus_bridge(bridge); 111 if (ret) { 112 pci_free_host_bridge(bridge); 113 return; 114 } 115 116 hose->bus = bus = bridge->bus; 117 118 need_domain_info = need_domain_info || pci_domain_nr(bus); 119 set_pci_need_domain_info(hose, need_domain_info); 120 121 next_busno = bus->busn_res.end + 1; 122 /* Don't allow 8-bit bus number overflow inside the hose - 123 reserve some space for bridges. */ 124 if (next_busno > 224) { 125 next_busno = 0; 126 need_domain_info = 1; 127 } 128 129 /* 130 * We insert PCI resources into the iomem_resource and 131 * ioport_resource trees in either pci_bus_claim_resources() 132 * or pci_bus_assign_resources(). 133 */ 134 if (pci_has_flag(PCI_PROBE_ONLY)) { 135 pci_bus_claim_resources(bus); 136 } else { 137 struct pci_bus *child; 138 139 pci_bus_size_bridges(bus); 140 pci_bus_assign_resources(bus); 141 list_for_each_entry(child, &bus->children, node) 142 pcie_bus_configure_settings(child); 143 } 144 pci_bus_add_devices(bus); 145 } 146 147 #ifdef CONFIG_OF 148 void pci_load_of_ranges(struct pci_controller *hose, struct device_node *node) 149 { 150 struct of_pci_range range; 151 struct of_pci_range_parser parser; 152 153 hose->of_node = node; 154 155 if (of_pci_range_parser_init(&parser, node)) 156 return; 157 158 for_each_of_pci_range(&parser, &range) { 159 struct resource *res = NULL; 160 161 switch (range.flags & IORESOURCE_TYPE_BITS) { 162 case IORESOURCE_IO: 163 hose->io_map_base = 164 (unsigned long)ioremap(range.cpu_addr, 165 range.size); 166 res = hose->io_resource; 167 break; 168 case IORESOURCE_MEM: 169 res = hose->mem_resource; 170 break; 171 } 172 if (res != NULL) { 173 res->name = node->full_name; 174 res->flags = range.flags; 175 res->start = range.cpu_addr; 176 res->end = range.cpu_addr + range.size - 1; 177 res->parent = res->child = res->sibling = NULL; 178 } 179 } 180 } 181 182 struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus) 183 { 184 struct pci_controller *hose = bus->sysdata; 185 186 return of_node_get(hose->of_node); 187 } 188 #endif 189 190 static DEFINE_MUTEX(pci_scan_mutex); 191 192 void register_pci_controller(struct pci_controller *hose) 193 { 194 struct resource *parent; 195 196 parent = hose->mem_resource->parent; 197 if (!parent) 198 parent = &iomem_resource; 199 200 if (request_resource(parent, hose->mem_resource) < 0) 201 goto out; 202 203 parent = hose->io_resource->parent; 204 if (!parent) 205 parent = &ioport_resource; 206 207 if (request_resource(parent, hose->io_resource) < 0) { 208 release_resource(hose->mem_resource); 209 goto out; 210 } 211 212 INIT_LIST_HEAD(&hose->list); 213 list_add_tail(&hose->list, &controllers); 214 215 /* 216 * Do not panic here but later - this might happen before console init. 217 */ 218 if (!hose->io_map_base) { 219 printk(KERN_WARNING 220 "registering PCI controller with io_map_base unset\n"); 221 } 222 223 /* 224 * Scan the bus if it is register after the PCI subsystem 225 * initialization. 226 */ 227 if (pci_initialized) { 228 mutex_lock(&pci_scan_mutex); 229 pcibios_scanbus(hose); 230 mutex_unlock(&pci_scan_mutex); 231 } 232 233 return; 234 235 out: 236 printk(KERN_WARNING 237 "Skipping PCI bus scan due to resource conflict\n"); 238 } 239 240 static int __init pcibios_init(void) 241 { 242 struct pci_controller *hose; 243 244 /* Scan all of the recorded PCI controllers. */ 245 list_for_each_entry(hose, &controllers, list) 246 pcibios_scanbus(hose); 247 248 pci_initialized = 1; 249 250 return 0; 251 } 252 253 subsys_initcall(pcibios_init); 254 255 int pcibios_enable_device(struct pci_dev *dev, int mask) 256 { 257 int err; 258 259 err = pci_enable_resources(dev, mask); 260 if (err < 0) 261 return err; 262 263 return pcibios_plat_dev_init(dev); 264 } 265 266 void pcibios_fixup_bus(struct pci_bus *bus) 267 { 268 struct pci_dev *dev = bus->self; 269 270 if (pci_has_flag(PCI_PROBE_ONLY) && dev && 271 (dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) { 272 pci_read_bridge_bases(bus); 273 } 274 } 275 276 char * (*pcibios_plat_setup)(char *str) __initdata; 277 278 char *__init pcibios_setup(char *str) 279 { 280 if (pcibios_plat_setup) 281 return pcibios_plat_setup(str); 282 return str; 283 } 284