1 /* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * Copyright (C) 2003 Christoph Hellwig (hch@lst.de) 7 * Copyright (C) 1999, 2000, 04 Ralf Baechle (ralf@linux-mips.org) 8 * Copyright (C) 1999, 2000 Silicon Graphics, Inc. 9 */ 10 #include <linux/init.h> 11 #include <linux/kernel.h> 12 #include <linux/pci.h> 13 #include <asm/sn/arch.h> 14 #include <asm/pci/bridge.h> 15 #include <asm/paccess.h> 16 #include <asm/sn/intr.h> 17 #include <asm/sn/sn0/hub.h> 18 19 extern unsigned int allocate_irqno(void); 20 21 /* 22 * Max #PCI busses we can handle; ie, max #PCI bridges. 23 */ 24 #define MAX_PCI_BUSSES 40 25 26 /* 27 * Max #PCI devices (like scsi controllers) we handle on a bus. 28 */ 29 #define MAX_DEVICES_PER_PCIBUS 8 30 31 /* 32 * XXX: No kmalloc available when we do our crosstalk scan, 33 * we should try to move it later in the boot process. 34 */ 35 static struct bridge_controller bridges[MAX_PCI_BUSSES]; 36 37 /* 38 * Translate from irq to software PCI bus number and PCI slot. 39 */ 40 struct bridge_controller *irq_to_bridge[MAX_PCI_BUSSES * MAX_DEVICES_PER_PCIBUS]; 41 int irq_to_slot[MAX_PCI_BUSSES * MAX_DEVICES_PER_PCIBUS]; 42 43 extern struct pci_ops bridge_pci_ops; 44 45 int __init bridge_probe(nasid_t nasid, int widget_id, int masterwid) 46 { 47 unsigned long offset = NODE_OFFSET(nasid); 48 struct bridge_controller *bc; 49 static int num_bridges = 0; 50 bridge_t *bridge; 51 int slot; 52 53 printk("a bridge\n"); 54 55 /* XXX: kludge alert.. */ 56 if (!num_bridges) 57 ioport_resource.end = ~0UL; 58 59 bc = &bridges[num_bridges]; 60 61 bc->pc.pci_ops = &bridge_pci_ops; 62 bc->pc.mem_resource = &bc->mem; 63 bc->pc.io_resource = &bc->io; 64 65 bc->pc.index = num_bridges; 66 67 bc->mem.name = "Bridge PCI MEM"; 68 bc->pc.mem_offset = offset; 69 bc->mem.start = 0; 70 bc->mem.end = ~0UL; 71 bc->mem.flags = IORESOURCE_MEM; 72 73 bc->io.name = "Bridge IO MEM"; 74 bc->pc.io_offset = offset; 75 bc->io.start = 0UL; 76 bc->io.end = ~0UL; 77 bc->io.flags = IORESOURCE_IO; 78 79 bc->irq_cpu = smp_processor_id(); 80 bc->widget_id = widget_id; 81 bc->nasid = nasid; 82 83 bc->baddr = (u64)masterwid << 60 | PCI64_ATTR_BAR; 84 85 /* 86 * point to this bridge 87 */ 88 bridge = (bridge_t *) RAW_NODE_SWIN_BASE(nasid, widget_id); 89 90 /* 91 * Clear all pending interrupts. 92 */ 93 bridge->b_int_rst_stat = BRIDGE_IRR_ALL_CLR; 94 95 /* 96 * Until otherwise set up, assume all interrupts are from slot 0 97 */ 98 bridge->b_int_device = 0x0; 99 100 /* 101 * swap pio's to pci mem and io space (big windows) 102 */ 103 bridge->b_wid_control |= BRIDGE_CTRL_IO_SWAP | 104 BRIDGE_CTRL_MEM_SWAP; 105 106 /* 107 * Hmm... IRIX sets additional bits in the address which 108 * are documented as reserved in the bridge docs. 109 */ 110 bridge->b_wid_int_upper = 0x8000 | (masterwid << 16); 111 bridge->b_wid_int_lower = 0x01800090; /* PI_INT_PEND_MOD off*/ 112 bridge->b_dir_map = (masterwid << 20); /* DMA */ 113 bridge->b_int_enable = 0; 114 115 for (slot = 0; slot < 8; slot ++) { 116 bridge->b_device[slot].reg |= BRIDGE_DEV_SWAP_DIR; 117 bc->pci_int[slot] = -1; 118 } 119 bridge->b_wid_tflush; /* wait until Bridge PIO complete */ 120 121 bc->base = bridge; 122 123 register_pci_controller(&bc->pc); 124 125 num_bridges++; 126 127 return 0; 128 } 129 130 /* 131 * All observed requests have pin == 1. We could have a global here, that 132 * gets incremented and returned every time - unfortunately, pci_map_irq 133 * may be called on the same device over and over, and need to return the 134 * same value. On O2000, pin can be 0 or 1, and PCI slots can be [0..7]. 135 * 136 * A given PCI device, in general, should be able to intr any of the cpus 137 * on any one of the hubs connected to its xbow. 138 */ 139 int __devinit pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin) 140 { 141 struct bridge_controller *bc = BRIDGE_CONTROLLER(dev->bus); 142 int irq = bc->pci_int[slot]; 143 144 if (irq == -1) { 145 irq = bc->pci_int[slot] = request_bridge_irq(bc); 146 if (irq < 0) 147 panic("Can't allocate interrupt for PCI device %s\n", 148 pci_name(dev)); 149 } 150 151 irq_to_bridge[irq] = bc; 152 irq_to_slot[irq] = slot; 153 154 return irq; 155 } 156 157 /* Do platform specific device initialization at pci_enable_device() time */ 158 int pcibios_plat_dev_init(struct pci_dev *dev) 159 { 160 return 0; 161 } 162 163 /* 164 * Device might live on a subordinate PCI bus. XXX Walk up the chain of buses 165 * to find the slot number in sense of the bridge device register. 166 * XXX This also means multiple devices might rely on conflicting bridge 167 * settings. 168 */ 169 170 static inline void pci_disable_swapping(struct pci_dev *dev) 171 { 172 struct bridge_controller *bc = BRIDGE_CONTROLLER(dev->bus); 173 bridge_t *bridge = bc->base; 174 int slot = PCI_SLOT(dev->devfn); 175 176 /* Turn off byte swapping */ 177 bridge->b_device[slot].reg &= ~BRIDGE_DEV_SWAP_DIR; 178 bridge->b_widget.w_tflush; /* Flush */ 179 } 180 181 static inline void pci_enable_swapping(struct pci_dev *dev) 182 { 183 struct bridge_controller *bc = BRIDGE_CONTROLLER(dev->bus); 184 bridge_t *bridge = bc->base; 185 int slot = PCI_SLOT(dev->devfn); 186 187 /* Turn on byte swapping */ 188 bridge->b_device[slot].reg |= BRIDGE_DEV_SWAP_DIR; 189 bridge->b_widget.w_tflush; /* Flush */ 190 } 191 192 static void __init pci_fixup_ioc3(struct pci_dev *d) 193 { 194 pci_disable_swapping(d); 195 } 196 197 int pcibus_to_node(struct pci_bus *bus) 198 { 199 struct bridge_controller *bc = BRIDGE_CONTROLLER(bus); 200 201 return bc->nasid; 202 } 203 204 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_IOC3, 205 pci_fixup_ioc3); 206