1 /* 2 * Atheros AR724X PCI host controller driver 3 * 4 * Copyright (C) 2011 René Bolldorf <xsecute@googlemail.com> 5 * Copyright (C) 2009-2011 Gabor Juhos <juhosg@openwrt.org> 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms of the GNU General Public License version 2 as published 9 * by the Free Software Foundation. 10 */ 11 12 #include <linux/irq.h> 13 #include <linux/pci.h> 14 #include <asm/mach-ath79/ath79.h> 15 #include <asm/mach-ath79/ar71xx_regs.h> 16 #include <asm/mach-ath79/pci.h> 17 18 #define AR724X_PCI_CFG_BASE 0x14000000 19 #define AR724X_PCI_CFG_SIZE 0x1000 20 #define AR724X_PCI_CTRL_BASE (AR71XX_APB_BASE + 0x000f0000) 21 #define AR724X_PCI_CTRL_SIZE 0x100 22 23 #define AR724X_PCI_MEM_BASE 0x10000000 24 #define AR724X_PCI_MEM_SIZE 0x08000000 25 26 #define AR724X_PCI_REG_INT_STATUS 0x4c 27 #define AR724X_PCI_REG_INT_MASK 0x50 28 29 #define AR724X_PCI_INT_DEV0 BIT(14) 30 31 #define AR724X_PCI_IRQ_COUNT 1 32 33 #define AR7240_BAR0_WAR_VALUE 0xffff 34 35 static DEFINE_SPINLOCK(ar724x_pci_lock); 36 static void __iomem *ar724x_pci_devcfg_base; 37 static void __iomem *ar724x_pci_ctrl_base; 38 39 static u32 ar724x_pci_bar0_value; 40 static bool ar724x_pci_bar0_is_cached; 41 42 static int ar724x_pci_read(struct pci_bus *bus, unsigned int devfn, int where, 43 int size, uint32_t *value) 44 { 45 unsigned long flags; 46 void __iomem *base; 47 u32 data; 48 49 if (devfn) 50 return PCIBIOS_DEVICE_NOT_FOUND; 51 52 base = ar724x_pci_devcfg_base; 53 54 spin_lock_irqsave(&ar724x_pci_lock, flags); 55 data = __raw_readl(base + (where & ~3)); 56 57 switch (size) { 58 case 1: 59 if (where & 1) 60 data >>= 8; 61 if (where & 2) 62 data >>= 16; 63 data &= 0xff; 64 break; 65 case 2: 66 if (where & 2) 67 data >>= 16; 68 data &= 0xffff; 69 break; 70 case 4: 71 break; 72 default: 73 spin_unlock_irqrestore(&ar724x_pci_lock, flags); 74 75 return PCIBIOS_BAD_REGISTER_NUMBER; 76 } 77 78 spin_unlock_irqrestore(&ar724x_pci_lock, flags); 79 80 if (where == PCI_BASE_ADDRESS_0 && size == 4 && 81 ar724x_pci_bar0_is_cached) { 82 /* use the cached value */ 83 *value = ar724x_pci_bar0_value; 84 } else { 85 *value = data; 86 } 87 88 return PCIBIOS_SUCCESSFUL; 89 } 90 91 static int ar724x_pci_write(struct pci_bus *bus, unsigned int devfn, int where, 92 int size, uint32_t value) 93 { 94 unsigned long flags; 95 void __iomem *base; 96 u32 data; 97 int s; 98 99 if (devfn) 100 return PCIBIOS_DEVICE_NOT_FOUND; 101 102 if (soc_is_ar7240() && where == PCI_BASE_ADDRESS_0 && size == 4) { 103 if (value != 0xffffffff) { 104 /* 105 * WAR for a hw issue. If the BAR0 register of the 106 * device is set to the proper base address, the 107 * memory space of the device is not accessible. 108 * 109 * Cache the intended value so it can be read back, 110 * and write a SoC specific constant value to the 111 * BAR0 register in order to make the device memory 112 * accessible. 113 */ 114 ar724x_pci_bar0_is_cached = true; 115 ar724x_pci_bar0_value = value; 116 117 value = AR7240_BAR0_WAR_VALUE; 118 } else { 119 ar724x_pci_bar0_is_cached = false; 120 } 121 } 122 123 base = ar724x_pci_devcfg_base; 124 125 spin_lock_irqsave(&ar724x_pci_lock, flags); 126 data = __raw_readl(base + (where & ~3)); 127 128 switch (size) { 129 case 1: 130 s = ((where & 3) * 8); 131 data &= ~(0xff << s); 132 data |= ((value & 0xff) << s); 133 break; 134 case 2: 135 s = ((where & 2) * 8); 136 data &= ~(0xffff << s); 137 data |= ((value & 0xffff) << s); 138 break; 139 case 4: 140 data = value; 141 break; 142 default: 143 spin_unlock_irqrestore(&ar724x_pci_lock, flags); 144 145 return PCIBIOS_BAD_REGISTER_NUMBER; 146 } 147 148 __raw_writel(data, base + (where & ~3)); 149 /* flush write */ 150 __raw_readl(base + (where & ~3)); 151 spin_unlock_irqrestore(&ar724x_pci_lock, flags); 152 153 return PCIBIOS_SUCCESSFUL; 154 } 155 156 static struct pci_ops ar724x_pci_ops = { 157 .read = ar724x_pci_read, 158 .write = ar724x_pci_write, 159 }; 160 161 static struct resource ar724x_io_resource = { 162 .name = "PCI IO space", 163 .start = 0, 164 .end = 0, 165 .flags = IORESOURCE_IO, 166 }; 167 168 static struct resource ar724x_mem_resource = { 169 .name = "PCI memory space", 170 .start = AR724X_PCI_MEM_BASE, 171 .end = AR724X_PCI_MEM_BASE + AR724X_PCI_MEM_SIZE - 1, 172 .flags = IORESOURCE_MEM, 173 }; 174 175 static struct pci_controller ar724x_pci_controller = { 176 .pci_ops = &ar724x_pci_ops, 177 .io_resource = &ar724x_io_resource, 178 .mem_resource = &ar724x_mem_resource, 179 }; 180 181 static void ar724x_pci_irq_handler(unsigned int irq, struct irq_desc *desc) 182 { 183 void __iomem *base; 184 u32 pending; 185 186 base = ar724x_pci_ctrl_base; 187 188 pending = __raw_readl(base + AR724X_PCI_REG_INT_STATUS) & 189 __raw_readl(base + AR724X_PCI_REG_INT_MASK); 190 191 if (pending & AR724X_PCI_INT_DEV0) 192 generic_handle_irq(ATH79_PCI_IRQ(0)); 193 194 else 195 spurious_interrupt(); 196 } 197 198 static void ar724x_pci_irq_unmask(struct irq_data *d) 199 { 200 void __iomem *base; 201 u32 t; 202 203 base = ar724x_pci_ctrl_base; 204 205 switch (d->irq) { 206 case ATH79_PCI_IRQ(0): 207 t = __raw_readl(base + AR724X_PCI_REG_INT_MASK); 208 __raw_writel(t | AR724X_PCI_INT_DEV0, 209 base + AR724X_PCI_REG_INT_MASK); 210 /* flush write */ 211 __raw_readl(base + AR724X_PCI_REG_INT_MASK); 212 } 213 } 214 215 static void ar724x_pci_irq_mask(struct irq_data *d) 216 { 217 void __iomem *base; 218 u32 t; 219 220 base = ar724x_pci_ctrl_base; 221 222 switch (d->irq) { 223 case ATH79_PCI_IRQ(0): 224 t = __raw_readl(base + AR724X_PCI_REG_INT_MASK); 225 __raw_writel(t & ~AR724X_PCI_INT_DEV0, 226 base + AR724X_PCI_REG_INT_MASK); 227 228 /* flush write */ 229 __raw_readl(base + AR724X_PCI_REG_INT_MASK); 230 231 t = __raw_readl(base + AR724X_PCI_REG_INT_STATUS); 232 __raw_writel(t | AR724X_PCI_INT_DEV0, 233 base + AR724X_PCI_REG_INT_STATUS); 234 235 /* flush write */ 236 __raw_readl(base + AR724X_PCI_REG_INT_STATUS); 237 } 238 } 239 240 static struct irq_chip ar724x_pci_irq_chip = { 241 .name = "AR724X PCI ", 242 .irq_mask = ar724x_pci_irq_mask, 243 .irq_unmask = ar724x_pci_irq_unmask, 244 .irq_mask_ack = ar724x_pci_irq_mask, 245 }; 246 247 static void __init ar724x_pci_irq_init(int irq) 248 { 249 void __iomem *base; 250 int i; 251 252 base = ar724x_pci_ctrl_base; 253 254 __raw_writel(0, base + AR724X_PCI_REG_INT_MASK); 255 __raw_writel(0, base + AR724X_PCI_REG_INT_STATUS); 256 257 BUILD_BUG_ON(ATH79_PCI_IRQ_COUNT < AR724X_PCI_IRQ_COUNT); 258 259 for (i = ATH79_PCI_IRQ_BASE; 260 i < ATH79_PCI_IRQ_BASE + AR724X_PCI_IRQ_COUNT; i++) 261 irq_set_chip_and_handler(i, &ar724x_pci_irq_chip, 262 handle_level_irq); 263 264 irq_set_chained_handler(irq, ar724x_pci_irq_handler); 265 } 266 267 int __init ar724x_pcibios_init(int irq) 268 { 269 int ret; 270 271 ret = -ENOMEM; 272 273 ar724x_pci_devcfg_base = ioremap(AR724X_PCI_CFG_BASE, 274 AR724X_PCI_CFG_SIZE); 275 if (ar724x_pci_devcfg_base == NULL) 276 goto err; 277 278 ar724x_pci_ctrl_base = ioremap(AR724X_PCI_CTRL_BASE, 279 AR724X_PCI_CTRL_SIZE); 280 if (ar724x_pci_ctrl_base == NULL) 281 goto err_unmap_devcfg; 282 283 ar724x_pci_irq_init(irq); 284 register_pci_controller(&ar724x_pci_controller); 285 286 return PCIBIOS_SUCCESSFUL; 287 288 err_unmap_devcfg: 289 iounmap(ar724x_pci_devcfg_base); 290 err: 291 return ret; 292 } 293