11da177e4SLinus Torvalds /* 289d63fe1SAtsushi Nemoto * Define the pci_ops for the PCIC on Toshiba TX4927, TX4938, etc. 31da177e4SLinus Torvalds * 489d63fe1SAtsushi Nemoto * Based on linux/arch/mips/pci/ops-tx4938.c, 589d63fe1SAtsushi Nemoto * linux/arch/mips/pci/fixup-rbtx4938.c, 689d63fe1SAtsushi Nemoto * linux/arch/mips/txx9/rbtx4938/setup.c, 789d63fe1SAtsushi Nemoto * and RBTX49xx patch from CELF patch archive. 889d63fe1SAtsushi Nemoto * 989d63fe1SAtsushi Nemoto * 2003-2005 (c) MontaVista Software, Inc. 101da177e4SLinus Torvalds * Copyright (C) 2004 by Ralf Baechle (ralf@linux-mips.org) 1189d63fe1SAtsushi Nemoto * (C) Copyright TOSHIBA CORPORATION 2000-2001, 2004-2007 121da177e4SLinus Torvalds * 131da177e4SLinus Torvalds * This program is free software; you can redistribute it and/or modify it 141da177e4SLinus Torvalds * under the terms of the GNU General Public License as published by the 151da177e4SLinus Torvalds * Free Software Foundation; either version 2 of the License, or (at your 161da177e4SLinus Torvalds * option) any later version. 171da177e4SLinus Torvalds */ 181da177e4SLinus Torvalds #include <linux/kernel.h> 1989d63fe1SAtsushi Nemoto #include <asm/txx9/tx4927pcic.h> 201da177e4SLinus Torvalds 2189d63fe1SAtsushi Nemoto static struct { 2289d63fe1SAtsushi Nemoto struct pci_controller *channel; 2389d63fe1SAtsushi Nemoto struct tx4927_pcic_reg __iomem *pcicptr; 2489d63fe1SAtsushi Nemoto } pcicptrs[2]; /* TX4938 has 2 pcic */ 251da177e4SLinus Torvalds 2689d63fe1SAtsushi Nemoto static void __init set_tx4927_pcicptr(struct pci_controller *channel, 2789d63fe1SAtsushi Nemoto struct tx4927_pcic_reg __iomem *pcicptr) 281da177e4SLinus Torvalds { 2989d63fe1SAtsushi Nemoto int i; 301da177e4SLinus Torvalds 3189d63fe1SAtsushi Nemoto for (i = 0; i < ARRAY_SIZE(pcicptrs); i++) { 3289d63fe1SAtsushi Nemoto if (pcicptrs[i].channel == channel) { 3389d63fe1SAtsushi Nemoto pcicptrs[i].pcicptr = pcicptr; 3489d63fe1SAtsushi Nemoto return; 351da177e4SLinus Torvalds } 3689d63fe1SAtsushi Nemoto } 3789d63fe1SAtsushi Nemoto for (i = 0; i < ARRAY_SIZE(pcicptrs); i++) { 3889d63fe1SAtsushi Nemoto if (!pcicptrs[i].channel) { 3989d63fe1SAtsushi Nemoto pcicptrs[i].channel = channel; 4089d63fe1SAtsushi Nemoto pcicptrs[i].pcicptr = pcicptr; 4189d63fe1SAtsushi Nemoto return; 4289d63fe1SAtsushi Nemoto } 4389d63fe1SAtsushi Nemoto } 4489d63fe1SAtsushi Nemoto BUG(); 4589d63fe1SAtsushi Nemoto } 4689d63fe1SAtsushi Nemoto 4789d63fe1SAtsushi Nemoto struct tx4927_pcic_reg __iomem *get_tx4927_pcicptr( 4889d63fe1SAtsushi Nemoto struct pci_controller *channel) 4989d63fe1SAtsushi Nemoto { 5089d63fe1SAtsushi Nemoto int i; 5189d63fe1SAtsushi Nemoto 5289d63fe1SAtsushi Nemoto for (i = 0; i < ARRAY_SIZE(pcicptrs); i++) { 5389d63fe1SAtsushi Nemoto if (pcicptrs[i].channel == channel) 5489d63fe1SAtsushi Nemoto return pcicptrs[i].pcicptr; 5589d63fe1SAtsushi Nemoto } 5689d63fe1SAtsushi Nemoto return NULL; 5789d63fe1SAtsushi Nemoto } 5889d63fe1SAtsushi Nemoto 5989d63fe1SAtsushi Nemoto static int mkaddr(struct pci_bus *bus, unsigned int devfn, int where, 6089d63fe1SAtsushi Nemoto struct tx4927_pcic_reg __iomem *pcicptr) 6189d63fe1SAtsushi Nemoto { 6289d63fe1SAtsushi Nemoto if (bus->parent == NULL && 6389d63fe1SAtsushi Nemoto devfn >= PCI_DEVFN(TX4927_PCIC_MAX_DEVNU, 0)) 6489d63fe1SAtsushi Nemoto return -1; 6589d63fe1SAtsushi Nemoto __raw_writel(((bus->number & 0xff) << 0x10) 6689d63fe1SAtsushi Nemoto | ((devfn & 0xff) << 0x08) | (where & 0xfc) 6789d63fe1SAtsushi Nemoto | (bus->parent ? 1 : 0), 6889d63fe1SAtsushi Nemoto &pcicptr->g2pcfgadrs); 691da177e4SLinus Torvalds /* clear M_ABORT and Disable M_ABORT Int. */ 7089d63fe1SAtsushi Nemoto __raw_writel((__raw_readl(&pcicptr->pcistatus) & 0x0000ffff) 7189d63fe1SAtsushi Nemoto | (PCI_STATUS_REC_MASTER_ABORT << 16), 7289d63fe1SAtsushi Nemoto &pcicptr->pcistatus); 731da177e4SLinus Torvalds return 0; 741da177e4SLinus Torvalds } 751da177e4SLinus Torvalds 7689d63fe1SAtsushi Nemoto static int check_abort(struct tx4927_pcic_reg __iomem *pcicptr) 771da177e4SLinus Torvalds { 781da177e4SLinus Torvalds int code = PCIBIOS_SUCCESSFUL; 7989d63fe1SAtsushi Nemoto 8089d63fe1SAtsushi Nemoto /* wait write cycle completion before checking error status */ 8189d63fe1SAtsushi Nemoto while (__raw_readl(&pcicptr->pcicstatus) & TX4927_PCIC_PCICSTATUS_IWB) 8289d63fe1SAtsushi Nemoto ; 8389d63fe1SAtsushi Nemoto if (__raw_readl(&pcicptr->pcistatus) 8489d63fe1SAtsushi Nemoto & (PCI_STATUS_REC_MASTER_ABORT << 16)) { 8589d63fe1SAtsushi Nemoto __raw_writel((__raw_readl(&pcicptr->pcistatus) & 0x0000ffff) 8689d63fe1SAtsushi Nemoto | (PCI_STATUS_REC_MASTER_ABORT << 16), 8789d63fe1SAtsushi Nemoto &pcicptr->pcistatus); 88*32d00d0fSAtsushi Nemoto /* flush write buffer */ 89*32d00d0fSAtsushi Nemoto iob(); 901da177e4SLinus Torvalds code = PCIBIOS_DEVICE_NOT_FOUND; 911da177e4SLinus Torvalds } 921da177e4SLinus Torvalds return code; 931da177e4SLinus Torvalds } 941da177e4SLinus Torvalds 9589d63fe1SAtsushi Nemoto static u8 icd_readb(int offset, struct tx4927_pcic_reg __iomem *pcicptr) 961da177e4SLinus Torvalds { 9789d63fe1SAtsushi Nemoto #ifdef __BIG_ENDIAN 9889d63fe1SAtsushi Nemoto offset ^= 3; 9989d63fe1SAtsushi Nemoto #endif 10089d63fe1SAtsushi Nemoto return __raw_readb((void __iomem *)&pcicptr->g2pcfgdata + offset); 10189d63fe1SAtsushi Nemoto } 10289d63fe1SAtsushi Nemoto static u16 icd_readw(int offset, struct tx4927_pcic_reg __iomem *pcicptr) 10389d63fe1SAtsushi Nemoto { 10489d63fe1SAtsushi Nemoto #ifdef __BIG_ENDIAN 10589d63fe1SAtsushi Nemoto offset ^= 2; 10689d63fe1SAtsushi Nemoto #endif 10789d63fe1SAtsushi Nemoto return __raw_readw((void __iomem *)&pcicptr->g2pcfgdata + offset); 10889d63fe1SAtsushi Nemoto } 10989d63fe1SAtsushi Nemoto static u32 icd_readl(struct tx4927_pcic_reg __iomem *pcicptr) 11089d63fe1SAtsushi Nemoto { 11189d63fe1SAtsushi Nemoto return __raw_readl(&pcicptr->g2pcfgdata); 11289d63fe1SAtsushi Nemoto } 11389d63fe1SAtsushi Nemoto static void icd_writeb(u8 val, int offset, 11489d63fe1SAtsushi Nemoto struct tx4927_pcic_reg __iomem *pcicptr) 11589d63fe1SAtsushi Nemoto { 11689d63fe1SAtsushi Nemoto #ifdef __BIG_ENDIAN 11789d63fe1SAtsushi Nemoto offset ^= 3; 11889d63fe1SAtsushi Nemoto #endif 11989d63fe1SAtsushi Nemoto __raw_writeb(val, (void __iomem *)&pcicptr->g2pcfgdata + offset); 12089d63fe1SAtsushi Nemoto } 12189d63fe1SAtsushi Nemoto static void icd_writew(u16 val, int offset, 12289d63fe1SAtsushi Nemoto struct tx4927_pcic_reg __iomem *pcicptr) 12389d63fe1SAtsushi Nemoto { 12489d63fe1SAtsushi Nemoto #ifdef __BIG_ENDIAN 12589d63fe1SAtsushi Nemoto offset ^= 2; 12689d63fe1SAtsushi Nemoto #endif 12789d63fe1SAtsushi Nemoto __raw_writew(val, (void __iomem *)&pcicptr->g2pcfgdata + offset); 12889d63fe1SAtsushi Nemoto } 12989d63fe1SAtsushi Nemoto static void icd_writel(u32 val, struct tx4927_pcic_reg __iomem *pcicptr) 13089d63fe1SAtsushi Nemoto { 13189d63fe1SAtsushi Nemoto __raw_writel(val, &pcicptr->g2pcfgdata); 1321da177e4SLinus Torvalds } 1331da177e4SLinus Torvalds 13489d63fe1SAtsushi Nemoto static struct tx4927_pcic_reg __iomem *pci_bus_to_pcicptr(struct pci_bus *bus) 13589d63fe1SAtsushi Nemoto { 13689d63fe1SAtsushi Nemoto struct pci_controller *channel = bus->sysdata; 13789d63fe1SAtsushi Nemoto return get_tx4927_pcicptr(channel); 1381da177e4SLinus Torvalds } 1391da177e4SLinus Torvalds 14089d63fe1SAtsushi Nemoto static int tx4927_pci_config_read(struct pci_bus *bus, unsigned int devfn, 14189d63fe1SAtsushi Nemoto int where, int size, u32 *val) 14289d63fe1SAtsushi Nemoto { 14389d63fe1SAtsushi Nemoto struct tx4927_pcic_reg __iomem *pcicptr = pci_bus_to_pcicptr(bus); 14489d63fe1SAtsushi Nemoto 14589d63fe1SAtsushi Nemoto if (mkaddr(bus, devfn, where, pcicptr)) { 1461da177e4SLinus Torvalds *val = 0xffffffff; 1471da177e4SLinus Torvalds return -1; 14889d63fe1SAtsushi Nemoto } 1491da177e4SLinus Torvalds switch (size) { 1501da177e4SLinus Torvalds case 1: 15189d63fe1SAtsushi Nemoto *val = icd_readb(where & 3, pcicptr); 1521da177e4SLinus Torvalds break; 1531da177e4SLinus Torvalds case 2: 15489d63fe1SAtsushi Nemoto *val = icd_readw(where & 3, pcicptr); 15589d63fe1SAtsushi Nemoto break; 15689d63fe1SAtsushi Nemoto default: 15789d63fe1SAtsushi Nemoto *val = icd_readl(pcicptr); 15889d63fe1SAtsushi Nemoto } 15989d63fe1SAtsushi Nemoto return check_abort(pcicptr); 16089d63fe1SAtsushi Nemoto } 16189d63fe1SAtsushi Nemoto 16289d63fe1SAtsushi Nemoto static int tx4927_pci_config_write(struct pci_bus *bus, unsigned int devfn, 16389d63fe1SAtsushi Nemoto int where, int size, u32 val) 16489d63fe1SAtsushi Nemoto { 16589d63fe1SAtsushi Nemoto struct tx4927_pcic_reg __iomem *pcicptr = pci_bus_to_pcicptr(bus); 16689d63fe1SAtsushi Nemoto 16789d63fe1SAtsushi Nemoto if (mkaddr(bus, devfn, where, pcicptr)) 16889d63fe1SAtsushi Nemoto return -1; 16989d63fe1SAtsushi Nemoto switch (size) { 17089d63fe1SAtsushi Nemoto case 1: 17189d63fe1SAtsushi Nemoto icd_writeb(val, where & 3, pcicptr); 17289d63fe1SAtsushi Nemoto break; 17389d63fe1SAtsushi Nemoto case 2: 17489d63fe1SAtsushi Nemoto icd_writew(val, where & 3, pcicptr); 17589d63fe1SAtsushi Nemoto break; 17689d63fe1SAtsushi Nemoto default: 17789d63fe1SAtsushi Nemoto icd_writel(val, pcicptr); 17889d63fe1SAtsushi Nemoto } 17989d63fe1SAtsushi Nemoto return check_abort(pcicptr); 18089d63fe1SAtsushi Nemoto } 18189d63fe1SAtsushi Nemoto 18289d63fe1SAtsushi Nemoto static struct pci_ops tx4927_pci_ops = { 18389d63fe1SAtsushi Nemoto .read = tx4927_pci_config_read, 18489d63fe1SAtsushi Nemoto .write = tx4927_pci_config_write, 18589d63fe1SAtsushi Nemoto }; 18689d63fe1SAtsushi Nemoto 18789d63fe1SAtsushi Nemoto static struct { 18889d63fe1SAtsushi Nemoto u8 trdyto; 18989d63fe1SAtsushi Nemoto u8 retryto; 19089d63fe1SAtsushi Nemoto u16 gbwc; 19189d63fe1SAtsushi Nemoto } tx4927_pci_opts __devinitdata = { 19289d63fe1SAtsushi Nemoto .trdyto = 0, 19389d63fe1SAtsushi Nemoto .retryto = 0, 19489d63fe1SAtsushi Nemoto .gbwc = 0xfe0, /* 4064 GBUSCLK for CCFG.GTOT=0b11 */ 19589d63fe1SAtsushi Nemoto }; 19689d63fe1SAtsushi Nemoto 19789d63fe1SAtsushi Nemoto void __init tx4927_pcic_setup(struct tx4927_pcic_reg __iomem *pcicptr, 19889d63fe1SAtsushi Nemoto struct pci_controller *channel, int extarb) 19989d63fe1SAtsushi Nemoto { 20089d63fe1SAtsushi Nemoto int i; 20189d63fe1SAtsushi Nemoto unsigned long flags; 20289d63fe1SAtsushi Nemoto 20389d63fe1SAtsushi Nemoto set_tx4927_pcicptr(channel, pcicptr); 20489d63fe1SAtsushi Nemoto 20589d63fe1SAtsushi Nemoto if (!channel->pci_ops) 20689d63fe1SAtsushi Nemoto printk(KERN_INFO 20789d63fe1SAtsushi Nemoto "PCIC -- DID:%04x VID:%04x RID:%02x Arbiter:%s\n", 20889d63fe1SAtsushi Nemoto __raw_readl(&pcicptr->pciid) >> 16, 20989d63fe1SAtsushi Nemoto __raw_readl(&pcicptr->pciid) & 0xffff, 21089d63fe1SAtsushi Nemoto __raw_readl(&pcicptr->pciccrev) & 0xff, 21189d63fe1SAtsushi Nemoto extarb ? "External" : "Internal"); 21289d63fe1SAtsushi Nemoto channel->pci_ops = &tx4927_pci_ops; 21389d63fe1SAtsushi Nemoto 21489d63fe1SAtsushi Nemoto local_irq_save(flags); 21589d63fe1SAtsushi Nemoto 21689d63fe1SAtsushi Nemoto /* Disable All Initiator Space */ 21789d63fe1SAtsushi Nemoto __raw_writel(__raw_readl(&pcicptr->pciccfg) 21889d63fe1SAtsushi Nemoto & ~(TX4927_PCIC_PCICCFG_G2PMEN(0) 21989d63fe1SAtsushi Nemoto | TX4927_PCIC_PCICCFG_G2PMEN(1) 22089d63fe1SAtsushi Nemoto | TX4927_PCIC_PCICCFG_G2PMEN(2) 22189d63fe1SAtsushi Nemoto | TX4927_PCIC_PCICCFG_G2PIOEN), 22289d63fe1SAtsushi Nemoto &pcicptr->pciccfg); 22389d63fe1SAtsushi Nemoto 22489d63fe1SAtsushi Nemoto /* GB->PCI mappings */ 22589d63fe1SAtsushi Nemoto __raw_writel((channel->io_resource->end - channel->io_resource->start) 22689d63fe1SAtsushi Nemoto >> 4, 22789d63fe1SAtsushi Nemoto &pcicptr->g2piomask); 22889d63fe1SAtsushi Nemoto ____raw_writeq((channel->io_resource->start + 22989d63fe1SAtsushi Nemoto channel->io_map_base - IO_BASE) | 23089d63fe1SAtsushi Nemoto #ifdef __BIG_ENDIAN 23189d63fe1SAtsushi Nemoto TX4927_PCIC_G2PIOGBASE_ECHG 2321da177e4SLinus Torvalds #else 23389d63fe1SAtsushi Nemoto TX4927_PCIC_G2PIOGBASE_BSDIS 2341da177e4SLinus Torvalds #endif 23589d63fe1SAtsushi Nemoto , &pcicptr->g2piogbase); 23689d63fe1SAtsushi Nemoto ____raw_writeq(channel->io_resource->start - channel->io_offset, 23789d63fe1SAtsushi Nemoto &pcicptr->g2piopbase); 23889d63fe1SAtsushi Nemoto for (i = 0; i < 3; i++) { 23989d63fe1SAtsushi Nemoto __raw_writel(0, &pcicptr->g2pmmask[i]); 24089d63fe1SAtsushi Nemoto ____raw_writeq(0, &pcicptr->g2pmgbase[i]); 24189d63fe1SAtsushi Nemoto ____raw_writeq(0, &pcicptr->g2pmpbase[i]); 24289d63fe1SAtsushi Nemoto } 24389d63fe1SAtsushi Nemoto if (channel->mem_resource->end) { 24489d63fe1SAtsushi Nemoto __raw_writel((channel->mem_resource->end 24589d63fe1SAtsushi Nemoto - channel->mem_resource->start) >> 4, 24689d63fe1SAtsushi Nemoto &pcicptr->g2pmmask[0]); 24789d63fe1SAtsushi Nemoto ____raw_writeq(channel->mem_resource->start | 24889d63fe1SAtsushi Nemoto #ifdef __BIG_ENDIAN 24989d63fe1SAtsushi Nemoto TX4927_PCIC_G2PMnGBASE_ECHG 25089d63fe1SAtsushi Nemoto #else 25189d63fe1SAtsushi Nemoto TX4927_PCIC_G2PMnGBASE_BSDIS 25289d63fe1SAtsushi Nemoto #endif 25389d63fe1SAtsushi Nemoto , &pcicptr->g2pmgbase[0]); 25489d63fe1SAtsushi Nemoto ____raw_writeq(channel->mem_resource->start - 25589d63fe1SAtsushi Nemoto channel->mem_offset, 25689d63fe1SAtsushi Nemoto &pcicptr->g2pmpbase[0]); 25789d63fe1SAtsushi Nemoto } 25889d63fe1SAtsushi Nemoto /* PCI->GB mappings (I/O 256B) */ 25989d63fe1SAtsushi Nemoto __raw_writel(0, &pcicptr->p2giopbase); /* 256B */ 26089d63fe1SAtsushi Nemoto ____raw_writeq(0, &pcicptr->p2giogbase); 26189d63fe1SAtsushi Nemoto /* PCI->GB mappings (MEM 512MB (64MB on R1.x)) */ 26289d63fe1SAtsushi Nemoto __raw_writel(0, &pcicptr->p2gm0plbase); 26389d63fe1SAtsushi Nemoto __raw_writel(0, &pcicptr->p2gm0pubase); 26489d63fe1SAtsushi Nemoto ____raw_writeq(TX4927_PCIC_P2GMnGBASE_TMEMEN | 26589d63fe1SAtsushi Nemoto #ifdef __BIG_ENDIAN 26689d63fe1SAtsushi Nemoto TX4927_PCIC_P2GMnGBASE_TECHG 26789d63fe1SAtsushi Nemoto #else 26889d63fe1SAtsushi Nemoto TX4927_PCIC_P2GMnGBASE_TBSDIS 26989d63fe1SAtsushi Nemoto #endif 27089d63fe1SAtsushi Nemoto , &pcicptr->p2gmgbase[0]); 27189d63fe1SAtsushi Nemoto /* PCI->GB mappings (MEM 16MB) */ 27289d63fe1SAtsushi Nemoto __raw_writel(0xffffffff, &pcicptr->p2gm1plbase); 27389d63fe1SAtsushi Nemoto __raw_writel(0xffffffff, &pcicptr->p2gm1pubase); 27489d63fe1SAtsushi Nemoto ____raw_writeq(0, &pcicptr->p2gmgbase[1]); 27589d63fe1SAtsushi Nemoto /* PCI->GB mappings (MEM 1MB) */ 27689d63fe1SAtsushi Nemoto __raw_writel(0xffffffff, &pcicptr->p2gm2pbase); /* 1MB */ 27789d63fe1SAtsushi Nemoto ____raw_writeq(0, &pcicptr->p2gmgbase[2]); 27889d63fe1SAtsushi Nemoto 27989d63fe1SAtsushi Nemoto /* Clear all (including IRBER) except for GBWC */ 28089d63fe1SAtsushi Nemoto __raw_writel((tx4927_pci_opts.gbwc << 16) 28189d63fe1SAtsushi Nemoto & TX4927_PCIC_PCICCFG_GBWC_MASK, 28289d63fe1SAtsushi Nemoto &pcicptr->pciccfg); 28389d63fe1SAtsushi Nemoto /* Enable Initiator Memory Space */ 28489d63fe1SAtsushi Nemoto if (channel->mem_resource->end) 28589d63fe1SAtsushi Nemoto __raw_writel(__raw_readl(&pcicptr->pciccfg) 28689d63fe1SAtsushi Nemoto | TX4927_PCIC_PCICCFG_G2PMEN(0), 28789d63fe1SAtsushi Nemoto &pcicptr->pciccfg); 28889d63fe1SAtsushi Nemoto /* Enable Initiator I/O Space */ 28989d63fe1SAtsushi Nemoto if (channel->io_resource->end) 29089d63fe1SAtsushi Nemoto __raw_writel(__raw_readl(&pcicptr->pciccfg) 29189d63fe1SAtsushi Nemoto | TX4927_PCIC_PCICCFG_G2PIOEN, 29289d63fe1SAtsushi Nemoto &pcicptr->pciccfg); 29389d63fe1SAtsushi Nemoto /* Enable Initiator Config */ 29489d63fe1SAtsushi Nemoto __raw_writel(__raw_readl(&pcicptr->pciccfg) 29589d63fe1SAtsushi Nemoto | TX4927_PCIC_PCICCFG_ICAEN | TX4927_PCIC_PCICCFG_TCAR, 29689d63fe1SAtsushi Nemoto &pcicptr->pciccfg); 29789d63fe1SAtsushi Nemoto 29889d63fe1SAtsushi Nemoto /* Do not use MEMMUL, MEMINF: YMFPCI card causes M_ABORT. */ 29989d63fe1SAtsushi Nemoto __raw_writel(0, &pcicptr->pcicfg1); 30089d63fe1SAtsushi Nemoto 30189d63fe1SAtsushi Nemoto __raw_writel((__raw_readl(&pcicptr->g2ptocnt) & ~0xffff) 30289d63fe1SAtsushi Nemoto | (tx4927_pci_opts.trdyto & 0xff) 30389d63fe1SAtsushi Nemoto | ((tx4927_pci_opts.retryto & 0xff) << 8), 30489d63fe1SAtsushi Nemoto &pcicptr->g2ptocnt); 30589d63fe1SAtsushi Nemoto 30689d63fe1SAtsushi Nemoto /* Clear All Local Bus Status */ 30789d63fe1SAtsushi Nemoto __raw_writel(TX4927_PCIC_PCICSTATUS_ALL, &pcicptr->pcicstatus); 30889d63fe1SAtsushi Nemoto /* Enable All Local Bus Interrupts */ 30989d63fe1SAtsushi Nemoto __raw_writel(TX4927_PCIC_PCICSTATUS_ALL, &pcicptr->pcicmask); 31089d63fe1SAtsushi Nemoto /* Clear All Initiator Status */ 31189d63fe1SAtsushi Nemoto __raw_writel(TX4927_PCIC_G2PSTATUS_ALL, &pcicptr->g2pstatus); 31289d63fe1SAtsushi Nemoto /* Enable All Initiator Interrupts */ 31389d63fe1SAtsushi Nemoto __raw_writel(TX4927_PCIC_G2PSTATUS_ALL, &pcicptr->g2pmask); 31489d63fe1SAtsushi Nemoto /* Clear All PCI Status Error */ 31589d63fe1SAtsushi Nemoto __raw_writel((__raw_readl(&pcicptr->pcistatus) & 0x0000ffff) 31689d63fe1SAtsushi Nemoto | (TX4927_PCIC_PCISTATUS_ALL << 16), 31789d63fe1SAtsushi Nemoto &pcicptr->pcistatus); 31889d63fe1SAtsushi Nemoto /* Enable All PCI Status Error Interrupts */ 31989d63fe1SAtsushi Nemoto __raw_writel(TX4927_PCIC_PCISTATUS_ALL, &pcicptr->pcimask); 32089d63fe1SAtsushi Nemoto 32189d63fe1SAtsushi Nemoto if (!extarb) { 32289d63fe1SAtsushi Nemoto /* Reset Bus Arbiter */ 32389d63fe1SAtsushi Nemoto __raw_writel(TX4927_PCIC_PBACFG_RPBA, &pcicptr->pbacfg); 32489d63fe1SAtsushi Nemoto __raw_writel(0, &pcicptr->pbabm); 32589d63fe1SAtsushi Nemoto /* Enable Bus Arbiter */ 32689d63fe1SAtsushi Nemoto __raw_writel(TX4927_PCIC_PBACFG_PBAEN, &pcicptr->pbacfg); 3271da177e4SLinus Torvalds } 3281da177e4SLinus Torvalds 32989d63fe1SAtsushi Nemoto __raw_writel(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY 33089d63fe1SAtsushi Nemoto | PCI_COMMAND_PARITY | PCI_COMMAND_SERR, 33189d63fe1SAtsushi Nemoto &pcicptr->pcistatus); 33289d63fe1SAtsushi Nemoto local_irq_restore(flags); 33389d63fe1SAtsushi Nemoto 33489d63fe1SAtsushi Nemoto printk(KERN_DEBUG 33589d63fe1SAtsushi Nemoto "PCI: COMMAND=%04x,PCIMASK=%04x," 33689d63fe1SAtsushi Nemoto "TRDYTO=%02x,RETRYTO=%02x,GBWC=%03x\n", 33789d63fe1SAtsushi Nemoto __raw_readl(&pcicptr->pcistatus) & 0xffff, 33889d63fe1SAtsushi Nemoto __raw_readl(&pcicptr->pcimask) & 0xffff, 33989d63fe1SAtsushi Nemoto __raw_readl(&pcicptr->g2ptocnt) & 0xff, 34089d63fe1SAtsushi Nemoto (__raw_readl(&pcicptr->g2ptocnt) & 0xff00) >> 8, 34189d63fe1SAtsushi Nemoto (__raw_readl(&pcicptr->pciccfg) >> 16) & 0xfff); 3421da177e4SLinus Torvalds } 3431da177e4SLinus Torvalds 34489d63fe1SAtsushi Nemoto static void tx4927_report_pcic_status1(struct tx4927_pcic_reg __iomem *pcicptr) 34589d63fe1SAtsushi Nemoto { 34689d63fe1SAtsushi Nemoto __u16 pcistatus = (__u16)(__raw_readl(&pcicptr->pcistatus) >> 16); 34789d63fe1SAtsushi Nemoto __u32 g2pstatus = __raw_readl(&pcicptr->g2pstatus); 34889d63fe1SAtsushi Nemoto __u32 pcicstatus = __raw_readl(&pcicptr->pcicstatus); 34989d63fe1SAtsushi Nemoto static struct { 35089d63fe1SAtsushi Nemoto __u32 flag; 35189d63fe1SAtsushi Nemoto const char *str; 35289d63fe1SAtsushi Nemoto } pcistat_tbl[] = { 35389d63fe1SAtsushi Nemoto { PCI_STATUS_DETECTED_PARITY, "DetectedParityError" }, 35489d63fe1SAtsushi Nemoto { PCI_STATUS_SIG_SYSTEM_ERROR, "SignaledSystemError" }, 35589d63fe1SAtsushi Nemoto { PCI_STATUS_REC_MASTER_ABORT, "ReceivedMasterAbort" }, 35689d63fe1SAtsushi Nemoto { PCI_STATUS_REC_TARGET_ABORT, "ReceivedTargetAbort" }, 35789d63fe1SAtsushi Nemoto { PCI_STATUS_SIG_TARGET_ABORT, "SignaledTargetAbort" }, 35889d63fe1SAtsushi Nemoto { PCI_STATUS_PARITY, "MasterParityError" }, 35989d63fe1SAtsushi Nemoto }, g2pstat_tbl[] = { 36089d63fe1SAtsushi Nemoto { TX4927_PCIC_G2PSTATUS_TTOE, "TIOE" }, 36189d63fe1SAtsushi Nemoto { TX4927_PCIC_G2PSTATUS_RTOE, "RTOE" }, 36289d63fe1SAtsushi Nemoto }, pcicstat_tbl[] = { 36389d63fe1SAtsushi Nemoto { TX4927_PCIC_PCICSTATUS_PME, "PME" }, 36489d63fe1SAtsushi Nemoto { TX4927_PCIC_PCICSTATUS_TLB, "TLB" }, 36589d63fe1SAtsushi Nemoto { TX4927_PCIC_PCICSTATUS_NIB, "NIB" }, 36689d63fe1SAtsushi Nemoto { TX4927_PCIC_PCICSTATUS_ZIB, "ZIB" }, 36789d63fe1SAtsushi Nemoto { TX4927_PCIC_PCICSTATUS_PERR, "PERR" }, 36889d63fe1SAtsushi Nemoto { TX4927_PCIC_PCICSTATUS_SERR, "SERR" }, 36989d63fe1SAtsushi Nemoto { TX4927_PCIC_PCICSTATUS_GBE, "GBE" }, 37089d63fe1SAtsushi Nemoto { TX4927_PCIC_PCICSTATUS_IWB, "IWB" }, 3711da177e4SLinus Torvalds }; 37289d63fe1SAtsushi Nemoto int i, cont; 3731da177e4SLinus Torvalds 37489d63fe1SAtsushi Nemoto printk(KERN_ERR ""); 37589d63fe1SAtsushi Nemoto if (pcistatus & TX4927_PCIC_PCISTATUS_ALL) { 37689d63fe1SAtsushi Nemoto printk(KERN_CONT "pcistat:%04x(", pcistatus); 37789d63fe1SAtsushi Nemoto for (i = 0, cont = 0; i < ARRAY_SIZE(pcistat_tbl); i++) 37889d63fe1SAtsushi Nemoto if (pcistatus & pcistat_tbl[i].flag) 37989d63fe1SAtsushi Nemoto printk(KERN_CONT "%s%s", 38089d63fe1SAtsushi Nemoto cont++ ? " " : "", pcistat_tbl[i].str); 38189d63fe1SAtsushi Nemoto printk(KERN_CONT ") "); 38289d63fe1SAtsushi Nemoto } 38389d63fe1SAtsushi Nemoto if (g2pstatus & TX4927_PCIC_G2PSTATUS_ALL) { 38489d63fe1SAtsushi Nemoto printk(KERN_CONT "g2pstatus:%08x(", g2pstatus); 38589d63fe1SAtsushi Nemoto for (i = 0, cont = 0; i < ARRAY_SIZE(g2pstat_tbl); i++) 38689d63fe1SAtsushi Nemoto if (g2pstatus & g2pstat_tbl[i].flag) 38789d63fe1SAtsushi Nemoto printk(KERN_CONT "%s%s", 38889d63fe1SAtsushi Nemoto cont++ ? " " : "", g2pstat_tbl[i].str); 38989d63fe1SAtsushi Nemoto printk(KERN_CONT ") "); 39089d63fe1SAtsushi Nemoto } 39189d63fe1SAtsushi Nemoto if (pcicstatus & TX4927_PCIC_PCICSTATUS_ALL) { 39289d63fe1SAtsushi Nemoto printk(KERN_CONT "pcicstatus:%08x(", pcicstatus); 39389d63fe1SAtsushi Nemoto for (i = 0, cont = 0; i < ARRAY_SIZE(pcicstat_tbl); i++) 39489d63fe1SAtsushi Nemoto if (pcicstatus & pcicstat_tbl[i].flag) 39589d63fe1SAtsushi Nemoto printk(KERN_CONT "%s%s", 39689d63fe1SAtsushi Nemoto cont++ ? " " : "", pcicstat_tbl[i].str); 39789d63fe1SAtsushi Nemoto printk(KERN_CONT ")"); 39889d63fe1SAtsushi Nemoto } 39989d63fe1SAtsushi Nemoto printk(KERN_CONT "\n"); 40089d63fe1SAtsushi Nemoto } 40189d63fe1SAtsushi Nemoto 40289d63fe1SAtsushi Nemoto void tx4927_report_pcic_status(void) 40389d63fe1SAtsushi Nemoto { 40489d63fe1SAtsushi Nemoto int i; 40589d63fe1SAtsushi Nemoto 40689d63fe1SAtsushi Nemoto for (i = 0; i < ARRAY_SIZE(pcicptrs); i++) { 40789d63fe1SAtsushi Nemoto if (pcicptrs[i].pcicptr) 40889d63fe1SAtsushi Nemoto tx4927_report_pcic_status1(pcicptrs[i].pcicptr); 40989d63fe1SAtsushi Nemoto } 41089d63fe1SAtsushi Nemoto } 411*32d00d0fSAtsushi Nemoto 412*32d00d0fSAtsushi Nemoto #ifdef CONFIG_TOSHIBA_FPCIB0 413*32d00d0fSAtsushi Nemoto static void __init tx4927_quirk_slc90e66_bridge(struct pci_dev *dev) 414*32d00d0fSAtsushi Nemoto { 415*32d00d0fSAtsushi Nemoto struct tx4927_pcic_reg __iomem *pcicptr = pci_bus_to_pcicptr(dev->bus); 416*32d00d0fSAtsushi Nemoto 417*32d00d0fSAtsushi Nemoto if (!pcicptr) 418*32d00d0fSAtsushi Nemoto return; 419*32d00d0fSAtsushi Nemoto if (__raw_readl(&pcicptr->pbacfg) & TX4927_PCIC_PBACFG_PBAEN) { 420*32d00d0fSAtsushi Nemoto /* Reset Bus Arbiter */ 421*32d00d0fSAtsushi Nemoto __raw_writel(TX4927_PCIC_PBACFG_RPBA, &pcicptr->pbacfg); 422*32d00d0fSAtsushi Nemoto /* 423*32d00d0fSAtsushi Nemoto * swap reqBP and reqXP (raise priority of SLC90E66). 424*32d00d0fSAtsushi Nemoto * SLC90E66(PCI-ISA bridge) is connected to REQ2 on 425*32d00d0fSAtsushi Nemoto * PCI Backplane board. 426*32d00d0fSAtsushi Nemoto */ 427*32d00d0fSAtsushi Nemoto __raw_writel(0x72543610, &pcicptr->pbareqport); 428*32d00d0fSAtsushi Nemoto __raw_writel(0, &pcicptr->pbabm); 429*32d00d0fSAtsushi Nemoto /* Use Fixed ParkMaster (required by SLC90E66) */ 430*32d00d0fSAtsushi Nemoto __raw_writel(TX4927_PCIC_PBACFG_FIXPA, &pcicptr->pbacfg); 431*32d00d0fSAtsushi Nemoto /* Enable Bus Arbiter */ 432*32d00d0fSAtsushi Nemoto __raw_writel(TX4927_PCIC_PBACFG_FIXPA | 433*32d00d0fSAtsushi Nemoto TX4927_PCIC_PBACFG_PBAEN, 434*32d00d0fSAtsushi Nemoto &pcicptr->pbacfg); 435*32d00d0fSAtsushi Nemoto printk(KERN_INFO "PCI: Use Fixed Park Master (REQPORT %08x)\n", 436*32d00d0fSAtsushi Nemoto __raw_readl(&pcicptr->pbareqport)); 437*32d00d0fSAtsushi Nemoto } 438*32d00d0fSAtsushi Nemoto } 439*32d00d0fSAtsushi Nemoto #define PCI_DEVICE_ID_EFAR_SLC90E66_0 0x9460 440*32d00d0fSAtsushi Nemoto DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_EFAR, PCI_DEVICE_ID_EFAR_SLC90E66_0, 441*32d00d0fSAtsushi Nemoto tx4927_quirk_slc90e66_bridge); 442*32d00d0fSAtsushi Nemoto #endif 443