1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 1999, 2000, 2004 MIPS Technologies, Inc. 4 * All rights reserved. 5 * Authors: Carsten Langgaard <carstenl@mips.com> 6 * Maciej W. Rozycki <macro@mips.com> 7 * 8 * Copyright (C) 2009 Lemote Inc. 9 * Author: Wu Zhangjin <wuzhangjin@gmail.com> 10 */ 11 #include <linux/types.h> 12 #include <linux/pci.h> 13 #include <linux/kernel.h> 14 #include <linux/export.h> 15 16 #include <loongson.h> 17 18 #ifdef CONFIG_CS5536 19 #include <cs5536/cs5536_pci.h> 20 #include <cs5536/cs5536.h> 21 #endif 22 23 #define PCI_ACCESS_READ 0 24 #define PCI_ACCESS_WRITE 1 25 26 #define CFG_SPACE_REG(offset) \ 27 (void *)CKSEG1ADDR(LOONGSON_PCICFG_BASE | (offset)) 28 #define ID_SEL_BEGIN 11 29 #define MAX_DEV_NUM (31 - ID_SEL_BEGIN) 30 31 32 static int loongson_pcibios_config_access(unsigned char access_type, 33 struct pci_bus *bus, 34 unsigned int devfn, int where, 35 u32 *data) 36 { 37 u32 busnum = bus->number; 38 u32 addr, type; 39 u32 dummy; 40 void *addrp; 41 int device = PCI_SLOT(devfn); 42 int function = PCI_FUNC(devfn); 43 int reg = where & ~3; 44 45 if (busnum == 0) { 46 /* board-specific part,currently,only fuloong2f,yeeloong2f 47 * use CS5536, fuloong2e use via686b, gdium has no 48 * south bridge 49 */ 50 #ifdef CONFIG_CS5536 51 /* cs5536_pci_conf_read4/write4() will call _rdmsr/_wrmsr() to 52 * access the registers PCI_MSR_ADDR, PCI_MSR_DATA_LO, 53 * PCI_MSR_DATA_HI, which is bigger than PCI_MSR_CTRL, so, it 54 * will not go this branch, but the others. so, no calling dead 55 * loop here. 56 */ 57 if ((PCI_IDSEL_CS5536 == device) && (reg < PCI_MSR_CTRL)) { 58 switch (access_type) { 59 case PCI_ACCESS_READ: 60 *data = cs5536_pci_conf_read4(function, reg); 61 break; 62 case PCI_ACCESS_WRITE: 63 cs5536_pci_conf_write4(function, reg, *data); 64 break; 65 } 66 return 0; 67 } 68 #endif 69 /* Type 0 configuration for onboard PCI bus */ 70 if (device > MAX_DEV_NUM) 71 return -1; 72 73 addr = (1 << (device + ID_SEL_BEGIN)) | (function << 8) | reg; 74 type = 0; 75 } else { 76 /* Type 1 configuration for offboard PCI bus */ 77 addr = (busnum << 16) | (device << 11) | (function << 8) | reg; 78 type = 0x10000; 79 } 80 81 /* Clear aborts */ 82 LOONGSON_PCICMD |= LOONGSON_PCICMD_MABORT_CLR | \ 83 LOONGSON_PCICMD_MTABORT_CLR; 84 85 LOONGSON_PCIMAP_CFG = (addr >> 16) | type; 86 87 /* Flush Bonito register block */ 88 dummy = LOONGSON_PCIMAP_CFG; 89 mmiowb(); 90 91 addrp = CFG_SPACE_REG(addr & 0xffff); 92 if (access_type == PCI_ACCESS_WRITE) 93 writel(cpu_to_le32(*data), addrp); 94 else 95 *data = le32_to_cpu(readl(addrp)); 96 97 /* Detect Master/Target abort */ 98 if (LOONGSON_PCICMD & (LOONGSON_PCICMD_MABORT_CLR | 99 LOONGSON_PCICMD_MTABORT_CLR)) { 100 /* Error occurred */ 101 102 /* Clear bits */ 103 LOONGSON_PCICMD |= (LOONGSON_PCICMD_MABORT_CLR | 104 LOONGSON_PCICMD_MTABORT_CLR); 105 106 return -1; 107 } 108 109 return 0; 110 111 } 112 113 114 /* 115 * We can't address 8 and 16 bit words directly. Instead we have to 116 * read/write a 32bit word and mask/modify the data we actually want. 117 */ 118 static int loongson_pcibios_read(struct pci_bus *bus, unsigned int devfn, 119 int where, int size, u32 *val) 120 { 121 u32 data = 0; 122 123 if ((size == 2) && (where & 1)) 124 return PCIBIOS_BAD_REGISTER_NUMBER; 125 else if ((size == 4) && (where & 3)) 126 return PCIBIOS_BAD_REGISTER_NUMBER; 127 128 if (loongson_pcibios_config_access(PCI_ACCESS_READ, bus, devfn, where, 129 &data)) 130 return -1; 131 132 if (size == 1) 133 *val = (data >> ((where & 3) << 3)) & 0xff; 134 else if (size == 2) 135 *val = (data >> ((where & 3) << 3)) & 0xffff; 136 else 137 *val = data; 138 139 return PCIBIOS_SUCCESSFUL; 140 } 141 142 static int loongson_pcibios_write(struct pci_bus *bus, unsigned int devfn, 143 int where, int size, u32 val) 144 { 145 u32 data = 0; 146 147 if ((size == 2) && (where & 1)) 148 return PCIBIOS_BAD_REGISTER_NUMBER; 149 else if ((size == 4) && (where & 3)) 150 return PCIBIOS_BAD_REGISTER_NUMBER; 151 152 if (size == 4) 153 data = val; 154 else { 155 if (loongson_pcibios_config_access(PCI_ACCESS_READ, bus, devfn, 156 where, &data)) 157 return -1; 158 159 if (size == 1) 160 data = (data & ~(0xff << ((where & 3) << 3))) | 161 (val << ((where & 3) << 3)); 162 else if (size == 2) 163 data = (data & ~(0xffff << ((where & 3) << 3))) | 164 (val << ((where & 3) << 3)); 165 } 166 167 if (loongson_pcibios_config_access(PCI_ACCESS_WRITE, bus, devfn, where, 168 &data)) 169 return -1; 170 171 return PCIBIOS_SUCCESSFUL; 172 } 173 174 struct pci_ops loongson_pci_ops = { 175 .read = loongson_pcibios_read, 176 .write = loongson_pcibios_write 177 }; 178 179 #ifdef CONFIG_CS5536 180 DEFINE_RAW_SPINLOCK(msr_lock); 181 182 void _rdmsr(u32 msr, u32 *hi, u32 *lo) 183 { 184 struct pci_bus bus = { 185 .number = PCI_BUS_CS5536 186 }; 187 u32 devfn = PCI_DEVFN(PCI_IDSEL_CS5536, 0); 188 unsigned long flags; 189 190 raw_spin_lock_irqsave(&msr_lock, flags); 191 loongson_pcibios_write(&bus, devfn, PCI_MSR_ADDR, 4, msr); 192 loongson_pcibios_read(&bus, devfn, PCI_MSR_DATA_LO, 4, lo); 193 loongson_pcibios_read(&bus, devfn, PCI_MSR_DATA_HI, 4, hi); 194 raw_spin_unlock_irqrestore(&msr_lock, flags); 195 } 196 EXPORT_SYMBOL(_rdmsr); 197 198 void _wrmsr(u32 msr, u32 hi, u32 lo) 199 { 200 struct pci_bus bus = { 201 .number = PCI_BUS_CS5536 202 }; 203 u32 devfn = PCI_DEVFN(PCI_IDSEL_CS5536, 0); 204 unsigned long flags; 205 206 raw_spin_lock_irqsave(&msr_lock, flags); 207 loongson_pcibios_write(&bus, devfn, PCI_MSR_ADDR, 4, msr); 208 loongson_pcibios_write(&bus, devfn, PCI_MSR_DATA_LO, 4, lo); 209 loongson_pcibios_write(&bus, devfn, PCI_MSR_DATA_HI, 4, hi); 210 raw_spin_unlock_irqrestore(&msr_lock, flags); 211 } 212 EXPORT_SYMBOL(_wrmsr); 213 #endif 214