1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Just-In-Time compiler for eBPF bytecode on MIPS. 4 * Implementation of JIT functions for 64-bit CPUs. 5 * 6 * Copyright (c) 2021 Anyfi Networks AB. 7 * Author: Johan Almbladh <johan.almbladh@gmail.com> 8 * 9 * Based on code and ideas from 10 * Copyright (c) 2017 Cavium, Inc. 11 * Copyright (c) 2017 Shubham Bansal <illusionist.neo@gmail.com> 12 * Copyright (c) 2011 Mircea Gherzan <mgherzan@gmail.com> 13 */ 14 15 #include <linux/errno.h> 16 #include <linux/filter.h> 17 #include <linux/bpf.h> 18 #include <asm/cpu-features.h> 19 #include <asm/isa-rev.h> 20 #include <asm/uasm.h> 21 22 #include "bpf_jit_comp.h" 23 24 /* MIPS t0-t3 are not available in the n64 ABI */ 25 #undef MIPS_R_T0 26 #undef MIPS_R_T1 27 #undef MIPS_R_T2 28 #undef MIPS_R_T3 29 30 /* Stack is 16-byte aligned in n64 ABI */ 31 #define MIPS_STACK_ALIGNMENT 16 32 33 /* Extra 64-bit eBPF registers used by JIT */ 34 #define JIT_REG_TC (MAX_BPF_JIT_REG + 0) 35 #define JIT_REG_ZX (MAX_BPF_JIT_REG + 1) 36 37 /* Number of prologue bytes to skip when doing a tail call */ 38 #define JIT_TCALL_SKIP 4 39 40 /* Callee-saved CPU registers that the JIT must preserve */ 41 #define JIT_CALLEE_REGS \ 42 (BIT(MIPS_R_S0) | \ 43 BIT(MIPS_R_S1) | \ 44 BIT(MIPS_R_S2) | \ 45 BIT(MIPS_R_S3) | \ 46 BIT(MIPS_R_S4) | \ 47 BIT(MIPS_R_S5) | \ 48 BIT(MIPS_R_S6) | \ 49 BIT(MIPS_R_S7) | \ 50 BIT(MIPS_R_GP) | \ 51 BIT(MIPS_R_FP) | \ 52 BIT(MIPS_R_RA)) 53 54 /* Caller-saved CPU registers available for JIT use */ 55 #define JIT_CALLER_REGS \ 56 (BIT(MIPS_R_A5) | \ 57 BIT(MIPS_R_A6) | \ 58 BIT(MIPS_R_A7)) 59 /* 60 * Mapping of 64-bit eBPF registers to 64-bit native MIPS registers. 61 * MIPS registers t4 - t7 may be used by the JIT as temporary registers. 62 * MIPS registers t8 - t9 are reserved for single-register common functions. 63 */ 64 static const u8 bpf2mips64[] = { 65 /* Return value from in-kernel function, and exit value from eBPF */ 66 [BPF_REG_0] = MIPS_R_V0, 67 /* Arguments from eBPF program to in-kernel function */ 68 [BPF_REG_1] = MIPS_R_A0, 69 [BPF_REG_2] = MIPS_R_A1, 70 [BPF_REG_3] = MIPS_R_A2, 71 [BPF_REG_4] = MIPS_R_A3, 72 [BPF_REG_5] = MIPS_R_A4, 73 /* Callee-saved registers that in-kernel function will preserve */ 74 [BPF_REG_6] = MIPS_R_S0, 75 [BPF_REG_7] = MIPS_R_S1, 76 [BPF_REG_8] = MIPS_R_S2, 77 [BPF_REG_9] = MIPS_R_S3, 78 /* Read-only frame pointer to access the eBPF stack */ 79 [BPF_REG_FP] = MIPS_R_FP, 80 /* Temporary register for blinding constants */ 81 [BPF_REG_AX] = MIPS_R_AT, 82 /* Tail call count register, caller-saved */ 83 [JIT_REG_TC] = MIPS_R_A5, 84 /* Constant for register zero-extension */ 85 [JIT_REG_ZX] = MIPS_R_V1, 86 }; 87 88 /* 89 * MIPS 32-bit operations on 64-bit registers generate a sign-extended 90 * result. However, the eBPF ISA mandates zero-extension, so we rely on the 91 * verifier to add that for us (emit_zext_ver). In addition, ALU arithmetic 92 * operations, right shift and byte swap require properly sign-extended 93 * operands or the result is unpredictable. We emit explicit sign-extensions 94 * in those cases. 95 */ 96 97 /* Sign extension */ 98 static void emit_sext(struct jit_context *ctx, u8 dst, u8 src) 99 { 100 emit(ctx, sll, dst, src, 0); 101 clobber_reg(ctx, dst); 102 } 103 104 /* Zero extension */ 105 static void emit_zext(struct jit_context *ctx, u8 dst) 106 { 107 if (cpu_has_mips64r2 || cpu_has_mips64r6) { 108 emit(ctx, dinsu, dst, MIPS_R_ZERO, 32, 32); 109 } else { 110 emit(ctx, and, dst, dst, bpf2mips64[JIT_REG_ZX]); 111 access_reg(ctx, JIT_REG_ZX); /* We need the ZX register */ 112 } 113 clobber_reg(ctx, dst); 114 } 115 116 /* Zero extension, if verifier does not do it for us */ 117 static void emit_zext_ver(struct jit_context *ctx, u8 dst) 118 { 119 if (!ctx->program->aux->verifier_zext) 120 emit_zext(ctx, dst); 121 } 122 123 /* dst = imm (64-bit) */ 124 static void emit_mov_i64(struct jit_context *ctx, u8 dst, u64 imm64) 125 { 126 if (imm64 >= 0xffffffffffff8000ULL || imm64 < 0x8000ULL) { 127 emit(ctx, daddiu, dst, MIPS_R_ZERO, (s16)imm64); 128 } else if (imm64 >= 0xffffffff80000000ULL || 129 (imm64 < 0x80000000 && imm64 > 0xffff)) { 130 emit(ctx, lui, dst, (s16)(imm64 >> 16)); 131 emit(ctx, ori, dst, dst, (u16)imm64 & 0xffff); 132 } else { 133 u8 acc = MIPS_R_ZERO; 134 int shift = 0; 135 int k; 136 137 for (k = 0; k < 4; k++) { 138 u16 half = imm64 >> (48 - 16 * k); 139 140 if (acc == dst) 141 shift += 16; 142 143 if (half) { 144 if (shift) 145 emit(ctx, dsll_safe, dst, dst, shift); 146 emit(ctx, ori, dst, acc, half); 147 acc = dst; 148 shift = 0; 149 } 150 } 151 if (shift) 152 emit(ctx, dsll_safe, dst, dst, shift); 153 } 154 clobber_reg(ctx, dst); 155 } 156 157 /* ALU immediate operation (64-bit) */ 158 static void emit_alu_i64(struct jit_context *ctx, u8 dst, s32 imm, u8 op) 159 { 160 switch (BPF_OP(op)) { 161 /* dst = dst | imm */ 162 case BPF_OR: 163 emit(ctx, ori, dst, dst, (u16)imm); 164 break; 165 /* dst = dst ^ imm */ 166 case BPF_XOR: 167 emit(ctx, xori, dst, dst, (u16)imm); 168 break; 169 /* dst = -dst */ 170 case BPF_NEG: 171 emit(ctx, dsubu, dst, MIPS_R_ZERO, dst); 172 break; 173 /* dst = dst << imm */ 174 case BPF_LSH: 175 emit(ctx, dsll_safe, dst, dst, imm); 176 break; 177 /* dst = dst >> imm */ 178 case BPF_RSH: 179 emit(ctx, dsrl_safe, dst, dst, imm); 180 break; 181 /* dst = dst >> imm (arithmetic) */ 182 case BPF_ARSH: 183 emit(ctx, dsra_safe, dst, dst, imm); 184 break; 185 /* dst = dst + imm */ 186 case BPF_ADD: 187 emit(ctx, daddiu, dst, dst, imm); 188 break; 189 /* dst = dst - imm */ 190 case BPF_SUB: 191 emit(ctx, daddiu, dst, dst, -imm); 192 break; 193 default: 194 /* Width-generic operations */ 195 emit_alu_i(ctx, dst, imm, op); 196 } 197 clobber_reg(ctx, dst); 198 } 199 200 /* ALU register operation (64-bit) */ 201 static void emit_alu_r64(struct jit_context *ctx, u8 dst, u8 src, u8 op) 202 { 203 switch (BPF_OP(op)) { 204 /* dst = dst << src */ 205 case BPF_LSH: 206 emit(ctx, dsllv, dst, dst, src); 207 break; 208 /* dst = dst >> src */ 209 case BPF_RSH: 210 emit(ctx, dsrlv, dst, dst, src); 211 break; 212 /* dst = dst >> src (arithmetic) */ 213 case BPF_ARSH: 214 emit(ctx, dsrav, dst, dst, src); 215 break; 216 /* dst = dst + src */ 217 case BPF_ADD: 218 emit(ctx, daddu, dst, dst, src); 219 break; 220 /* dst = dst - src */ 221 case BPF_SUB: 222 emit(ctx, dsubu, dst, dst, src); 223 break; 224 /* dst = dst * src */ 225 case BPF_MUL: 226 if (cpu_has_mips64r6) { 227 emit(ctx, dmulu, dst, dst, src); 228 } else { 229 emit(ctx, dmultu, dst, src); 230 emit(ctx, mflo, dst); 231 /* Ensure multiplication is completed */ 232 if (IS_ENABLED(CONFIG_CPU_R4000_WORKAROUNDS)) 233 emit(ctx, mfhi, MIPS_R_ZERO); 234 } 235 break; 236 /* dst = dst / src */ 237 case BPF_DIV: 238 if (cpu_has_mips64r6) { 239 emit(ctx, ddivu_r6, dst, dst, src); 240 } else { 241 emit(ctx, ddivu, dst, src); 242 emit(ctx, mflo, dst); 243 } 244 break; 245 /* dst = dst % src */ 246 case BPF_MOD: 247 if (cpu_has_mips64r6) { 248 emit(ctx, dmodu, dst, dst, src); 249 } else { 250 emit(ctx, ddivu, dst, src); 251 emit(ctx, mfhi, dst); 252 } 253 break; 254 default: 255 /* Width-generic operations */ 256 emit_alu_r(ctx, dst, src, op); 257 } 258 clobber_reg(ctx, dst); 259 } 260 261 /* Swap sub words in a register double word */ 262 static void emit_swap_r64(struct jit_context *ctx, u8 dst, u8 mask, u32 bits) 263 { 264 u8 tmp = MIPS_R_T9; 265 266 emit(ctx, and, tmp, dst, mask); /* tmp = dst & mask */ 267 emit(ctx, dsll, tmp, tmp, bits); /* tmp = tmp << bits */ 268 emit(ctx, dsrl, dst, dst, bits); /* dst = dst >> bits */ 269 emit(ctx, and, dst, dst, mask); /* dst = dst & mask */ 270 emit(ctx, or, dst, dst, tmp); /* dst = dst | tmp */ 271 } 272 273 /* Swap bytes and truncate a register double word, word or half word */ 274 static void emit_bswap_r64(struct jit_context *ctx, u8 dst, u32 width) 275 { 276 switch (width) { 277 /* Swap bytes in a double word */ 278 case 64: 279 if (cpu_has_mips64r2 || cpu_has_mips64r6) { 280 emit(ctx, dsbh, dst, dst); 281 emit(ctx, dshd, dst, dst); 282 } else { 283 u8 t1 = MIPS_R_T6; 284 u8 t2 = MIPS_R_T7; 285 286 emit(ctx, dsll32, t2, dst, 0); /* t2 = dst << 32 */ 287 emit(ctx, dsrl32, dst, dst, 0); /* dst = dst >> 32 */ 288 emit(ctx, or, dst, dst, t2); /* dst = dst | t2 */ 289 290 emit(ctx, ori, t2, MIPS_R_ZERO, 0xffff); 291 emit(ctx, dsll32, t1, t2, 0); /* t1 = t2 << 32 */ 292 emit(ctx, or, t1, t1, t2); /* t1 = t1 | t2 */ 293 emit_swap_r64(ctx, dst, t1, 16);/* dst = swap16(dst) */ 294 295 emit(ctx, lui, t2, 0xff); /* t2 = 0x00ff0000 */ 296 emit(ctx, ori, t2, t2, 0xff); /* t2 = t2 | 0x00ff */ 297 emit(ctx, dsll32, t1, t2, 0); /* t1 = t2 << 32 */ 298 emit(ctx, or, t1, t1, t2); /* t1 = t1 | t2 */ 299 emit_swap_r64(ctx, dst, t1, 8); /* dst = swap8(dst) */ 300 } 301 break; 302 /* Swap bytes in a half word */ 303 /* Swap bytes in a word */ 304 case 32: 305 case 16: 306 emit_sext(ctx, dst, dst); 307 emit_bswap_r(ctx, dst, width); 308 emit_zext(ctx, dst); 309 break; 310 } 311 clobber_reg(ctx, dst); 312 } 313 314 /* Truncate a register double word, word or half word */ 315 static void emit_trunc_r64(struct jit_context *ctx, u8 dst, u32 width) 316 { 317 switch (width) { 318 case 64: 319 break; 320 /* Zero-extend a word */ 321 case 32: 322 emit_zext(ctx, dst); 323 break; 324 /* Zero-extend a half word */ 325 case 16: 326 emit(ctx, andi, dst, dst, 0xffff); 327 break; 328 } 329 clobber_reg(ctx, dst); 330 } 331 332 /* Load operation: dst = *(size*)(src + off) */ 333 static void emit_ldx(struct jit_context *ctx, u8 dst, u8 src, s16 off, u8 size) 334 { 335 switch (size) { 336 /* Load a byte */ 337 case BPF_B: 338 emit(ctx, lbu, dst, off, src); 339 break; 340 /* Load a half word */ 341 case BPF_H: 342 emit(ctx, lhu, dst, off, src); 343 break; 344 /* Load a word */ 345 case BPF_W: 346 emit(ctx, lwu, dst, off, src); 347 break; 348 /* Load a double word */ 349 case BPF_DW: 350 emit(ctx, ld, dst, off, src); 351 break; 352 } 353 clobber_reg(ctx, dst); 354 } 355 356 /* Store operation: *(size *)(dst + off) = src */ 357 static void emit_stx(struct jit_context *ctx, u8 dst, u8 src, s16 off, u8 size) 358 { 359 switch (size) { 360 /* Store a byte */ 361 case BPF_B: 362 emit(ctx, sb, src, off, dst); 363 break; 364 /* Store a half word */ 365 case BPF_H: 366 emit(ctx, sh, src, off, dst); 367 break; 368 /* Store a word */ 369 case BPF_W: 370 emit(ctx, sw, src, off, dst); 371 break; 372 /* Store a double word */ 373 case BPF_DW: 374 emit(ctx, sd, src, off, dst); 375 break; 376 } 377 } 378 379 /* Atomic read-modify-write */ 380 static void emit_atomic_r64(struct jit_context *ctx, 381 u8 dst, u8 src, s16 off, u8 code) 382 { 383 u8 t1 = MIPS_R_T6; 384 u8 t2 = MIPS_R_T7; 385 386 LLSC_sync(ctx); 387 emit(ctx, lld, t1, off, dst); 388 switch (code) { 389 case BPF_ADD: 390 case BPF_ADD | BPF_FETCH: 391 emit(ctx, daddu, t2, t1, src); 392 break; 393 case BPF_AND: 394 case BPF_AND | BPF_FETCH: 395 emit(ctx, and, t2, t1, src); 396 break; 397 case BPF_OR: 398 case BPF_OR | BPF_FETCH: 399 emit(ctx, or, t2, t1, src); 400 break; 401 case BPF_XOR: 402 case BPF_XOR | BPF_FETCH: 403 emit(ctx, xor, t2, t1, src); 404 break; 405 case BPF_XCHG: 406 emit(ctx, move, t2, src); 407 break; 408 } 409 emit(ctx, scd, t2, off, dst); 410 emit(ctx, LLSC_beqz, t2, -16 - LLSC_offset); 411 emit(ctx, nop); /* Delay slot */ 412 413 if (code & BPF_FETCH) { 414 emit(ctx, move, src, t1); 415 clobber_reg(ctx, src); 416 } 417 } 418 419 /* Atomic compare-and-exchange */ 420 static void emit_cmpxchg_r64(struct jit_context *ctx, u8 dst, u8 src, s16 off) 421 { 422 u8 r0 = bpf2mips64[BPF_REG_0]; 423 u8 t1 = MIPS_R_T6; 424 u8 t2 = MIPS_R_T7; 425 426 LLSC_sync(ctx); 427 emit(ctx, lld, t1, off, dst); 428 emit(ctx, bne, t1, r0, 12); 429 emit(ctx, move, t2, src); /* Delay slot */ 430 emit(ctx, scd, t2, off, dst); 431 emit(ctx, LLSC_beqz, t2, -20 - LLSC_offset); 432 emit(ctx, move, r0, t1); /* Delay slot */ 433 434 clobber_reg(ctx, r0); 435 } 436 437 /* Function call */ 438 static int emit_call(struct jit_context *ctx, const struct bpf_insn *insn) 439 { 440 u8 zx = bpf2mips64[JIT_REG_ZX]; 441 u8 tmp = MIPS_R_T6; 442 bool fixed; 443 u64 addr; 444 445 /* Decode the call address */ 446 if (bpf_jit_get_func_addr(ctx->program, insn, false, 447 &addr, &fixed) < 0) 448 return -1; 449 if (!fixed) 450 return -1; 451 452 /* Push caller-saved registers on stack */ 453 push_regs(ctx, ctx->clobbered & JIT_CALLER_REGS, 0, 0); 454 455 /* Emit function call */ 456 emit_mov_i64(ctx, tmp, addr & JALR_MASK); 457 emit(ctx, jalr, MIPS_R_RA, tmp); 458 emit(ctx, nop); /* Delay slot */ 459 460 /* Restore caller-saved registers */ 461 pop_regs(ctx, ctx->clobbered & JIT_CALLER_REGS, 0, 0); 462 463 /* Re-initialize the JIT zero-extension register if accessed */ 464 if (ctx->accessed & BIT(JIT_REG_ZX)) { 465 emit(ctx, daddiu, zx, MIPS_R_ZERO, -1); 466 emit(ctx, dsrl32, zx, zx, 0); 467 } 468 469 clobber_reg(ctx, MIPS_R_RA); 470 clobber_reg(ctx, MIPS_R_V0); 471 clobber_reg(ctx, MIPS_R_V1); 472 return 0; 473 } 474 475 /* Function tail call */ 476 static int emit_tail_call(struct jit_context *ctx) 477 { 478 u8 ary = bpf2mips64[BPF_REG_2]; 479 u8 ind = bpf2mips64[BPF_REG_3]; 480 u8 tcc = bpf2mips64[JIT_REG_TC]; 481 u8 tmp = MIPS_R_T6; 482 int off; 483 484 /* 485 * Tail call: 486 * eBPF R1 - function argument (context ptr), passed in a0-a1 487 * eBPF R2 - ptr to object with array of function entry points 488 * eBPF R3 - array index of function to be called 489 */ 490 491 /* if (ind >= ary->map.max_entries) goto out */ 492 off = offsetof(struct bpf_array, map.max_entries); 493 if (off > 0x7fff) 494 return -1; 495 emit(ctx, lwu, tmp, off, ary); /* tmp = ary->map.max_entrs*/ 496 emit(ctx, sltu, tmp, ind, tmp); /* tmp = ind < t1 */ 497 emit(ctx, beqz, tmp, get_offset(ctx, 1)); /* PC += off(1) if tmp == 0*/ 498 499 /* if (--TCC < 0) goto out */ 500 emit(ctx, daddiu, tcc, tcc, -1); /* tcc-- (delay slot) */ 501 emit(ctx, bltz, tcc, get_offset(ctx, 1)); /* PC += off(1) if tcc < 0 */ 502 /* (next insn delay slot) */ 503 /* prog = ary->ptrs[ind] */ 504 off = offsetof(struct bpf_array, ptrs); 505 if (off > 0x7fff) 506 return -1; 507 emit(ctx, dsll, tmp, ind, 3); /* tmp = ind << 3 */ 508 emit(ctx, daddu, tmp, tmp, ary); /* tmp += ary */ 509 emit(ctx, ld, tmp, off, tmp); /* tmp = *(tmp + off) */ 510 511 /* if (prog == 0) goto out */ 512 emit(ctx, beqz, tmp, get_offset(ctx, 1)); /* PC += off(1) if tmp == 0*/ 513 emit(ctx, nop); /* Delay slot */ 514 515 /* func = prog->bpf_func + 8 (prologue skip offset) */ 516 off = offsetof(struct bpf_prog, bpf_func); 517 if (off > 0x7fff) 518 return -1; 519 emit(ctx, ld, tmp, off, tmp); /* tmp = *(tmp + off) */ 520 emit(ctx, daddiu, tmp, tmp, JIT_TCALL_SKIP); /* tmp += skip (4) */ 521 522 /* goto func */ 523 build_epilogue(ctx, tmp); 524 access_reg(ctx, JIT_REG_TC); 525 return 0; 526 } 527 528 /* 529 * Stack frame layout for a JITed program (stack grows down). 530 * 531 * Higher address : Previous stack frame : 532 * +===========================+ <--- MIPS sp before call 533 * | Callee-saved registers, | 534 * | including RA and FP | 535 * +---------------------------+ <--- eBPF FP (MIPS fp) 536 * | Local eBPF variables | 537 * | allocated by program | 538 * +---------------------------+ 539 * | Reserved for caller-saved | 540 * | registers | 541 * Lower address +===========================+ <--- MIPS sp 542 */ 543 544 /* Build program prologue to set up the stack and registers */ 545 void build_prologue(struct jit_context *ctx) 546 { 547 u8 fp = bpf2mips64[BPF_REG_FP]; 548 u8 tc = bpf2mips64[JIT_REG_TC]; 549 u8 zx = bpf2mips64[JIT_REG_ZX]; 550 int stack, saved, locals, reserved; 551 552 /* 553 * In the unlikely event that the TCC limit is raised to more 554 * than 16 bits, it is clamped to the maximum value allowed for 555 * the generated code (0xffff). It is better fail to compile 556 * instead of degrading gracefully. 557 */ 558 BUILD_BUG_ON(MAX_TAIL_CALL_CNT > 0xffff); 559 560 /* 561 * The first instruction initializes the tail call count register. 562 * On a tail call, the calling function jumps into the prologue 563 * after this instruction. 564 */ 565 emit(ctx, ori, tc, MIPS_R_ZERO, MAX_TAIL_CALL_CNT); 566 567 /* === Entry-point for tail calls === */ 568 569 /* 570 * If the eBPF frame pointer and tail call count registers were 571 * accessed they must be preserved. Mark them as clobbered here 572 * to save and restore them on the stack as needed. 573 */ 574 if (ctx->accessed & BIT(BPF_REG_FP)) 575 clobber_reg(ctx, fp); 576 if (ctx->accessed & BIT(JIT_REG_TC)) 577 clobber_reg(ctx, tc); 578 if (ctx->accessed & BIT(JIT_REG_ZX)) 579 clobber_reg(ctx, zx); 580 581 /* Compute the stack space needed for callee-saved registers */ 582 saved = hweight32(ctx->clobbered & JIT_CALLEE_REGS) * sizeof(u64); 583 saved = ALIGN(saved, MIPS_STACK_ALIGNMENT); 584 585 /* Stack space used by eBPF program local data */ 586 locals = ALIGN(ctx->program->aux->stack_depth, MIPS_STACK_ALIGNMENT); 587 588 /* 589 * If we are emitting function calls, reserve extra stack space for 590 * caller-saved registers needed by the JIT. The required space is 591 * computed automatically during resource usage discovery (pass 1). 592 */ 593 reserved = ctx->stack_used; 594 595 /* Allocate the stack frame */ 596 stack = ALIGN(saved + locals + reserved, MIPS_STACK_ALIGNMENT); 597 if (stack) 598 emit(ctx, daddiu, MIPS_R_SP, MIPS_R_SP, -stack); 599 600 /* Store callee-saved registers on stack */ 601 push_regs(ctx, ctx->clobbered & JIT_CALLEE_REGS, 0, stack - saved); 602 603 /* Initialize the eBPF frame pointer if accessed */ 604 if (ctx->accessed & BIT(BPF_REG_FP)) 605 emit(ctx, daddiu, fp, MIPS_R_SP, stack - saved); 606 607 /* Initialize the ePF JIT zero-extension register if accessed */ 608 if (ctx->accessed & BIT(JIT_REG_ZX)) { 609 emit(ctx, daddiu, zx, MIPS_R_ZERO, -1); 610 emit(ctx, dsrl32, zx, zx, 0); 611 } 612 613 ctx->saved_size = saved; 614 ctx->stack_size = stack; 615 } 616 617 /* Build the program epilogue to restore the stack and registers */ 618 void build_epilogue(struct jit_context *ctx, int dest_reg) 619 { 620 /* Restore callee-saved registers from stack */ 621 pop_regs(ctx, ctx->clobbered & JIT_CALLEE_REGS, 0, 622 ctx->stack_size - ctx->saved_size); 623 624 /* Release the stack frame */ 625 if (ctx->stack_size) 626 emit(ctx, daddiu, MIPS_R_SP, MIPS_R_SP, ctx->stack_size); 627 628 /* Jump to return address and sign-extend the 32-bit return value */ 629 emit(ctx, jr, dest_reg); 630 emit(ctx, sll, MIPS_R_V0, MIPS_R_V0, 0); /* Delay slot */ 631 } 632 633 /* Build one eBPF instruction */ 634 int build_insn(const struct bpf_insn *insn, struct jit_context *ctx) 635 { 636 u8 dst = bpf2mips64[insn->dst_reg]; 637 u8 src = bpf2mips64[insn->src_reg]; 638 u8 res = bpf2mips64[BPF_REG_0]; 639 u8 code = insn->code; 640 s16 off = insn->off; 641 s32 imm = insn->imm; 642 s32 val, rel; 643 u8 alu, jmp; 644 645 switch (code) { 646 /* ALU operations */ 647 /* dst = imm */ 648 case BPF_ALU | BPF_MOV | BPF_K: 649 emit_mov_i(ctx, dst, imm); 650 emit_zext_ver(ctx, dst); 651 break; 652 /* dst = src */ 653 case BPF_ALU | BPF_MOV | BPF_X: 654 if (imm == 1) { 655 /* Special mov32 for zext */ 656 emit_zext(ctx, dst); 657 } else { 658 emit_mov_r(ctx, dst, src); 659 emit_zext_ver(ctx, dst); 660 } 661 break; 662 /* dst = -dst */ 663 case BPF_ALU | BPF_NEG: 664 emit_sext(ctx, dst, dst); 665 emit_alu_i(ctx, dst, 0, BPF_NEG); 666 emit_zext_ver(ctx, dst); 667 break; 668 /* dst = dst & imm */ 669 /* dst = dst | imm */ 670 /* dst = dst ^ imm */ 671 /* dst = dst << imm */ 672 case BPF_ALU | BPF_OR | BPF_K: 673 case BPF_ALU | BPF_AND | BPF_K: 674 case BPF_ALU | BPF_XOR | BPF_K: 675 case BPF_ALU | BPF_LSH | BPF_K: 676 if (!valid_alu_i(BPF_OP(code), imm)) { 677 emit_mov_i(ctx, MIPS_R_T4, imm); 678 emit_alu_r(ctx, dst, MIPS_R_T4, BPF_OP(code)); 679 } else if (rewrite_alu_i(BPF_OP(code), imm, &alu, &val)) { 680 emit_alu_i(ctx, dst, val, alu); 681 } 682 emit_zext_ver(ctx, dst); 683 break; 684 /* dst = dst >> imm */ 685 /* dst = dst >> imm (arithmetic) */ 686 /* dst = dst + imm */ 687 /* dst = dst - imm */ 688 /* dst = dst * imm */ 689 /* dst = dst / imm */ 690 /* dst = dst % imm */ 691 case BPF_ALU | BPF_RSH | BPF_K: 692 case BPF_ALU | BPF_ARSH | BPF_K: 693 case BPF_ALU | BPF_ADD | BPF_K: 694 case BPF_ALU | BPF_SUB | BPF_K: 695 case BPF_ALU | BPF_MUL | BPF_K: 696 case BPF_ALU | BPF_DIV | BPF_K: 697 case BPF_ALU | BPF_MOD | BPF_K: 698 if (!valid_alu_i(BPF_OP(code), imm)) { 699 emit_sext(ctx, dst, dst); 700 emit_mov_i(ctx, MIPS_R_T4, imm); 701 emit_alu_r(ctx, dst, MIPS_R_T4, BPF_OP(code)); 702 } else if (rewrite_alu_i(BPF_OP(code), imm, &alu, &val)) { 703 emit_sext(ctx, dst, dst); 704 emit_alu_i(ctx, dst, val, alu); 705 } 706 emit_zext_ver(ctx, dst); 707 break; 708 /* dst = dst & src */ 709 /* dst = dst | src */ 710 /* dst = dst ^ src */ 711 /* dst = dst << src */ 712 case BPF_ALU | BPF_AND | BPF_X: 713 case BPF_ALU | BPF_OR | BPF_X: 714 case BPF_ALU | BPF_XOR | BPF_X: 715 case BPF_ALU | BPF_LSH | BPF_X: 716 emit_alu_r(ctx, dst, src, BPF_OP(code)); 717 emit_zext_ver(ctx, dst); 718 break; 719 /* dst = dst >> src */ 720 /* dst = dst >> src (arithmetic) */ 721 /* dst = dst + src */ 722 /* dst = dst - src */ 723 /* dst = dst * src */ 724 /* dst = dst / src */ 725 /* dst = dst % src */ 726 case BPF_ALU | BPF_RSH | BPF_X: 727 case BPF_ALU | BPF_ARSH | BPF_X: 728 case BPF_ALU | BPF_ADD | BPF_X: 729 case BPF_ALU | BPF_SUB | BPF_X: 730 case BPF_ALU | BPF_MUL | BPF_X: 731 case BPF_ALU | BPF_DIV | BPF_X: 732 case BPF_ALU | BPF_MOD | BPF_X: 733 emit_sext(ctx, dst, dst); 734 emit_sext(ctx, MIPS_R_T4, src); 735 emit_alu_r(ctx, dst, MIPS_R_T4, BPF_OP(code)); 736 emit_zext_ver(ctx, dst); 737 break; 738 /* dst = imm (64-bit) */ 739 case BPF_ALU64 | BPF_MOV | BPF_K: 740 emit_mov_i(ctx, dst, imm); 741 break; 742 /* dst = src (64-bit) */ 743 case BPF_ALU64 | BPF_MOV | BPF_X: 744 emit_mov_r(ctx, dst, src); 745 break; 746 /* dst = -dst (64-bit) */ 747 case BPF_ALU64 | BPF_NEG: 748 emit_alu_i64(ctx, dst, 0, BPF_NEG); 749 break; 750 /* dst = dst & imm (64-bit) */ 751 /* dst = dst | imm (64-bit) */ 752 /* dst = dst ^ imm (64-bit) */ 753 /* dst = dst << imm (64-bit) */ 754 /* dst = dst >> imm (64-bit) */ 755 /* dst = dst >> imm ((64-bit, arithmetic) */ 756 /* dst = dst + imm (64-bit) */ 757 /* dst = dst - imm (64-bit) */ 758 /* dst = dst * imm (64-bit) */ 759 /* dst = dst / imm (64-bit) */ 760 /* dst = dst % imm (64-bit) */ 761 case BPF_ALU64 | BPF_AND | BPF_K: 762 case BPF_ALU64 | BPF_OR | BPF_K: 763 case BPF_ALU64 | BPF_XOR | BPF_K: 764 case BPF_ALU64 | BPF_LSH | BPF_K: 765 case BPF_ALU64 | BPF_RSH | BPF_K: 766 case BPF_ALU64 | BPF_ARSH | BPF_K: 767 case BPF_ALU64 | BPF_ADD | BPF_K: 768 case BPF_ALU64 | BPF_SUB | BPF_K: 769 case BPF_ALU64 | BPF_MUL | BPF_K: 770 case BPF_ALU64 | BPF_DIV | BPF_K: 771 case BPF_ALU64 | BPF_MOD | BPF_K: 772 if (!valid_alu_i(BPF_OP(code), imm)) { 773 emit_mov_i(ctx, MIPS_R_T4, imm); 774 emit_alu_r64(ctx, dst, MIPS_R_T4, BPF_OP(code)); 775 } else if (rewrite_alu_i(BPF_OP(code), imm, &alu, &val)) { 776 emit_alu_i64(ctx, dst, val, alu); 777 } 778 break; 779 /* dst = dst & src (64-bit) */ 780 /* dst = dst | src (64-bit) */ 781 /* dst = dst ^ src (64-bit) */ 782 /* dst = dst << src (64-bit) */ 783 /* dst = dst >> src (64-bit) */ 784 /* dst = dst >> src (64-bit, arithmetic) */ 785 /* dst = dst + src (64-bit) */ 786 /* dst = dst - src (64-bit) */ 787 /* dst = dst * src (64-bit) */ 788 /* dst = dst / src (64-bit) */ 789 /* dst = dst % src (64-bit) */ 790 case BPF_ALU64 | BPF_AND | BPF_X: 791 case BPF_ALU64 | BPF_OR | BPF_X: 792 case BPF_ALU64 | BPF_XOR | BPF_X: 793 case BPF_ALU64 | BPF_LSH | BPF_X: 794 case BPF_ALU64 | BPF_RSH | BPF_X: 795 case BPF_ALU64 | BPF_ARSH | BPF_X: 796 case BPF_ALU64 | BPF_ADD | BPF_X: 797 case BPF_ALU64 | BPF_SUB | BPF_X: 798 case BPF_ALU64 | BPF_MUL | BPF_X: 799 case BPF_ALU64 | BPF_DIV | BPF_X: 800 case BPF_ALU64 | BPF_MOD | BPF_X: 801 emit_alu_r64(ctx, dst, src, BPF_OP(code)); 802 break; 803 /* dst = htole(dst) */ 804 /* dst = htobe(dst) */ 805 case BPF_ALU | BPF_END | BPF_FROM_LE: 806 case BPF_ALU | BPF_END | BPF_FROM_BE: 807 if (BPF_SRC(code) == 808 #ifdef __BIG_ENDIAN 809 BPF_FROM_LE 810 #else 811 BPF_FROM_BE 812 #endif 813 ) 814 emit_bswap_r64(ctx, dst, imm); 815 else 816 emit_trunc_r64(ctx, dst, imm); 817 break; 818 /* dst = imm64 */ 819 case BPF_LD | BPF_IMM | BPF_DW: 820 emit_mov_i64(ctx, dst, (u32)imm | ((u64)insn[1].imm << 32)); 821 return 1; 822 /* LDX: dst = *(size *)(src + off) */ 823 case BPF_LDX | BPF_MEM | BPF_W: 824 case BPF_LDX | BPF_MEM | BPF_H: 825 case BPF_LDX | BPF_MEM | BPF_B: 826 case BPF_LDX | BPF_MEM | BPF_DW: 827 emit_ldx(ctx, dst, src, off, BPF_SIZE(code)); 828 break; 829 /* ST: *(size *)(dst + off) = imm */ 830 case BPF_ST | BPF_MEM | BPF_W: 831 case BPF_ST | BPF_MEM | BPF_H: 832 case BPF_ST | BPF_MEM | BPF_B: 833 case BPF_ST | BPF_MEM | BPF_DW: 834 emit_mov_i(ctx, MIPS_R_T4, imm); 835 emit_stx(ctx, dst, MIPS_R_T4, off, BPF_SIZE(code)); 836 break; 837 /* STX: *(size *)(dst + off) = src */ 838 case BPF_STX | BPF_MEM | BPF_W: 839 case BPF_STX | BPF_MEM | BPF_H: 840 case BPF_STX | BPF_MEM | BPF_B: 841 case BPF_STX | BPF_MEM | BPF_DW: 842 emit_stx(ctx, dst, src, off, BPF_SIZE(code)); 843 break; 844 /* Speculation barrier */ 845 case BPF_ST | BPF_NOSPEC: 846 break; 847 /* Atomics */ 848 case BPF_STX | BPF_ATOMIC | BPF_W: 849 case BPF_STX | BPF_ATOMIC | BPF_DW: 850 switch (imm) { 851 case BPF_ADD: 852 case BPF_ADD | BPF_FETCH: 853 case BPF_AND: 854 case BPF_AND | BPF_FETCH: 855 case BPF_OR: 856 case BPF_OR | BPF_FETCH: 857 case BPF_XOR: 858 case BPF_XOR | BPF_FETCH: 859 case BPF_XCHG: 860 if (BPF_SIZE(code) == BPF_DW) { 861 emit_atomic_r64(ctx, dst, src, off, imm); 862 } else if (imm & BPF_FETCH) { 863 u8 tmp = dst; 864 865 if (src == dst) { /* Don't overwrite dst */ 866 emit_mov_r(ctx, MIPS_R_T4, dst); 867 tmp = MIPS_R_T4; 868 } 869 emit_sext(ctx, src, src); 870 emit_atomic_r(ctx, tmp, src, off, imm); 871 emit_zext_ver(ctx, src); 872 } else { /* 32-bit, no fetch */ 873 emit_sext(ctx, MIPS_R_T4, src); 874 emit_atomic_r(ctx, dst, MIPS_R_T4, off, imm); 875 } 876 break; 877 case BPF_CMPXCHG: 878 if (BPF_SIZE(code) == BPF_DW) { 879 emit_cmpxchg_r64(ctx, dst, src, off); 880 } else { 881 u8 tmp = res; 882 883 if (res == dst) /* Don't overwrite dst */ 884 tmp = MIPS_R_T4; 885 emit_sext(ctx, tmp, res); 886 emit_sext(ctx, MIPS_R_T5, src); 887 emit_cmpxchg_r(ctx, dst, MIPS_R_T5, tmp, off); 888 if (res == dst) /* Restore result */ 889 emit_mov_r(ctx, res, MIPS_R_T4); 890 /* Result zext inserted by verifier */ 891 } 892 break; 893 default: 894 goto notyet; 895 } 896 break; 897 /* PC += off if dst == src */ 898 /* PC += off if dst != src */ 899 /* PC += off if dst & src */ 900 /* PC += off if dst > src */ 901 /* PC += off if dst >= src */ 902 /* PC += off if dst < src */ 903 /* PC += off if dst <= src */ 904 /* PC += off if dst > src (signed) */ 905 /* PC += off if dst >= src (signed) */ 906 /* PC += off if dst < src (signed) */ 907 /* PC += off if dst <= src (signed) */ 908 case BPF_JMP32 | BPF_JEQ | BPF_X: 909 case BPF_JMP32 | BPF_JNE | BPF_X: 910 case BPF_JMP32 | BPF_JSET | BPF_X: 911 case BPF_JMP32 | BPF_JGT | BPF_X: 912 case BPF_JMP32 | BPF_JGE | BPF_X: 913 case BPF_JMP32 | BPF_JLT | BPF_X: 914 case BPF_JMP32 | BPF_JLE | BPF_X: 915 case BPF_JMP32 | BPF_JSGT | BPF_X: 916 case BPF_JMP32 | BPF_JSGE | BPF_X: 917 case BPF_JMP32 | BPF_JSLT | BPF_X: 918 case BPF_JMP32 | BPF_JSLE | BPF_X: 919 if (off == 0) 920 break; 921 setup_jmp_r(ctx, dst == src, BPF_OP(code), off, &jmp, &rel); 922 emit_sext(ctx, MIPS_R_T4, dst); /* Sign-extended dst */ 923 emit_sext(ctx, MIPS_R_T5, src); /* Sign-extended src */ 924 emit_jmp_r(ctx, MIPS_R_T4, MIPS_R_T5, rel, jmp); 925 if (finish_jmp(ctx, jmp, off) < 0) 926 goto toofar; 927 break; 928 /* PC += off if dst == imm */ 929 /* PC += off if dst != imm */ 930 /* PC += off if dst & imm */ 931 /* PC += off if dst > imm */ 932 /* PC += off if dst >= imm */ 933 /* PC += off if dst < imm */ 934 /* PC += off if dst <= imm */ 935 /* PC += off if dst > imm (signed) */ 936 /* PC += off if dst >= imm (signed) */ 937 /* PC += off if dst < imm (signed) */ 938 /* PC += off if dst <= imm (signed) */ 939 case BPF_JMP32 | BPF_JEQ | BPF_K: 940 case BPF_JMP32 | BPF_JNE | BPF_K: 941 case BPF_JMP32 | BPF_JSET | BPF_K: 942 case BPF_JMP32 | BPF_JGT | BPF_K: 943 case BPF_JMP32 | BPF_JGE | BPF_K: 944 case BPF_JMP32 | BPF_JLT | BPF_K: 945 case BPF_JMP32 | BPF_JLE | BPF_K: 946 case BPF_JMP32 | BPF_JSGT | BPF_K: 947 case BPF_JMP32 | BPF_JSGE | BPF_K: 948 case BPF_JMP32 | BPF_JSLT | BPF_K: 949 case BPF_JMP32 | BPF_JSLE | BPF_K: 950 if (off == 0) 951 break; 952 setup_jmp_i(ctx, imm, 32, BPF_OP(code), off, &jmp, &rel); 953 emit_sext(ctx, MIPS_R_T4, dst); /* Sign-extended dst */ 954 if (valid_jmp_i(jmp, imm)) { 955 emit_jmp_i(ctx, MIPS_R_T4, imm, rel, jmp); 956 } else { 957 /* Move large immediate to register, sign-extended */ 958 emit_mov_i(ctx, MIPS_R_T5, imm); 959 emit_jmp_r(ctx, MIPS_R_T4, MIPS_R_T5, rel, jmp); 960 } 961 if (finish_jmp(ctx, jmp, off) < 0) 962 goto toofar; 963 break; 964 /* PC += off if dst == src */ 965 /* PC += off if dst != src */ 966 /* PC += off if dst & src */ 967 /* PC += off if dst > src */ 968 /* PC += off if dst >= src */ 969 /* PC += off if dst < src */ 970 /* PC += off if dst <= src */ 971 /* PC += off if dst > src (signed) */ 972 /* PC += off if dst >= src (signed) */ 973 /* PC += off if dst < src (signed) */ 974 /* PC += off if dst <= src (signed) */ 975 case BPF_JMP | BPF_JEQ | BPF_X: 976 case BPF_JMP | BPF_JNE | BPF_X: 977 case BPF_JMP | BPF_JSET | BPF_X: 978 case BPF_JMP | BPF_JGT | BPF_X: 979 case BPF_JMP | BPF_JGE | BPF_X: 980 case BPF_JMP | BPF_JLT | BPF_X: 981 case BPF_JMP | BPF_JLE | BPF_X: 982 case BPF_JMP | BPF_JSGT | BPF_X: 983 case BPF_JMP | BPF_JSGE | BPF_X: 984 case BPF_JMP | BPF_JSLT | BPF_X: 985 case BPF_JMP | BPF_JSLE | BPF_X: 986 if (off == 0) 987 break; 988 setup_jmp_r(ctx, dst == src, BPF_OP(code), off, &jmp, &rel); 989 emit_jmp_r(ctx, dst, src, rel, jmp); 990 if (finish_jmp(ctx, jmp, off) < 0) 991 goto toofar; 992 break; 993 /* PC += off if dst == imm */ 994 /* PC += off if dst != imm */ 995 /* PC += off if dst & imm */ 996 /* PC += off if dst > imm */ 997 /* PC += off if dst >= imm */ 998 /* PC += off if dst < imm */ 999 /* PC += off if dst <= imm */ 1000 /* PC += off if dst > imm (signed) */ 1001 /* PC += off if dst >= imm (signed) */ 1002 /* PC += off if dst < imm (signed) */ 1003 /* PC += off if dst <= imm (signed) */ 1004 case BPF_JMP | BPF_JEQ | BPF_K: 1005 case BPF_JMP | BPF_JNE | BPF_K: 1006 case BPF_JMP | BPF_JSET | BPF_K: 1007 case BPF_JMP | BPF_JGT | BPF_K: 1008 case BPF_JMP | BPF_JGE | BPF_K: 1009 case BPF_JMP | BPF_JLT | BPF_K: 1010 case BPF_JMP | BPF_JLE | BPF_K: 1011 case BPF_JMP | BPF_JSGT | BPF_K: 1012 case BPF_JMP | BPF_JSGE | BPF_K: 1013 case BPF_JMP | BPF_JSLT | BPF_K: 1014 case BPF_JMP | BPF_JSLE | BPF_K: 1015 if (off == 0) 1016 break; 1017 setup_jmp_i(ctx, imm, 64, BPF_OP(code), off, &jmp, &rel); 1018 if (valid_jmp_i(jmp, imm)) { 1019 emit_jmp_i(ctx, dst, imm, rel, jmp); 1020 } else { 1021 /* Move large immediate to register */ 1022 emit_mov_i(ctx, MIPS_R_T4, imm); 1023 emit_jmp_r(ctx, dst, MIPS_R_T4, rel, jmp); 1024 } 1025 if (finish_jmp(ctx, jmp, off) < 0) 1026 goto toofar; 1027 break; 1028 /* PC += off */ 1029 case BPF_JMP | BPF_JA: 1030 if (off == 0) 1031 break; 1032 if (emit_ja(ctx, off) < 0) 1033 goto toofar; 1034 break; 1035 /* Tail call */ 1036 case BPF_JMP | BPF_TAIL_CALL: 1037 if (emit_tail_call(ctx) < 0) 1038 goto invalid; 1039 break; 1040 /* Function call */ 1041 case BPF_JMP | BPF_CALL: 1042 if (emit_call(ctx, insn) < 0) 1043 goto invalid; 1044 break; 1045 /* Function return */ 1046 case BPF_JMP | BPF_EXIT: 1047 /* 1048 * Optimization: when last instruction is EXIT 1049 * simply continue to epilogue. 1050 */ 1051 if (ctx->bpf_index == ctx->program->len - 1) 1052 break; 1053 if (emit_exit(ctx) < 0) 1054 goto toofar; 1055 break; 1056 1057 default: 1058 invalid: 1059 pr_err_once("unknown opcode %02x\n", code); 1060 return -EINVAL; 1061 notyet: 1062 pr_info_once("*** NOT YET: opcode %02x ***\n", code); 1063 return -EFAULT; 1064 toofar: 1065 pr_info_once("*** TOO FAR: jump at %u opcode %02x ***\n", 1066 ctx->bpf_index, code); 1067 return -E2BIG; 1068 } 1069 return 0; 1070 } 1071