1 /* 2 * Carsten Langgaard, carstenl@mips.com 3 * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved. 4 * 5 * This program is free software; you can distribute it and/or modify it 6 * under the terms of the GNU General Public License (Version 2) as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 12 * for more details. 13 * 14 * You should have received a copy of the GNU General Public License along 15 * with this program; if not, write to the Free Software Foundation, Inc., 16 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. 17 * 18 * Setting up the clock on the MIPS boards. 19 */ 20 #include <linux/types.h> 21 #include <linux/i8253.h> 22 #include <linux/init.h> 23 #include <linux/kernel_stat.h> 24 #include <linux/sched.h> 25 #include <linux/spinlock.h> 26 #include <linux/interrupt.h> 27 #include <linux/irqchip/mips-gic.h> 28 #include <linux/timex.h> 29 #include <linux/mc146818rtc.h> 30 31 #include <asm/cpu.h> 32 #include <asm/mipsregs.h> 33 #include <asm/mipsmtregs.h> 34 #include <asm/hardirq.h> 35 #include <asm/irq.h> 36 #include <asm/div64.h> 37 #include <asm/setup.h> 38 #include <asm/time.h> 39 #include <asm/mc146818-time.h> 40 #include <asm/msc01_ic.h> 41 42 #include <asm/mips-boards/generic.h> 43 #include <asm/mips-boards/maltaint.h> 44 45 static int mips_cpu_timer_irq; 46 static int mips_cpu_perf_irq; 47 extern int cp0_perfcount_irq; 48 49 static unsigned int gic_frequency; 50 51 static void mips_timer_dispatch(void) 52 { 53 do_IRQ(mips_cpu_timer_irq); 54 } 55 56 static void mips_perf_dispatch(void) 57 { 58 do_IRQ(mips_cpu_perf_irq); 59 } 60 61 static unsigned int freqround(unsigned int freq, unsigned int amount) 62 { 63 freq += amount; 64 freq -= freq % (amount*2); 65 return freq; 66 } 67 68 /* 69 * Estimate CPU and GIC frequencies. 70 */ 71 static void __init estimate_frequencies(void) 72 { 73 unsigned long flags; 74 unsigned int count, start; 75 cycle_t giccount = 0, gicstart = 0; 76 77 #if defined(CONFIG_KVM_GUEST) && CONFIG_KVM_GUEST_TIMER_FREQ 78 mips_hpt_frequency = CONFIG_KVM_GUEST_TIMER_FREQ * 1000000; 79 return; 80 #endif 81 82 local_irq_save(flags); 83 84 /* Start counter exactly on falling edge of update flag. */ 85 while (CMOS_READ(RTC_REG_A) & RTC_UIP); 86 while (!(CMOS_READ(RTC_REG_A) & RTC_UIP)); 87 88 /* Initialize counters. */ 89 start = read_c0_count(); 90 if (gic_present) 91 gicstart = gic_read_count(); 92 93 /* Read counter exactly on falling edge of update flag. */ 94 while (CMOS_READ(RTC_REG_A) & RTC_UIP); 95 while (!(CMOS_READ(RTC_REG_A) & RTC_UIP)); 96 97 count = read_c0_count(); 98 if (gic_present) 99 giccount = gic_read_count(); 100 101 local_irq_restore(flags); 102 103 count -= start; 104 mips_hpt_frequency = count; 105 106 if (gic_present) { 107 giccount -= gicstart; 108 gic_frequency = giccount; 109 } 110 } 111 112 void read_persistent_clock(struct timespec *ts) 113 { 114 ts->tv_sec = mc146818_get_cmos_time(); 115 ts->tv_nsec = 0; 116 } 117 118 int get_c0_perfcount_int(void) 119 { 120 if (cpu_has_veic) { 121 set_vi_handler(MSC01E_INT_PERFCTR, mips_perf_dispatch); 122 mips_cpu_perf_irq = MSC01E_INT_BASE + MSC01E_INT_PERFCTR; 123 } else if (gic_present) { 124 mips_cpu_perf_irq = gic_get_c0_perfcount_int(); 125 } else if (cp0_perfcount_irq >= 0) { 126 mips_cpu_perf_irq = MIPS_CPU_IRQ_BASE + cp0_perfcount_irq; 127 } else { 128 mips_cpu_perf_irq = -1; 129 } 130 131 return mips_cpu_perf_irq; 132 } 133 134 unsigned int get_c0_compare_int(void) 135 { 136 if (cpu_has_veic) { 137 set_vi_handler(MSC01E_INT_CPUCTR, mips_timer_dispatch); 138 mips_cpu_timer_irq = MSC01E_INT_BASE + MSC01E_INT_CPUCTR; 139 } else if (gic_present) { 140 mips_cpu_timer_irq = gic_get_c0_compare_int(); 141 } else { 142 mips_cpu_timer_irq = MIPS_CPU_IRQ_BASE + cp0_compare_irq; 143 } 144 145 return mips_cpu_timer_irq; 146 } 147 148 static void __init init_rtc(void) 149 { 150 /* stop the clock whilst setting it up */ 151 CMOS_WRITE(RTC_SET | RTC_24H, RTC_CONTROL); 152 153 /* 32KHz time base */ 154 CMOS_WRITE(RTC_REF_CLCK_32KHZ, RTC_FREQ_SELECT); 155 156 /* start the clock */ 157 CMOS_WRITE(RTC_24H, RTC_CONTROL); 158 } 159 160 void __init plat_time_init(void) 161 { 162 unsigned int prid = read_c0_prid() & (PRID_COMP_MASK | PRID_IMP_MASK); 163 unsigned int freq; 164 165 init_rtc(); 166 estimate_frequencies(); 167 168 freq = mips_hpt_frequency; 169 if ((prid != (PRID_COMP_MIPS | PRID_IMP_20KC)) && 170 (prid != (PRID_COMP_MIPS | PRID_IMP_25KF))) 171 freq *= 2; 172 freq = freqround(freq, 5000); 173 printk("CPU frequency %d.%02d MHz\n", freq/1000000, 174 (freq%1000000)*100/1000000); 175 176 mips_scroll_message(); 177 178 #ifdef CONFIG_I8253 179 /* Only Malta has a PIT. */ 180 setup_pit_timer(); 181 #endif 182 183 #ifdef CONFIG_MIPS_GIC 184 if (gic_present) { 185 freq = freqround(gic_frequency, 5000); 186 printk("GIC frequency %d.%02d MHz\n", freq/1000000, 187 (freq%1000000)*100/1000000); 188 #ifdef CONFIG_CLKSRC_MIPS_GIC 189 gic_clocksource_init(gic_frequency); 190 #endif 191 } 192 #endif 193 } 194