xref: /linux/arch/mips/mti-malta/malta-time.c (revision 905e46acd3272d04566fec49afbd7ad9e2ed9ae3)
1 /*
2  * Carsten Langgaard, carstenl@mips.com
3  * Copyright (C) 1999,2000 MIPS Technologies, Inc.  All rights reserved.
4  *
5  *  This program is free software; you can distribute it and/or modify it
6  *  under the terms of the GNU General Public License (Version 2) as
7  *  published by the Free Software Foundation.
8  *
9  *  This program is distributed in the hope it will be useful, but WITHOUT
10  *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11  *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
12  *  for more details.
13  *
14  *  You should have received a copy of the GNU General Public License along
15  *  with this program; if not, write to the Free Software Foundation, Inc.,
16  *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
17  *
18  * Setting up the clock on the MIPS boards.
19  */
20 #include <linux/types.h>
21 #include <linux/i8253.h>
22 #include <linux/init.h>
23 #include <linux/kernel_stat.h>
24 #include <linux/libfdt.h>
25 #include <linux/math64.h>
26 #include <linux/sched.h>
27 #include <linux/spinlock.h>
28 #include <linux/interrupt.h>
29 #include <linux/irqchip/mips-gic.h>
30 #include <linux/timex.h>
31 #include <linux/mc146818rtc.h>
32 
33 #include <asm/cpu.h>
34 #include <asm/mipsregs.h>
35 #include <asm/mipsmtregs.h>
36 #include <asm/hardirq.h>
37 #include <asm/irq.h>
38 #include <asm/div64.h>
39 #include <asm/setup.h>
40 #include <asm/time.h>
41 #include <asm/mc146818-time.h>
42 #include <asm/msc01_ic.h>
43 
44 #include <asm/mips-boards/generic.h>
45 #include <asm/mips-boards/maltaint.h>
46 
47 static int mips_cpu_timer_irq;
48 static int mips_cpu_perf_irq;
49 extern int cp0_perfcount_irq;
50 
51 static unsigned int gic_frequency;
52 
53 static void mips_timer_dispatch(void)
54 {
55 	do_IRQ(mips_cpu_timer_irq);
56 }
57 
58 static void mips_perf_dispatch(void)
59 {
60 	do_IRQ(mips_cpu_perf_irq);
61 }
62 
63 static unsigned int freqround(unsigned int freq, unsigned int amount)
64 {
65 	freq += amount;
66 	freq -= freq % (amount*2);
67 	return freq;
68 }
69 
70 /*
71  * Estimate CPU and GIC frequencies.
72  */
73 static void __init estimate_frequencies(void)
74 {
75 	unsigned long flags;
76 	unsigned int count, start;
77 	unsigned char secs1, secs2, ctrl;
78 	int secs;
79 	u64 giccount = 0, gicstart = 0;
80 
81 #if defined(CONFIG_KVM_GUEST) && CONFIG_KVM_GUEST_TIMER_FREQ
82 	mips_hpt_frequency = CONFIG_KVM_GUEST_TIMER_FREQ * 1000000;
83 	return;
84 #endif
85 
86 	local_irq_save(flags);
87 
88 	if (gic_present)
89 		gic_start_count();
90 
91 	/*
92 	 * Read counters exactly on rising edge of update flag.
93 	 * This helps get an accurate reading under virtualisation.
94 	 */
95 	while (CMOS_READ(RTC_REG_A) & RTC_UIP);
96 	while (!(CMOS_READ(RTC_REG_A) & RTC_UIP));
97 	start = read_c0_count();
98 	if (gic_present)
99 		gicstart = gic_read_count();
100 
101 	/* Wait for falling edge before reading RTC. */
102 	while (CMOS_READ(RTC_REG_A) & RTC_UIP);
103 	secs1 = CMOS_READ(RTC_SECONDS);
104 
105 	/* Read counters again exactly on rising edge of update flag. */
106 	while (!(CMOS_READ(RTC_REG_A) & RTC_UIP));
107 	count = read_c0_count();
108 	if (gic_present)
109 		giccount = gic_read_count();
110 
111 	/* Wait for falling edge before reading RTC again. */
112 	while (CMOS_READ(RTC_REG_A) & RTC_UIP);
113 	secs2 = CMOS_READ(RTC_SECONDS);
114 
115 	ctrl = CMOS_READ(RTC_CONTROL);
116 
117 	local_irq_restore(flags);
118 
119 	if (!(ctrl & RTC_DM_BINARY) || RTC_ALWAYS_BCD) {
120 		secs1 = bcd2bin(secs1);
121 		secs2 = bcd2bin(secs2);
122 	}
123 	secs = secs2 - secs1;
124 	if (secs < 1)
125 		secs += 60;
126 
127 	count -= start;
128 	count /= secs;
129 	mips_hpt_frequency = count;
130 
131 	if (gic_present) {
132 		giccount = div_u64(giccount - gicstart, secs);
133 		gic_frequency = giccount;
134 	}
135 }
136 
137 void read_persistent_clock(struct timespec *ts)
138 {
139 	ts->tv_sec = mc146818_get_cmos_time();
140 	ts->tv_nsec = 0;
141 }
142 
143 int get_c0_fdc_int(void)
144 {
145 	/*
146 	 * Some cores claim the FDC is routable through the GIC, but it doesn't
147 	 * actually seem to be connected for those Malta bitstreams.
148 	 */
149 	switch (current_cpu_type()) {
150 	case CPU_INTERAPTIV:
151 	case CPU_PROAPTIV:
152 		return -1;
153 	};
154 
155 	if (cpu_has_veic)
156 		return -1;
157 	else if (gic_present)
158 		return gic_get_c0_fdc_int();
159 	else if (cp0_fdc_irq >= 0)
160 		return MIPS_CPU_IRQ_BASE + cp0_fdc_irq;
161 	else
162 		return -1;
163 }
164 
165 int get_c0_perfcount_int(void)
166 {
167 	if (cpu_has_veic) {
168 		set_vi_handler(MSC01E_INT_PERFCTR, mips_perf_dispatch);
169 		mips_cpu_perf_irq = MSC01E_INT_BASE + MSC01E_INT_PERFCTR;
170 	} else if (gic_present) {
171 		mips_cpu_perf_irq = gic_get_c0_perfcount_int();
172 	} else if (cp0_perfcount_irq >= 0) {
173 		mips_cpu_perf_irq = MIPS_CPU_IRQ_BASE + cp0_perfcount_irq;
174 	} else {
175 		mips_cpu_perf_irq = -1;
176 	}
177 
178 	return mips_cpu_perf_irq;
179 }
180 EXPORT_SYMBOL_GPL(get_c0_perfcount_int);
181 
182 unsigned int get_c0_compare_int(void)
183 {
184 	if (cpu_has_veic) {
185 		set_vi_handler(MSC01E_INT_CPUCTR, mips_timer_dispatch);
186 		mips_cpu_timer_irq = MSC01E_INT_BASE + MSC01E_INT_CPUCTR;
187 	} else if (gic_present) {
188 		mips_cpu_timer_irq = gic_get_c0_compare_int();
189 	} else {
190 		mips_cpu_timer_irq = MIPS_CPU_IRQ_BASE + cp0_compare_irq;
191 	}
192 
193 	return mips_cpu_timer_irq;
194 }
195 
196 static void __init init_rtc(void)
197 {
198 	unsigned char freq, ctrl;
199 
200 	/* Set 32KHz time base if not already set */
201 	freq = CMOS_READ(RTC_FREQ_SELECT);
202 	if ((freq & RTC_DIV_CTL) != RTC_REF_CLCK_32KHZ)
203 		CMOS_WRITE(RTC_REF_CLCK_32KHZ, RTC_FREQ_SELECT);
204 
205 	/* Ensure SET bit is clear so RTC can run */
206 	ctrl = CMOS_READ(RTC_CONTROL);
207 	if (ctrl & RTC_SET)
208 		CMOS_WRITE(ctrl & ~RTC_SET, RTC_CONTROL);
209 }
210 
211 #ifdef CONFIG_CLKSRC_MIPS_GIC
212 static u32 gic_frequency_dt;
213 
214 static struct property gic_frequency_prop = {
215 	.name = "clock-frequency",
216 	.length = sizeof(u32),
217 	.value = &gic_frequency_dt,
218 };
219 
220 static void update_gic_frequency_dt(void)
221 {
222 	struct device_node *node;
223 
224 	gic_frequency_dt = cpu_to_be32(gic_frequency);
225 
226 	node = of_find_compatible_node(NULL, NULL, "mti,gic-timer");
227 	if (!node) {
228 		pr_err("mti,gic-timer device node not found\n");
229 		return;
230 	}
231 
232 	if (of_update_property(node, &gic_frequency_prop) < 0)
233 		pr_err("error updating gic frequency property\n");
234 }
235 
236 #endif
237 
238 void __init plat_time_init(void)
239 {
240 	unsigned int prid = read_c0_prid() & (PRID_COMP_MASK | PRID_IMP_MASK);
241 	unsigned int freq;
242 
243 	init_rtc();
244 	estimate_frequencies();
245 
246 	freq = mips_hpt_frequency;
247 	if ((prid != (PRID_COMP_MIPS | PRID_IMP_20KC)) &&
248 	    (prid != (PRID_COMP_MIPS | PRID_IMP_25KF)))
249 		freq *= 2;
250 	freq = freqround(freq, 5000);
251 	printk("CPU frequency %d.%02d MHz\n", freq/1000000,
252 	       (freq%1000000)*100/1000000);
253 
254 	mips_scroll_message();
255 
256 #ifdef CONFIG_I8253
257 	/* Only Malta has a PIT. */
258 	setup_pit_timer();
259 #endif
260 
261 #ifdef CONFIG_MIPS_GIC
262 	if (gic_present) {
263 		freq = freqround(gic_frequency, 5000);
264 		printk("GIC frequency %d.%02d MHz\n", freq/1000000,
265 		       (freq%1000000)*100/1000000);
266 #ifdef CONFIG_CLKSRC_MIPS_GIC
267 		update_gic_frequency_dt();
268 		clocksource_probe();
269 #endif
270 	}
271 #endif
272 }
273