1 /* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * A small micro-assembler. It is intentionally kept simple, does only 7 * support a subset of instructions, and does not try to hide pipeline 8 * effects like branch delay slots. 9 * 10 * Copyright (C) 2004, 2005, 2006, 2008 Thiemo Seufer 11 * Copyright (C) 2005, 2007 Maciej W. Rozycki 12 * Copyright (C) 2006 Ralf Baechle (ralf@linux-mips.org) 13 */ 14 15 #include <linux/kernel.h> 16 #include <linux/types.h> 17 #include <linux/init.h> 18 19 #include <asm/inst.h> 20 #include <asm/elf.h> 21 #include <asm/bugs.h> 22 #include <asm/uasm.h> 23 24 enum fields { 25 RS = 0x001, 26 RT = 0x002, 27 RD = 0x004, 28 RE = 0x008, 29 SIMM = 0x010, 30 UIMM = 0x020, 31 BIMM = 0x040, 32 JIMM = 0x080, 33 FUNC = 0x100, 34 SET = 0x200, 35 SCIMM = 0x400 36 }; 37 38 #define OP_MASK 0x3f 39 #define OP_SH 26 40 #define RS_MASK 0x1f 41 #define RS_SH 21 42 #define RT_MASK 0x1f 43 #define RT_SH 16 44 #define RD_MASK 0x1f 45 #define RD_SH 11 46 #define RE_MASK 0x1f 47 #define RE_SH 6 48 #define IMM_MASK 0xffff 49 #define IMM_SH 0 50 #define JIMM_MASK 0x3ffffff 51 #define JIMM_SH 0 52 #define FUNC_MASK 0x3f 53 #define FUNC_SH 0 54 #define SET_MASK 0x7 55 #define SET_SH 0 56 #define SCIMM_MASK 0xfffff 57 #define SCIMM_SH 6 58 59 enum opcode { 60 insn_invalid, 61 insn_addu, insn_addiu, insn_and, insn_andi, insn_beq, 62 insn_beql, insn_bgez, insn_bgezl, insn_bltz, insn_bltzl, 63 insn_bne, insn_cache, insn_daddu, insn_daddiu, insn_dmfc0, 64 insn_dmtc0, insn_dsll, insn_dsll32, insn_dsra, insn_dsrl, 65 insn_dsrl32, insn_drotr, insn_dsubu, insn_eret, insn_j, insn_jal, 66 insn_jr, insn_ld, insn_ll, insn_lld, insn_lui, insn_lw, insn_mfc0, 67 insn_mtc0, insn_or, insn_ori, insn_pref, insn_rfe, insn_sc, insn_scd, 68 insn_sd, insn_sll, insn_sra, insn_srl, insn_rotr, insn_subu, insn_sw, 69 insn_tlbp, insn_tlbr, insn_tlbwi, insn_tlbwr, insn_xor, insn_xori, 70 insn_dins, insn_syscall 71 }; 72 73 struct insn { 74 enum opcode opcode; 75 u32 match; 76 enum fields fields; 77 }; 78 79 /* This macro sets the non-variable bits of an instruction. */ 80 #define M(a, b, c, d, e, f) \ 81 ((a) << OP_SH \ 82 | (b) << RS_SH \ 83 | (c) << RT_SH \ 84 | (d) << RD_SH \ 85 | (e) << RE_SH \ 86 | (f) << FUNC_SH) 87 88 static struct insn insn_table[] __cpuinitdata = { 89 { insn_addiu, M(addiu_op, 0, 0, 0, 0, 0), RS | RT | SIMM }, 90 { insn_addu, M(spec_op, 0, 0, 0, 0, addu_op), RS | RT | RD }, 91 { insn_and, M(spec_op, 0, 0, 0, 0, and_op), RS | RT | RD }, 92 { insn_andi, M(andi_op, 0, 0, 0, 0, 0), RS | RT | UIMM }, 93 { insn_beq, M(beq_op, 0, 0, 0, 0, 0), RS | RT | BIMM }, 94 { insn_beql, M(beql_op, 0, 0, 0, 0, 0), RS | RT | BIMM }, 95 { insn_bgez, M(bcond_op, 0, bgez_op, 0, 0, 0), RS | BIMM }, 96 { insn_bgezl, M(bcond_op, 0, bgezl_op, 0, 0, 0), RS | BIMM }, 97 { insn_bltz, M(bcond_op, 0, bltz_op, 0, 0, 0), RS | BIMM }, 98 { insn_bltzl, M(bcond_op, 0, bltzl_op, 0, 0, 0), RS | BIMM }, 99 { insn_bne, M(bne_op, 0, 0, 0, 0, 0), RS | RT | BIMM }, 100 { insn_cache, M(cache_op, 0, 0, 0, 0, 0), RS | RT | SIMM }, 101 { insn_daddiu, M(daddiu_op, 0, 0, 0, 0, 0), RS | RT | SIMM }, 102 { insn_daddu, M(spec_op, 0, 0, 0, 0, daddu_op), RS | RT | RD }, 103 { insn_dmfc0, M(cop0_op, dmfc_op, 0, 0, 0, 0), RT | RD | SET}, 104 { insn_dmtc0, M(cop0_op, dmtc_op, 0, 0, 0, 0), RT | RD | SET}, 105 { insn_dsll, M(spec_op, 0, 0, 0, 0, dsll_op), RT | RD | RE }, 106 { insn_dsll32, M(spec_op, 0, 0, 0, 0, dsll32_op), RT | RD | RE }, 107 { insn_dsra, M(spec_op, 0, 0, 0, 0, dsra_op), RT | RD | RE }, 108 { insn_dsrl, M(spec_op, 0, 0, 0, 0, dsrl_op), RT | RD | RE }, 109 { insn_dsrl32, M(spec_op, 0, 0, 0, 0, dsrl32_op), RT | RD | RE }, 110 { insn_drotr, M(spec_op, 1, 0, 0, 0, dsrl_op), RT | RD | RE }, 111 { insn_dsubu, M(spec_op, 0, 0, 0, 0, dsubu_op), RS | RT | RD }, 112 { insn_eret, M(cop0_op, cop_op, 0, 0, 0, eret_op), 0 }, 113 { insn_j, M(j_op, 0, 0, 0, 0, 0), JIMM }, 114 { insn_jal, M(jal_op, 0, 0, 0, 0, 0), JIMM }, 115 { insn_jr, M(spec_op, 0, 0, 0, 0, jr_op), RS }, 116 { insn_ld, M(ld_op, 0, 0, 0, 0, 0), RS | RT | SIMM }, 117 { insn_ll, M(ll_op, 0, 0, 0, 0, 0), RS | RT | SIMM }, 118 { insn_lld, M(lld_op, 0, 0, 0, 0, 0), RS | RT | SIMM }, 119 { insn_lui, M(lui_op, 0, 0, 0, 0, 0), RT | SIMM }, 120 { insn_lw, M(lw_op, 0, 0, 0, 0, 0), RS | RT | SIMM }, 121 { insn_mfc0, M(cop0_op, mfc_op, 0, 0, 0, 0), RT | RD | SET}, 122 { insn_mtc0, M(cop0_op, mtc_op, 0, 0, 0, 0), RT | RD | SET}, 123 { insn_or, M(spec_op, 0, 0, 0, 0, or_op), RS | RT | RD }, 124 { insn_ori, M(ori_op, 0, 0, 0, 0, 0), RS | RT | UIMM }, 125 { insn_pref, M(pref_op, 0, 0, 0, 0, 0), RS | RT | SIMM }, 126 { insn_rfe, M(cop0_op, cop_op, 0, 0, 0, rfe_op), 0 }, 127 { insn_sc, M(sc_op, 0, 0, 0, 0, 0), RS | RT | SIMM }, 128 { insn_scd, M(scd_op, 0, 0, 0, 0, 0), RS | RT | SIMM }, 129 { insn_sd, M(sd_op, 0, 0, 0, 0, 0), RS | RT | SIMM }, 130 { insn_sll, M(spec_op, 0, 0, 0, 0, sll_op), RT | RD | RE }, 131 { insn_sra, M(spec_op, 0, 0, 0, 0, sra_op), RT | RD | RE }, 132 { insn_srl, M(spec_op, 0, 0, 0, 0, srl_op), RT | RD | RE }, 133 { insn_rotr, M(spec_op, 1, 0, 0, 0, srl_op), RT | RD | RE }, 134 { insn_subu, M(spec_op, 0, 0, 0, 0, subu_op), RS | RT | RD }, 135 { insn_sw, M(sw_op, 0, 0, 0, 0, 0), RS | RT | SIMM }, 136 { insn_tlbp, M(cop0_op, cop_op, 0, 0, 0, tlbp_op), 0 }, 137 { insn_tlbr, M(cop0_op, cop_op, 0, 0, 0, tlbr_op), 0 }, 138 { insn_tlbwi, M(cop0_op, cop_op, 0, 0, 0, tlbwi_op), 0 }, 139 { insn_tlbwr, M(cop0_op, cop_op, 0, 0, 0, tlbwr_op), 0 }, 140 { insn_xor, M(spec_op, 0, 0, 0, 0, xor_op), RS | RT | RD }, 141 { insn_xori, M(xori_op, 0, 0, 0, 0, 0), RS | RT | UIMM }, 142 { insn_dins, M(spec3_op, 0, 0, 0, 0, dins_op), RS | RT | RD | RE }, 143 { insn_syscall, M(spec_op, 0, 0, 0, 0, syscall_op), SCIMM}, 144 { insn_invalid, 0, 0 } 145 }; 146 147 #undef M 148 149 static inline __cpuinit u32 build_rs(u32 arg) 150 { 151 if (arg & ~RS_MASK) 152 printk(KERN_WARNING "Micro-assembler field overflow\n"); 153 154 return (arg & RS_MASK) << RS_SH; 155 } 156 157 static inline __cpuinit u32 build_rt(u32 arg) 158 { 159 if (arg & ~RT_MASK) 160 printk(KERN_WARNING "Micro-assembler field overflow\n"); 161 162 return (arg & RT_MASK) << RT_SH; 163 } 164 165 static inline __cpuinit u32 build_rd(u32 arg) 166 { 167 if (arg & ~RD_MASK) 168 printk(KERN_WARNING "Micro-assembler field overflow\n"); 169 170 return (arg & RD_MASK) << RD_SH; 171 } 172 173 static inline __cpuinit u32 build_re(u32 arg) 174 { 175 if (arg & ~RE_MASK) 176 printk(KERN_WARNING "Micro-assembler field overflow\n"); 177 178 return (arg & RE_MASK) << RE_SH; 179 } 180 181 static inline __cpuinit u32 build_simm(s32 arg) 182 { 183 if (arg > 0x7fff || arg < -0x8000) 184 printk(KERN_WARNING "Micro-assembler field overflow\n"); 185 186 return arg & 0xffff; 187 } 188 189 static inline __cpuinit u32 build_uimm(u32 arg) 190 { 191 if (arg & ~IMM_MASK) 192 printk(KERN_WARNING "Micro-assembler field overflow\n"); 193 194 return arg & IMM_MASK; 195 } 196 197 static inline __cpuinit u32 build_bimm(s32 arg) 198 { 199 if (arg > 0x1ffff || arg < -0x20000) 200 printk(KERN_WARNING "Micro-assembler field overflow\n"); 201 202 if (arg & 0x3) 203 printk(KERN_WARNING "Invalid micro-assembler branch target\n"); 204 205 return ((arg < 0) ? (1 << 15) : 0) | ((arg >> 2) & 0x7fff); 206 } 207 208 static inline __cpuinit u32 build_jimm(u32 arg) 209 { 210 if (arg & ~((JIMM_MASK) << 2)) 211 printk(KERN_WARNING "Micro-assembler field overflow\n"); 212 213 return (arg >> 2) & JIMM_MASK; 214 } 215 216 static inline __cpuinit u32 build_scimm(u32 arg) 217 { 218 if (arg & ~SCIMM_MASK) 219 printk(KERN_WARNING "Micro-assembler field overflow\n"); 220 221 return (arg & SCIMM_MASK) << SCIMM_SH; 222 } 223 224 static inline __cpuinit u32 build_func(u32 arg) 225 { 226 if (arg & ~FUNC_MASK) 227 printk(KERN_WARNING "Micro-assembler field overflow\n"); 228 229 return arg & FUNC_MASK; 230 } 231 232 static inline __cpuinit u32 build_set(u32 arg) 233 { 234 if (arg & ~SET_MASK) 235 printk(KERN_WARNING "Micro-assembler field overflow\n"); 236 237 return arg & SET_MASK; 238 } 239 240 /* 241 * The order of opcode arguments is implicitly left to right, 242 * starting with RS and ending with FUNC or IMM. 243 */ 244 static void __cpuinit build_insn(u32 **buf, enum opcode opc, ...) 245 { 246 struct insn *ip = NULL; 247 unsigned int i; 248 va_list ap; 249 u32 op; 250 251 for (i = 0; insn_table[i].opcode != insn_invalid; i++) 252 if (insn_table[i].opcode == opc) { 253 ip = &insn_table[i]; 254 break; 255 } 256 257 if (!ip || (opc == insn_daddiu && r4k_daddiu_bug())) 258 panic("Unsupported Micro-assembler instruction %d", opc); 259 260 op = ip->match; 261 va_start(ap, opc); 262 if (ip->fields & RS) 263 op |= build_rs(va_arg(ap, u32)); 264 if (ip->fields & RT) 265 op |= build_rt(va_arg(ap, u32)); 266 if (ip->fields & RD) 267 op |= build_rd(va_arg(ap, u32)); 268 if (ip->fields & RE) 269 op |= build_re(va_arg(ap, u32)); 270 if (ip->fields & SIMM) 271 op |= build_simm(va_arg(ap, s32)); 272 if (ip->fields & UIMM) 273 op |= build_uimm(va_arg(ap, u32)); 274 if (ip->fields & BIMM) 275 op |= build_bimm(va_arg(ap, s32)); 276 if (ip->fields & JIMM) 277 op |= build_jimm(va_arg(ap, u32)); 278 if (ip->fields & FUNC) 279 op |= build_func(va_arg(ap, u32)); 280 if (ip->fields & SET) 281 op |= build_set(va_arg(ap, u32)); 282 if (ip->fields & SCIMM) 283 op |= build_scimm(va_arg(ap, u32)); 284 va_end(ap); 285 286 **buf = op; 287 (*buf)++; 288 } 289 290 #define I_u1u2u3(op) \ 291 Ip_u1u2u3(op) \ 292 { \ 293 build_insn(buf, insn##op, a, b, c); \ 294 } 295 296 #define I_u2u1u3(op) \ 297 Ip_u2u1u3(op) \ 298 { \ 299 build_insn(buf, insn##op, b, a, c); \ 300 } 301 302 #define I_u3u1u2(op) \ 303 Ip_u3u1u2(op) \ 304 { \ 305 build_insn(buf, insn##op, b, c, a); \ 306 } 307 308 #define I_u1u2s3(op) \ 309 Ip_u1u2s3(op) \ 310 { \ 311 build_insn(buf, insn##op, a, b, c); \ 312 } 313 314 #define I_u2s3u1(op) \ 315 Ip_u2s3u1(op) \ 316 { \ 317 build_insn(buf, insn##op, c, a, b); \ 318 } 319 320 #define I_u2u1s3(op) \ 321 Ip_u2u1s3(op) \ 322 { \ 323 build_insn(buf, insn##op, b, a, c); \ 324 } 325 326 #define I_u2u1msbu3(op) \ 327 Ip_u2u1msbu3(op) \ 328 { \ 329 build_insn(buf, insn##op, b, a, c+d-1, c); \ 330 } 331 332 #define I_u1u2(op) \ 333 Ip_u1u2(op) \ 334 { \ 335 build_insn(buf, insn##op, a, b); \ 336 } 337 338 #define I_u1s2(op) \ 339 Ip_u1s2(op) \ 340 { \ 341 build_insn(buf, insn##op, a, b); \ 342 } 343 344 #define I_u1(op) \ 345 Ip_u1(op) \ 346 { \ 347 build_insn(buf, insn##op, a); \ 348 } 349 350 #define I_0(op) \ 351 Ip_0(op) \ 352 { \ 353 build_insn(buf, insn##op); \ 354 } 355 356 I_u2u1s3(_addiu) 357 I_u3u1u2(_addu) 358 I_u2u1u3(_andi) 359 I_u3u1u2(_and) 360 I_u1u2s3(_beq) 361 I_u1u2s3(_beql) 362 I_u1s2(_bgez) 363 I_u1s2(_bgezl) 364 I_u1s2(_bltz) 365 I_u1s2(_bltzl) 366 I_u1u2s3(_bne) 367 I_u2s3u1(_cache) 368 I_u1u2u3(_dmfc0) 369 I_u1u2u3(_dmtc0) 370 I_u2u1s3(_daddiu) 371 I_u3u1u2(_daddu) 372 I_u2u1u3(_dsll) 373 I_u2u1u3(_dsll32) 374 I_u2u1u3(_dsra) 375 I_u2u1u3(_dsrl) 376 I_u2u1u3(_dsrl32) 377 I_u2u1u3(_drotr) 378 I_u3u1u2(_dsubu) 379 I_0(_eret) 380 I_u1(_j) 381 I_u1(_jal) 382 I_u1(_jr) 383 I_u2s3u1(_ld) 384 I_u2s3u1(_ll) 385 I_u2s3u1(_lld) 386 I_u1s2(_lui) 387 I_u2s3u1(_lw) 388 I_u1u2u3(_mfc0) 389 I_u1u2u3(_mtc0) 390 I_u2u1u3(_ori) 391 I_u3u1u2(_or) 392 I_u2s3u1(_pref) 393 I_0(_rfe) 394 I_u2s3u1(_sc) 395 I_u2s3u1(_scd) 396 I_u2s3u1(_sd) 397 I_u2u1u3(_sll) 398 I_u2u1u3(_sra) 399 I_u2u1u3(_srl) 400 I_u2u1u3(_rotr) 401 I_u3u1u2(_subu) 402 I_u2s3u1(_sw) 403 I_0(_tlbp) 404 I_0(_tlbr) 405 I_0(_tlbwi) 406 I_0(_tlbwr) 407 I_u3u1u2(_xor) 408 I_u2u1u3(_xori) 409 I_u2u1msbu3(_dins); 410 I_u1(_syscall); 411 412 /* Handle labels. */ 413 void __cpuinit uasm_build_label(struct uasm_label **lab, u32 *addr, int lid) 414 { 415 (*lab)->addr = addr; 416 (*lab)->lab = lid; 417 (*lab)++; 418 } 419 420 int __cpuinit uasm_in_compat_space_p(long addr) 421 { 422 /* Is this address in 32bit compat space? */ 423 #ifdef CONFIG_64BIT 424 return (((addr) & 0xffffffff00000000L) == 0xffffffff00000000L); 425 #else 426 return 1; 427 #endif 428 } 429 430 static int __cpuinit uasm_rel_highest(long val) 431 { 432 #ifdef CONFIG_64BIT 433 return ((((val + 0x800080008000L) >> 48) & 0xffff) ^ 0x8000) - 0x8000; 434 #else 435 return 0; 436 #endif 437 } 438 439 static int __cpuinit uasm_rel_higher(long val) 440 { 441 #ifdef CONFIG_64BIT 442 return ((((val + 0x80008000L) >> 32) & 0xffff) ^ 0x8000) - 0x8000; 443 #else 444 return 0; 445 #endif 446 } 447 448 int __cpuinit uasm_rel_hi(long val) 449 { 450 return ((((val + 0x8000L) >> 16) & 0xffff) ^ 0x8000) - 0x8000; 451 } 452 453 int __cpuinit uasm_rel_lo(long val) 454 { 455 return ((val & 0xffff) ^ 0x8000) - 0x8000; 456 } 457 458 void __cpuinit UASM_i_LA_mostly(u32 **buf, unsigned int rs, long addr) 459 { 460 if (!uasm_in_compat_space_p(addr)) { 461 uasm_i_lui(buf, rs, uasm_rel_highest(addr)); 462 if (uasm_rel_higher(addr)) 463 uasm_i_daddiu(buf, rs, rs, uasm_rel_higher(addr)); 464 if (uasm_rel_hi(addr)) { 465 uasm_i_dsll(buf, rs, rs, 16); 466 uasm_i_daddiu(buf, rs, rs, uasm_rel_hi(addr)); 467 uasm_i_dsll(buf, rs, rs, 16); 468 } else 469 uasm_i_dsll32(buf, rs, rs, 0); 470 } else 471 uasm_i_lui(buf, rs, uasm_rel_hi(addr)); 472 } 473 474 void __cpuinit UASM_i_LA(u32 **buf, unsigned int rs, long addr) 475 { 476 UASM_i_LA_mostly(buf, rs, addr); 477 if (uasm_rel_lo(addr)) { 478 if (!uasm_in_compat_space_p(addr)) 479 uasm_i_daddiu(buf, rs, rs, uasm_rel_lo(addr)); 480 else 481 uasm_i_addiu(buf, rs, rs, uasm_rel_lo(addr)); 482 } 483 } 484 485 /* Handle relocations. */ 486 void __cpuinit 487 uasm_r_mips_pc16(struct uasm_reloc **rel, u32 *addr, int lid) 488 { 489 (*rel)->addr = addr; 490 (*rel)->type = R_MIPS_PC16; 491 (*rel)->lab = lid; 492 (*rel)++; 493 } 494 495 static inline void __cpuinit 496 __resolve_relocs(struct uasm_reloc *rel, struct uasm_label *lab) 497 { 498 long laddr = (long)lab->addr; 499 long raddr = (long)rel->addr; 500 501 switch (rel->type) { 502 case R_MIPS_PC16: 503 *rel->addr |= build_bimm(laddr - (raddr + 4)); 504 break; 505 506 default: 507 panic("Unsupported Micro-assembler relocation %d", 508 rel->type); 509 } 510 } 511 512 void __cpuinit 513 uasm_resolve_relocs(struct uasm_reloc *rel, struct uasm_label *lab) 514 { 515 struct uasm_label *l; 516 517 for (; rel->lab != UASM_LABEL_INVALID; rel++) 518 for (l = lab; l->lab != UASM_LABEL_INVALID; l++) 519 if (rel->lab == l->lab) 520 __resolve_relocs(rel, l); 521 } 522 523 void __cpuinit 524 uasm_move_relocs(struct uasm_reloc *rel, u32 *first, u32 *end, long off) 525 { 526 for (; rel->lab != UASM_LABEL_INVALID; rel++) 527 if (rel->addr >= first && rel->addr < end) 528 rel->addr += off; 529 } 530 531 void __cpuinit 532 uasm_move_labels(struct uasm_label *lab, u32 *first, u32 *end, long off) 533 { 534 for (; lab->lab != UASM_LABEL_INVALID; lab++) 535 if (lab->addr >= first && lab->addr < end) 536 lab->addr += off; 537 } 538 539 void __cpuinit 540 uasm_copy_handler(struct uasm_reloc *rel, struct uasm_label *lab, u32 *first, 541 u32 *end, u32 *target) 542 { 543 long off = (long)(target - first); 544 545 memcpy(target, first, (end - first) * sizeof(u32)); 546 547 uasm_move_relocs(rel, first, end, off); 548 uasm_move_labels(lab, first, end, off); 549 } 550 551 int __cpuinit uasm_insn_has_bdelay(struct uasm_reloc *rel, u32 *addr) 552 { 553 for (; rel->lab != UASM_LABEL_INVALID; rel++) { 554 if (rel->addr == addr 555 && (rel->type == R_MIPS_PC16 556 || rel->type == R_MIPS_26)) 557 return 1; 558 } 559 560 return 0; 561 } 562 563 /* Convenience functions for labeled branches. */ 564 void __cpuinit 565 uasm_il_bltz(u32 **p, struct uasm_reloc **r, unsigned int reg, int lid) 566 { 567 uasm_r_mips_pc16(r, *p, lid); 568 uasm_i_bltz(p, reg, 0); 569 } 570 571 void __cpuinit 572 uasm_il_b(u32 **p, struct uasm_reloc **r, int lid) 573 { 574 uasm_r_mips_pc16(r, *p, lid); 575 uasm_i_b(p, 0); 576 } 577 578 void __cpuinit 579 uasm_il_beqz(u32 **p, struct uasm_reloc **r, unsigned int reg, int lid) 580 { 581 uasm_r_mips_pc16(r, *p, lid); 582 uasm_i_beqz(p, reg, 0); 583 } 584 585 void __cpuinit 586 uasm_il_beqzl(u32 **p, struct uasm_reloc **r, unsigned int reg, int lid) 587 { 588 uasm_r_mips_pc16(r, *p, lid); 589 uasm_i_beqzl(p, reg, 0); 590 } 591 592 void __cpuinit 593 uasm_il_bne(u32 **p, struct uasm_reloc **r, unsigned int reg1, 594 unsigned int reg2, int lid) 595 { 596 uasm_r_mips_pc16(r, *p, lid); 597 uasm_i_bne(p, reg1, reg2, 0); 598 } 599 600 void __cpuinit 601 uasm_il_bnez(u32 **p, struct uasm_reloc **r, unsigned int reg, int lid) 602 { 603 uasm_r_mips_pc16(r, *p, lid); 604 uasm_i_bnez(p, reg, 0); 605 } 606 607 void __cpuinit 608 uasm_il_bgezl(u32 **p, struct uasm_reloc **r, unsigned int reg, int lid) 609 { 610 uasm_r_mips_pc16(r, *p, lid); 611 uasm_i_bgezl(p, reg, 0); 612 } 613 614 void __cpuinit 615 uasm_il_bgez(u32 **p, struct uasm_reloc **r, unsigned int reg, int lid) 616 { 617 uasm_r_mips_pc16(r, *p, lid); 618 uasm_i_bgez(p, reg, 0); 619 } 620