1abc597feSSteven J. Hill /* 2abc597feSSteven J. Hill * This file is subject to the terms and conditions of the GNU General Public 3abc597feSSteven J. Hill * License. See the file "COPYING" in the main directory of this archive 4abc597feSSteven J. Hill * for more details. 5abc597feSSteven J. Hill * 6abc597feSSteven J. Hill * A small micro-assembler. It is intentionally kept simple, does only 7abc597feSSteven J. Hill * support a subset of instructions, and does not try to hide pipeline 8abc597feSSteven J. Hill * effects like branch delay slots. 9abc597feSSteven J. Hill * 10abc597feSSteven J. Hill * Copyright (C) 2004, 2005, 2006, 2008 Thiemo Seufer 11abc597feSSteven J. Hill * Copyright (C) 2005, 2007 Maciej W. Rozycki 12abc597feSSteven J. Hill * Copyright (C) 2006 Ralf Baechle (ralf@linux-mips.org) 13abc597feSSteven J. Hill * Copyright (C) 2012, 2013 MIPS Technologies, Inc. All rights reserved. 14abc597feSSteven J. Hill */ 15abc597feSSteven J. Hill 16abc597feSSteven J. Hill #include <linux/kernel.h> 17abc597feSSteven J. Hill #include <linux/types.h> 18abc597feSSteven J. Hill 19abc597feSSteven J. Hill #include <asm/inst.h> 20abc597feSSteven J. Hill #include <asm/elf.h> 21abc597feSSteven J. Hill #include <asm/bugs.h> 22abc597feSSteven J. Hill #include <asm/uasm.h> 23abc597feSSteven J. Hill 24abc597feSSteven J. Hill #define RS_MASK 0x1f 25abc597feSSteven J. Hill #define RS_SH 21 26abc597feSSteven J. Hill #define RT_MASK 0x1f 27abc597feSSteven J. Hill #define RT_SH 16 28abc597feSSteven J. Hill #define SCIMM_MASK 0xfffff 29abc597feSSteven J. Hill #define SCIMM_SH 6 30abc597feSSteven J. Hill 31abc597feSSteven J. Hill /* This macro sets the non-variable bits of an instruction. */ 32abc597feSSteven J. Hill #define M(a, b, c, d, e, f) \ 33abc597feSSteven J. Hill ((a) << OP_SH \ 34abc597feSSteven J. Hill | (b) << RS_SH \ 35abc597feSSteven J. Hill | (c) << RT_SH \ 36abc597feSSteven J. Hill | (d) << RD_SH \ 37abc597feSSteven J. Hill | (e) << RE_SH \ 38abc597feSSteven J. Hill | (f) << FUNC_SH) 39abc597feSSteven J. Hill 40a168b8f1SLeonid Yegoshin /* This macro sets the non-variable bits of an R6 instruction. */ 41a168b8f1SLeonid Yegoshin #define M6(a, b, c, d, e) \ 42a168b8f1SLeonid Yegoshin ((a) << OP_SH \ 43a168b8f1SLeonid Yegoshin | (b) << RS_SH \ 44a168b8f1SLeonid Yegoshin | (c) << RT_SH \ 45a168b8f1SLeonid Yegoshin | (d) << SIMM9_SH \ 46a168b8f1SLeonid Yegoshin | (e) << FUNC_SH) 47a168b8f1SLeonid Yegoshin 48abc597feSSteven J. Hill #include "uasm.c" 49abc597feSSteven J. Hill 5000e06297SThomas Petazzoni static const struct insn insn_table[insn_invalid] = { 51ce807d5fSDavid Daney [insn_addiu] = {M(addiu_op, 0, 0, 0, 0, 0), RS | RT | SIMM}, 52ce807d5fSDavid Daney [insn_addu] = {M(spec_op, 0, 0, 0, 0, addu_op), RS | RT | RD}, 53ce807d5fSDavid Daney [insn_and] = {M(spec_op, 0, 0, 0, 0, and_op), RS | RT | RD}, 54ce807d5fSDavid Daney [insn_andi] = {M(andi_op, 0, 0, 0, 0, 0), RS | RT | UIMM}, 55ce807d5fSDavid Daney [insn_bbit0] = {M(lwc2_op, 0, 0, 0, 0, 0), RS | RT | BIMM}, 56ce807d5fSDavid Daney [insn_bbit1] = {M(swc2_op, 0, 0, 0, 0, 0), RS | RT | BIMM}, 57ce807d5fSDavid Daney [insn_beq] = {M(beq_op, 0, 0, 0, 0, 0), RS | RT | BIMM}, 58ce807d5fSDavid Daney [insn_beql] = {M(beql_op, 0, 0, 0, 0, 0), RS | RT | BIMM}, 59ce807d5fSDavid Daney [insn_bgez] = {M(bcond_op, 0, bgez_op, 0, 0, 0), RS | BIMM}, 60ce807d5fSDavid Daney [insn_bgezl] = {M(bcond_op, 0, bgezl_op, 0, 0, 0), RS | BIMM}, 61dc190129SDavid Daney [insn_bgtz] = {M(bgtz_op, 0, 0, 0, 0, 0), RS | BIMM}, 62dc190129SDavid Daney [insn_blez] = {M(blez_op, 0, 0, 0, 0, 0), RS | BIMM}, 63ce807d5fSDavid Daney [insn_bltz] = {M(bcond_op, 0, bltz_op, 0, 0, 0), RS | BIMM}, 64ce807d5fSDavid Daney [insn_bltzl] = {M(bcond_op, 0, bltzl_op, 0, 0, 0), RS | BIMM}, 65ce807d5fSDavid Daney [insn_bne] = {M(bne_op, 0, 0, 0, 0, 0), RS | RT | BIMM}, 66dc190129SDavid Daney [insn_break] = {M(spec_op, 0, 0, 0, 0, break_op), SCIMM}, 67a168b8f1SLeonid Yegoshin #ifndef CONFIG_CPU_MIPSR6 68ce807d5fSDavid Daney [insn_cache] = {M(cache_op, 0, 0, 0, 0, 0), RS | RT | SIMM}, 69a168b8f1SLeonid Yegoshin #else 70ce807d5fSDavid Daney [insn_cache] = {M6(spec3_op, 0, 0, 0, cache6_op), RS | RT | SIMM9}, 71a168b8f1SLeonid Yegoshin #endif 72ce807d5fSDavid Daney [insn_cfc1] = {M(cop1_op, cfc_op, 0, 0, 0, 0), RT | RD}, 73ce807d5fSDavid Daney [insn_cfcmsa] = {M(msa_op, 0, msa_cfc_op, 0, 0, msa_elm_op), RD | RE}, 74ce807d5fSDavid Daney [insn_ctc1] = {M(cop1_op, ctc_op, 0, 0, 0, 0), RT | RD}, 75ce807d5fSDavid Daney [insn_ctcmsa] = {M(msa_op, 0, msa_ctc_op, 0, 0, msa_elm_op), RD | RE}, 76ce807d5fSDavid Daney [insn_daddiu] = {M(daddiu_op, 0, 0, 0, 0, 0), RS | RT | SIMM}, 77ce807d5fSDavid Daney [insn_daddu] = {M(spec_op, 0, 0, 0, 0, daddu_op), RS | RT | RD}, 78dc190129SDavid Daney [insn_ddivu] = {M(spec_op, 0, 0, 0, 0, ddivu_op), RS | RT}, 79*0d1d17b9SHassan Naveed [insn_ddivu_r6] = {M(spec_op, 0, 0, 0, ddivu_ddivu6_op, ddivu_op), 80*0d1d17b9SHassan Naveed RS | RT | RD}, 81ce807d5fSDavid Daney [insn_di] = {M(cop0_op, mfmc0_op, 0, 12, 0, 0), RT}, 82ce807d5fSDavid Daney [insn_dins] = {M(spec3_op, 0, 0, 0, 0, dins_op), RS | RT | RD | RE}, 83ce807d5fSDavid Daney [insn_dinsm] = {M(spec3_op, 0, 0, 0, 0, dinsm_op), RS | RT | RD | RE}, 84dc190129SDavid Daney [insn_dinsu] = {M(spec3_op, 0, 0, 0, 0, dinsu_op), RS | RT | RD | RE}, 85ce807d5fSDavid Daney [insn_divu] = {M(spec_op, 0, 0, 0, 0, divu_op), RS | RT}, 86*0d1d17b9SHassan Naveed [insn_divu_r6] = {M(spec_op, 0, 0, 0, divu_divu6_op, divu_op), 87*0d1d17b9SHassan Naveed RS | RT | RD}, 88ce807d5fSDavid Daney [insn_dmfc0] = {M(cop0_op, dmfc_op, 0, 0, 0, 0), RT | RD | SET}, 89*0d1d17b9SHassan Naveed [insn_dmodu] = {M(spec_op, 0, 0, 0, ddivu_dmodu_op, ddivu_op), 90*0d1d17b9SHassan Naveed RS | RT | RD}, 91ce807d5fSDavid Daney [insn_dmtc0] = {M(cop0_op, dmtc_op, 0, 0, 0, 0), RT | RD | SET}, 92dc190129SDavid Daney [insn_dmultu] = {M(spec_op, 0, 0, 0, 0, dmultu_op), RS | RT}, 93*0d1d17b9SHassan Naveed [insn_dmulu] = {M(spec_op, 0, 0, 0, dmult_dmul_op, dmultu_op), 94*0d1d17b9SHassan Naveed RS | RT | RD}, 95ce807d5fSDavid Daney [insn_drotr] = {M(spec_op, 1, 0, 0, 0, dsrl_op), RT | RD | RE}, 96ce807d5fSDavid Daney [insn_drotr32] = {M(spec_op, 1, 0, 0, 0, dsrl32_op), RT | RD | RE}, 97dc190129SDavid Daney [insn_dsbh] = {M(spec3_op, 0, 0, 0, dsbh_op, dbshfl_op), RT | RD}, 98dc190129SDavid Daney [insn_dshd] = {M(spec3_op, 0, 0, 0, dshd_op, dbshfl_op), RT | RD}, 99ce807d5fSDavid Daney [insn_dsll] = {M(spec_op, 0, 0, 0, 0, dsll_op), RT | RD | RE}, 100ce807d5fSDavid Daney [insn_dsll32] = {M(spec_op, 0, 0, 0, 0, dsll32_op), RT | RD | RE}, 101dc190129SDavid Daney [insn_dsllv] = {M(spec_op, 0, 0, 0, 0, dsllv_op), RS | RT | RD}, 102ce807d5fSDavid Daney [insn_dsra] = {M(spec_op, 0, 0, 0, 0, dsra_op), RT | RD | RE}, 103dc190129SDavid Daney [insn_dsra32] = {M(spec_op, 0, 0, 0, 0, dsra32_op), RT | RD | RE}, 104dc190129SDavid Daney [insn_dsrav] = {M(spec_op, 0, 0, 0, 0, dsrav_op), RS | RT | RD}, 105ce807d5fSDavid Daney [insn_dsrl] = {M(spec_op, 0, 0, 0, 0, dsrl_op), RT | RD | RE}, 106ce807d5fSDavid Daney [insn_dsrl32] = {M(spec_op, 0, 0, 0, 0, dsrl32_op), RT | RD | RE}, 107dc190129SDavid Daney [insn_dsrlv] = {M(spec_op, 0, 0, 0, 0, dsrlv_op), RS | RT | RD}, 108ce807d5fSDavid Daney [insn_dsubu] = {M(spec_op, 0, 0, 0, 0, dsubu_op), RS | RT | RD}, 109ce807d5fSDavid Daney [insn_eret] = {M(cop0_op, cop_op, 0, 0, 0, eret_op), 0}, 110ce807d5fSDavid Daney [insn_ext] = {M(spec3_op, 0, 0, 0, 0, ext_op), RS | RT | RD | RE}, 111ce807d5fSDavid Daney [insn_ins] = {M(spec3_op, 0, 0, 0, 0, ins_op), RS | RT | RD | RE}, 112ce807d5fSDavid Daney [insn_j] = {M(j_op, 0, 0, 0, 0, 0), JIMM}, 113ce807d5fSDavid Daney [insn_jal] = {M(jal_op, 0, 0, 0, 0, 0), JIMM}, 114ce807d5fSDavid Daney [insn_jalr] = {M(spec_op, 0, 0, 0, 0, jalr_op), RS | RD}, 115a168b8f1SLeonid Yegoshin #ifndef CONFIG_CPU_MIPSR6 116ce807d5fSDavid Daney [insn_jr] = {M(spec_op, 0, 0, 0, 0, jr_op), RS}, 117a168b8f1SLeonid Yegoshin #else 118ce807d5fSDavid Daney [insn_jr] = {M(spec_op, 0, 0, 0, 0, jalr_op), RS}, 119a168b8f1SLeonid Yegoshin #endif 120ce807d5fSDavid Daney [insn_lb] = {M(lb_op, 0, 0, 0, 0, 0), RS | RT | SIMM}, 121dc190129SDavid Daney [insn_lbu] = {M(lbu_op, 0, 0, 0, 0, 0), RS | RT | SIMM}, 122ce807d5fSDavid Daney [insn_ld] = {M(ld_op, 0, 0, 0, 0, 0), RS | RT | SIMM}, 123ce807d5fSDavid Daney [insn_lddir] = {M(lwc2_op, 0, 0, 0, lddir_op, mult_op), RS | RT | RD}, 124ce807d5fSDavid Daney [insn_ldpte] = {M(lwc2_op, 0, 0, 0, ldpte_op, mult_op), RS | RD}, 125ce807d5fSDavid Daney [insn_ldx] = {M(spec3_op, 0, 0, 0, ldx_op, lx_op), RS | RT | RD}, 126ce807d5fSDavid Daney [insn_lh] = {M(lh_op, 0, 0, 0, 0, 0), RS | RT | SIMM}, 127ce807d5fSDavid Daney [insn_lhu] = {M(lhu_op, 0, 0, 0, 0, 0), RS | RT | SIMM}, 128a168b8f1SLeonid Yegoshin #ifndef CONFIG_CPU_MIPSR6 129ce807d5fSDavid Daney [insn_ll] = {M(ll_op, 0, 0, 0, 0, 0), RS | RT | SIMM}, 130ce807d5fSDavid Daney [insn_lld] = {M(lld_op, 0, 0, 0, 0, 0), RS | RT | SIMM}, 131a168b8f1SLeonid Yegoshin #else 132ce807d5fSDavid Daney [insn_ll] = {M6(spec3_op, 0, 0, 0, ll6_op), RS | RT | SIMM9}, 133ce807d5fSDavid Daney [insn_lld] = {M6(spec3_op, 0, 0, 0, lld6_op), RS | RT | SIMM9}, 134a168b8f1SLeonid Yegoshin #endif 135ce807d5fSDavid Daney [insn_lui] = {M(lui_op, 0, 0, 0, 0, 0), RT | SIMM}, 136ce807d5fSDavid Daney [insn_lw] = {M(lw_op, 0, 0, 0, 0, 0), RS | RT | SIMM}, 137dc190129SDavid Daney [insn_lwu] = {M(lwu_op, 0, 0, 0, 0, 0), RS | RT | SIMM}, 138ce807d5fSDavid Daney [insn_lwx] = {M(spec3_op, 0, 0, 0, lwx_op, lx_op), RS | RT | RD}, 139ce807d5fSDavid Daney [insn_mfc0] = {M(cop0_op, mfc_op, 0, 0, 0, 0), RT | RD | SET}, 140ce807d5fSDavid Daney [insn_mfhc0] = {M(cop0_op, mfhc0_op, 0, 0, 0, 0), RT | RD | SET}, 141ce807d5fSDavid Daney [insn_mfhi] = {M(spec_op, 0, 0, 0, 0, mfhi_op), RD}, 142ce807d5fSDavid Daney [insn_mflo] = {M(spec_op, 0, 0, 0, 0, mflo_op), RD}, 143*0d1d17b9SHassan Naveed [insn_modu] = {M(spec_op, 0, 0, 0, divu_modu_op, divu_op), 144*0d1d17b9SHassan Naveed RS | RT | RD}, 145dc190129SDavid Daney [insn_movn] = {M(spec_op, 0, 0, 0, 0, movn_op), RS | RT | RD}, 146dc190129SDavid Daney [insn_movz] = {M(spec_op, 0, 0, 0, 0, movz_op), RS | RT | RD}, 147ce807d5fSDavid Daney [insn_mtc0] = {M(cop0_op, mtc_op, 0, 0, 0, 0), RT | RD | SET}, 148ce807d5fSDavid Daney [insn_mthc0] = {M(cop0_op, mthc0_op, 0, 0, 0, 0), RT | RD | SET}, 149ce807d5fSDavid Daney [insn_mthi] = {M(spec_op, 0, 0, 0, 0, mthi_op), RS}, 150ce807d5fSDavid Daney [insn_mtlo] = {M(spec_op, 0, 0, 0, 0, mtlo_op), RS}, 151*0d1d17b9SHassan Naveed [insn_mulu] = {M(spec_op, 0, 0, 0, multu_mulu_op, multu_op), 152*0d1d17b9SHassan Naveed RS | RT | RD}, 1536f63405cSJames Hogan #ifndef CONFIG_CPU_MIPSR6 154ce807d5fSDavid Daney [insn_mul] = {M(spec2_op, 0, 0, 0, 0, mul_op), RS | RT | RD}, 1556f63405cSJames Hogan #else 156ce807d5fSDavid Daney [insn_mul] = {M(spec_op, 0, 0, 0, mult_mul_op, mult_op), RS | RT | RD}, 1576f63405cSJames Hogan #endif 158dc190129SDavid Daney [insn_multu] = {M(spec_op, 0, 0, 0, 0, multu_op), RS | RT}, 159dc190129SDavid Daney [insn_nor] = {M(spec_op, 0, 0, 0, 0, nor_op), RS | RT | RD}, 160ce807d5fSDavid Daney [insn_or] = {M(spec_op, 0, 0, 0, 0, or_op), RS | RT | RD}, 161ce807d5fSDavid Daney [insn_ori] = {M(ori_op, 0, 0, 0, 0, 0), RS | RT | UIMM}, 162a168b8f1SLeonid Yegoshin #ifndef CONFIG_CPU_MIPSR6 163ce807d5fSDavid Daney [insn_pref] = {M(pref_op, 0, 0, 0, 0, 0), RS | RT | SIMM}, 164a168b8f1SLeonid Yegoshin #else 165ce807d5fSDavid Daney [insn_pref] = {M6(spec3_op, 0, 0, 0, pref6_op), RS | RT | SIMM9}, 166a168b8f1SLeonid Yegoshin #endif 167ce807d5fSDavid Daney [insn_rfe] = {M(cop0_op, cop_op, 0, 0, 0, rfe_op), 0}, 168ce807d5fSDavid Daney [insn_rotr] = {M(spec_op, 1, 0, 0, 0, srl_op), RT | RD | RE}, 169dc190129SDavid Daney [insn_sb] = {M(sb_op, 0, 0, 0, 0, 0), RS | RT | SIMM}, 170a168b8f1SLeonid Yegoshin #ifndef CONFIG_CPU_MIPSR6 171ce807d5fSDavid Daney [insn_sc] = {M(sc_op, 0, 0, 0, 0, 0), RS | RT | SIMM}, 172ce807d5fSDavid Daney [insn_scd] = {M(scd_op, 0, 0, 0, 0, 0), RS | RT | SIMM}, 173a168b8f1SLeonid Yegoshin #else 174ce807d5fSDavid Daney [insn_sc] = {M6(spec3_op, 0, 0, 0, sc6_op), RS | RT | SIMM9}, 175ce807d5fSDavid Daney [insn_scd] = {M6(spec3_op, 0, 0, 0, scd6_op), RS | RT | SIMM9}, 176a168b8f1SLeonid Yegoshin #endif 177ce807d5fSDavid Daney [insn_sd] = {M(sd_op, 0, 0, 0, 0, 0), RS | RT | SIMM}, 178*0d1d17b9SHassan Naveed [insn_seleqz] = {M(spec_op, 0, 0, 0, 0, seleqz_op), RS | RT | RD}, 179*0d1d17b9SHassan Naveed [insn_selnez] = {M(spec_op, 0, 0, 0, 0, selnez_op), RS | RT | RD}, 180dc190129SDavid Daney [insn_sh] = {M(sh_op, 0, 0, 0, 0, 0), RS | RT | SIMM}, 181ce807d5fSDavid Daney [insn_sll] = {M(spec_op, 0, 0, 0, 0, sll_op), RT | RD | RE}, 182ce807d5fSDavid Daney [insn_sllv] = {M(spec_op, 0, 0, 0, 0, sllv_op), RS | RT | RD}, 183ce807d5fSDavid Daney [insn_slt] = {M(spec_op, 0, 0, 0, 0, slt_op), RS | RT | RD}, 184dc190129SDavid Daney [insn_slti] = {M(slti_op, 0, 0, 0, 0, 0), RS | RT | SIMM}, 185ce807d5fSDavid Daney [insn_sltiu] = {M(sltiu_op, 0, 0, 0, 0, 0), RS | RT | SIMM}, 186ce807d5fSDavid Daney [insn_sltu] = {M(spec_op, 0, 0, 0, 0, sltu_op), RS | RT | RD}, 187ce807d5fSDavid Daney [insn_sra] = {M(spec_op, 0, 0, 0, 0, sra_op), RT | RD | RE}, 188ee94b90cSJiong Wang [insn_srav] = {M(spec_op, 0, 0, 0, 0, srav_op), RS | RT | RD}, 189ce807d5fSDavid Daney [insn_srl] = {M(spec_op, 0, 0, 0, 0, srl_op), RT | RD | RE}, 190ce807d5fSDavid Daney [insn_srlv] = {M(spec_op, 0, 0, 0, 0, srlv_op), RS | RT | RD}, 191ce807d5fSDavid Daney [insn_subu] = {M(spec_op, 0, 0, 0, 0, subu_op), RS | RT | RD}, 192ce807d5fSDavid Daney [insn_sw] = {M(sw_op, 0, 0, 0, 0, 0), RS | RT | SIMM}, 193ce807d5fSDavid Daney [insn_sync] = {M(spec_op, 0, 0, 0, 0, sync_op), RE}, 194ce807d5fSDavid Daney [insn_syscall] = {M(spec_op, 0, 0, 0, 0, syscall_op), SCIMM}, 195ce807d5fSDavid Daney [insn_tlbp] = {M(cop0_op, cop_op, 0, 0, 0, tlbp_op), 0}, 196ce807d5fSDavid Daney [insn_tlbr] = {M(cop0_op, cop_op, 0, 0, 0, tlbr_op), 0}, 197ce807d5fSDavid Daney [insn_tlbwi] = {M(cop0_op, cop_op, 0, 0, 0, tlbwi_op), 0}, 198ce807d5fSDavid Daney [insn_tlbwr] = {M(cop0_op, cop_op, 0, 0, 0, tlbwr_op), 0}, 199ce807d5fSDavid Daney [insn_wait] = {M(cop0_op, cop_op, 0, 0, 0, wait_op), SCIMM}, 200ce807d5fSDavid Daney [insn_wsbh] = {M(spec3_op, 0, 0, 0, wsbh_op, bshfl_op), RT | RD}, 201ce807d5fSDavid Daney [insn_xor] = {M(spec_op, 0, 0, 0, 0, xor_op), RS | RT | RD}, 202ce807d5fSDavid Daney [insn_xori] = {M(xori_op, 0, 0, 0, 0, 0), RS | RT | UIMM}, 203ce807d5fSDavid Daney [insn_yield] = {M(spec3_op, 0, 0, 0, 0, yield_op), RS | RD}, 204abc597feSSteven J. Hill }; 205abc597feSSteven J. Hill 206abc597feSSteven J. Hill #undef M 207abc597feSSteven J. Hill 208078a55fcSPaul Gortmaker static inline u32 build_bimm(s32 arg) 209abc597feSSteven J. Hill { 210abc597feSSteven J. Hill WARN(arg > 0x1ffff || arg < -0x20000, 211abc597feSSteven J. Hill KERN_WARNING "Micro-assembler field overflow\n"); 212abc597feSSteven J. Hill 213abc597feSSteven J. Hill WARN(arg & 0x3, KERN_WARNING "Invalid micro-assembler branch target\n"); 214abc597feSSteven J. Hill 215abc597feSSteven J. Hill return ((arg < 0) ? (1 << 15) : 0) | ((arg >> 2) & 0x7fff); 216abc597feSSteven J. Hill } 217abc597feSSteven J. Hill 218078a55fcSPaul Gortmaker static inline u32 build_jimm(u32 arg) 219abc597feSSteven J. Hill { 220abc597feSSteven J. Hill WARN(arg & ~(JIMM_MASK << 2), 221abc597feSSteven J. Hill KERN_WARNING "Micro-assembler field overflow\n"); 222abc597feSSteven J. Hill 223abc597feSSteven J. Hill return (arg >> 2) & JIMM_MASK; 224abc597feSSteven J. Hill } 225abc597feSSteven J. Hill 226abc597feSSteven J. Hill /* 227abc597feSSteven J. Hill * The order of opcode arguments is implicitly left to right, 228abc597feSSteven J. Hill * starting with RS and ending with FUNC or IMM. 229abc597feSSteven J. Hill */ 230078a55fcSPaul Gortmaker static void build_insn(u32 **buf, enum opcode opc, ...) 231abc597feSSteven J. Hill { 232ce807d5fSDavid Daney const struct insn *ip; 233abc597feSSteven J. Hill va_list ap; 234abc597feSSteven J. Hill u32 op; 235abc597feSSteven J. Hill 236ce807d5fSDavid Daney if (opc < 0 || opc >= insn_invalid || 237ce807d5fSDavid Daney (opc == insn_daddiu && r4k_daddiu_bug()) || 238ce807d5fSDavid Daney (insn_table[opc].match == 0 && insn_table[opc].fields == 0)) 239abc597feSSteven J. Hill panic("Unsupported Micro-assembler instruction %d", opc); 240abc597feSSteven J. Hill 241ce807d5fSDavid Daney ip = &insn_table[opc]; 242ce807d5fSDavid Daney 243abc597feSSteven J. Hill op = ip->match; 244abc597feSSteven J. Hill va_start(ap, opc); 245abc597feSSteven J. Hill if (ip->fields & RS) 246abc597feSSteven J. Hill op |= build_rs(va_arg(ap, u32)); 247abc597feSSteven J. Hill if (ip->fields & RT) 248abc597feSSteven J. Hill op |= build_rt(va_arg(ap, u32)); 249abc597feSSteven J. Hill if (ip->fields & RD) 250abc597feSSteven J. Hill op |= build_rd(va_arg(ap, u32)); 251abc597feSSteven J. Hill if (ip->fields & RE) 252abc597feSSteven J. Hill op |= build_re(va_arg(ap, u32)); 253abc597feSSteven J. Hill if (ip->fields & SIMM) 254abc597feSSteven J. Hill op |= build_simm(va_arg(ap, s32)); 255abc597feSSteven J. Hill if (ip->fields & UIMM) 256abc597feSSteven J. Hill op |= build_uimm(va_arg(ap, u32)); 257abc597feSSteven J. Hill if (ip->fields & BIMM) 258abc597feSSteven J. Hill op |= build_bimm(va_arg(ap, s32)); 259abc597feSSteven J. Hill if (ip->fields & JIMM) 260abc597feSSteven J. Hill op |= build_jimm(va_arg(ap, u32)); 261abc597feSSteven J. Hill if (ip->fields & FUNC) 262abc597feSSteven J. Hill op |= build_func(va_arg(ap, u32)); 263abc597feSSteven J. Hill if (ip->fields & SET) 264abc597feSSteven J. Hill op |= build_set(va_arg(ap, u32)); 265abc597feSSteven J. Hill if (ip->fields & SCIMM) 266abc597feSSteven J. Hill op |= build_scimm(va_arg(ap, u32)); 267a168b8f1SLeonid Yegoshin if (ip->fields & SIMM9) 268a168b8f1SLeonid Yegoshin op |= build_scimm9(va_arg(ap, u32)); 269abc597feSSteven J. Hill va_end(ap); 270abc597feSSteven J. Hill 271abc597feSSteven J. Hill **buf = op; 272abc597feSSteven J. Hill (*buf)++; 273abc597feSSteven J. Hill } 274abc597feSSteven J. Hill 275078a55fcSPaul Gortmaker static inline void 276abc597feSSteven J. Hill __resolve_relocs(struct uasm_reloc *rel, struct uasm_label *lab) 277abc597feSSteven J. Hill { 278abc597feSSteven J. Hill long laddr = (long)lab->addr; 279abc597feSSteven J. Hill long raddr = (long)rel->addr; 280abc597feSSteven J. Hill 281abc597feSSteven J. Hill switch (rel->type) { 282abc597feSSteven J. Hill case R_MIPS_PC16: 283abc597feSSteven J. Hill *rel->addr |= build_bimm(laddr - (raddr + 4)); 284abc597feSSteven J. Hill break; 285abc597feSSteven J. Hill 286abc597feSSteven J. Hill default: 287abc597feSSteven J. Hill panic("Unsupported Micro-assembler relocation %d", 288abc597feSSteven J. Hill rel->type); 289abc597feSSteven J. Hill } 290abc597feSSteven J. Hill } 291