1 /* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * Synthesize TLB refill handlers at runtime. 7 * 8 * Copyright (C) 2004, 2005, 2006, 2008 Thiemo Seufer 9 * Copyright (C) 2005, 2007, 2008, 2009 Maciej W. Rozycki 10 * Copyright (C) 2006 Ralf Baechle (ralf@linux-mips.org) 11 * Copyright (C) 2008, 2009 Cavium Networks, Inc. 12 * Copyright (C) 2011 MIPS Technologies, Inc. 13 * 14 * ... and the days got worse and worse and now you see 15 * I've gone completely out of my mind. 16 * 17 * They're coming to take me a away haha 18 * they're coming to take me a away hoho hihi haha 19 * to the funny farm where code is beautiful all the time ... 20 * 21 * (Condolences to Napoleon XIV) 22 */ 23 24 #include <linux/bug.h> 25 #include <linux/export.h> 26 #include <linux/kernel.h> 27 #include <linux/types.h> 28 #include <linux/smp.h> 29 #include <linux/string.h> 30 #include <linux/cache.h> 31 #include <linux/pgtable.h> 32 33 #include <asm/cacheflush.h> 34 #include <asm/cpu-type.h> 35 #include <asm/mmu_context.h> 36 #include <asm/war.h> 37 #include <asm/uasm.h> 38 #include <asm/setup.h> 39 #include <asm/tlbex.h> 40 41 static int mips_xpa_disabled; 42 43 static int __init xpa_disable(char *s) 44 { 45 mips_xpa_disabled = 1; 46 47 return 1; 48 } 49 50 __setup("noxpa", xpa_disable); 51 52 /* 53 * TLB load/store/modify handlers. 54 * 55 * Only the fastpath gets synthesized at runtime, the slowpath for 56 * do_page_fault remains normal asm. 57 */ 58 extern void tlb_do_page_fault_0(void); 59 extern void tlb_do_page_fault_1(void); 60 61 struct work_registers { 62 int r1; 63 int r2; 64 int r3; 65 }; 66 67 struct tlb_reg_save { 68 unsigned long a; 69 unsigned long b; 70 } ____cacheline_aligned_in_smp; 71 72 static struct tlb_reg_save handler_reg_save[NR_CPUS]; 73 74 static inline int r45k_bvahwbug(void) 75 { 76 /* XXX: We should probe for the presence of this bug, but we don't. */ 77 return 0; 78 } 79 80 static inline int r4k_250MHZhwbug(void) 81 { 82 /* XXX: We should probe for the presence of this bug, but we don't. */ 83 return 0; 84 } 85 86 extern int sb1250_m3_workaround_needed(void); 87 88 static inline int __maybe_unused bcm1250_m3_war(void) 89 { 90 if (IS_ENABLED(CONFIG_SB1_PASS_2_WORKAROUNDS)) 91 return sb1250_m3_workaround_needed(); 92 return 0; 93 } 94 95 static inline int __maybe_unused r10000_llsc_war(void) 96 { 97 return IS_ENABLED(CONFIG_WAR_R10000_LLSC); 98 } 99 100 static int use_bbit_insns(void) 101 { 102 switch (current_cpu_type()) { 103 case CPU_CAVIUM_OCTEON: 104 case CPU_CAVIUM_OCTEON_PLUS: 105 case CPU_CAVIUM_OCTEON2: 106 case CPU_CAVIUM_OCTEON3: 107 return 1; 108 default: 109 return 0; 110 } 111 } 112 113 static int use_lwx_insns(void) 114 { 115 switch (current_cpu_type()) { 116 case CPU_CAVIUM_OCTEON2: 117 case CPU_CAVIUM_OCTEON3: 118 return 1; 119 default: 120 return 0; 121 } 122 } 123 #if defined(CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE) && \ 124 CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE > 0 125 static bool scratchpad_available(void) 126 { 127 return true; 128 } 129 static int scratchpad_offset(int i) 130 { 131 /* 132 * CVMSEG starts at address -32768 and extends for 133 * CAVIUM_OCTEON_CVMSEG_SIZE 128 byte cache lines. 134 */ 135 i += 1; /* Kernel use starts at the top and works down. */ 136 return CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE * 128 - (8 * i) - 32768; 137 } 138 #else 139 static bool scratchpad_available(void) 140 { 141 return false; 142 } 143 static int scratchpad_offset(int i) 144 { 145 BUG(); 146 /* Really unreachable, but evidently some GCC want this. */ 147 return 0; 148 } 149 #endif 150 /* 151 * Found by experiment: At least some revisions of the 4kc throw under 152 * some circumstances a machine check exception, triggered by invalid 153 * values in the index register. Delaying the tlbp instruction until 154 * after the next branch, plus adding an additional nop in front of 155 * tlbwi/tlbwr avoids the invalid index register values. Nobody knows 156 * why; it's not an issue caused by the core RTL. 157 * 158 */ 159 static int m4kc_tlbp_war(void) 160 { 161 return current_cpu_type() == CPU_4KC; 162 } 163 164 /* Handle labels (which must be positive integers). */ 165 enum label_id { 166 label_second_part = 1, 167 label_leave, 168 label_vmalloc, 169 label_vmalloc_done, 170 label_tlbw_hazard_0, 171 label_split = label_tlbw_hazard_0 + 8, 172 label_tlbl_goaround1, 173 label_tlbl_goaround2, 174 label_nopage_tlbl, 175 label_nopage_tlbs, 176 label_nopage_tlbm, 177 label_smp_pgtable_change, 178 label_r3000_write_probe_fail, 179 label_large_segbits_fault, 180 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT 181 label_tlb_huge_update, 182 #endif 183 }; 184 185 UASM_L_LA(_second_part) 186 UASM_L_LA(_leave) 187 UASM_L_LA(_vmalloc) 188 UASM_L_LA(_vmalloc_done) 189 /* _tlbw_hazard_x is handled differently. */ 190 UASM_L_LA(_split) 191 UASM_L_LA(_tlbl_goaround1) 192 UASM_L_LA(_tlbl_goaround2) 193 UASM_L_LA(_nopage_tlbl) 194 UASM_L_LA(_nopage_tlbs) 195 UASM_L_LA(_nopage_tlbm) 196 UASM_L_LA(_smp_pgtable_change) 197 UASM_L_LA(_r3000_write_probe_fail) 198 UASM_L_LA(_large_segbits_fault) 199 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT 200 UASM_L_LA(_tlb_huge_update) 201 #endif 202 203 static int hazard_instance; 204 205 static void uasm_bgezl_hazard(u32 **p, struct uasm_reloc **r, int instance) 206 { 207 switch (instance) { 208 case 0 ... 7: 209 uasm_il_bgezl(p, r, 0, label_tlbw_hazard_0 + instance); 210 return; 211 default: 212 BUG(); 213 } 214 } 215 216 static void uasm_bgezl_label(struct uasm_label **l, u32 **p, int instance) 217 { 218 switch (instance) { 219 case 0 ... 7: 220 uasm_build_label(l, *p, label_tlbw_hazard_0 + instance); 221 break; 222 default: 223 BUG(); 224 } 225 } 226 227 /* 228 * pgtable bits are assigned dynamically depending on processor feature 229 * and statically based on kernel configuration. This spits out the actual 230 * values the kernel is using. Required to make sense from disassembled 231 * TLB exception handlers. 232 */ 233 static void output_pgtable_bits_defines(void) 234 { 235 #define pr_define(fmt, ...) \ 236 pr_debug("#define " fmt, ##__VA_ARGS__) 237 238 pr_debug("#include <asm/asm.h>\n"); 239 pr_debug("#include <asm/regdef.h>\n"); 240 pr_debug("\n"); 241 242 pr_define("_PAGE_PRESENT_SHIFT %d\n", _PAGE_PRESENT_SHIFT); 243 pr_define("_PAGE_NO_READ_SHIFT %d\n", _PAGE_NO_READ_SHIFT); 244 pr_define("_PAGE_WRITE_SHIFT %d\n", _PAGE_WRITE_SHIFT); 245 pr_define("_PAGE_ACCESSED_SHIFT %d\n", _PAGE_ACCESSED_SHIFT); 246 pr_define("_PAGE_MODIFIED_SHIFT %d\n", _PAGE_MODIFIED_SHIFT); 247 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT 248 pr_define("_PAGE_HUGE_SHIFT %d\n", _PAGE_HUGE_SHIFT); 249 #endif 250 #ifdef _PAGE_NO_EXEC_SHIFT 251 if (cpu_has_rixi) 252 pr_define("_PAGE_NO_EXEC_SHIFT %d\n", _PAGE_NO_EXEC_SHIFT); 253 #endif 254 pr_define("_PAGE_GLOBAL_SHIFT %d\n", _PAGE_GLOBAL_SHIFT); 255 pr_define("_PAGE_VALID_SHIFT %d\n", _PAGE_VALID_SHIFT); 256 pr_define("_PAGE_DIRTY_SHIFT %d\n", _PAGE_DIRTY_SHIFT); 257 pr_define("_PFN_SHIFT %d\n", _PFN_SHIFT); 258 pr_debug("\n"); 259 } 260 261 static inline void dump_handler(const char *symbol, const void *start, const void *end) 262 { 263 unsigned int count = (end - start) / sizeof(u32); 264 const u32 *handler = start; 265 int i; 266 267 pr_debug("LEAF(%s)\n", symbol); 268 269 pr_debug("\t.set push\n"); 270 pr_debug("\t.set noreorder\n"); 271 272 for (i = 0; i < count; i++) 273 pr_debug("\t.word\t0x%08x\t\t# %p\n", handler[i], &handler[i]); 274 275 pr_debug("\t.set\tpop\n"); 276 277 pr_debug("\tEND(%s)\n", symbol); 278 } 279 280 /* The only general purpose registers allowed in TLB handlers. */ 281 #define K0 26 282 #define K1 27 283 284 /* Some CP0 registers */ 285 #define C0_INDEX 0, 0 286 #define C0_ENTRYLO0 2, 0 287 #define C0_TCBIND 2, 2 288 #define C0_ENTRYLO1 3, 0 289 #define C0_CONTEXT 4, 0 290 #define C0_PAGEMASK 5, 0 291 #define C0_PWBASE 5, 5 292 #define C0_PWFIELD 5, 6 293 #define C0_PWSIZE 5, 7 294 #define C0_PWCTL 6, 6 295 #define C0_BADVADDR 8, 0 296 #define C0_PGD 9, 7 297 #define C0_ENTRYHI 10, 0 298 #define C0_EPC 14, 0 299 #define C0_XCONTEXT 20, 0 300 301 #ifdef CONFIG_64BIT 302 # define GET_CONTEXT(buf, reg) UASM_i_MFC0(buf, reg, C0_XCONTEXT) 303 #else 304 # define GET_CONTEXT(buf, reg) UASM_i_MFC0(buf, reg, C0_CONTEXT) 305 #endif 306 307 /* The worst case length of the handler is around 18 instructions for 308 * R3000-style TLBs and up to 63 instructions for R4000-style TLBs. 309 * Maximum space available is 32 instructions for R3000 and 64 310 * instructions for R4000. 311 * 312 * We deliberately chose a buffer size of 128, so we won't scribble 313 * over anything important on overflow before we panic. 314 */ 315 static u32 tlb_handler[128]; 316 317 /* simply assume worst case size for labels and relocs */ 318 static struct uasm_label labels[128]; 319 static struct uasm_reloc relocs[128]; 320 321 static int check_for_high_segbits; 322 static bool fill_includes_sw_bits; 323 324 static unsigned int kscratch_used_mask; 325 326 static inline int __maybe_unused c0_kscratch(void) 327 { 328 return 31; 329 } 330 331 static int allocate_kscratch(void) 332 { 333 int r; 334 unsigned int a = cpu_data[0].kscratch_mask & ~kscratch_used_mask; 335 336 r = ffs(a); 337 338 if (r == 0) 339 return -1; 340 341 r--; /* make it zero based */ 342 343 kscratch_used_mask |= (1 << r); 344 345 return r; 346 } 347 348 static int scratch_reg; 349 int pgd_reg; 350 EXPORT_SYMBOL_GPL(pgd_reg); 351 enum vmalloc64_mode {not_refill, refill_scratch, refill_noscratch}; 352 353 static struct work_registers build_get_work_registers(u32 **p) 354 { 355 struct work_registers r; 356 357 if (scratch_reg >= 0) { 358 /* Save in CPU local C0_KScratch? */ 359 UASM_i_MTC0(p, 1, c0_kscratch(), scratch_reg); 360 r.r1 = K0; 361 r.r2 = K1; 362 r.r3 = 1; 363 return r; 364 } 365 366 if (num_possible_cpus() > 1) { 367 /* Get smp_processor_id */ 368 UASM_i_CPUID_MFC0(p, K0, SMP_CPUID_REG); 369 UASM_i_SRL_SAFE(p, K0, K0, SMP_CPUID_REGSHIFT); 370 371 /* handler_reg_save index in K0 */ 372 UASM_i_SLL(p, K0, K0, ilog2(sizeof(struct tlb_reg_save))); 373 374 UASM_i_LA(p, K1, (long)&handler_reg_save); 375 UASM_i_ADDU(p, K0, K0, K1); 376 } else { 377 UASM_i_LA(p, K0, (long)&handler_reg_save); 378 } 379 /* K0 now points to save area, save $1 and $2 */ 380 UASM_i_SW(p, 1, offsetof(struct tlb_reg_save, a), K0); 381 UASM_i_SW(p, 2, offsetof(struct tlb_reg_save, b), K0); 382 383 r.r1 = K1; 384 r.r2 = 1; 385 r.r3 = 2; 386 return r; 387 } 388 389 static void build_restore_work_registers(u32 **p) 390 { 391 if (scratch_reg >= 0) { 392 uasm_i_ehb(p); 393 UASM_i_MFC0(p, 1, c0_kscratch(), scratch_reg); 394 return; 395 } 396 /* K0 already points to save area, restore $1 and $2 */ 397 UASM_i_LW(p, 1, offsetof(struct tlb_reg_save, a), K0); 398 UASM_i_LW(p, 2, offsetof(struct tlb_reg_save, b), K0); 399 } 400 401 #ifndef CONFIG_MIPS_PGD_C0_CONTEXT 402 403 /* 404 * CONFIG_MIPS_PGD_C0_CONTEXT implies 64 bit and lack of pgd_current, 405 * we cannot do r3000 under these circumstances. 406 * 407 * The R3000 TLB handler is simple. 408 */ 409 static void build_r3000_tlb_refill_handler(void) 410 { 411 long pgdc = (long)pgd_current; 412 u32 *p; 413 414 memset(tlb_handler, 0, sizeof(tlb_handler)); 415 p = tlb_handler; 416 417 uasm_i_mfc0(&p, K0, C0_BADVADDR); 418 uasm_i_lui(&p, K1, uasm_rel_hi(pgdc)); /* cp0 delay */ 419 uasm_i_lw(&p, K1, uasm_rel_lo(pgdc), K1); 420 uasm_i_srl(&p, K0, K0, 22); /* load delay */ 421 uasm_i_sll(&p, K0, K0, 2); 422 uasm_i_addu(&p, K1, K1, K0); 423 uasm_i_mfc0(&p, K0, C0_CONTEXT); 424 uasm_i_lw(&p, K1, 0, K1); /* cp0 delay */ 425 uasm_i_andi(&p, K0, K0, 0xffc); /* load delay */ 426 uasm_i_addu(&p, K1, K1, K0); 427 uasm_i_lw(&p, K0, 0, K1); 428 uasm_i_nop(&p); /* load delay */ 429 uasm_i_mtc0(&p, K0, C0_ENTRYLO0); 430 uasm_i_mfc0(&p, K1, C0_EPC); /* cp0 delay */ 431 uasm_i_tlbwr(&p); /* cp0 delay */ 432 uasm_i_jr(&p, K1); 433 uasm_i_rfe(&p); /* branch delay */ 434 435 if (p > tlb_handler + 32) 436 panic("TLB refill handler space exceeded"); 437 438 pr_debug("Wrote TLB refill handler (%u instructions).\n", 439 (unsigned int)(p - tlb_handler)); 440 441 memcpy((void *)ebase, tlb_handler, 0x80); 442 local_flush_icache_range(ebase, ebase + 0x80); 443 dump_handler("r3000_tlb_refill", (u32 *)ebase, (u32 *)(ebase + 0x80)); 444 } 445 #endif /* CONFIG_MIPS_PGD_C0_CONTEXT */ 446 447 /* 448 * The R4000 TLB handler is much more complicated. We have two 449 * consecutive handler areas with 32 instructions space each. 450 * Since they aren't used at the same time, we can overflow in the 451 * other one.To keep things simple, we first assume linear space, 452 * then we relocate it to the final handler layout as needed. 453 */ 454 static u32 final_handler[64]; 455 456 /* 457 * Hazards 458 * 459 * From the IDT errata for the QED RM5230 (Nevada), processor revision 1.0: 460 * 2. A timing hazard exists for the TLBP instruction. 461 * 462 * stalling_instruction 463 * TLBP 464 * 465 * The JTLB is being read for the TLBP throughout the stall generated by the 466 * previous instruction. This is not really correct as the stalling instruction 467 * can modify the address used to access the JTLB. The failure symptom is that 468 * the TLBP instruction will use an address created for the stalling instruction 469 * and not the address held in C0_ENHI and thus report the wrong results. 470 * 471 * The software work-around is to not allow the instruction preceding the TLBP 472 * to stall - make it an NOP or some other instruction guaranteed not to stall. 473 * 474 * Errata 2 will not be fixed. This errata is also on the R5000. 475 * 476 * As if we MIPS hackers wouldn't know how to nop pipelines happy ... 477 */ 478 static void __maybe_unused build_tlb_probe_entry(u32 **p) 479 { 480 switch (current_cpu_type()) { 481 /* Found by experiment: R4600 v2.0/R4700 needs this, too. */ 482 case CPU_R4600: 483 case CPU_R4700: 484 case CPU_R5000: 485 case CPU_NEVADA: 486 uasm_i_nop(p); 487 uasm_i_tlbp(p); 488 break; 489 490 default: 491 uasm_i_tlbp(p); 492 break; 493 } 494 } 495 496 void build_tlb_write_entry(u32 **p, struct uasm_label **l, 497 struct uasm_reloc **r, 498 enum tlb_write_entry wmode) 499 { 500 void(*tlbw)(u32 **) = NULL; 501 502 switch (wmode) { 503 case tlb_random: tlbw = uasm_i_tlbwr; break; 504 case tlb_indexed: tlbw = uasm_i_tlbwi; break; 505 } 506 507 if (cpu_has_mips_r2_r6) { 508 if (cpu_has_mips_r2_exec_hazard) 509 uasm_i_ehb(p); 510 tlbw(p); 511 return; 512 } 513 514 switch (current_cpu_type()) { 515 case CPU_R4000PC: 516 case CPU_R4000SC: 517 case CPU_R4000MC: 518 case CPU_R4400PC: 519 case CPU_R4400SC: 520 case CPU_R4400MC: 521 /* 522 * This branch uses up a mtc0 hazard nop slot and saves 523 * two nops after the tlbw instruction. 524 */ 525 uasm_bgezl_hazard(p, r, hazard_instance); 526 tlbw(p); 527 uasm_bgezl_label(l, p, hazard_instance); 528 hazard_instance++; 529 uasm_i_nop(p); 530 break; 531 532 case CPU_R4600: 533 case CPU_R4700: 534 uasm_i_nop(p); 535 tlbw(p); 536 uasm_i_nop(p); 537 break; 538 539 case CPU_R5000: 540 case CPU_NEVADA: 541 uasm_i_nop(p); /* QED specifies 2 nops hazard */ 542 uasm_i_nop(p); /* QED specifies 2 nops hazard */ 543 tlbw(p); 544 break; 545 546 case CPU_R4300: 547 case CPU_5KC: 548 case CPU_TX49XX: 549 case CPU_PR4450: 550 uasm_i_nop(p); 551 tlbw(p); 552 break; 553 554 case CPU_R10000: 555 case CPU_R12000: 556 case CPU_R14000: 557 case CPU_R16000: 558 case CPU_4KC: 559 case CPU_4KEC: 560 case CPU_M14KC: 561 case CPU_M14KEC: 562 case CPU_SB1: 563 case CPU_SB1A: 564 case CPU_4KSC: 565 case CPU_20KC: 566 case CPU_25KF: 567 case CPU_BMIPS32: 568 case CPU_BMIPS3300: 569 case CPU_BMIPS4350: 570 case CPU_BMIPS4380: 571 case CPU_BMIPS5000: 572 case CPU_LOONGSON2EF: 573 case CPU_LOONGSON64: 574 case CPU_R5500: 575 if (m4kc_tlbp_war()) 576 uasm_i_nop(p); 577 fallthrough; 578 case CPU_ALCHEMY: 579 tlbw(p); 580 break; 581 582 case CPU_RM7000: 583 uasm_i_nop(p); 584 uasm_i_nop(p); 585 uasm_i_nop(p); 586 uasm_i_nop(p); 587 tlbw(p); 588 break; 589 590 case CPU_VR4111: 591 case CPU_VR4121: 592 case CPU_VR4122: 593 case CPU_VR4181: 594 case CPU_VR4181A: 595 uasm_i_nop(p); 596 uasm_i_nop(p); 597 tlbw(p); 598 uasm_i_nop(p); 599 uasm_i_nop(p); 600 break; 601 602 case CPU_VR4131: 603 case CPU_VR4133: 604 uasm_i_nop(p); 605 uasm_i_nop(p); 606 tlbw(p); 607 break; 608 609 case CPU_XBURST: 610 tlbw(p); 611 uasm_i_nop(p); 612 break; 613 614 default: 615 panic("No TLB refill handler yet (CPU type: %d)", 616 current_cpu_type()); 617 break; 618 } 619 } 620 EXPORT_SYMBOL_GPL(build_tlb_write_entry); 621 622 static __maybe_unused void build_convert_pte_to_entrylo(u32 **p, 623 unsigned int reg) 624 { 625 if (_PAGE_GLOBAL_SHIFT == 0) { 626 /* pte_t is already in EntryLo format */ 627 return; 628 } 629 630 if (cpu_has_rixi && !!_PAGE_NO_EXEC) { 631 if (fill_includes_sw_bits) { 632 UASM_i_ROTR(p, reg, reg, ilog2(_PAGE_GLOBAL)); 633 } else { 634 UASM_i_SRL(p, reg, reg, ilog2(_PAGE_NO_EXEC)); 635 UASM_i_ROTR(p, reg, reg, 636 ilog2(_PAGE_GLOBAL) - ilog2(_PAGE_NO_EXEC)); 637 } 638 } else { 639 #ifdef CONFIG_PHYS_ADDR_T_64BIT 640 uasm_i_dsrl_safe(p, reg, reg, ilog2(_PAGE_GLOBAL)); 641 #else 642 UASM_i_SRL(p, reg, reg, ilog2(_PAGE_GLOBAL)); 643 #endif 644 } 645 } 646 647 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT 648 649 static void build_restore_pagemask(u32 **p, struct uasm_reloc **r, 650 unsigned int tmp, enum label_id lid, 651 int restore_scratch) 652 { 653 if (restore_scratch) { 654 /* 655 * Ensure the MFC0 below observes the value written to the 656 * KScratch register by the prior MTC0. 657 */ 658 if (scratch_reg >= 0) 659 uasm_i_ehb(p); 660 661 /* Reset default page size */ 662 if (PM_DEFAULT_MASK >> 16) { 663 uasm_i_lui(p, tmp, PM_DEFAULT_MASK >> 16); 664 uasm_i_ori(p, tmp, tmp, PM_DEFAULT_MASK & 0xffff); 665 uasm_i_mtc0(p, tmp, C0_PAGEMASK); 666 uasm_il_b(p, r, lid); 667 } else if (PM_DEFAULT_MASK) { 668 uasm_i_ori(p, tmp, 0, PM_DEFAULT_MASK); 669 uasm_i_mtc0(p, tmp, C0_PAGEMASK); 670 uasm_il_b(p, r, lid); 671 } else { 672 uasm_i_mtc0(p, 0, C0_PAGEMASK); 673 uasm_il_b(p, r, lid); 674 } 675 if (scratch_reg >= 0) 676 UASM_i_MFC0(p, 1, c0_kscratch(), scratch_reg); 677 else 678 UASM_i_LW(p, 1, scratchpad_offset(0), 0); 679 } else { 680 /* Reset default page size */ 681 if (PM_DEFAULT_MASK >> 16) { 682 uasm_i_lui(p, tmp, PM_DEFAULT_MASK >> 16); 683 uasm_i_ori(p, tmp, tmp, PM_DEFAULT_MASK & 0xffff); 684 uasm_il_b(p, r, lid); 685 uasm_i_mtc0(p, tmp, C0_PAGEMASK); 686 } else if (PM_DEFAULT_MASK) { 687 uasm_i_ori(p, tmp, 0, PM_DEFAULT_MASK); 688 uasm_il_b(p, r, lid); 689 uasm_i_mtc0(p, tmp, C0_PAGEMASK); 690 } else { 691 uasm_il_b(p, r, lid); 692 uasm_i_mtc0(p, 0, C0_PAGEMASK); 693 } 694 } 695 } 696 697 static void build_huge_tlb_write_entry(u32 **p, struct uasm_label **l, 698 struct uasm_reloc **r, 699 unsigned int tmp, 700 enum tlb_write_entry wmode, 701 int restore_scratch) 702 { 703 /* Set huge page tlb entry size */ 704 uasm_i_lui(p, tmp, PM_HUGE_MASK >> 16); 705 uasm_i_ori(p, tmp, tmp, PM_HUGE_MASK & 0xffff); 706 uasm_i_mtc0(p, tmp, C0_PAGEMASK); 707 708 build_tlb_write_entry(p, l, r, wmode); 709 710 build_restore_pagemask(p, r, tmp, label_leave, restore_scratch); 711 } 712 713 /* 714 * Check if Huge PTE is present, if so then jump to LABEL. 715 */ 716 static void 717 build_is_huge_pte(u32 **p, struct uasm_reloc **r, unsigned int tmp, 718 unsigned int pmd, int lid) 719 { 720 UASM_i_LW(p, tmp, 0, pmd); 721 if (use_bbit_insns()) { 722 uasm_il_bbit1(p, r, tmp, ilog2(_PAGE_HUGE), lid); 723 } else { 724 uasm_i_andi(p, tmp, tmp, _PAGE_HUGE); 725 uasm_il_bnez(p, r, tmp, lid); 726 } 727 } 728 729 static void build_huge_update_entries(u32 **p, unsigned int pte, 730 unsigned int tmp) 731 { 732 int small_sequence; 733 734 /* 735 * A huge PTE describes an area the size of the 736 * configured huge page size. This is twice the 737 * of the large TLB entry size we intend to use. 738 * A TLB entry half the size of the configured 739 * huge page size is configured into entrylo0 740 * and entrylo1 to cover the contiguous huge PTE 741 * address space. 742 */ 743 small_sequence = (HPAGE_SIZE >> 7) < 0x10000; 744 745 /* We can clobber tmp. It isn't used after this.*/ 746 if (!small_sequence) 747 uasm_i_lui(p, tmp, HPAGE_SIZE >> (7 + 16)); 748 749 build_convert_pte_to_entrylo(p, pte); 750 UASM_i_MTC0(p, pte, C0_ENTRYLO0); /* load it */ 751 /* convert to entrylo1 */ 752 if (small_sequence) 753 UASM_i_ADDIU(p, pte, pte, HPAGE_SIZE >> 7); 754 else 755 UASM_i_ADDU(p, pte, pte, tmp); 756 757 UASM_i_MTC0(p, pte, C0_ENTRYLO1); /* load it */ 758 } 759 760 static void build_huge_handler_tail(u32 **p, struct uasm_reloc **r, 761 struct uasm_label **l, 762 unsigned int pte, 763 unsigned int ptr, 764 unsigned int flush) 765 { 766 #ifdef CONFIG_SMP 767 UASM_i_SC(p, pte, 0, ptr); 768 uasm_il_beqz(p, r, pte, label_tlb_huge_update); 769 UASM_i_LW(p, pte, 0, ptr); /* Needed because SC killed our PTE */ 770 #else 771 UASM_i_SW(p, pte, 0, ptr); 772 #endif 773 if (cpu_has_ftlb && flush) { 774 BUG_ON(!cpu_has_tlbinv); 775 776 UASM_i_MFC0(p, ptr, C0_ENTRYHI); 777 uasm_i_ori(p, ptr, ptr, MIPS_ENTRYHI_EHINV); 778 UASM_i_MTC0(p, ptr, C0_ENTRYHI); 779 build_tlb_write_entry(p, l, r, tlb_indexed); 780 781 uasm_i_xori(p, ptr, ptr, MIPS_ENTRYHI_EHINV); 782 UASM_i_MTC0(p, ptr, C0_ENTRYHI); 783 build_huge_update_entries(p, pte, ptr); 784 build_huge_tlb_write_entry(p, l, r, pte, tlb_random, 0); 785 786 return; 787 } 788 789 build_huge_update_entries(p, pte, ptr); 790 build_huge_tlb_write_entry(p, l, r, pte, tlb_indexed, 0); 791 } 792 #endif /* CONFIG_MIPS_HUGE_TLB_SUPPORT */ 793 794 #ifdef CONFIG_64BIT 795 /* 796 * TMP and PTR are scratch. 797 * TMP will be clobbered, PTR will hold the pmd entry. 798 */ 799 void build_get_pmde64(u32 **p, struct uasm_label **l, struct uasm_reloc **r, 800 unsigned int tmp, unsigned int ptr) 801 { 802 #ifndef CONFIG_MIPS_PGD_C0_CONTEXT 803 long pgdc = (long)pgd_current; 804 #endif 805 /* 806 * The vmalloc handling is not in the hotpath. 807 */ 808 uasm_i_dmfc0(p, tmp, C0_BADVADDR); 809 810 if (check_for_high_segbits) { 811 /* 812 * The kernel currently implicitely assumes that the 813 * MIPS SEGBITS parameter for the processor is 814 * (PGDIR_SHIFT+PGDIR_BITS) or less, and will never 815 * allocate virtual addresses outside the maximum 816 * range for SEGBITS = (PGDIR_SHIFT+PGDIR_BITS). But 817 * that doesn't prevent user code from accessing the 818 * higher xuseg addresses. Here, we make sure that 819 * everything but the lower xuseg addresses goes down 820 * the module_alloc/vmalloc path. 821 */ 822 uasm_i_dsrl_safe(p, ptr, tmp, PGDIR_SHIFT + PGD_ORDER + PAGE_SHIFT - 3); 823 uasm_il_bnez(p, r, ptr, label_vmalloc); 824 } else { 825 uasm_il_bltz(p, r, tmp, label_vmalloc); 826 } 827 /* No uasm_i_nop needed here, since the next insn doesn't touch TMP. */ 828 829 if (pgd_reg != -1) { 830 /* pgd is in pgd_reg */ 831 if (cpu_has_ldpte) 832 UASM_i_MFC0(p, ptr, C0_PWBASE); 833 else 834 UASM_i_MFC0(p, ptr, c0_kscratch(), pgd_reg); 835 } else { 836 #if defined(CONFIG_MIPS_PGD_C0_CONTEXT) 837 /* 838 * &pgd << 11 stored in CONTEXT [23..63]. 839 */ 840 UASM_i_MFC0(p, ptr, C0_CONTEXT); 841 842 /* Clear lower 23 bits of context. */ 843 uasm_i_dins(p, ptr, 0, 0, 23); 844 845 /* insert bit[63:59] of CAC_BASE into bit[11:6] of ptr */ 846 uasm_i_ori(p, ptr, ptr, ((u64)(CAC_BASE) >> 53)); 847 uasm_i_drotr(p, ptr, ptr, 11); 848 #elif defined(CONFIG_SMP) 849 UASM_i_CPUID_MFC0(p, ptr, SMP_CPUID_REG); 850 uasm_i_dsrl_safe(p, ptr, ptr, SMP_CPUID_PTRSHIFT); 851 UASM_i_LA_mostly(p, tmp, pgdc); 852 uasm_i_daddu(p, ptr, ptr, tmp); 853 uasm_i_dmfc0(p, tmp, C0_BADVADDR); 854 uasm_i_ld(p, ptr, uasm_rel_lo(pgdc), ptr); 855 #else 856 UASM_i_LA_mostly(p, ptr, pgdc); 857 uasm_i_ld(p, ptr, uasm_rel_lo(pgdc), ptr); 858 #endif 859 } 860 861 uasm_l_vmalloc_done(l, *p); 862 863 /* get pgd offset in bytes */ 864 uasm_i_dsrl_safe(p, tmp, tmp, PGDIR_SHIFT - 3); 865 866 uasm_i_andi(p, tmp, tmp, (PTRS_PER_PGD - 1)<<3); 867 uasm_i_daddu(p, ptr, ptr, tmp); /* add in pgd offset */ 868 #ifndef __PAGETABLE_PUD_FOLDED 869 uasm_i_dmfc0(p, tmp, C0_BADVADDR); /* get faulting address */ 870 uasm_i_ld(p, ptr, 0, ptr); /* get pud pointer */ 871 uasm_i_dsrl_safe(p, tmp, tmp, PUD_SHIFT - 3); /* get pud offset in bytes */ 872 uasm_i_andi(p, tmp, tmp, (PTRS_PER_PUD - 1) << 3); 873 uasm_i_daddu(p, ptr, ptr, tmp); /* add in pud offset */ 874 #endif 875 #ifndef __PAGETABLE_PMD_FOLDED 876 uasm_i_dmfc0(p, tmp, C0_BADVADDR); /* get faulting address */ 877 uasm_i_ld(p, ptr, 0, ptr); /* get pmd pointer */ 878 uasm_i_dsrl_safe(p, tmp, tmp, PMD_SHIFT-3); /* get pmd offset in bytes */ 879 uasm_i_andi(p, tmp, tmp, (PTRS_PER_PMD - 1)<<3); 880 uasm_i_daddu(p, ptr, ptr, tmp); /* add in pmd offset */ 881 #endif 882 } 883 EXPORT_SYMBOL_GPL(build_get_pmde64); 884 885 /* 886 * BVADDR is the faulting address, PTR is scratch. 887 * PTR will hold the pgd for vmalloc. 888 */ 889 static void 890 build_get_pgd_vmalloc64(u32 **p, struct uasm_label **l, struct uasm_reloc **r, 891 unsigned int bvaddr, unsigned int ptr, 892 enum vmalloc64_mode mode) 893 { 894 long swpd = (long)swapper_pg_dir; 895 int single_insn_swpd; 896 int did_vmalloc_branch = 0; 897 898 single_insn_swpd = uasm_in_compat_space_p(swpd) && !uasm_rel_lo(swpd); 899 900 uasm_l_vmalloc(l, *p); 901 902 if (mode != not_refill && check_for_high_segbits) { 903 if (single_insn_swpd) { 904 uasm_il_bltz(p, r, bvaddr, label_vmalloc_done); 905 uasm_i_lui(p, ptr, uasm_rel_hi(swpd)); 906 did_vmalloc_branch = 1; 907 /* fall through */ 908 } else { 909 uasm_il_bgez(p, r, bvaddr, label_large_segbits_fault); 910 } 911 } 912 if (!did_vmalloc_branch) { 913 if (single_insn_swpd) { 914 uasm_il_b(p, r, label_vmalloc_done); 915 uasm_i_lui(p, ptr, uasm_rel_hi(swpd)); 916 } else { 917 UASM_i_LA_mostly(p, ptr, swpd); 918 uasm_il_b(p, r, label_vmalloc_done); 919 if (uasm_in_compat_space_p(swpd)) 920 uasm_i_addiu(p, ptr, ptr, uasm_rel_lo(swpd)); 921 else 922 uasm_i_daddiu(p, ptr, ptr, uasm_rel_lo(swpd)); 923 } 924 } 925 if (mode != not_refill && check_for_high_segbits) { 926 uasm_l_large_segbits_fault(l, *p); 927 928 if (mode == refill_scratch && scratch_reg >= 0) 929 uasm_i_ehb(p); 930 931 /* 932 * We get here if we are an xsseg address, or if we are 933 * an xuseg address above (PGDIR_SHIFT+PGDIR_BITS) boundary. 934 * 935 * Ignoring xsseg (assume disabled so would generate 936 * (address errors?), the only remaining possibility 937 * is the upper xuseg addresses. On processors with 938 * TLB_SEGBITS <= PGDIR_SHIFT+PGDIR_BITS, these 939 * addresses would have taken an address error. We try 940 * to mimic that here by taking a load/istream page 941 * fault. 942 */ 943 if (IS_ENABLED(CONFIG_CPU_LOONGSON3_WORKAROUNDS)) 944 uasm_i_sync(p, 0); 945 UASM_i_LA(p, ptr, (unsigned long)tlb_do_page_fault_0); 946 uasm_i_jr(p, ptr); 947 948 if (mode == refill_scratch) { 949 if (scratch_reg >= 0) 950 UASM_i_MFC0(p, 1, c0_kscratch(), scratch_reg); 951 else 952 UASM_i_LW(p, 1, scratchpad_offset(0), 0); 953 } else { 954 uasm_i_nop(p); 955 } 956 } 957 } 958 959 #else /* !CONFIG_64BIT */ 960 961 /* 962 * TMP and PTR are scratch. 963 * TMP will be clobbered, PTR will hold the pgd entry. 964 */ 965 void build_get_pgde32(u32 **p, unsigned int tmp, unsigned int ptr) 966 { 967 if (pgd_reg != -1) { 968 /* pgd is in pgd_reg */ 969 uasm_i_mfc0(p, ptr, c0_kscratch(), pgd_reg); 970 uasm_i_mfc0(p, tmp, C0_BADVADDR); /* get faulting address */ 971 } else { 972 long pgdc = (long)pgd_current; 973 974 /* 32 bit SMP has smp_processor_id() stored in CONTEXT. */ 975 #ifdef CONFIG_SMP 976 uasm_i_mfc0(p, ptr, SMP_CPUID_REG); 977 UASM_i_LA_mostly(p, tmp, pgdc); 978 uasm_i_srl(p, ptr, ptr, SMP_CPUID_PTRSHIFT); 979 uasm_i_addu(p, ptr, tmp, ptr); 980 #else 981 UASM_i_LA_mostly(p, ptr, pgdc); 982 #endif 983 uasm_i_mfc0(p, tmp, C0_BADVADDR); /* get faulting address */ 984 uasm_i_lw(p, ptr, uasm_rel_lo(pgdc), ptr); 985 } 986 uasm_i_srl(p, tmp, tmp, PGDIR_SHIFT); /* get pgd only bits */ 987 uasm_i_sll(p, tmp, tmp, PGD_T_LOG2); 988 uasm_i_addu(p, ptr, ptr, tmp); /* add in pgd offset */ 989 } 990 EXPORT_SYMBOL_GPL(build_get_pgde32); 991 992 #endif /* !CONFIG_64BIT */ 993 994 static void build_adjust_context(u32 **p, unsigned int ctx) 995 { 996 unsigned int shift = 4 - (PTE_T_LOG2 + 1) + PAGE_SHIFT - 12; 997 unsigned int mask = (PTRS_PER_PTE / 2 - 1) << (PTE_T_LOG2 + 1); 998 999 switch (current_cpu_type()) { 1000 case CPU_VR41XX: 1001 case CPU_VR4111: 1002 case CPU_VR4121: 1003 case CPU_VR4122: 1004 case CPU_VR4131: 1005 case CPU_VR4181: 1006 case CPU_VR4181A: 1007 case CPU_VR4133: 1008 shift += 2; 1009 break; 1010 1011 default: 1012 break; 1013 } 1014 1015 if (shift) 1016 UASM_i_SRL(p, ctx, ctx, shift); 1017 uasm_i_andi(p, ctx, ctx, mask); 1018 } 1019 1020 void build_get_ptep(u32 **p, unsigned int tmp, unsigned int ptr) 1021 { 1022 /* 1023 * Bug workaround for the Nevada. It seems as if under certain 1024 * circumstances the move from cp0_context might produce a 1025 * bogus result when the mfc0 instruction and its consumer are 1026 * in a different cacheline or a load instruction, probably any 1027 * memory reference, is between them. 1028 */ 1029 switch (current_cpu_type()) { 1030 case CPU_NEVADA: 1031 UASM_i_LW(p, ptr, 0, ptr); 1032 GET_CONTEXT(p, tmp); /* get context reg */ 1033 break; 1034 1035 default: 1036 GET_CONTEXT(p, tmp); /* get context reg */ 1037 UASM_i_LW(p, ptr, 0, ptr); 1038 break; 1039 } 1040 1041 build_adjust_context(p, tmp); 1042 UASM_i_ADDU(p, ptr, ptr, tmp); /* add in offset */ 1043 } 1044 EXPORT_SYMBOL_GPL(build_get_ptep); 1045 1046 void build_update_entries(u32 **p, unsigned int tmp, unsigned int ptep) 1047 { 1048 int pte_off_even = 0; 1049 int pte_off_odd = sizeof(pte_t); 1050 1051 #if defined(CONFIG_CPU_MIPS32) && defined(CONFIG_PHYS_ADDR_T_64BIT) 1052 /* The low 32 bits of EntryLo is stored in pte_high */ 1053 pte_off_even += offsetof(pte_t, pte_high); 1054 pte_off_odd += offsetof(pte_t, pte_high); 1055 #endif 1056 1057 if (IS_ENABLED(CONFIG_XPA)) { 1058 uasm_i_lw(p, tmp, pte_off_even, ptep); /* even pte */ 1059 UASM_i_ROTR(p, tmp, tmp, ilog2(_PAGE_GLOBAL)); 1060 UASM_i_MTC0(p, tmp, C0_ENTRYLO0); 1061 1062 if (cpu_has_xpa && !mips_xpa_disabled) { 1063 uasm_i_lw(p, tmp, 0, ptep); 1064 uasm_i_ext(p, tmp, tmp, 0, 24); 1065 uasm_i_mthc0(p, tmp, C0_ENTRYLO0); 1066 } 1067 1068 uasm_i_lw(p, tmp, pte_off_odd, ptep); /* odd pte */ 1069 UASM_i_ROTR(p, tmp, tmp, ilog2(_PAGE_GLOBAL)); 1070 UASM_i_MTC0(p, tmp, C0_ENTRYLO1); 1071 1072 if (cpu_has_xpa && !mips_xpa_disabled) { 1073 uasm_i_lw(p, tmp, sizeof(pte_t), ptep); 1074 uasm_i_ext(p, tmp, tmp, 0, 24); 1075 uasm_i_mthc0(p, tmp, C0_ENTRYLO1); 1076 } 1077 return; 1078 } 1079 1080 UASM_i_LW(p, tmp, pte_off_even, ptep); /* get even pte */ 1081 UASM_i_LW(p, ptep, pte_off_odd, ptep); /* get odd pte */ 1082 if (r45k_bvahwbug()) 1083 build_tlb_probe_entry(p); 1084 build_convert_pte_to_entrylo(p, tmp); 1085 if (r4k_250MHZhwbug()) 1086 UASM_i_MTC0(p, 0, C0_ENTRYLO0); 1087 UASM_i_MTC0(p, tmp, C0_ENTRYLO0); /* load it */ 1088 build_convert_pte_to_entrylo(p, ptep); 1089 if (r45k_bvahwbug()) 1090 uasm_i_mfc0(p, tmp, C0_INDEX); 1091 if (r4k_250MHZhwbug()) 1092 UASM_i_MTC0(p, 0, C0_ENTRYLO1); 1093 UASM_i_MTC0(p, ptep, C0_ENTRYLO1); /* load it */ 1094 } 1095 EXPORT_SYMBOL_GPL(build_update_entries); 1096 1097 struct mips_huge_tlb_info { 1098 int huge_pte; 1099 int restore_scratch; 1100 bool need_reload_pte; 1101 }; 1102 1103 static struct mips_huge_tlb_info 1104 build_fast_tlb_refill_handler (u32 **p, struct uasm_label **l, 1105 struct uasm_reloc **r, unsigned int tmp, 1106 unsigned int ptr, int c0_scratch_reg) 1107 { 1108 struct mips_huge_tlb_info rv; 1109 unsigned int even, odd; 1110 int vmalloc_branch_delay_filled = 0; 1111 const int scratch = 1; /* Our extra working register */ 1112 1113 rv.huge_pte = scratch; 1114 rv.restore_scratch = 0; 1115 rv.need_reload_pte = false; 1116 1117 if (check_for_high_segbits) { 1118 UASM_i_MFC0(p, tmp, C0_BADVADDR); 1119 1120 if (pgd_reg != -1) 1121 UASM_i_MFC0(p, ptr, c0_kscratch(), pgd_reg); 1122 else 1123 UASM_i_MFC0(p, ptr, C0_CONTEXT); 1124 1125 if (c0_scratch_reg >= 0) 1126 UASM_i_MTC0(p, scratch, c0_kscratch(), c0_scratch_reg); 1127 else 1128 UASM_i_SW(p, scratch, scratchpad_offset(0), 0); 1129 1130 uasm_i_dsrl_safe(p, scratch, tmp, 1131 PGDIR_SHIFT + PGD_ORDER + PAGE_SHIFT - 3); 1132 uasm_il_bnez(p, r, scratch, label_vmalloc); 1133 1134 if (pgd_reg == -1) { 1135 vmalloc_branch_delay_filled = 1; 1136 /* Clear lower 23 bits of context. */ 1137 uasm_i_dins(p, ptr, 0, 0, 23); 1138 } 1139 } else { 1140 if (pgd_reg != -1) 1141 UASM_i_MFC0(p, ptr, c0_kscratch(), pgd_reg); 1142 else 1143 UASM_i_MFC0(p, ptr, C0_CONTEXT); 1144 1145 UASM_i_MFC0(p, tmp, C0_BADVADDR); 1146 1147 if (c0_scratch_reg >= 0) 1148 UASM_i_MTC0(p, scratch, c0_kscratch(), c0_scratch_reg); 1149 else 1150 UASM_i_SW(p, scratch, scratchpad_offset(0), 0); 1151 1152 if (pgd_reg == -1) 1153 /* Clear lower 23 bits of context. */ 1154 uasm_i_dins(p, ptr, 0, 0, 23); 1155 1156 uasm_il_bltz(p, r, tmp, label_vmalloc); 1157 } 1158 1159 if (pgd_reg == -1) { 1160 vmalloc_branch_delay_filled = 1; 1161 /* insert bit[63:59] of CAC_BASE into bit[11:6] of ptr */ 1162 uasm_i_ori(p, ptr, ptr, ((u64)(CAC_BASE) >> 53)); 1163 1164 uasm_i_drotr(p, ptr, ptr, 11); 1165 } 1166 1167 #ifdef __PAGETABLE_PMD_FOLDED 1168 #define LOC_PTEP scratch 1169 #else 1170 #define LOC_PTEP ptr 1171 #endif 1172 1173 if (!vmalloc_branch_delay_filled) 1174 /* get pgd offset in bytes */ 1175 uasm_i_dsrl_safe(p, scratch, tmp, PGDIR_SHIFT - 3); 1176 1177 uasm_l_vmalloc_done(l, *p); 1178 1179 /* 1180 * tmp ptr 1181 * fall-through case = badvaddr *pgd_current 1182 * vmalloc case = badvaddr swapper_pg_dir 1183 */ 1184 1185 if (vmalloc_branch_delay_filled) 1186 /* get pgd offset in bytes */ 1187 uasm_i_dsrl_safe(p, scratch, tmp, PGDIR_SHIFT - 3); 1188 1189 #ifdef __PAGETABLE_PMD_FOLDED 1190 GET_CONTEXT(p, tmp); /* get context reg */ 1191 #endif 1192 uasm_i_andi(p, scratch, scratch, (PTRS_PER_PGD - 1) << 3); 1193 1194 if (use_lwx_insns()) { 1195 UASM_i_LWX(p, LOC_PTEP, scratch, ptr); 1196 } else { 1197 uasm_i_daddu(p, ptr, ptr, scratch); /* add in pgd offset */ 1198 uasm_i_ld(p, LOC_PTEP, 0, ptr); /* get pmd pointer */ 1199 } 1200 1201 #ifndef __PAGETABLE_PUD_FOLDED 1202 /* get pud offset in bytes */ 1203 uasm_i_dsrl_safe(p, scratch, tmp, PUD_SHIFT - 3); 1204 uasm_i_andi(p, scratch, scratch, (PTRS_PER_PUD - 1) << 3); 1205 1206 if (use_lwx_insns()) { 1207 UASM_i_LWX(p, ptr, scratch, ptr); 1208 } else { 1209 uasm_i_daddu(p, ptr, ptr, scratch); /* add in pmd offset */ 1210 UASM_i_LW(p, ptr, 0, ptr); 1211 } 1212 /* ptr contains a pointer to PMD entry */ 1213 /* tmp contains the address */ 1214 #endif 1215 1216 #ifndef __PAGETABLE_PMD_FOLDED 1217 /* get pmd offset in bytes */ 1218 uasm_i_dsrl_safe(p, scratch, tmp, PMD_SHIFT - 3); 1219 uasm_i_andi(p, scratch, scratch, (PTRS_PER_PMD - 1) << 3); 1220 GET_CONTEXT(p, tmp); /* get context reg */ 1221 1222 if (use_lwx_insns()) { 1223 UASM_i_LWX(p, scratch, scratch, ptr); 1224 } else { 1225 uasm_i_daddu(p, ptr, ptr, scratch); /* add in pmd offset */ 1226 UASM_i_LW(p, scratch, 0, ptr); 1227 } 1228 #endif 1229 /* Adjust the context during the load latency. */ 1230 build_adjust_context(p, tmp); 1231 1232 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT 1233 uasm_il_bbit1(p, r, scratch, ilog2(_PAGE_HUGE), label_tlb_huge_update); 1234 /* 1235 * The in the LWX case we don't want to do the load in the 1236 * delay slot. It cannot issue in the same cycle and may be 1237 * speculative and unneeded. 1238 */ 1239 if (use_lwx_insns()) 1240 uasm_i_nop(p); 1241 #endif /* CONFIG_MIPS_HUGE_TLB_SUPPORT */ 1242 1243 1244 /* build_update_entries */ 1245 if (use_lwx_insns()) { 1246 even = ptr; 1247 odd = tmp; 1248 UASM_i_LWX(p, even, scratch, tmp); 1249 UASM_i_ADDIU(p, tmp, tmp, sizeof(pte_t)); 1250 UASM_i_LWX(p, odd, scratch, tmp); 1251 } else { 1252 UASM_i_ADDU(p, ptr, scratch, tmp); /* add in offset */ 1253 even = tmp; 1254 odd = ptr; 1255 UASM_i_LW(p, even, 0, ptr); /* get even pte */ 1256 UASM_i_LW(p, odd, sizeof(pte_t), ptr); /* get odd pte */ 1257 } 1258 if (cpu_has_rixi) { 1259 uasm_i_drotr(p, even, even, ilog2(_PAGE_GLOBAL)); 1260 UASM_i_MTC0(p, even, C0_ENTRYLO0); /* load it */ 1261 uasm_i_drotr(p, odd, odd, ilog2(_PAGE_GLOBAL)); 1262 } else { 1263 uasm_i_dsrl_safe(p, even, even, ilog2(_PAGE_GLOBAL)); 1264 UASM_i_MTC0(p, even, C0_ENTRYLO0); /* load it */ 1265 uasm_i_dsrl_safe(p, odd, odd, ilog2(_PAGE_GLOBAL)); 1266 } 1267 UASM_i_MTC0(p, odd, C0_ENTRYLO1); /* load it */ 1268 1269 if (c0_scratch_reg >= 0) { 1270 uasm_i_ehb(p); 1271 UASM_i_MFC0(p, scratch, c0_kscratch(), c0_scratch_reg); 1272 build_tlb_write_entry(p, l, r, tlb_random); 1273 uasm_l_leave(l, *p); 1274 rv.restore_scratch = 1; 1275 } else if (PAGE_SHIFT == 14 || PAGE_SHIFT == 13) { 1276 build_tlb_write_entry(p, l, r, tlb_random); 1277 uasm_l_leave(l, *p); 1278 UASM_i_LW(p, scratch, scratchpad_offset(0), 0); 1279 } else { 1280 UASM_i_LW(p, scratch, scratchpad_offset(0), 0); 1281 build_tlb_write_entry(p, l, r, tlb_random); 1282 uasm_l_leave(l, *p); 1283 rv.restore_scratch = 1; 1284 } 1285 1286 uasm_i_eret(p); /* return from trap */ 1287 1288 return rv; 1289 } 1290 1291 /* 1292 * For a 64-bit kernel, we are using the 64-bit XTLB refill exception 1293 * because EXL == 0. If we wrap, we can also use the 32 instruction 1294 * slots before the XTLB refill exception handler which belong to the 1295 * unused TLB refill exception. 1296 */ 1297 #define MIPS64_REFILL_INSNS 32 1298 1299 static void build_r4000_tlb_refill_handler(void) 1300 { 1301 u32 *p = tlb_handler; 1302 struct uasm_label *l = labels; 1303 struct uasm_reloc *r = relocs; 1304 u32 *f; 1305 unsigned int final_len; 1306 struct mips_huge_tlb_info htlb_info __maybe_unused; 1307 enum vmalloc64_mode vmalloc_mode __maybe_unused; 1308 1309 memset(tlb_handler, 0, sizeof(tlb_handler)); 1310 memset(labels, 0, sizeof(labels)); 1311 memset(relocs, 0, sizeof(relocs)); 1312 memset(final_handler, 0, sizeof(final_handler)); 1313 1314 if (IS_ENABLED(CONFIG_64BIT) && (scratch_reg >= 0 || scratchpad_available()) && use_bbit_insns()) { 1315 htlb_info = build_fast_tlb_refill_handler(&p, &l, &r, K0, K1, 1316 scratch_reg); 1317 vmalloc_mode = refill_scratch; 1318 } else { 1319 htlb_info.huge_pte = K0; 1320 htlb_info.restore_scratch = 0; 1321 htlb_info.need_reload_pte = true; 1322 vmalloc_mode = refill_noscratch; 1323 /* 1324 * create the plain linear handler 1325 */ 1326 if (bcm1250_m3_war()) { 1327 unsigned int segbits = 44; 1328 1329 uasm_i_dmfc0(&p, K0, C0_BADVADDR); 1330 uasm_i_dmfc0(&p, K1, C0_ENTRYHI); 1331 uasm_i_xor(&p, K0, K0, K1); 1332 uasm_i_dsrl_safe(&p, K1, K0, 62); 1333 uasm_i_dsrl_safe(&p, K0, K0, 12 + 1); 1334 uasm_i_dsll_safe(&p, K0, K0, 64 + 12 + 1 - segbits); 1335 uasm_i_or(&p, K0, K0, K1); 1336 uasm_il_bnez(&p, &r, K0, label_leave); 1337 /* No need for uasm_i_nop */ 1338 } 1339 1340 #ifdef CONFIG_64BIT 1341 build_get_pmde64(&p, &l, &r, K0, K1); /* get pmd in K1 */ 1342 #else 1343 build_get_pgde32(&p, K0, K1); /* get pgd in K1 */ 1344 #endif 1345 1346 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT 1347 build_is_huge_pte(&p, &r, K0, K1, label_tlb_huge_update); 1348 #endif 1349 1350 build_get_ptep(&p, K0, K1); 1351 build_update_entries(&p, K0, K1); 1352 build_tlb_write_entry(&p, &l, &r, tlb_random); 1353 uasm_l_leave(&l, p); 1354 uasm_i_eret(&p); /* return from trap */ 1355 } 1356 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT 1357 uasm_l_tlb_huge_update(&l, p); 1358 if (htlb_info.need_reload_pte) 1359 UASM_i_LW(&p, htlb_info.huge_pte, 0, K1); 1360 build_huge_update_entries(&p, htlb_info.huge_pte, K1); 1361 build_huge_tlb_write_entry(&p, &l, &r, K0, tlb_random, 1362 htlb_info.restore_scratch); 1363 #endif 1364 1365 #ifdef CONFIG_64BIT 1366 build_get_pgd_vmalloc64(&p, &l, &r, K0, K1, vmalloc_mode); 1367 #endif 1368 1369 /* 1370 * Overflow check: For the 64bit handler, we need at least one 1371 * free instruction slot for the wrap-around branch. In worst 1372 * case, if the intended insertion point is a delay slot, we 1373 * need three, with the second nop'ed and the third being 1374 * unused. 1375 */ 1376 switch (boot_cpu_type()) { 1377 default: 1378 if (sizeof(long) == 4) { 1379 fallthrough; 1380 case CPU_LOONGSON2EF: 1381 /* Loongson2 ebase is different than r4k, we have more space */ 1382 if ((p - tlb_handler) > 64) 1383 panic("TLB refill handler space exceeded"); 1384 /* 1385 * Now fold the handler in the TLB refill handler space. 1386 */ 1387 f = final_handler; 1388 /* Simplest case, just copy the handler. */ 1389 uasm_copy_handler(relocs, labels, tlb_handler, p, f); 1390 final_len = p - tlb_handler; 1391 break; 1392 } else { 1393 if (((p - tlb_handler) > (MIPS64_REFILL_INSNS * 2) - 1) 1394 || (((p - tlb_handler) > (MIPS64_REFILL_INSNS * 2) - 3) 1395 && uasm_insn_has_bdelay(relocs, 1396 tlb_handler + MIPS64_REFILL_INSNS - 3))) 1397 panic("TLB refill handler space exceeded"); 1398 /* 1399 * Now fold the handler in the TLB refill handler space. 1400 */ 1401 f = final_handler + MIPS64_REFILL_INSNS; 1402 if ((p - tlb_handler) <= MIPS64_REFILL_INSNS) { 1403 /* Just copy the handler. */ 1404 uasm_copy_handler(relocs, labels, tlb_handler, p, f); 1405 final_len = p - tlb_handler; 1406 } else { 1407 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT 1408 const enum label_id ls = label_tlb_huge_update; 1409 #else 1410 const enum label_id ls = label_vmalloc; 1411 #endif 1412 u32 *split; 1413 int ov = 0; 1414 int i; 1415 1416 for (i = 0; i < ARRAY_SIZE(labels) && labels[i].lab != ls; i++) 1417 ; 1418 BUG_ON(i == ARRAY_SIZE(labels)); 1419 split = labels[i].addr; 1420 1421 /* 1422 * See if we have overflown one way or the other. 1423 */ 1424 if (split > tlb_handler + MIPS64_REFILL_INSNS || 1425 split < p - MIPS64_REFILL_INSNS) 1426 ov = 1; 1427 1428 if (ov) { 1429 /* 1430 * Split two instructions before the end. One 1431 * for the branch and one for the instruction 1432 * in the delay slot. 1433 */ 1434 split = tlb_handler + MIPS64_REFILL_INSNS - 2; 1435 1436 /* 1437 * If the branch would fall in a delay slot, 1438 * we must back up an additional instruction 1439 * so that it is no longer in a delay slot. 1440 */ 1441 if (uasm_insn_has_bdelay(relocs, split - 1)) 1442 split--; 1443 } 1444 /* Copy first part of the handler. */ 1445 uasm_copy_handler(relocs, labels, tlb_handler, split, f); 1446 f += split - tlb_handler; 1447 1448 if (ov) { 1449 /* Insert branch. */ 1450 uasm_l_split(&l, final_handler); 1451 uasm_il_b(&f, &r, label_split); 1452 if (uasm_insn_has_bdelay(relocs, split)) 1453 uasm_i_nop(&f); 1454 else { 1455 uasm_copy_handler(relocs, labels, 1456 split, split + 1, f); 1457 uasm_move_labels(labels, f, f + 1, -1); 1458 f++; 1459 split++; 1460 } 1461 } 1462 1463 /* Copy the rest of the handler. */ 1464 uasm_copy_handler(relocs, labels, split, p, final_handler); 1465 final_len = (f - (final_handler + MIPS64_REFILL_INSNS)) + 1466 (p - split); 1467 } 1468 } 1469 break; 1470 } 1471 1472 uasm_resolve_relocs(relocs, labels); 1473 pr_debug("Wrote TLB refill handler (%u instructions).\n", 1474 final_len); 1475 1476 memcpy((void *)ebase, final_handler, 0x100); 1477 local_flush_icache_range(ebase, ebase + 0x100); 1478 dump_handler("r4000_tlb_refill", (u32 *)ebase, (u32 *)(ebase + 0x100)); 1479 } 1480 1481 static void setup_pw(void) 1482 { 1483 unsigned int pwctl; 1484 unsigned long pgd_i, pgd_w; 1485 #ifndef __PAGETABLE_PMD_FOLDED 1486 unsigned long pmd_i, pmd_w; 1487 #endif 1488 unsigned long pt_i, pt_w; 1489 unsigned long pte_i, pte_w; 1490 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT 1491 unsigned long psn; 1492 1493 psn = ilog2(_PAGE_HUGE); /* bit used to indicate huge page */ 1494 #endif 1495 pgd_i = PGDIR_SHIFT; /* 1st level PGD */ 1496 #ifndef __PAGETABLE_PMD_FOLDED 1497 pgd_w = PGDIR_SHIFT - PMD_SHIFT + PGD_ORDER; 1498 1499 pmd_i = PMD_SHIFT; /* 2nd level PMD */ 1500 pmd_w = PMD_SHIFT - PAGE_SHIFT; 1501 #else 1502 pgd_w = PGDIR_SHIFT - PAGE_SHIFT + PGD_ORDER; 1503 #endif 1504 1505 pt_i = PAGE_SHIFT; /* 3rd level PTE */ 1506 pt_w = PAGE_SHIFT - 3; 1507 1508 pte_i = ilog2(_PAGE_GLOBAL); 1509 pte_w = 0; 1510 pwctl = 1 << 30; /* Set PWDirExt */ 1511 1512 #ifndef __PAGETABLE_PMD_FOLDED 1513 write_c0_pwfield(pgd_i << 24 | pmd_i << 12 | pt_i << 6 | pte_i); 1514 write_c0_pwsize(1 << 30 | pgd_w << 24 | pmd_w << 12 | pt_w << 6 | pte_w); 1515 #else 1516 write_c0_pwfield(pgd_i << 24 | pt_i << 6 | pte_i); 1517 write_c0_pwsize(1 << 30 | pgd_w << 24 | pt_w << 6 | pte_w); 1518 #endif 1519 1520 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT 1521 pwctl |= (1 << 6 | psn); 1522 #endif 1523 write_c0_pwctl(pwctl); 1524 write_c0_kpgd((long)swapper_pg_dir); 1525 kscratch_used_mask |= (1 << 7); /* KScratch6 is used for KPGD */ 1526 } 1527 1528 static void build_loongson3_tlb_refill_handler(void) 1529 { 1530 u32 *p = tlb_handler; 1531 struct uasm_label *l = labels; 1532 struct uasm_reloc *r = relocs; 1533 1534 memset(labels, 0, sizeof(labels)); 1535 memset(relocs, 0, sizeof(relocs)); 1536 memset(tlb_handler, 0, sizeof(tlb_handler)); 1537 1538 if (check_for_high_segbits) { 1539 uasm_i_dmfc0(&p, K0, C0_BADVADDR); 1540 uasm_i_dsrl_safe(&p, K1, K0, PGDIR_SHIFT + PGD_ORDER + PAGE_SHIFT - 3); 1541 uasm_il_beqz(&p, &r, K1, label_vmalloc); 1542 uasm_i_nop(&p); 1543 1544 uasm_il_bgez(&p, &r, K0, label_large_segbits_fault); 1545 uasm_i_nop(&p); 1546 uasm_l_vmalloc(&l, p); 1547 } 1548 1549 uasm_i_dmfc0(&p, K1, C0_PGD); 1550 1551 uasm_i_lddir(&p, K0, K1, 3); /* global page dir */ 1552 #ifndef __PAGETABLE_PMD_FOLDED 1553 uasm_i_lddir(&p, K1, K0, 1); /* middle page dir */ 1554 #endif 1555 uasm_i_ldpte(&p, K1, 0); /* even */ 1556 uasm_i_ldpte(&p, K1, 1); /* odd */ 1557 uasm_i_tlbwr(&p); 1558 1559 /* restore page mask */ 1560 if (PM_DEFAULT_MASK >> 16) { 1561 uasm_i_lui(&p, K0, PM_DEFAULT_MASK >> 16); 1562 uasm_i_ori(&p, K0, K0, PM_DEFAULT_MASK & 0xffff); 1563 uasm_i_mtc0(&p, K0, C0_PAGEMASK); 1564 } else if (PM_DEFAULT_MASK) { 1565 uasm_i_ori(&p, K0, 0, PM_DEFAULT_MASK); 1566 uasm_i_mtc0(&p, K0, C0_PAGEMASK); 1567 } else { 1568 uasm_i_mtc0(&p, 0, C0_PAGEMASK); 1569 } 1570 1571 uasm_i_eret(&p); 1572 1573 if (check_for_high_segbits) { 1574 uasm_l_large_segbits_fault(&l, p); 1575 UASM_i_LA(&p, K1, (unsigned long)tlb_do_page_fault_0); 1576 uasm_i_jr(&p, K1); 1577 uasm_i_nop(&p); 1578 } 1579 1580 uasm_resolve_relocs(relocs, labels); 1581 memcpy((void *)(ebase + 0x80), tlb_handler, 0x80); 1582 local_flush_icache_range(ebase + 0x80, ebase + 0x100); 1583 dump_handler("loongson3_tlb_refill", 1584 (u32 *)(ebase + 0x80), (u32 *)(ebase + 0x100)); 1585 } 1586 1587 static void build_setup_pgd(void) 1588 { 1589 const int a0 = 4; 1590 const int __maybe_unused a1 = 5; 1591 const int __maybe_unused a2 = 6; 1592 u32 *p = (u32 *)msk_isa16_mode((ulong)tlbmiss_handler_setup_pgd); 1593 #ifndef CONFIG_MIPS_PGD_C0_CONTEXT 1594 long pgdc = (long)pgd_current; 1595 #endif 1596 1597 memset(p, 0, tlbmiss_handler_setup_pgd_end - (char *)p); 1598 memset(labels, 0, sizeof(labels)); 1599 memset(relocs, 0, sizeof(relocs)); 1600 pgd_reg = allocate_kscratch(); 1601 #ifdef CONFIG_MIPS_PGD_C0_CONTEXT 1602 if (pgd_reg == -1) { 1603 struct uasm_label *l = labels; 1604 struct uasm_reloc *r = relocs; 1605 1606 /* PGD << 11 in c0_Context */ 1607 /* 1608 * If it is a ckseg0 address, convert to a physical 1609 * address. Shifting right by 29 and adding 4 will 1610 * result in zero for these addresses. 1611 * 1612 */ 1613 UASM_i_SRA(&p, a1, a0, 29); 1614 UASM_i_ADDIU(&p, a1, a1, 4); 1615 uasm_il_bnez(&p, &r, a1, label_tlbl_goaround1); 1616 uasm_i_nop(&p); 1617 uasm_i_dinsm(&p, a0, 0, 29, 64 - 29); 1618 uasm_l_tlbl_goaround1(&l, p); 1619 UASM_i_SLL(&p, a0, a0, 11); 1620 UASM_i_MTC0(&p, a0, C0_CONTEXT); 1621 uasm_i_jr(&p, 31); 1622 uasm_i_ehb(&p); 1623 } else { 1624 /* PGD in c0_KScratch */ 1625 if (cpu_has_ldpte) 1626 UASM_i_MTC0(&p, a0, C0_PWBASE); 1627 else 1628 UASM_i_MTC0(&p, a0, c0_kscratch(), pgd_reg); 1629 uasm_i_jr(&p, 31); 1630 uasm_i_ehb(&p); 1631 } 1632 #else 1633 #ifdef CONFIG_SMP 1634 /* Save PGD to pgd_current[smp_processor_id()] */ 1635 UASM_i_CPUID_MFC0(&p, a1, SMP_CPUID_REG); 1636 UASM_i_SRL_SAFE(&p, a1, a1, SMP_CPUID_PTRSHIFT); 1637 UASM_i_LA_mostly(&p, a2, pgdc); 1638 UASM_i_ADDU(&p, a2, a2, a1); 1639 UASM_i_SW(&p, a0, uasm_rel_lo(pgdc), a2); 1640 #else 1641 UASM_i_LA_mostly(&p, a2, pgdc); 1642 UASM_i_SW(&p, a0, uasm_rel_lo(pgdc), a2); 1643 #endif /* SMP */ 1644 1645 /* if pgd_reg is allocated, save PGD also to scratch register */ 1646 if (pgd_reg != -1) { 1647 UASM_i_MTC0(&p, a0, c0_kscratch(), pgd_reg); 1648 uasm_i_jr(&p, 31); 1649 uasm_i_ehb(&p); 1650 } else { 1651 uasm_i_jr(&p, 31); 1652 uasm_i_nop(&p); 1653 } 1654 #endif 1655 if (p >= (u32 *)tlbmiss_handler_setup_pgd_end) 1656 panic("tlbmiss_handler_setup_pgd space exceeded"); 1657 1658 uasm_resolve_relocs(relocs, labels); 1659 pr_debug("Wrote tlbmiss_handler_setup_pgd (%u instructions).\n", 1660 (unsigned int)(p - (u32 *)tlbmiss_handler_setup_pgd)); 1661 1662 dump_handler("tlbmiss_handler", tlbmiss_handler_setup_pgd, 1663 tlbmiss_handler_setup_pgd_end); 1664 } 1665 1666 static void 1667 iPTE_LW(u32 **p, unsigned int pte, unsigned int ptr) 1668 { 1669 #ifdef CONFIG_SMP 1670 if (IS_ENABLED(CONFIG_CPU_LOONGSON3_WORKAROUNDS)) 1671 uasm_i_sync(p, 0); 1672 # ifdef CONFIG_PHYS_ADDR_T_64BIT 1673 if (cpu_has_64bits) 1674 uasm_i_lld(p, pte, 0, ptr); 1675 else 1676 # endif 1677 UASM_i_LL(p, pte, 0, ptr); 1678 #else 1679 # ifdef CONFIG_PHYS_ADDR_T_64BIT 1680 if (cpu_has_64bits) 1681 uasm_i_ld(p, pte, 0, ptr); 1682 else 1683 # endif 1684 UASM_i_LW(p, pte, 0, ptr); 1685 #endif 1686 } 1687 1688 static void 1689 iPTE_SW(u32 **p, struct uasm_reloc **r, unsigned int pte, unsigned int ptr, 1690 unsigned int mode, unsigned int scratch) 1691 { 1692 unsigned int hwmode = mode & (_PAGE_VALID | _PAGE_DIRTY); 1693 unsigned int swmode = mode & ~hwmode; 1694 1695 if (IS_ENABLED(CONFIG_XPA) && !cpu_has_64bits) { 1696 uasm_i_lui(p, scratch, swmode >> 16); 1697 uasm_i_or(p, pte, pte, scratch); 1698 BUG_ON(swmode & 0xffff); 1699 } else { 1700 uasm_i_ori(p, pte, pte, mode); 1701 } 1702 1703 #ifdef CONFIG_SMP 1704 # ifdef CONFIG_PHYS_ADDR_T_64BIT 1705 if (cpu_has_64bits) 1706 uasm_i_scd(p, pte, 0, ptr); 1707 else 1708 # endif 1709 UASM_i_SC(p, pte, 0, ptr); 1710 1711 if (r10000_llsc_war()) 1712 uasm_il_beqzl(p, r, pte, label_smp_pgtable_change); 1713 else 1714 uasm_il_beqz(p, r, pte, label_smp_pgtable_change); 1715 1716 # ifdef CONFIG_PHYS_ADDR_T_64BIT 1717 if (!cpu_has_64bits) { 1718 /* no uasm_i_nop needed */ 1719 uasm_i_ll(p, pte, sizeof(pte_t) / 2, ptr); 1720 uasm_i_ori(p, pte, pte, hwmode); 1721 BUG_ON(hwmode & ~0xffff); 1722 uasm_i_sc(p, pte, sizeof(pte_t) / 2, ptr); 1723 uasm_il_beqz(p, r, pte, label_smp_pgtable_change); 1724 /* no uasm_i_nop needed */ 1725 uasm_i_lw(p, pte, 0, ptr); 1726 } else 1727 uasm_i_nop(p); 1728 # else 1729 uasm_i_nop(p); 1730 # endif 1731 #else 1732 # ifdef CONFIG_PHYS_ADDR_T_64BIT 1733 if (cpu_has_64bits) 1734 uasm_i_sd(p, pte, 0, ptr); 1735 else 1736 # endif 1737 UASM_i_SW(p, pte, 0, ptr); 1738 1739 # ifdef CONFIG_PHYS_ADDR_T_64BIT 1740 if (!cpu_has_64bits) { 1741 uasm_i_lw(p, pte, sizeof(pte_t) / 2, ptr); 1742 uasm_i_ori(p, pte, pte, hwmode); 1743 BUG_ON(hwmode & ~0xffff); 1744 uasm_i_sw(p, pte, sizeof(pte_t) / 2, ptr); 1745 uasm_i_lw(p, pte, 0, ptr); 1746 } 1747 # endif 1748 #endif 1749 } 1750 1751 /* 1752 * Check if PTE is present, if not then jump to LABEL. PTR points to 1753 * the page table where this PTE is located, PTE will be re-loaded 1754 * with it's original value. 1755 */ 1756 static void 1757 build_pte_present(u32 **p, struct uasm_reloc **r, 1758 int pte, int ptr, int scratch, enum label_id lid) 1759 { 1760 int t = scratch >= 0 ? scratch : pte; 1761 int cur = pte; 1762 1763 if (cpu_has_rixi) { 1764 if (use_bbit_insns()) { 1765 uasm_il_bbit0(p, r, pte, ilog2(_PAGE_PRESENT), lid); 1766 uasm_i_nop(p); 1767 } else { 1768 if (_PAGE_PRESENT_SHIFT) { 1769 uasm_i_srl(p, t, cur, _PAGE_PRESENT_SHIFT); 1770 cur = t; 1771 } 1772 uasm_i_andi(p, t, cur, 1); 1773 uasm_il_beqz(p, r, t, lid); 1774 if (pte == t) 1775 /* You lose the SMP race :-(*/ 1776 iPTE_LW(p, pte, ptr); 1777 } 1778 } else { 1779 if (_PAGE_PRESENT_SHIFT) { 1780 uasm_i_srl(p, t, cur, _PAGE_PRESENT_SHIFT); 1781 cur = t; 1782 } 1783 uasm_i_andi(p, t, cur, 1784 (_PAGE_PRESENT | _PAGE_NO_READ) >> _PAGE_PRESENT_SHIFT); 1785 uasm_i_xori(p, t, t, _PAGE_PRESENT >> _PAGE_PRESENT_SHIFT); 1786 uasm_il_bnez(p, r, t, lid); 1787 if (pte == t) 1788 /* You lose the SMP race :-(*/ 1789 iPTE_LW(p, pte, ptr); 1790 } 1791 } 1792 1793 /* Make PTE valid, store result in PTR. */ 1794 static void 1795 build_make_valid(u32 **p, struct uasm_reloc **r, unsigned int pte, 1796 unsigned int ptr, unsigned int scratch) 1797 { 1798 unsigned int mode = _PAGE_VALID | _PAGE_ACCESSED; 1799 1800 iPTE_SW(p, r, pte, ptr, mode, scratch); 1801 } 1802 1803 /* 1804 * Check if PTE can be written to, if not branch to LABEL. Regardless 1805 * restore PTE with value from PTR when done. 1806 */ 1807 static void 1808 build_pte_writable(u32 **p, struct uasm_reloc **r, 1809 unsigned int pte, unsigned int ptr, int scratch, 1810 enum label_id lid) 1811 { 1812 int t = scratch >= 0 ? scratch : pte; 1813 int cur = pte; 1814 1815 if (_PAGE_PRESENT_SHIFT) { 1816 uasm_i_srl(p, t, cur, _PAGE_PRESENT_SHIFT); 1817 cur = t; 1818 } 1819 uasm_i_andi(p, t, cur, 1820 (_PAGE_PRESENT | _PAGE_WRITE) >> _PAGE_PRESENT_SHIFT); 1821 uasm_i_xori(p, t, t, 1822 (_PAGE_PRESENT | _PAGE_WRITE) >> _PAGE_PRESENT_SHIFT); 1823 uasm_il_bnez(p, r, t, lid); 1824 if (pte == t) 1825 /* You lose the SMP race :-(*/ 1826 iPTE_LW(p, pte, ptr); 1827 else 1828 uasm_i_nop(p); 1829 } 1830 1831 /* Make PTE writable, update software status bits as well, then store 1832 * at PTR. 1833 */ 1834 static void 1835 build_make_write(u32 **p, struct uasm_reloc **r, unsigned int pte, 1836 unsigned int ptr, unsigned int scratch) 1837 { 1838 unsigned int mode = (_PAGE_ACCESSED | _PAGE_MODIFIED | _PAGE_VALID 1839 | _PAGE_DIRTY); 1840 1841 iPTE_SW(p, r, pte, ptr, mode, scratch); 1842 } 1843 1844 /* 1845 * Check if PTE can be modified, if not branch to LABEL. Regardless 1846 * restore PTE with value from PTR when done. 1847 */ 1848 static void 1849 build_pte_modifiable(u32 **p, struct uasm_reloc **r, 1850 unsigned int pte, unsigned int ptr, int scratch, 1851 enum label_id lid) 1852 { 1853 if (use_bbit_insns()) { 1854 uasm_il_bbit0(p, r, pte, ilog2(_PAGE_WRITE), lid); 1855 uasm_i_nop(p); 1856 } else { 1857 int t = scratch >= 0 ? scratch : pte; 1858 uasm_i_srl(p, t, pte, _PAGE_WRITE_SHIFT); 1859 uasm_i_andi(p, t, t, 1); 1860 uasm_il_beqz(p, r, t, lid); 1861 if (pte == t) 1862 /* You lose the SMP race :-(*/ 1863 iPTE_LW(p, pte, ptr); 1864 } 1865 } 1866 1867 #ifndef CONFIG_MIPS_PGD_C0_CONTEXT 1868 1869 1870 /* 1871 * R3000 style TLB load/store/modify handlers. 1872 */ 1873 1874 /* 1875 * This places the pte into ENTRYLO0 and writes it with tlbwi. 1876 * Then it returns. 1877 */ 1878 static void 1879 build_r3000_pte_reload_tlbwi(u32 **p, unsigned int pte, unsigned int tmp) 1880 { 1881 uasm_i_mtc0(p, pte, C0_ENTRYLO0); /* cp0 delay */ 1882 uasm_i_mfc0(p, tmp, C0_EPC); /* cp0 delay */ 1883 uasm_i_tlbwi(p); 1884 uasm_i_jr(p, tmp); 1885 uasm_i_rfe(p); /* branch delay */ 1886 } 1887 1888 /* 1889 * This places the pte into ENTRYLO0 and writes it with tlbwi 1890 * or tlbwr as appropriate. This is because the index register 1891 * may have the probe fail bit set as a result of a trap on a 1892 * kseg2 access, i.e. without refill. Then it returns. 1893 */ 1894 static void 1895 build_r3000_tlb_reload_write(u32 **p, struct uasm_label **l, 1896 struct uasm_reloc **r, unsigned int pte, 1897 unsigned int tmp) 1898 { 1899 uasm_i_mfc0(p, tmp, C0_INDEX); 1900 uasm_i_mtc0(p, pte, C0_ENTRYLO0); /* cp0 delay */ 1901 uasm_il_bltz(p, r, tmp, label_r3000_write_probe_fail); /* cp0 delay */ 1902 uasm_i_mfc0(p, tmp, C0_EPC); /* branch delay */ 1903 uasm_i_tlbwi(p); /* cp0 delay */ 1904 uasm_i_jr(p, tmp); 1905 uasm_i_rfe(p); /* branch delay */ 1906 uasm_l_r3000_write_probe_fail(l, *p); 1907 uasm_i_tlbwr(p); /* cp0 delay */ 1908 uasm_i_jr(p, tmp); 1909 uasm_i_rfe(p); /* branch delay */ 1910 } 1911 1912 static void 1913 build_r3000_tlbchange_handler_head(u32 **p, unsigned int pte, 1914 unsigned int ptr) 1915 { 1916 long pgdc = (long)pgd_current; 1917 1918 uasm_i_mfc0(p, pte, C0_BADVADDR); 1919 uasm_i_lui(p, ptr, uasm_rel_hi(pgdc)); /* cp0 delay */ 1920 uasm_i_lw(p, ptr, uasm_rel_lo(pgdc), ptr); 1921 uasm_i_srl(p, pte, pte, 22); /* load delay */ 1922 uasm_i_sll(p, pte, pte, 2); 1923 uasm_i_addu(p, ptr, ptr, pte); 1924 uasm_i_mfc0(p, pte, C0_CONTEXT); 1925 uasm_i_lw(p, ptr, 0, ptr); /* cp0 delay */ 1926 uasm_i_andi(p, pte, pte, 0xffc); /* load delay */ 1927 uasm_i_addu(p, ptr, ptr, pte); 1928 uasm_i_lw(p, pte, 0, ptr); 1929 uasm_i_tlbp(p); /* load delay */ 1930 } 1931 1932 static void build_r3000_tlb_load_handler(void) 1933 { 1934 u32 *p = (u32 *)handle_tlbl; 1935 struct uasm_label *l = labels; 1936 struct uasm_reloc *r = relocs; 1937 1938 memset(p, 0, handle_tlbl_end - (char *)p); 1939 memset(labels, 0, sizeof(labels)); 1940 memset(relocs, 0, sizeof(relocs)); 1941 1942 build_r3000_tlbchange_handler_head(&p, K0, K1); 1943 build_pte_present(&p, &r, K0, K1, -1, label_nopage_tlbl); 1944 uasm_i_nop(&p); /* load delay */ 1945 build_make_valid(&p, &r, K0, K1, -1); 1946 build_r3000_tlb_reload_write(&p, &l, &r, K0, K1); 1947 1948 uasm_l_nopage_tlbl(&l, p); 1949 uasm_i_j(&p, (unsigned long)tlb_do_page_fault_0 & 0x0fffffff); 1950 uasm_i_nop(&p); 1951 1952 if (p >= (u32 *)handle_tlbl_end) 1953 panic("TLB load handler fastpath space exceeded"); 1954 1955 uasm_resolve_relocs(relocs, labels); 1956 pr_debug("Wrote TLB load handler fastpath (%u instructions).\n", 1957 (unsigned int)(p - (u32 *)handle_tlbl)); 1958 1959 dump_handler("r3000_tlb_load", handle_tlbl, handle_tlbl_end); 1960 } 1961 1962 static void build_r3000_tlb_store_handler(void) 1963 { 1964 u32 *p = (u32 *)handle_tlbs; 1965 struct uasm_label *l = labels; 1966 struct uasm_reloc *r = relocs; 1967 1968 memset(p, 0, handle_tlbs_end - (char *)p); 1969 memset(labels, 0, sizeof(labels)); 1970 memset(relocs, 0, sizeof(relocs)); 1971 1972 build_r3000_tlbchange_handler_head(&p, K0, K1); 1973 build_pte_writable(&p, &r, K0, K1, -1, label_nopage_tlbs); 1974 uasm_i_nop(&p); /* load delay */ 1975 build_make_write(&p, &r, K0, K1, -1); 1976 build_r3000_tlb_reload_write(&p, &l, &r, K0, K1); 1977 1978 uasm_l_nopage_tlbs(&l, p); 1979 uasm_i_j(&p, (unsigned long)tlb_do_page_fault_1 & 0x0fffffff); 1980 uasm_i_nop(&p); 1981 1982 if (p >= (u32 *)handle_tlbs_end) 1983 panic("TLB store handler fastpath space exceeded"); 1984 1985 uasm_resolve_relocs(relocs, labels); 1986 pr_debug("Wrote TLB store handler fastpath (%u instructions).\n", 1987 (unsigned int)(p - (u32 *)handle_tlbs)); 1988 1989 dump_handler("r3000_tlb_store", handle_tlbs, handle_tlbs_end); 1990 } 1991 1992 static void build_r3000_tlb_modify_handler(void) 1993 { 1994 u32 *p = (u32 *)handle_tlbm; 1995 struct uasm_label *l = labels; 1996 struct uasm_reloc *r = relocs; 1997 1998 memset(p, 0, handle_tlbm_end - (char *)p); 1999 memset(labels, 0, sizeof(labels)); 2000 memset(relocs, 0, sizeof(relocs)); 2001 2002 build_r3000_tlbchange_handler_head(&p, K0, K1); 2003 build_pte_modifiable(&p, &r, K0, K1, -1, label_nopage_tlbm); 2004 uasm_i_nop(&p); /* load delay */ 2005 build_make_write(&p, &r, K0, K1, -1); 2006 build_r3000_pte_reload_tlbwi(&p, K0, K1); 2007 2008 uasm_l_nopage_tlbm(&l, p); 2009 uasm_i_j(&p, (unsigned long)tlb_do_page_fault_1 & 0x0fffffff); 2010 uasm_i_nop(&p); 2011 2012 if (p >= (u32 *)handle_tlbm_end) 2013 panic("TLB modify handler fastpath space exceeded"); 2014 2015 uasm_resolve_relocs(relocs, labels); 2016 pr_debug("Wrote TLB modify handler fastpath (%u instructions).\n", 2017 (unsigned int)(p - (u32 *)handle_tlbm)); 2018 2019 dump_handler("r3000_tlb_modify", handle_tlbm, handle_tlbm_end); 2020 } 2021 #endif /* CONFIG_MIPS_PGD_C0_CONTEXT */ 2022 2023 static bool cpu_has_tlbex_tlbp_race(void) 2024 { 2025 /* 2026 * When a Hardware Table Walker is running it can replace TLB entries 2027 * at any time, leading to a race between it & the CPU. 2028 */ 2029 if (cpu_has_htw) 2030 return true; 2031 2032 /* 2033 * If the CPU shares FTLB RAM with its siblings then our entry may be 2034 * replaced at any time by a sibling performing a write to the FTLB. 2035 */ 2036 if (cpu_has_shared_ftlb_ram) 2037 return true; 2038 2039 /* In all other cases there ought to be no race condition to handle */ 2040 return false; 2041 } 2042 2043 /* 2044 * R4000 style TLB load/store/modify handlers. 2045 */ 2046 static struct work_registers 2047 build_r4000_tlbchange_handler_head(u32 **p, struct uasm_label **l, 2048 struct uasm_reloc **r) 2049 { 2050 struct work_registers wr = build_get_work_registers(p); 2051 2052 #ifdef CONFIG_64BIT 2053 build_get_pmde64(p, l, r, wr.r1, wr.r2); /* get pmd in ptr */ 2054 #else 2055 build_get_pgde32(p, wr.r1, wr.r2); /* get pgd in ptr */ 2056 #endif 2057 2058 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT 2059 /* 2060 * For huge tlb entries, pmd doesn't contain an address but 2061 * instead contains the tlb pte. Check the PAGE_HUGE bit and 2062 * see if we need to jump to huge tlb processing. 2063 */ 2064 build_is_huge_pte(p, r, wr.r1, wr.r2, label_tlb_huge_update); 2065 #endif 2066 2067 UASM_i_MFC0(p, wr.r1, C0_BADVADDR); 2068 UASM_i_LW(p, wr.r2, 0, wr.r2); 2069 UASM_i_SRL(p, wr.r1, wr.r1, PAGE_SHIFT + PTE_ORDER - PTE_T_LOG2); 2070 uasm_i_andi(p, wr.r1, wr.r1, (PTRS_PER_PTE - 1) << PTE_T_LOG2); 2071 UASM_i_ADDU(p, wr.r2, wr.r2, wr.r1); 2072 2073 #ifdef CONFIG_SMP 2074 uasm_l_smp_pgtable_change(l, *p); 2075 #endif 2076 iPTE_LW(p, wr.r1, wr.r2); /* get even pte */ 2077 if (!m4kc_tlbp_war()) { 2078 build_tlb_probe_entry(p); 2079 if (cpu_has_tlbex_tlbp_race()) { 2080 /* race condition happens, leaving */ 2081 uasm_i_ehb(p); 2082 uasm_i_mfc0(p, wr.r3, C0_INDEX); 2083 uasm_il_bltz(p, r, wr.r3, label_leave); 2084 uasm_i_nop(p); 2085 } 2086 } 2087 return wr; 2088 } 2089 2090 static void 2091 build_r4000_tlbchange_handler_tail(u32 **p, struct uasm_label **l, 2092 struct uasm_reloc **r, unsigned int tmp, 2093 unsigned int ptr) 2094 { 2095 uasm_i_ori(p, ptr, ptr, sizeof(pte_t)); 2096 uasm_i_xori(p, ptr, ptr, sizeof(pte_t)); 2097 build_update_entries(p, tmp, ptr); 2098 build_tlb_write_entry(p, l, r, tlb_indexed); 2099 uasm_l_leave(l, *p); 2100 build_restore_work_registers(p); 2101 uasm_i_eret(p); /* return from trap */ 2102 2103 #ifdef CONFIG_64BIT 2104 build_get_pgd_vmalloc64(p, l, r, tmp, ptr, not_refill); 2105 #endif 2106 } 2107 2108 static void build_r4000_tlb_load_handler(void) 2109 { 2110 u32 *p = (u32 *)msk_isa16_mode((ulong)handle_tlbl); 2111 struct uasm_label *l = labels; 2112 struct uasm_reloc *r = relocs; 2113 struct work_registers wr; 2114 2115 memset(p, 0, handle_tlbl_end - (char *)p); 2116 memset(labels, 0, sizeof(labels)); 2117 memset(relocs, 0, sizeof(relocs)); 2118 2119 if (bcm1250_m3_war()) { 2120 unsigned int segbits = 44; 2121 2122 uasm_i_dmfc0(&p, K0, C0_BADVADDR); 2123 uasm_i_dmfc0(&p, K1, C0_ENTRYHI); 2124 uasm_i_xor(&p, K0, K0, K1); 2125 uasm_i_dsrl_safe(&p, K1, K0, 62); 2126 uasm_i_dsrl_safe(&p, K0, K0, 12 + 1); 2127 uasm_i_dsll_safe(&p, K0, K0, 64 + 12 + 1 - segbits); 2128 uasm_i_or(&p, K0, K0, K1); 2129 uasm_il_bnez(&p, &r, K0, label_leave); 2130 /* No need for uasm_i_nop */ 2131 } 2132 2133 wr = build_r4000_tlbchange_handler_head(&p, &l, &r); 2134 build_pte_present(&p, &r, wr.r1, wr.r2, wr.r3, label_nopage_tlbl); 2135 if (m4kc_tlbp_war()) 2136 build_tlb_probe_entry(&p); 2137 2138 if (cpu_has_rixi && !cpu_has_rixiex) { 2139 /* 2140 * If the page is not _PAGE_VALID, RI or XI could not 2141 * have triggered it. Skip the expensive test.. 2142 */ 2143 if (use_bbit_insns()) { 2144 uasm_il_bbit0(&p, &r, wr.r1, ilog2(_PAGE_VALID), 2145 label_tlbl_goaround1); 2146 } else { 2147 uasm_i_andi(&p, wr.r3, wr.r1, _PAGE_VALID); 2148 uasm_il_beqz(&p, &r, wr.r3, label_tlbl_goaround1); 2149 } 2150 uasm_i_nop(&p); 2151 2152 /* 2153 * Warn if something may race with us & replace the TLB entry 2154 * before we read it here. Everything with such races should 2155 * also have dedicated RiXi exception handlers, so this 2156 * shouldn't be hit. 2157 */ 2158 WARN(cpu_has_tlbex_tlbp_race(), "Unhandled race in RiXi path"); 2159 2160 uasm_i_tlbr(&p); 2161 2162 switch (current_cpu_type()) { 2163 default: 2164 if (cpu_has_mips_r2_exec_hazard) { 2165 uasm_i_ehb(&p); 2166 fallthrough; 2167 2168 case CPU_CAVIUM_OCTEON: 2169 case CPU_CAVIUM_OCTEON_PLUS: 2170 case CPU_CAVIUM_OCTEON2: 2171 break; 2172 } 2173 } 2174 2175 /* Examine entrylo 0 or 1 based on ptr. */ 2176 if (use_bbit_insns()) { 2177 uasm_i_bbit0(&p, wr.r2, ilog2(sizeof(pte_t)), 8); 2178 } else { 2179 uasm_i_andi(&p, wr.r3, wr.r2, sizeof(pte_t)); 2180 uasm_i_beqz(&p, wr.r3, 8); 2181 } 2182 /* load it in the delay slot*/ 2183 UASM_i_MFC0(&p, wr.r3, C0_ENTRYLO0); 2184 /* load it if ptr is odd */ 2185 UASM_i_MFC0(&p, wr.r3, C0_ENTRYLO1); 2186 /* 2187 * If the entryLo (now in wr.r3) is valid (bit 1), RI or 2188 * XI must have triggered it. 2189 */ 2190 if (use_bbit_insns()) { 2191 uasm_il_bbit1(&p, &r, wr.r3, 1, label_nopage_tlbl); 2192 uasm_i_nop(&p); 2193 uasm_l_tlbl_goaround1(&l, p); 2194 } else { 2195 uasm_i_andi(&p, wr.r3, wr.r3, 2); 2196 uasm_il_bnez(&p, &r, wr.r3, label_nopage_tlbl); 2197 uasm_i_nop(&p); 2198 } 2199 uasm_l_tlbl_goaround1(&l, p); 2200 } 2201 build_make_valid(&p, &r, wr.r1, wr.r2, wr.r3); 2202 build_r4000_tlbchange_handler_tail(&p, &l, &r, wr.r1, wr.r2); 2203 2204 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT 2205 /* 2206 * This is the entry point when build_r4000_tlbchange_handler_head 2207 * spots a huge page. 2208 */ 2209 uasm_l_tlb_huge_update(&l, p); 2210 iPTE_LW(&p, wr.r1, wr.r2); 2211 build_pte_present(&p, &r, wr.r1, wr.r2, wr.r3, label_nopage_tlbl); 2212 build_tlb_probe_entry(&p); 2213 2214 if (cpu_has_rixi && !cpu_has_rixiex) { 2215 /* 2216 * If the page is not _PAGE_VALID, RI or XI could not 2217 * have triggered it. Skip the expensive test.. 2218 */ 2219 if (use_bbit_insns()) { 2220 uasm_il_bbit0(&p, &r, wr.r1, ilog2(_PAGE_VALID), 2221 label_tlbl_goaround2); 2222 } else { 2223 uasm_i_andi(&p, wr.r3, wr.r1, _PAGE_VALID); 2224 uasm_il_beqz(&p, &r, wr.r3, label_tlbl_goaround2); 2225 } 2226 uasm_i_nop(&p); 2227 2228 /* 2229 * Warn if something may race with us & replace the TLB entry 2230 * before we read it here. Everything with such races should 2231 * also have dedicated RiXi exception handlers, so this 2232 * shouldn't be hit. 2233 */ 2234 WARN(cpu_has_tlbex_tlbp_race(), "Unhandled race in RiXi path"); 2235 2236 uasm_i_tlbr(&p); 2237 2238 switch (current_cpu_type()) { 2239 default: 2240 if (cpu_has_mips_r2_exec_hazard) { 2241 uasm_i_ehb(&p); 2242 2243 case CPU_CAVIUM_OCTEON: 2244 case CPU_CAVIUM_OCTEON_PLUS: 2245 case CPU_CAVIUM_OCTEON2: 2246 break; 2247 } 2248 } 2249 2250 /* Examine entrylo 0 or 1 based on ptr. */ 2251 if (use_bbit_insns()) { 2252 uasm_i_bbit0(&p, wr.r2, ilog2(sizeof(pte_t)), 8); 2253 } else { 2254 uasm_i_andi(&p, wr.r3, wr.r2, sizeof(pte_t)); 2255 uasm_i_beqz(&p, wr.r3, 8); 2256 } 2257 /* load it in the delay slot*/ 2258 UASM_i_MFC0(&p, wr.r3, C0_ENTRYLO0); 2259 /* load it if ptr is odd */ 2260 UASM_i_MFC0(&p, wr.r3, C0_ENTRYLO1); 2261 /* 2262 * If the entryLo (now in wr.r3) is valid (bit 1), RI or 2263 * XI must have triggered it. 2264 */ 2265 if (use_bbit_insns()) { 2266 uasm_il_bbit0(&p, &r, wr.r3, 1, label_tlbl_goaround2); 2267 } else { 2268 uasm_i_andi(&p, wr.r3, wr.r3, 2); 2269 uasm_il_beqz(&p, &r, wr.r3, label_tlbl_goaround2); 2270 } 2271 if (PM_DEFAULT_MASK == 0) 2272 uasm_i_nop(&p); 2273 /* 2274 * We clobbered C0_PAGEMASK, restore it. On the other branch 2275 * it is restored in build_huge_tlb_write_entry. 2276 */ 2277 build_restore_pagemask(&p, &r, wr.r3, label_nopage_tlbl, 0); 2278 2279 uasm_l_tlbl_goaround2(&l, p); 2280 } 2281 uasm_i_ori(&p, wr.r1, wr.r1, (_PAGE_ACCESSED | _PAGE_VALID)); 2282 build_huge_handler_tail(&p, &r, &l, wr.r1, wr.r2, 1); 2283 #endif 2284 2285 uasm_l_nopage_tlbl(&l, p); 2286 if (IS_ENABLED(CONFIG_CPU_LOONGSON3_WORKAROUNDS)) 2287 uasm_i_sync(&p, 0); 2288 build_restore_work_registers(&p); 2289 #ifdef CONFIG_CPU_MICROMIPS 2290 if ((unsigned long)tlb_do_page_fault_0 & 1) { 2291 uasm_i_lui(&p, K0, uasm_rel_hi((long)tlb_do_page_fault_0)); 2292 uasm_i_addiu(&p, K0, K0, uasm_rel_lo((long)tlb_do_page_fault_0)); 2293 uasm_i_jr(&p, K0); 2294 } else 2295 #endif 2296 uasm_i_j(&p, (unsigned long)tlb_do_page_fault_0 & 0x0fffffff); 2297 uasm_i_nop(&p); 2298 2299 if (p >= (u32 *)handle_tlbl_end) 2300 panic("TLB load handler fastpath space exceeded"); 2301 2302 uasm_resolve_relocs(relocs, labels); 2303 pr_debug("Wrote TLB load handler fastpath (%u instructions).\n", 2304 (unsigned int)(p - (u32 *)handle_tlbl)); 2305 2306 dump_handler("r4000_tlb_load", handle_tlbl, handle_tlbl_end); 2307 } 2308 2309 static void build_r4000_tlb_store_handler(void) 2310 { 2311 u32 *p = (u32 *)msk_isa16_mode((ulong)handle_tlbs); 2312 struct uasm_label *l = labels; 2313 struct uasm_reloc *r = relocs; 2314 struct work_registers wr; 2315 2316 memset(p, 0, handle_tlbs_end - (char *)p); 2317 memset(labels, 0, sizeof(labels)); 2318 memset(relocs, 0, sizeof(relocs)); 2319 2320 wr = build_r4000_tlbchange_handler_head(&p, &l, &r); 2321 build_pte_writable(&p, &r, wr.r1, wr.r2, wr.r3, label_nopage_tlbs); 2322 if (m4kc_tlbp_war()) 2323 build_tlb_probe_entry(&p); 2324 build_make_write(&p, &r, wr.r1, wr.r2, wr.r3); 2325 build_r4000_tlbchange_handler_tail(&p, &l, &r, wr.r1, wr.r2); 2326 2327 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT 2328 /* 2329 * This is the entry point when 2330 * build_r4000_tlbchange_handler_head spots a huge page. 2331 */ 2332 uasm_l_tlb_huge_update(&l, p); 2333 iPTE_LW(&p, wr.r1, wr.r2); 2334 build_pte_writable(&p, &r, wr.r1, wr.r2, wr.r3, label_nopage_tlbs); 2335 build_tlb_probe_entry(&p); 2336 uasm_i_ori(&p, wr.r1, wr.r1, 2337 _PAGE_ACCESSED | _PAGE_MODIFIED | _PAGE_VALID | _PAGE_DIRTY); 2338 build_huge_handler_tail(&p, &r, &l, wr.r1, wr.r2, 1); 2339 #endif 2340 2341 uasm_l_nopage_tlbs(&l, p); 2342 if (IS_ENABLED(CONFIG_CPU_LOONGSON3_WORKAROUNDS)) 2343 uasm_i_sync(&p, 0); 2344 build_restore_work_registers(&p); 2345 #ifdef CONFIG_CPU_MICROMIPS 2346 if ((unsigned long)tlb_do_page_fault_1 & 1) { 2347 uasm_i_lui(&p, K0, uasm_rel_hi((long)tlb_do_page_fault_1)); 2348 uasm_i_addiu(&p, K0, K0, uasm_rel_lo((long)tlb_do_page_fault_1)); 2349 uasm_i_jr(&p, K0); 2350 } else 2351 #endif 2352 uasm_i_j(&p, (unsigned long)tlb_do_page_fault_1 & 0x0fffffff); 2353 uasm_i_nop(&p); 2354 2355 if (p >= (u32 *)handle_tlbs_end) 2356 panic("TLB store handler fastpath space exceeded"); 2357 2358 uasm_resolve_relocs(relocs, labels); 2359 pr_debug("Wrote TLB store handler fastpath (%u instructions).\n", 2360 (unsigned int)(p - (u32 *)handle_tlbs)); 2361 2362 dump_handler("r4000_tlb_store", handle_tlbs, handle_tlbs_end); 2363 } 2364 2365 static void build_r4000_tlb_modify_handler(void) 2366 { 2367 u32 *p = (u32 *)msk_isa16_mode((ulong)handle_tlbm); 2368 struct uasm_label *l = labels; 2369 struct uasm_reloc *r = relocs; 2370 struct work_registers wr; 2371 2372 memset(p, 0, handle_tlbm_end - (char *)p); 2373 memset(labels, 0, sizeof(labels)); 2374 memset(relocs, 0, sizeof(relocs)); 2375 2376 wr = build_r4000_tlbchange_handler_head(&p, &l, &r); 2377 build_pte_modifiable(&p, &r, wr.r1, wr.r2, wr.r3, label_nopage_tlbm); 2378 if (m4kc_tlbp_war()) 2379 build_tlb_probe_entry(&p); 2380 /* Present and writable bits set, set accessed and dirty bits. */ 2381 build_make_write(&p, &r, wr.r1, wr.r2, wr.r3); 2382 build_r4000_tlbchange_handler_tail(&p, &l, &r, wr.r1, wr.r2); 2383 2384 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT 2385 /* 2386 * This is the entry point when 2387 * build_r4000_tlbchange_handler_head spots a huge page. 2388 */ 2389 uasm_l_tlb_huge_update(&l, p); 2390 iPTE_LW(&p, wr.r1, wr.r2); 2391 build_pte_modifiable(&p, &r, wr.r1, wr.r2, wr.r3, label_nopage_tlbm); 2392 build_tlb_probe_entry(&p); 2393 uasm_i_ori(&p, wr.r1, wr.r1, 2394 _PAGE_ACCESSED | _PAGE_MODIFIED | _PAGE_VALID | _PAGE_DIRTY); 2395 build_huge_handler_tail(&p, &r, &l, wr.r1, wr.r2, 0); 2396 #endif 2397 2398 uasm_l_nopage_tlbm(&l, p); 2399 if (IS_ENABLED(CONFIG_CPU_LOONGSON3_WORKAROUNDS)) 2400 uasm_i_sync(&p, 0); 2401 build_restore_work_registers(&p); 2402 #ifdef CONFIG_CPU_MICROMIPS 2403 if ((unsigned long)tlb_do_page_fault_1 & 1) { 2404 uasm_i_lui(&p, K0, uasm_rel_hi((long)tlb_do_page_fault_1)); 2405 uasm_i_addiu(&p, K0, K0, uasm_rel_lo((long)tlb_do_page_fault_1)); 2406 uasm_i_jr(&p, K0); 2407 } else 2408 #endif 2409 uasm_i_j(&p, (unsigned long)tlb_do_page_fault_1 & 0x0fffffff); 2410 uasm_i_nop(&p); 2411 2412 if (p >= (u32 *)handle_tlbm_end) 2413 panic("TLB modify handler fastpath space exceeded"); 2414 2415 uasm_resolve_relocs(relocs, labels); 2416 pr_debug("Wrote TLB modify handler fastpath (%u instructions).\n", 2417 (unsigned int)(p - (u32 *)handle_tlbm)); 2418 2419 dump_handler("r4000_tlb_modify", handle_tlbm, handle_tlbm_end); 2420 } 2421 2422 static void flush_tlb_handlers(void) 2423 { 2424 local_flush_icache_range((unsigned long)handle_tlbl, 2425 (unsigned long)handle_tlbl_end); 2426 local_flush_icache_range((unsigned long)handle_tlbs, 2427 (unsigned long)handle_tlbs_end); 2428 local_flush_icache_range((unsigned long)handle_tlbm, 2429 (unsigned long)handle_tlbm_end); 2430 local_flush_icache_range((unsigned long)tlbmiss_handler_setup_pgd, 2431 (unsigned long)tlbmiss_handler_setup_pgd_end); 2432 } 2433 2434 static void print_htw_config(void) 2435 { 2436 unsigned long config; 2437 unsigned int pwctl; 2438 const int field = 2 * sizeof(unsigned long); 2439 2440 config = read_c0_pwfield(); 2441 pr_debug("PWField (0x%0*lx): GDI: 0x%02lx UDI: 0x%02lx MDI: 0x%02lx PTI: 0x%02lx PTEI: 0x%02lx\n", 2442 field, config, 2443 (config & MIPS_PWFIELD_GDI_MASK) >> MIPS_PWFIELD_GDI_SHIFT, 2444 (config & MIPS_PWFIELD_UDI_MASK) >> MIPS_PWFIELD_UDI_SHIFT, 2445 (config & MIPS_PWFIELD_MDI_MASK) >> MIPS_PWFIELD_MDI_SHIFT, 2446 (config & MIPS_PWFIELD_PTI_MASK) >> MIPS_PWFIELD_PTI_SHIFT, 2447 (config & MIPS_PWFIELD_PTEI_MASK) >> MIPS_PWFIELD_PTEI_SHIFT); 2448 2449 config = read_c0_pwsize(); 2450 pr_debug("PWSize (0x%0*lx): PS: 0x%lx GDW: 0x%02lx UDW: 0x%02lx MDW: 0x%02lx PTW: 0x%02lx PTEW: 0x%02lx\n", 2451 field, config, 2452 (config & MIPS_PWSIZE_PS_MASK) >> MIPS_PWSIZE_PS_SHIFT, 2453 (config & MIPS_PWSIZE_GDW_MASK) >> MIPS_PWSIZE_GDW_SHIFT, 2454 (config & MIPS_PWSIZE_UDW_MASK) >> MIPS_PWSIZE_UDW_SHIFT, 2455 (config & MIPS_PWSIZE_MDW_MASK) >> MIPS_PWSIZE_MDW_SHIFT, 2456 (config & MIPS_PWSIZE_PTW_MASK) >> MIPS_PWSIZE_PTW_SHIFT, 2457 (config & MIPS_PWSIZE_PTEW_MASK) >> MIPS_PWSIZE_PTEW_SHIFT); 2458 2459 pwctl = read_c0_pwctl(); 2460 pr_debug("PWCtl (0x%x): PWEn: 0x%x XK: 0x%x XS: 0x%x XU: 0x%x DPH: 0x%x HugePg: 0x%x Psn: 0x%x\n", 2461 pwctl, 2462 (pwctl & MIPS_PWCTL_PWEN_MASK) >> MIPS_PWCTL_PWEN_SHIFT, 2463 (pwctl & MIPS_PWCTL_XK_MASK) >> MIPS_PWCTL_XK_SHIFT, 2464 (pwctl & MIPS_PWCTL_XS_MASK) >> MIPS_PWCTL_XS_SHIFT, 2465 (pwctl & MIPS_PWCTL_XU_MASK) >> MIPS_PWCTL_XU_SHIFT, 2466 (pwctl & MIPS_PWCTL_DPH_MASK) >> MIPS_PWCTL_DPH_SHIFT, 2467 (pwctl & MIPS_PWCTL_HUGEPG_MASK) >> MIPS_PWCTL_HUGEPG_SHIFT, 2468 (pwctl & MIPS_PWCTL_PSN_MASK) >> MIPS_PWCTL_PSN_SHIFT); 2469 } 2470 2471 static void config_htw_params(void) 2472 { 2473 unsigned long pwfield, pwsize, ptei; 2474 unsigned int config; 2475 2476 /* 2477 * We are using 2-level page tables, so we only need to 2478 * setup GDW and PTW appropriately. UDW and MDW will remain 0. 2479 * The default value of GDI/UDI/MDI/PTI is 0xc. It is illegal to 2480 * write values less than 0xc in these fields because the entire 2481 * write will be dropped. As a result of which, we must preserve 2482 * the original reset values and overwrite only what we really want. 2483 */ 2484 2485 pwfield = read_c0_pwfield(); 2486 /* re-initialize the GDI field */ 2487 pwfield &= ~MIPS_PWFIELD_GDI_MASK; 2488 pwfield |= PGDIR_SHIFT << MIPS_PWFIELD_GDI_SHIFT; 2489 /* re-initialize the PTI field including the even/odd bit */ 2490 pwfield &= ~MIPS_PWFIELD_PTI_MASK; 2491 pwfield |= PAGE_SHIFT << MIPS_PWFIELD_PTI_SHIFT; 2492 if (CONFIG_PGTABLE_LEVELS >= 3) { 2493 pwfield &= ~MIPS_PWFIELD_MDI_MASK; 2494 pwfield |= PMD_SHIFT << MIPS_PWFIELD_MDI_SHIFT; 2495 } 2496 /* Set the PTEI right shift */ 2497 ptei = _PAGE_GLOBAL_SHIFT << MIPS_PWFIELD_PTEI_SHIFT; 2498 pwfield |= ptei; 2499 write_c0_pwfield(pwfield); 2500 /* Check whether the PTEI value is supported */ 2501 back_to_back_c0_hazard(); 2502 pwfield = read_c0_pwfield(); 2503 if (((pwfield & MIPS_PWFIELD_PTEI_MASK) << MIPS_PWFIELD_PTEI_SHIFT) 2504 != ptei) { 2505 pr_warn("Unsupported PTEI field value: 0x%lx. HTW will not be enabled", 2506 ptei); 2507 /* 2508 * Drop option to avoid HTW being enabled via another path 2509 * (eg htw_reset()) 2510 */ 2511 current_cpu_data.options &= ~MIPS_CPU_HTW; 2512 return; 2513 } 2514 2515 pwsize = ilog2(PTRS_PER_PGD) << MIPS_PWSIZE_GDW_SHIFT; 2516 pwsize |= ilog2(PTRS_PER_PTE) << MIPS_PWSIZE_PTW_SHIFT; 2517 if (CONFIG_PGTABLE_LEVELS >= 3) 2518 pwsize |= ilog2(PTRS_PER_PMD) << MIPS_PWSIZE_MDW_SHIFT; 2519 2520 /* Set pointer size to size of directory pointers */ 2521 if (IS_ENABLED(CONFIG_64BIT)) 2522 pwsize |= MIPS_PWSIZE_PS_MASK; 2523 /* PTEs may be multiple pointers long (e.g. with XPA) */ 2524 pwsize |= ((PTE_T_LOG2 - PGD_T_LOG2) << MIPS_PWSIZE_PTEW_SHIFT) 2525 & MIPS_PWSIZE_PTEW_MASK; 2526 2527 write_c0_pwsize(pwsize); 2528 2529 /* Make sure everything is set before we enable the HTW */ 2530 back_to_back_c0_hazard(); 2531 2532 /* 2533 * Enable HTW (and only for XUSeg on 64-bit), and disable the rest of 2534 * the pwctl fields. 2535 */ 2536 config = 1 << MIPS_PWCTL_PWEN_SHIFT; 2537 if (IS_ENABLED(CONFIG_64BIT)) 2538 config |= MIPS_PWCTL_XU_MASK; 2539 write_c0_pwctl(config); 2540 pr_info("Hardware Page Table Walker enabled\n"); 2541 2542 print_htw_config(); 2543 } 2544 2545 static void config_xpa_params(void) 2546 { 2547 #ifdef CONFIG_XPA 2548 unsigned int pagegrain; 2549 2550 if (mips_xpa_disabled) { 2551 pr_info("Extended Physical Addressing (XPA) disabled\n"); 2552 return; 2553 } 2554 2555 pagegrain = read_c0_pagegrain(); 2556 write_c0_pagegrain(pagegrain | PG_ELPA); 2557 back_to_back_c0_hazard(); 2558 pagegrain = read_c0_pagegrain(); 2559 2560 if (pagegrain & PG_ELPA) 2561 pr_info("Extended Physical Addressing (XPA) enabled\n"); 2562 else 2563 panic("Extended Physical Addressing (XPA) disabled"); 2564 #endif 2565 } 2566 2567 static void check_pabits(void) 2568 { 2569 unsigned long entry; 2570 unsigned pabits, fillbits; 2571 2572 if (!cpu_has_rixi || !_PAGE_NO_EXEC) { 2573 /* 2574 * We'll only be making use of the fact that we can rotate bits 2575 * into the fill if the CPU supports RIXI, so don't bother 2576 * probing this for CPUs which don't. 2577 */ 2578 return; 2579 } 2580 2581 write_c0_entrylo0(~0ul); 2582 back_to_back_c0_hazard(); 2583 entry = read_c0_entrylo0(); 2584 2585 /* clear all non-PFN bits */ 2586 entry &= ~((1 << MIPS_ENTRYLO_PFN_SHIFT) - 1); 2587 entry &= ~(MIPS_ENTRYLO_RI | MIPS_ENTRYLO_XI); 2588 2589 /* find a lower bound on PABITS, and upper bound on fill bits */ 2590 pabits = fls_long(entry) + 6; 2591 fillbits = max_t(int, (int)BITS_PER_LONG - pabits, 0); 2592 2593 /* minus the RI & XI bits */ 2594 fillbits -= min_t(unsigned, fillbits, 2); 2595 2596 if (fillbits >= ilog2(_PAGE_NO_EXEC)) 2597 fill_includes_sw_bits = true; 2598 2599 pr_debug("Entry* registers contain %u fill bits\n", fillbits); 2600 } 2601 2602 void build_tlb_refill_handler(void) 2603 { 2604 /* 2605 * The refill handler is generated per-CPU, multi-node systems 2606 * may have local storage for it. The other handlers are only 2607 * needed once. 2608 */ 2609 static int run_once = 0; 2610 2611 if (IS_ENABLED(CONFIG_XPA) && !cpu_has_rixi) 2612 panic("Kernels supporting XPA currently require CPUs with RIXI"); 2613 2614 output_pgtable_bits_defines(); 2615 check_pabits(); 2616 2617 #ifdef CONFIG_64BIT 2618 check_for_high_segbits = current_cpu_data.vmbits > (PGDIR_SHIFT + PGD_ORDER + PAGE_SHIFT - 3); 2619 #endif 2620 2621 if (cpu_has_3kex) { 2622 #ifndef CONFIG_MIPS_PGD_C0_CONTEXT 2623 if (!run_once) { 2624 build_setup_pgd(); 2625 build_r3000_tlb_refill_handler(); 2626 build_r3000_tlb_load_handler(); 2627 build_r3000_tlb_store_handler(); 2628 build_r3000_tlb_modify_handler(); 2629 flush_tlb_handlers(); 2630 run_once++; 2631 } 2632 #else 2633 panic("No R3000 TLB refill handler"); 2634 #endif 2635 return; 2636 } 2637 2638 if (cpu_has_ldpte) 2639 setup_pw(); 2640 2641 if (!run_once) { 2642 scratch_reg = allocate_kscratch(); 2643 build_setup_pgd(); 2644 build_r4000_tlb_load_handler(); 2645 build_r4000_tlb_store_handler(); 2646 build_r4000_tlb_modify_handler(); 2647 if (cpu_has_ldpte) 2648 build_loongson3_tlb_refill_handler(); 2649 else 2650 build_r4000_tlb_refill_handler(); 2651 flush_tlb_handlers(); 2652 run_once++; 2653 } 2654 if (cpu_has_xpa) 2655 config_xpa_params(); 2656 if (cpu_has_htw) 2657 config_htw_params(); 2658 } 2659