1 /* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * Synthesize TLB refill handlers at runtime. 7 * 8 * Copyright (C) 2004,2005 by Thiemo Seufer 9 * Copyright (C) 2005 Maciej W. Rozycki 10 * Copyright (C) 2006 Ralf Baechle (ralf@linux-mips.org) 11 * 12 * ... and the days got worse and worse and now you see 13 * I've gone completly out of my mind. 14 * 15 * They're coming to take me a away haha 16 * they're coming to take me a away hoho hihi haha 17 * to the funny farm where code is beautiful all the time ... 18 * 19 * (Condolences to Napoleon XIV) 20 */ 21 22 #include <stdarg.h> 23 24 #include <linux/config.h> 25 #include <linux/mm.h> 26 #include <linux/kernel.h> 27 #include <linux/types.h> 28 #include <linux/string.h> 29 #include <linux/init.h> 30 31 #include <asm/pgtable.h> 32 #include <asm/cacheflush.h> 33 #include <asm/mmu_context.h> 34 #include <asm/inst.h> 35 #include <asm/elf.h> 36 #include <asm/smp.h> 37 #include <asm/war.h> 38 39 /* #define DEBUG_TLB */ 40 41 static __init int __attribute__((unused)) r45k_bvahwbug(void) 42 { 43 /* XXX: We should probe for the presence of this bug, but we don't. */ 44 return 0; 45 } 46 47 static __init int __attribute__((unused)) r4k_250MHZhwbug(void) 48 { 49 /* XXX: We should probe for the presence of this bug, but we don't. */ 50 return 0; 51 } 52 53 static __init int __attribute__((unused)) bcm1250_m3_war(void) 54 { 55 return BCM1250_M3_WAR; 56 } 57 58 static __init int __attribute__((unused)) r10000_llsc_war(void) 59 { 60 return R10000_LLSC_WAR; 61 } 62 63 /* 64 * A little micro-assembler, intended for TLB refill handler 65 * synthesizing. It is intentionally kept simple, does only support 66 * a subset of instructions, and does not try to hide pipeline effects 67 * like branch delay slots. 68 */ 69 70 enum fields 71 { 72 RS = 0x001, 73 RT = 0x002, 74 RD = 0x004, 75 RE = 0x008, 76 SIMM = 0x010, 77 UIMM = 0x020, 78 BIMM = 0x040, 79 JIMM = 0x080, 80 FUNC = 0x100, 81 SET = 0x200 82 }; 83 84 #define OP_MASK 0x2f 85 #define OP_SH 26 86 #define RS_MASK 0x1f 87 #define RS_SH 21 88 #define RT_MASK 0x1f 89 #define RT_SH 16 90 #define RD_MASK 0x1f 91 #define RD_SH 11 92 #define RE_MASK 0x1f 93 #define RE_SH 6 94 #define IMM_MASK 0xffff 95 #define IMM_SH 0 96 #define JIMM_MASK 0x3ffffff 97 #define JIMM_SH 0 98 #define FUNC_MASK 0x2f 99 #define FUNC_SH 0 100 #define SET_MASK 0x7 101 #define SET_SH 0 102 103 enum opcode { 104 insn_invalid, 105 insn_addu, insn_addiu, insn_and, insn_andi, insn_beq, 106 insn_beql, insn_bgez, insn_bgezl, insn_bltz, insn_bltzl, 107 insn_bne, insn_daddu, insn_daddiu, insn_dmfc0, insn_dmtc0, 108 insn_dsll, insn_dsll32, insn_dsra, insn_dsrl, 109 insn_dsubu, insn_eret, insn_j, insn_jal, insn_jr, insn_ld, 110 insn_ll, insn_lld, insn_lui, insn_lw, insn_mfc0, insn_mtc0, 111 insn_ori, insn_rfe, insn_sc, insn_scd, insn_sd, insn_sll, 112 insn_sra, insn_srl, insn_subu, insn_sw, insn_tlbp, insn_tlbwi, 113 insn_tlbwr, insn_xor, insn_xori 114 }; 115 116 struct insn { 117 enum opcode opcode; 118 u32 match; 119 enum fields fields; 120 }; 121 122 /* This macro sets the non-variable bits of an instruction. */ 123 #define M(a, b, c, d, e, f) \ 124 ((a) << OP_SH \ 125 | (b) << RS_SH \ 126 | (c) << RT_SH \ 127 | (d) << RD_SH \ 128 | (e) << RE_SH \ 129 | (f) << FUNC_SH) 130 131 static __initdata struct insn insn_table[] = { 132 { insn_addiu, M(addiu_op,0,0,0,0,0), RS | RT | SIMM }, 133 { insn_addu, M(spec_op,0,0,0,0,addu_op), RS | RT | RD }, 134 { insn_and, M(spec_op,0,0,0,0,and_op), RS | RT | RD }, 135 { insn_andi, M(andi_op,0,0,0,0,0), RS | RT | UIMM }, 136 { insn_beq, M(beq_op,0,0,0,0,0), RS | RT | BIMM }, 137 { insn_beql, M(beql_op,0,0,0,0,0), RS | RT | BIMM }, 138 { insn_bgez, M(bcond_op,0,bgez_op,0,0,0), RS | BIMM }, 139 { insn_bgezl, M(bcond_op,0,bgezl_op,0,0,0), RS | BIMM }, 140 { insn_bltz, M(bcond_op,0,bltz_op,0,0,0), RS | BIMM }, 141 { insn_bltzl, M(bcond_op,0,bltzl_op,0,0,0), RS | BIMM }, 142 { insn_bne, M(bne_op,0,0,0,0,0), RS | RT | BIMM }, 143 { insn_daddiu, M(daddiu_op,0,0,0,0,0), RS | RT | SIMM }, 144 { insn_daddu, M(spec_op,0,0,0,0,daddu_op), RS | RT | RD }, 145 { insn_dmfc0, M(cop0_op,dmfc_op,0,0,0,0), RT | RD | SET}, 146 { insn_dmtc0, M(cop0_op,dmtc_op,0,0,0,0), RT | RD | SET}, 147 { insn_dsll, M(spec_op,0,0,0,0,dsll_op), RT | RD | RE }, 148 { insn_dsll32, M(spec_op,0,0,0,0,dsll32_op), RT | RD | RE }, 149 { insn_dsra, M(spec_op,0,0,0,0,dsra_op), RT | RD | RE }, 150 { insn_dsrl, M(spec_op,0,0,0,0,dsrl_op), RT | RD | RE }, 151 { insn_dsubu, M(spec_op,0,0,0,0,dsubu_op), RS | RT | RD }, 152 { insn_eret, M(cop0_op,cop_op,0,0,0,eret_op), 0 }, 153 { insn_j, M(j_op,0,0,0,0,0), JIMM }, 154 { insn_jal, M(jal_op,0,0,0,0,0), JIMM }, 155 { insn_jr, M(spec_op,0,0,0,0,jr_op), RS }, 156 { insn_ld, M(ld_op,0,0,0,0,0), RS | RT | SIMM }, 157 { insn_ll, M(ll_op,0,0,0,0,0), RS | RT | SIMM }, 158 { insn_lld, M(lld_op,0,0,0,0,0), RS | RT | SIMM }, 159 { insn_lui, M(lui_op,0,0,0,0,0), RT | SIMM }, 160 { insn_lw, M(lw_op,0,0,0,0,0), RS | RT | SIMM }, 161 { insn_mfc0, M(cop0_op,mfc_op,0,0,0,0), RT | RD | SET}, 162 { insn_mtc0, M(cop0_op,mtc_op,0,0,0,0), RT | RD | SET}, 163 { insn_ori, M(ori_op,0,0,0,0,0), RS | RT | UIMM }, 164 { insn_rfe, M(cop0_op,cop_op,0,0,0,rfe_op), 0 }, 165 { insn_sc, M(sc_op,0,0,0,0,0), RS | RT | SIMM }, 166 { insn_scd, M(scd_op,0,0,0,0,0), RS | RT | SIMM }, 167 { insn_sd, M(sd_op,0,0,0,0,0), RS | RT | SIMM }, 168 { insn_sll, M(spec_op,0,0,0,0,sll_op), RT | RD | RE }, 169 { insn_sra, M(spec_op,0,0,0,0,sra_op), RT | RD | RE }, 170 { insn_srl, M(spec_op,0,0,0,0,srl_op), RT | RD | RE }, 171 { insn_subu, M(spec_op,0,0,0,0,subu_op), RS | RT | RD }, 172 { insn_sw, M(sw_op,0,0,0,0,0), RS | RT | SIMM }, 173 { insn_tlbp, M(cop0_op,cop_op,0,0,0,tlbp_op), 0 }, 174 { insn_tlbwi, M(cop0_op,cop_op,0,0,0,tlbwi_op), 0 }, 175 { insn_tlbwr, M(cop0_op,cop_op,0,0,0,tlbwr_op), 0 }, 176 { insn_xor, M(spec_op,0,0,0,0,xor_op), RS | RT | RD }, 177 { insn_xori, M(xori_op,0,0,0,0,0), RS | RT | UIMM }, 178 { insn_invalid, 0, 0 } 179 }; 180 181 #undef M 182 183 static __init u32 build_rs(u32 arg) 184 { 185 if (arg & ~RS_MASK) 186 printk(KERN_WARNING "TLB synthesizer field overflow\n"); 187 188 return (arg & RS_MASK) << RS_SH; 189 } 190 191 static __init u32 build_rt(u32 arg) 192 { 193 if (arg & ~RT_MASK) 194 printk(KERN_WARNING "TLB synthesizer field overflow\n"); 195 196 return (arg & RT_MASK) << RT_SH; 197 } 198 199 static __init u32 build_rd(u32 arg) 200 { 201 if (arg & ~RD_MASK) 202 printk(KERN_WARNING "TLB synthesizer field overflow\n"); 203 204 return (arg & RD_MASK) << RD_SH; 205 } 206 207 static __init u32 build_re(u32 arg) 208 { 209 if (arg & ~RE_MASK) 210 printk(KERN_WARNING "TLB synthesizer field overflow\n"); 211 212 return (arg & RE_MASK) << RE_SH; 213 } 214 215 static __init u32 build_simm(s32 arg) 216 { 217 if (arg > 0x7fff || arg < -0x8000) 218 printk(KERN_WARNING "TLB synthesizer field overflow\n"); 219 220 return arg & 0xffff; 221 } 222 223 static __init u32 build_uimm(u32 arg) 224 { 225 if (arg & ~IMM_MASK) 226 printk(KERN_WARNING "TLB synthesizer field overflow\n"); 227 228 return arg & IMM_MASK; 229 } 230 231 static __init u32 build_bimm(s32 arg) 232 { 233 if (arg > 0x1ffff || arg < -0x20000) 234 printk(KERN_WARNING "TLB synthesizer field overflow\n"); 235 236 if (arg & 0x3) 237 printk(KERN_WARNING "Invalid TLB synthesizer branch target\n"); 238 239 return ((arg < 0) ? (1 << 15) : 0) | ((arg >> 2) & 0x7fff); 240 } 241 242 static __init u32 build_jimm(u32 arg) 243 { 244 if (arg & ~((JIMM_MASK) << 2)) 245 printk(KERN_WARNING "TLB synthesizer field overflow\n"); 246 247 return (arg >> 2) & JIMM_MASK; 248 } 249 250 static __init u32 build_func(u32 arg) 251 { 252 if (arg & ~FUNC_MASK) 253 printk(KERN_WARNING "TLB synthesizer field overflow\n"); 254 255 return arg & FUNC_MASK; 256 } 257 258 static __init u32 build_set(u32 arg) 259 { 260 if (arg & ~SET_MASK) 261 printk(KERN_WARNING "TLB synthesizer field overflow\n"); 262 263 return arg & SET_MASK; 264 } 265 266 /* 267 * The order of opcode arguments is implicitly left to right, 268 * starting with RS and ending with FUNC or IMM. 269 */ 270 static void __init build_insn(u32 **buf, enum opcode opc, ...) 271 { 272 struct insn *ip = NULL; 273 unsigned int i; 274 va_list ap; 275 u32 op; 276 277 for (i = 0; insn_table[i].opcode != insn_invalid; i++) 278 if (insn_table[i].opcode == opc) { 279 ip = &insn_table[i]; 280 break; 281 } 282 283 if (!ip) 284 panic("Unsupported TLB synthesizer instruction %d", opc); 285 286 op = ip->match; 287 va_start(ap, opc); 288 if (ip->fields & RS) op |= build_rs(va_arg(ap, u32)); 289 if (ip->fields & RT) op |= build_rt(va_arg(ap, u32)); 290 if (ip->fields & RD) op |= build_rd(va_arg(ap, u32)); 291 if (ip->fields & RE) op |= build_re(va_arg(ap, u32)); 292 if (ip->fields & SIMM) op |= build_simm(va_arg(ap, s32)); 293 if (ip->fields & UIMM) op |= build_uimm(va_arg(ap, u32)); 294 if (ip->fields & BIMM) op |= build_bimm(va_arg(ap, s32)); 295 if (ip->fields & JIMM) op |= build_jimm(va_arg(ap, u32)); 296 if (ip->fields & FUNC) op |= build_func(va_arg(ap, u32)); 297 if (ip->fields & SET) op |= build_set(va_arg(ap, u32)); 298 va_end(ap); 299 300 **buf = op; 301 (*buf)++; 302 } 303 304 #define I_u1u2u3(op) \ 305 static inline void __init i##op(u32 **buf, unsigned int a, \ 306 unsigned int b, unsigned int c) \ 307 { \ 308 build_insn(buf, insn##op, a, b, c); \ 309 } 310 311 #define I_u2u1u3(op) \ 312 static inline void __init i##op(u32 **buf, unsigned int a, \ 313 unsigned int b, unsigned int c) \ 314 { \ 315 build_insn(buf, insn##op, b, a, c); \ 316 } 317 318 #define I_u3u1u2(op) \ 319 static inline void __init i##op(u32 **buf, unsigned int a, \ 320 unsigned int b, unsigned int c) \ 321 { \ 322 build_insn(buf, insn##op, b, c, a); \ 323 } 324 325 #define I_u1u2s3(op) \ 326 static inline void __init i##op(u32 **buf, unsigned int a, \ 327 unsigned int b, signed int c) \ 328 { \ 329 build_insn(buf, insn##op, a, b, c); \ 330 } 331 332 #define I_u2s3u1(op) \ 333 static inline void __init i##op(u32 **buf, unsigned int a, \ 334 signed int b, unsigned int c) \ 335 { \ 336 build_insn(buf, insn##op, c, a, b); \ 337 } 338 339 #define I_u2u1s3(op) \ 340 static inline void __init i##op(u32 **buf, unsigned int a, \ 341 unsigned int b, signed int c) \ 342 { \ 343 build_insn(buf, insn##op, b, a, c); \ 344 } 345 346 #define I_u1u2(op) \ 347 static inline void __init i##op(u32 **buf, unsigned int a, \ 348 unsigned int b) \ 349 { \ 350 build_insn(buf, insn##op, a, b); \ 351 } 352 353 #define I_u1s2(op) \ 354 static inline void __init i##op(u32 **buf, unsigned int a, \ 355 signed int b) \ 356 { \ 357 build_insn(buf, insn##op, a, b); \ 358 } 359 360 #define I_u1(op) \ 361 static inline void __init i##op(u32 **buf, unsigned int a) \ 362 { \ 363 build_insn(buf, insn##op, a); \ 364 } 365 366 #define I_0(op) \ 367 static inline void __init i##op(u32 **buf) \ 368 { \ 369 build_insn(buf, insn##op); \ 370 } 371 372 I_u2u1s3(_addiu); 373 I_u3u1u2(_addu); 374 I_u2u1u3(_andi); 375 I_u3u1u2(_and); 376 I_u1u2s3(_beq); 377 I_u1u2s3(_beql); 378 I_u1s2(_bgez); 379 I_u1s2(_bgezl); 380 I_u1s2(_bltz); 381 I_u1s2(_bltzl); 382 I_u1u2s3(_bne); 383 I_u1u2u3(_dmfc0); 384 I_u1u2u3(_dmtc0); 385 I_u2u1s3(_daddiu); 386 I_u3u1u2(_daddu); 387 I_u2u1u3(_dsll); 388 I_u2u1u3(_dsll32); 389 I_u2u1u3(_dsra); 390 I_u2u1u3(_dsrl); 391 I_u3u1u2(_dsubu); 392 I_0(_eret); 393 I_u1(_j); 394 I_u1(_jal); 395 I_u1(_jr); 396 I_u2s3u1(_ld); 397 I_u2s3u1(_ll); 398 I_u2s3u1(_lld); 399 I_u1s2(_lui); 400 I_u2s3u1(_lw); 401 I_u1u2u3(_mfc0); 402 I_u1u2u3(_mtc0); 403 I_u2u1u3(_ori); 404 I_0(_rfe); 405 I_u2s3u1(_sc); 406 I_u2s3u1(_scd); 407 I_u2s3u1(_sd); 408 I_u2u1u3(_sll); 409 I_u2u1u3(_sra); 410 I_u2u1u3(_srl); 411 I_u3u1u2(_subu); 412 I_u2s3u1(_sw); 413 I_0(_tlbp); 414 I_0(_tlbwi); 415 I_0(_tlbwr); 416 I_u3u1u2(_xor) 417 I_u2u1u3(_xori); 418 419 /* 420 * handling labels 421 */ 422 423 enum label_id { 424 label_invalid, 425 label_second_part, 426 label_leave, 427 label_vmalloc, 428 label_vmalloc_done, 429 label_tlbw_hazard, 430 label_split, 431 label_nopage_tlbl, 432 label_nopage_tlbs, 433 label_nopage_tlbm, 434 label_smp_pgtable_change, 435 label_r3000_write_probe_fail, 436 }; 437 438 struct label { 439 u32 *addr; 440 enum label_id lab; 441 }; 442 443 static __init void build_label(struct label **lab, u32 *addr, 444 enum label_id l) 445 { 446 (*lab)->addr = addr; 447 (*lab)->lab = l; 448 (*lab)++; 449 } 450 451 #define L_LA(lb) \ 452 static inline void l##lb(struct label **lab, u32 *addr) \ 453 { \ 454 build_label(lab, addr, label##lb); \ 455 } 456 457 L_LA(_second_part) 458 L_LA(_leave) 459 L_LA(_vmalloc) 460 L_LA(_vmalloc_done) 461 L_LA(_tlbw_hazard) 462 L_LA(_split) 463 L_LA(_nopage_tlbl) 464 L_LA(_nopage_tlbs) 465 L_LA(_nopage_tlbm) 466 L_LA(_smp_pgtable_change) 467 L_LA(_r3000_write_probe_fail) 468 469 /* convenience macros for instructions */ 470 #ifdef CONFIG_64BIT 471 # define i_LW(buf, rs, rt, off) i_ld(buf, rs, rt, off) 472 # define i_SW(buf, rs, rt, off) i_sd(buf, rs, rt, off) 473 # define i_SLL(buf, rs, rt, sh) i_dsll(buf, rs, rt, sh) 474 # define i_SRA(buf, rs, rt, sh) i_dsra(buf, rs, rt, sh) 475 # define i_SRL(buf, rs, rt, sh) i_dsrl(buf, rs, rt, sh) 476 # define i_MFC0(buf, rt, rd...) i_dmfc0(buf, rt, rd) 477 # define i_MTC0(buf, rt, rd...) i_dmtc0(buf, rt, rd) 478 # define i_ADDIU(buf, rs, rt, val) i_daddiu(buf, rs, rt, val) 479 # define i_ADDU(buf, rs, rt, rd) i_daddu(buf, rs, rt, rd) 480 # define i_SUBU(buf, rs, rt, rd) i_dsubu(buf, rs, rt, rd) 481 # define i_LL(buf, rs, rt, off) i_lld(buf, rs, rt, off) 482 # define i_SC(buf, rs, rt, off) i_scd(buf, rs, rt, off) 483 #else 484 # define i_LW(buf, rs, rt, off) i_lw(buf, rs, rt, off) 485 # define i_SW(buf, rs, rt, off) i_sw(buf, rs, rt, off) 486 # define i_SLL(buf, rs, rt, sh) i_sll(buf, rs, rt, sh) 487 # define i_SRA(buf, rs, rt, sh) i_sra(buf, rs, rt, sh) 488 # define i_SRL(buf, rs, rt, sh) i_srl(buf, rs, rt, sh) 489 # define i_MFC0(buf, rt, rd...) i_mfc0(buf, rt, rd) 490 # define i_MTC0(buf, rt, rd...) i_mtc0(buf, rt, rd) 491 # define i_ADDIU(buf, rs, rt, val) i_addiu(buf, rs, rt, val) 492 # define i_ADDU(buf, rs, rt, rd) i_addu(buf, rs, rt, rd) 493 # define i_SUBU(buf, rs, rt, rd) i_subu(buf, rs, rt, rd) 494 # define i_LL(buf, rs, rt, off) i_ll(buf, rs, rt, off) 495 # define i_SC(buf, rs, rt, off) i_sc(buf, rs, rt, off) 496 #endif 497 498 #define i_b(buf, off) i_beq(buf, 0, 0, off) 499 #define i_beqz(buf, rs, off) i_beq(buf, rs, 0, off) 500 #define i_beqzl(buf, rs, off) i_beql(buf, rs, 0, off) 501 #define i_bnez(buf, rs, off) i_bne(buf, rs, 0, off) 502 #define i_bnezl(buf, rs, off) i_bnel(buf, rs, 0, off) 503 #define i_move(buf, a, b) i_ADDU(buf, a, 0, b) 504 #define i_nop(buf) i_sll(buf, 0, 0, 0) 505 #define i_ssnop(buf) i_sll(buf, 0, 0, 1) 506 #define i_ehb(buf) i_sll(buf, 0, 0, 3) 507 508 #ifdef CONFIG_64BIT 509 static __init int __attribute__((unused)) in_compat_space_p(long addr) 510 { 511 /* Is this address in 32bit compat space? */ 512 return (((addr) & 0xffffffff00000000L) == 0xffffffff00000000L); 513 } 514 515 static __init int __attribute__((unused)) rel_highest(long val) 516 { 517 return ((((val + 0x800080008000L) >> 48) & 0xffff) ^ 0x8000) - 0x8000; 518 } 519 520 static __init int __attribute__((unused)) rel_higher(long val) 521 { 522 return ((((val + 0x80008000L) >> 32) & 0xffff) ^ 0x8000) - 0x8000; 523 } 524 #endif 525 526 static __init int rel_hi(long val) 527 { 528 return ((((val + 0x8000L) >> 16) & 0xffff) ^ 0x8000) - 0x8000; 529 } 530 531 static __init int rel_lo(long val) 532 { 533 return ((val & 0xffff) ^ 0x8000) - 0x8000; 534 } 535 536 static __init void i_LA_mostly(u32 **buf, unsigned int rs, long addr) 537 { 538 #ifdef CONFIG_64BIT 539 if (!in_compat_space_p(addr)) { 540 i_lui(buf, rs, rel_highest(addr)); 541 if (rel_higher(addr)) 542 i_daddiu(buf, rs, rs, rel_higher(addr)); 543 if (rel_hi(addr)) { 544 i_dsll(buf, rs, rs, 16); 545 i_daddiu(buf, rs, rs, rel_hi(addr)); 546 i_dsll(buf, rs, rs, 16); 547 } else 548 i_dsll32(buf, rs, rs, 0); 549 } else 550 #endif 551 i_lui(buf, rs, rel_hi(addr)); 552 } 553 554 static __init void __attribute__((unused)) i_LA(u32 **buf, unsigned int rs, 555 long addr) 556 { 557 i_LA_mostly(buf, rs, addr); 558 if (rel_lo(addr)) 559 i_ADDIU(buf, rs, rs, rel_lo(addr)); 560 } 561 562 /* 563 * handle relocations 564 */ 565 566 struct reloc { 567 u32 *addr; 568 unsigned int type; 569 enum label_id lab; 570 }; 571 572 static __init void r_mips_pc16(struct reloc **rel, u32 *addr, 573 enum label_id l) 574 { 575 (*rel)->addr = addr; 576 (*rel)->type = R_MIPS_PC16; 577 (*rel)->lab = l; 578 (*rel)++; 579 } 580 581 static inline void __resolve_relocs(struct reloc *rel, struct label *lab) 582 { 583 long laddr = (long)lab->addr; 584 long raddr = (long)rel->addr; 585 586 switch (rel->type) { 587 case R_MIPS_PC16: 588 *rel->addr |= build_bimm(laddr - (raddr + 4)); 589 break; 590 591 default: 592 panic("Unsupported TLB synthesizer relocation %d", 593 rel->type); 594 } 595 } 596 597 static __init void resolve_relocs(struct reloc *rel, struct label *lab) 598 { 599 struct label *l; 600 601 for (; rel->lab != label_invalid; rel++) 602 for (l = lab; l->lab != label_invalid; l++) 603 if (rel->lab == l->lab) 604 __resolve_relocs(rel, l); 605 } 606 607 static __init void move_relocs(struct reloc *rel, u32 *first, u32 *end, 608 long off) 609 { 610 for (; rel->lab != label_invalid; rel++) 611 if (rel->addr >= first && rel->addr < end) 612 rel->addr += off; 613 } 614 615 static __init void move_labels(struct label *lab, u32 *first, u32 *end, 616 long off) 617 { 618 for (; lab->lab != label_invalid; lab++) 619 if (lab->addr >= first && lab->addr < end) 620 lab->addr += off; 621 } 622 623 static __init void copy_handler(struct reloc *rel, struct label *lab, 624 u32 *first, u32 *end, u32 *target) 625 { 626 long off = (long)(target - first); 627 628 memcpy(target, first, (end - first) * sizeof(u32)); 629 630 move_relocs(rel, first, end, off); 631 move_labels(lab, first, end, off); 632 } 633 634 static __init int __attribute__((unused)) insn_has_bdelay(struct reloc *rel, 635 u32 *addr) 636 { 637 for (; rel->lab != label_invalid; rel++) { 638 if (rel->addr == addr 639 && (rel->type == R_MIPS_PC16 640 || rel->type == R_MIPS_26)) 641 return 1; 642 } 643 644 return 0; 645 } 646 647 /* convenience functions for labeled branches */ 648 static void __init __attribute__((unused)) 649 il_bltz(u32 **p, struct reloc **r, unsigned int reg, enum label_id l) 650 { 651 r_mips_pc16(r, *p, l); 652 i_bltz(p, reg, 0); 653 } 654 655 static void __init __attribute__((unused)) il_b(u32 **p, struct reloc **r, 656 enum label_id l) 657 { 658 r_mips_pc16(r, *p, l); 659 i_b(p, 0); 660 } 661 662 static void __init il_beqz(u32 **p, struct reloc **r, unsigned int reg, 663 enum label_id l) 664 { 665 r_mips_pc16(r, *p, l); 666 i_beqz(p, reg, 0); 667 } 668 669 static void __init __attribute__((unused)) 670 il_beqzl(u32 **p, struct reloc **r, unsigned int reg, enum label_id l) 671 { 672 r_mips_pc16(r, *p, l); 673 i_beqzl(p, reg, 0); 674 } 675 676 static void __init il_bnez(u32 **p, struct reloc **r, unsigned int reg, 677 enum label_id l) 678 { 679 r_mips_pc16(r, *p, l); 680 i_bnez(p, reg, 0); 681 } 682 683 static void __init il_bgezl(u32 **p, struct reloc **r, unsigned int reg, 684 enum label_id l) 685 { 686 r_mips_pc16(r, *p, l); 687 i_bgezl(p, reg, 0); 688 } 689 690 /* The only general purpose registers allowed in TLB handlers. */ 691 #define K0 26 692 #define K1 27 693 694 /* Some CP0 registers */ 695 #define C0_INDEX 0, 0 696 #define C0_ENTRYLO0 2, 0 697 #define C0_TCBIND 2, 2 698 #define C0_ENTRYLO1 3, 0 699 #define C0_CONTEXT 4, 0 700 #define C0_BADVADDR 8, 0 701 #define C0_ENTRYHI 10, 0 702 #define C0_EPC 14, 0 703 #define C0_XCONTEXT 20, 0 704 705 #ifdef CONFIG_64BIT 706 # define GET_CONTEXT(buf, reg) i_MFC0(buf, reg, C0_XCONTEXT) 707 #else 708 # define GET_CONTEXT(buf, reg) i_MFC0(buf, reg, C0_CONTEXT) 709 #endif 710 711 /* The worst case length of the handler is around 18 instructions for 712 * R3000-style TLBs and up to 63 instructions for R4000-style TLBs. 713 * Maximum space available is 32 instructions for R3000 and 64 714 * instructions for R4000. 715 * 716 * We deliberately chose a buffer size of 128, so we won't scribble 717 * over anything important on overflow before we panic. 718 */ 719 static __initdata u32 tlb_handler[128]; 720 721 /* simply assume worst case size for labels and relocs */ 722 static __initdata struct label labels[128]; 723 static __initdata struct reloc relocs[128]; 724 725 /* 726 * The R3000 TLB handler is simple. 727 */ 728 static void __init build_r3000_tlb_refill_handler(void) 729 { 730 long pgdc = (long)pgd_current; 731 u32 *p; 732 733 memset(tlb_handler, 0, sizeof(tlb_handler)); 734 p = tlb_handler; 735 736 i_mfc0(&p, K0, C0_BADVADDR); 737 i_lui(&p, K1, rel_hi(pgdc)); /* cp0 delay */ 738 i_lw(&p, K1, rel_lo(pgdc), K1); 739 i_srl(&p, K0, K0, 22); /* load delay */ 740 i_sll(&p, K0, K0, 2); 741 i_addu(&p, K1, K1, K0); 742 i_mfc0(&p, K0, C0_CONTEXT); 743 i_lw(&p, K1, 0, K1); /* cp0 delay */ 744 i_andi(&p, K0, K0, 0xffc); /* load delay */ 745 i_addu(&p, K1, K1, K0); 746 i_lw(&p, K0, 0, K1); 747 i_nop(&p); /* load delay */ 748 i_mtc0(&p, K0, C0_ENTRYLO0); 749 i_mfc0(&p, K1, C0_EPC); /* cp0 delay */ 750 i_tlbwr(&p); /* cp0 delay */ 751 i_jr(&p, K1); 752 i_rfe(&p); /* branch delay */ 753 754 if (p > tlb_handler + 32) 755 panic("TLB refill handler space exceeded"); 756 757 printk("Synthesized TLB refill handler (%u instructions).\n", 758 (unsigned int)(p - tlb_handler)); 759 #ifdef DEBUG_TLB 760 { 761 int i; 762 763 for (i = 0; i < (p - tlb_handler); i++) 764 printk("%08x\n", tlb_handler[i]); 765 } 766 #endif 767 768 memcpy((void *)ebase, tlb_handler, 0x80); 769 } 770 771 /* 772 * The R4000 TLB handler is much more complicated. We have two 773 * consecutive handler areas with 32 instructions space each. 774 * Since they aren't used at the same time, we can overflow in the 775 * other one.To keep things simple, we first assume linear space, 776 * then we relocate it to the final handler layout as needed. 777 */ 778 static __initdata u32 final_handler[64]; 779 780 /* 781 * Hazards 782 * 783 * From the IDT errata for the QED RM5230 (Nevada), processor revision 1.0: 784 * 2. A timing hazard exists for the TLBP instruction. 785 * 786 * stalling_instruction 787 * TLBP 788 * 789 * The JTLB is being read for the TLBP throughout the stall generated by the 790 * previous instruction. This is not really correct as the stalling instruction 791 * can modify the address used to access the JTLB. The failure symptom is that 792 * the TLBP instruction will use an address created for the stalling instruction 793 * and not the address held in C0_ENHI and thus report the wrong results. 794 * 795 * The software work-around is to not allow the instruction preceding the TLBP 796 * to stall - make it an NOP or some other instruction guaranteed not to stall. 797 * 798 * Errata 2 will not be fixed. This errata is also on the R5000. 799 * 800 * As if we MIPS hackers wouldn't know how to nop pipelines happy ... 801 */ 802 static __init void __attribute__((unused)) build_tlb_probe_entry(u32 **p) 803 { 804 switch (current_cpu_data.cputype) { 805 /* Found by experiment: R4600 v2.0 needs this, too. */ 806 case CPU_R4600: 807 case CPU_R5000: 808 case CPU_R5000A: 809 case CPU_NEVADA: 810 i_nop(p); 811 i_tlbp(p); 812 break; 813 814 default: 815 i_tlbp(p); 816 break; 817 } 818 } 819 820 /* 821 * Write random or indexed TLB entry, and care about the hazards from 822 * the preceeding mtc0 and for the following eret. 823 */ 824 enum tlb_write_entry { tlb_random, tlb_indexed }; 825 826 static __init void build_tlb_write_entry(u32 **p, struct label **l, 827 struct reloc **r, 828 enum tlb_write_entry wmode) 829 { 830 void(*tlbw)(u32 **) = NULL; 831 832 switch (wmode) { 833 case tlb_random: tlbw = i_tlbwr; break; 834 case tlb_indexed: tlbw = i_tlbwi; break; 835 } 836 837 switch (current_cpu_data.cputype) { 838 case CPU_R4000PC: 839 case CPU_R4000SC: 840 case CPU_R4000MC: 841 case CPU_R4400PC: 842 case CPU_R4400SC: 843 case CPU_R4400MC: 844 /* 845 * This branch uses up a mtc0 hazard nop slot and saves 846 * two nops after the tlbw instruction. 847 */ 848 il_bgezl(p, r, 0, label_tlbw_hazard); 849 tlbw(p); 850 l_tlbw_hazard(l, *p); 851 i_nop(p); 852 break; 853 854 case CPU_R4600: 855 case CPU_R4700: 856 case CPU_R5000: 857 case CPU_R5000A: 858 i_nop(p); 859 tlbw(p); 860 i_nop(p); 861 break; 862 863 case CPU_R4300: 864 case CPU_5KC: 865 case CPU_TX49XX: 866 case CPU_AU1000: 867 case CPU_AU1100: 868 case CPU_AU1500: 869 case CPU_AU1550: 870 case CPU_AU1200: 871 case CPU_PR4450: 872 i_nop(p); 873 tlbw(p); 874 break; 875 876 case CPU_R10000: 877 case CPU_R12000: 878 case CPU_4KC: 879 case CPU_SB1: 880 case CPU_SB1A: 881 case CPU_4KSC: 882 case CPU_20KC: 883 case CPU_25KF: 884 tlbw(p); 885 break; 886 887 case CPU_NEVADA: 888 i_nop(p); /* QED specifies 2 nops hazard */ 889 /* 890 * This branch uses up a mtc0 hazard nop slot and saves 891 * a nop after the tlbw instruction. 892 */ 893 il_bgezl(p, r, 0, label_tlbw_hazard); 894 tlbw(p); 895 l_tlbw_hazard(l, *p); 896 break; 897 898 case CPU_RM7000: 899 i_nop(p); 900 i_nop(p); 901 i_nop(p); 902 i_nop(p); 903 tlbw(p); 904 break; 905 906 case CPU_4KEC: 907 case CPU_24K: 908 case CPU_34K: 909 i_ehb(p); 910 tlbw(p); 911 break; 912 913 case CPU_RM9000: 914 /* 915 * When the JTLB is updated by tlbwi or tlbwr, a subsequent 916 * use of the JTLB for instructions should not occur for 4 917 * cpu cycles and use for data translations should not occur 918 * for 3 cpu cycles. 919 */ 920 i_ssnop(p); 921 i_ssnop(p); 922 i_ssnop(p); 923 i_ssnop(p); 924 tlbw(p); 925 i_ssnop(p); 926 i_ssnop(p); 927 i_ssnop(p); 928 i_ssnop(p); 929 break; 930 931 case CPU_VR4111: 932 case CPU_VR4121: 933 case CPU_VR4122: 934 case CPU_VR4181: 935 case CPU_VR4181A: 936 i_nop(p); 937 i_nop(p); 938 tlbw(p); 939 i_nop(p); 940 i_nop(p); 941 break; 942 943 case CPU_VR4131: 944 case CPU_VR4133: 945 case CPU_R5432: 946 i_nop(p); 947 i_nop(p); 948 tlbw(p); 949 break; 950 951 default: 952 panic("No TLB refill handler yet (CPU type: %d)", 953 current_cpu_data.cputype); 954 break; 955 } 956 } 957 958 #ifdef CONFIG_64BIT 959 /* 960 * TMP and PTR are scratch. 961 * TMP will be clobbered, PTR will hold the pmd entry. 962 */ 963 static __init void 964 build_get_pmde64(u32 **p, struct label **l, struct reloc **r, 965 unsigned int tmp, unsigned int ptr) 966 { 967 long pgdc = (long)pgd_current; 968 969 /* 970 * The vmalloc handling is not in the hotpath. 971 */ 972 i_dmfc0(p, tmp, C0_BADVADDR); 973 il_bltz(p, r, tmp, label_vmalloc); 974 /* No i_nop needed here, since the next insn doesn't touch TMP. */ 975 976 #ifdef CONFIG_SMP 977 # ifdef CONFIG_MIPS_MT_SMTC 978 /* 979 * SMTC uses TCBind value as "CPU" index 980 */ 981 i_mfc0(p, ptr, C0_TCBIND); 982 i_dsrl(p, ptr, ptr, 19); 983 # else 984 /* 985 * 64 bit SMP running in XKPHYS has smp_processor_id() << 3 986 * stored in CONTEXT. 987 */ 988 i_dmfc0(p, ptr, C0_CONTEXT); 989 i_dsrl(p, ptr, ptr, 23); 990 #endif 991 i_LA_mostly(p, tmp, pgdc); 992 i_daddu(p, ptr, ptr, tmp); 993 i_dmfc0(p, tmp, C0_BADVADDR); 994 i_ld(p, ptr, rel_lo(pgdc), ptr); 995 #else 996 i_LA_mostly(p, ptr, pgdc); 997 i_ld(p, ptr, rel_lo(pgdc), ptr); 998 #endif 999 1000 l_vmalloc_done(l, *p); 1001 i_dsrl(p, tmp, tmp, PGDIR_SHIFT-3); /* get pgd offset in bytes */ 1002 i_andi(p, tmp, tmp, (PTRS_PER_PGD - 1)<<3); 1003 i_daddu(p, ptr, ptr, tmp); /* add in pgd offset */ 1004 i_dmfc0(p, tmp, C0_BADVADDR); /* get faulting address */ 1005 i_ld(p, ptr, 0, ptr); /* get pmd pointer */ 1006 i_dsrl(p, tmp, tmp, PMD_SHIFT-3); /* get pmd offset in bytes */ 1007 i_andi(p, tmp, tmp, (PTRS_PER_PMD - 1)<<3); 1008 i_daddu(p, ptr, ptr, tmp); /* add in pmd offset */ 1009 } 1010 1011 /* 1012 * BVADDR is the faulting address, PTR is scratch. 1013 * PTR will hold the pgd for vmalloc. 1014 */ 1015 static __init void 1016 build_get_pgd_vmalloc64(u32 **p, struct label **l, struct reloc **r, 1017 unsigned int bvaddr, unsigned int ptr) 1018 { 1019 long swpd = (long)swapper_pg_dir; 1020 1021 l_vmalloc(l, *p); 1022 i_LA(p, ptr, VMALLOC_START); 1023 i_dsubu(p, bvaddr, bvaddr, ptr); 1024 1025 if (in_compat_space_p(swpd) && !rel_lo(swpd)) { 1026 il_b(p, r, label_vmalloc_done); 1027 i_lui(p, ptr, rel_hi(swpd)); 1028 } else { 1029 i_LA_mostly(p, ptr, swpd); 1030 il_b(p, r, label_vmalloc_done); 1031 i_daddiu(p, ptr, ptr, rel_lo(swpd)); 1032 } 1033 } 1034 1035 #else /* !CONFIG_64BIT */ 1036 1037 /* 1038 * TMP and PTR are scratch. 1039 * TMP will be clobbered, PTR will hold the pgd entry. 1040 */ 1041 static __init void __attribute__((unused)) 1042 build_get_pgde32(u32 **p, unsigned int tmp, unsigned int ptr) 1043 { 1044 long pgdc = (long)pgd_current; 1045 1046 /* 32 bit SMP has smp_processor_id() stored in CONTEXT. */ 1047 #ifdef CONFIG_SMP 1048 #ifdef CONFIG_MIPS_MT_SMTC 1049 /* 1050 * SMTC uses TCBind value as "CPU" index 1051 */ 1052 i_mfc0(p, ptr, C0_TCBIND); 1053 i_LA_mostly(p, tmp, pgdc); 1054 i_srl(p, ptr, ptr, 19); 1055 #else 1056 /* 1057 * smp_processor_id() << 3 is stored in CONTEXT. 1058 */ 1059 i_mfc0(p, ptr, C0_CONTEXT); 1060 i_LA_mostly(p, tmp, pgdc); 1061 i_srl(p, ptr, ptr, 23); 1062 #endif 1063 i_addu(p, ptr, tmp, ptr); 1064 #else 1065 i_LA_mostly(p, ptr, pgdc); 1066 #endif 1067 i_mfc0(p, tmp, C0_BADVADDR); /* get faulting address */ 1068 i_lw(p, ptr, rel_lo(pgdc), ptr); 1069 i_srl(p, tmp, tmp, PGDIR_SHIFT); /* get pgd only bits */ 1070 i_sll(p, tmp, tmp, PGD_T_LOG2); 1071 i_addu(p, ptr, ptr, tmp); /* add in pgd offset */ 1072 } 1073 1074 #endif /* !CONFIG_64BIT */ 1075 1076 static __init void build_adjust_context(u32 **p, unsigned int ctx) 1077 { 1078 unsigned int shift = 4 - (PTE_T_LOG2 + 1); 1079 unsigned int mask = (PTRS_PER_PTE / 2 - 1) << (PTE_T_LOG2 + 1); 1080 1081 switch (current_cpu_data.cputype) { 1082 case CPU_VR41XX: 1083 case CPU_VR4111: 1084 case CPU_VR4121: 1085 case CPU_VR4122: 1086 case CPU_VR4131: 1087 case CPU_VR4181: 1088 case CPU_VR4181A: 1089 case CPU_VR4133: 1090 shift += 2; 1091 break; 1092 1093 default: 1094 break; 1095 } 1096 1097 if (shift) 1098 i_SRL(p, ctx, ctx, shift); 1099 i_andi(p, ctx, ctx, mask); 1100 } 1101 1102 static __init void build_get_ptep(u32 **p, unsigned int tmp, unsigned int ptr) 1103 { 1104 /* 1105 * Bug workaround for the Nevada. It seems as if under certain 1106 * circumstances the move from cp0_context might produce a 1107 * bogus result when the mfc0 instruction and its consumer are 1108 * in a different cacheline or a load instruction, probably any 1109 * memory reference, is between them. 1110 */ 1111 switch (current_cpu_data.cputype) { 1112 case CPU_NEVADA: 1113 i_LW(p, ptr, 0, ptr); 1114 GET_CONTEXT(p, tmp); /* get context reg */ 1115 break; 1116 1117 default: 1118 GET_CONTEXT(p, tmp); /* get context reg */ 1119 i_LW(p, ptr, 0, ptr); 1120 break; 1121 } 1122 1123 build_adjust_context(p, tmp); 1124 i_ADDU(p, ptr, ptr, tmp); /* add in offset */ 1125 } 1126 1127 static __init void build_update_entries(u32 **p, unsigned int tmp, 1128 unsigned int ptep) 1129 { 1130 /* 1131 * 64bit address support (36bit on a 32bit CPU) in a 32bit 1132 * Kernel is a special case. Only a few CPUs use it. 1133 */ 1134 #ifdef CONFIG_64BIT_PHYS_ADDR 1135 if (cpu_has_64bits) { 1136 i_ld(p, tmp, 0, ptep); /* get even pte */ 1137 i_ld(p, ptep, sizeof(pte_t), ptep); /* get odd pte */ 1138 i_dsrl(p, tmp, tmp, 6); /* convert to entrylo0 */ 1139 i_mtc0(p, tmp, C0_ENTRYLO0); /* load it */ 1140 i_dsrl(p, ptep, ptep, 6); /* convert to entrylo1 */ 1141 i_mtc0(p, ptep, C0_ENTRYLO1); /* load it */ 1142 } else { 1143 int pte_off_even = sizeof(pte_t) / 2; 1144 int pte_off_odd = pte_off_even + sizeof(pte_t); 1145 1146 /* The pte entries are pre-shifted */ 1147 i_lw(p, tmp, pte_off_even, ptep); /* get even pte */ 1148 i_mtc0(p, tmp, C0_ENTRYLO0); /* load it */ 1149 i_lw(p, ptep, pte_off_odd, ptep); /* get odd pte */ 1150 i_mtc0(p, ptep, C0_ENTRYLO1); /* load it */ 1151 } 1152 #else 1153 i_LW(p, tmp, 0, ptep); /* get even pte */ 1154 i_LW(p, ptep, sizeof(pte_t), ptep); /* get odd pte */ 1155 if (r45k_bvahwbug()) 1156 build_tlb_probe_entry(p); 1157 i_SRL(p, tmp, tmp, 6); /* convert to entrylo0 */ 1158 if (r4k_250MHZhwbug()) 1159 i_mtc0(p, 0, C0_ENTRYLO0); 1160 i_mtc0(p, tmp, C0_ENTRYLO0); /* load it */ 1161 i_SRL(p, ptep, ptep, 6); /* convert to entrylo1 */ 1162 if (r45k_bvahwbug()) 1163 i_mfc0(p, tmp, C0_INDEX); 1164 if (r4k_250MHZhwbug()) 1165 i_mtc0(p, 0, C0_ENTRYLO1); 1166 i_mtc0(p, ptep, C0_ENTRYLO1); /* load it */ 1167 #endif 1168 } 1169 1170 static void __init build_r4000_tlb_refill_handler(void) 1171 { 1172 u32 *p = tlb_handler; 1173 struct label *l = labels; 1174 struct reloc *r = relocs; 1175 u32 *f; 1176 unsigned int final_len; 1177 1178 memset(tlb_handler, 0, sizeof(tlb_handler)); 1179 memset(labels, 0, sizeof(labels)); 1180 memset(relocs, 0, sizeof(relocs)); 1181 memset(final_handler, 0, sizeof(final_handler)); 1182 1183 /* 1184 * create the plain linear handler 1185 */ 1186 if (bcm1250_m3_war()) { 1187 i_MFC0(&p, K0, C0_BADVADDR); 1188 i_MFC0(&p, K1, C0_ENTRYHI); 1189 i_xor(&p, K0, K0, K1); 1190 i_SRL(&p, K0, K0, PAGE_SHIFT + 1); 1191 il_bnez(&p, &r, K0, label_leave); 1192 /* No need for i_nop */ 1193 } 1194 1195 #ifdef CONFIG_64BIT 1196 build_get_pmde64(&p, &l, &r, K0, K1); /* get pmd in K1 */ 1197 #else 1198 build_get_pgde32(&p, K0, K1); /* get pgd in K1 */ 1199 #endif 1200 1201 build_get_ptep(&p, K0, K1); 1202 build_update_entries(&p, K0, K1); 1203 build_tlb_write_entry(&p, &l, &r, tlb_random); 1204 l_leave(&l, p); 1205 i_eret(&p); /* return from trap */ 1206 1207 #ifdef CONFIG_64BIT 1208 build_get_pgd_vmalloc64(&p, &l, &r, K0, K1); 1209 #endif 1210 1211 /* 1212 * Overflow check: For the 64bit handler, we need at least one 1213 * free instruction slot for the wrap-around branch. In worst 1214 * case, if the intended insertion point is a delay slot, we 1215 * need three, with the the second nop'ed and the third being 1216 * unused. 1217 */ 1218 #ifdef CONFIG_32BIT 1219 if ((p - tlb_handler) > 64) 1220 panic("TLB refill handler space exceeded"); 1221 #else 1222 if (((p - tlb_handler) > 63) 1223 || (((p - tlb_handler) > 61) 1224 && insn_has_bdelay(relocs, tlb_handler + 29))) 1225 panic("TLB refill handler space exceeded"); 1226 #endif 1227 1228 /* 1229 * Now fold the handler in the TLB refill handler space. 1230 */ 1231 #ifdef CONFIG_32BIT 1232 f = final_handler; 1233 /* Simplest case, just copy the handler. */ 1234 copy_handler(relocs, labels, tlb_handler, p, f); 1235 final_len = p - tlb_handler; 1236 #else /* CONFIG_64BIT */ 1237 f = final_handler + 32; 1238 if ((p - tlb_handler) <= 32) { 1239 /* Just copy the handler. */ 1240 copy_handler(relocs, labels, tlb_handler, p, f); 1241 final_len = p - tlb_handler; 1242 } else { 1243 u32 *split = tlb_handler + 30; 1244 1245 /* 1246 * Find the split point. 1247 */ 1248 if (insn_has_bdelay(relocs, split - 1)) 1249 split--; 1250 1251 /* Copy first part of the handler. */ 1252 copy_handler(relocs, labels, tlb_handler, split, f); 1253 f += split - tlb_handler; 1254 1255 /* Insert branch. */ 1256 l_split(&l, final_handler); 1257 il_b(&f, &r, label_split); 1258 if (insn_has_bdelay(relocs, split)) 1259 i_nop(&f); 1260 else { 1261 copy_handler(relocs, labels, split, split + 1, f); 1262 move_labels(labels, f, f + 1, -1); 1263 f++; 1264 split++; 1265 } 1266 1267 /* Copy the rest of the handler. */ 1268 copy_handler(relocs, labels, split, p, final_handler); 1269 final_len = (f - (final_handler + 32)) + (p - split); 1270 } 1271 #endif /* CONFIG_64BIT */ 1272 1273 resolve_relocs(relocs, labels); 1274 printk("Synthesized TLB refill handler (%u instructions).\n", 1275 final_len); 1276 1277 #ifdef DEBUG_TLB 1278 { 1279 int i; 1280 1281 f = final_handler; 1282 #ifdef CONFIG_64BIT 1283 if (final_len > 32) 1284 final_len = 64; 1285 else 1286 f = final_handler + 32; 1287 #endif /* CONFIG_64BIT */ 1288 for (i = 0; i < final_len; i++) 1289 printk("%08x\n", f[i]); 1290 } 1291 #endif 1292 1293 memcpy((void *)ebase, final_handler, 0x100); 1294 } 1295 1296 /* 1297 * TLB load/store/modify handlers. 1298 * 1299 * Only the fastpath gets synthesized at runtime, the slowpath for 1300 * do_page_fault remains normal asm. 1301 */ 1302 extern void tlb_do_page_fault_0(void); 1303 extern void tlb_do_page_fault_1(void); 1304 1305 #define __tlb_handler_align \ 1306 __attribute__((__aligned__(1 << CONFIG_MIPS_L1_CACHE_SHIFT))) 1307 1308 /* 1309 * 128 instructions for the fastpath handler is generous and should 1310 * never be exceeded. 1311 */ 1312 #define FASTPATH_SIZE 128 1313 1314 u32 __tlb_handler_align handle_tlbl[FASTPATH_SIZE]; 1315 u32 __tlb_handler_align handle_tlbs[FASTPATH_SIZE]; 1316 u32 __tlb_handler_align handle_tlbm[FASTPATH_SIZE]; 1317 1318 static void __init 1319 iPTE_LW(u32 **p, struct label **l, unsigned int pte, unsigned int ptr) 1320 { 1321 #ifdef CONFIG_SMP 1322 # ifdef CONFIG_64BIT_PHYS_ADDR 1323 if (cpu_has_64bits) 1324 i_lld(p, pte, 0, ptr); 1325 else 1326 # endif 1327 i_LL(p, pte, 0, ptr); 1328 #else 1329 # ifdef CONFIG_64BIT_PHYS_ADDR 1330 if (cpu_has_64bits) 1331 i_ld(p, pte, 0, ptr); 1332 else 1333 # endif 1334 i_LW(p, pte, 0, ptr); 1335 #endif 1336 } 1337 1338 static void __init 1339 iPTE_SW(u32 **p, struct reloc **r, unsigned int pte, unsigned int ptr, 1340 unsigned int mode) 1341 { 1342 #ifdef CONFIG_64BIT_PHYS_ADDR 1343 unsigned int hwmode = mode & (_PAGE_VALID | _PAGE_DIRTY); 1344 #endif 1345 1346 i_ori(p, pte, pte, mode); 1347 #ifdef CONFIG_SMP 1348 # ifdef CONFIG_64BIT_PHYS_ADDR 1349 if (cpu_has_64bits) 1350 i_scd(p, pte, 0, ptr); 1351 else 1352 # endif 1353 i_SC(p, pte, 0, ptr); 1354 1355 if (r10000_llsc_war()) 1356 il_beqzl(p, r, pte, label_smp_pgtable_change); 1357 else 1358 il_beqz(p, r, pte, label_smp_pgtable_change); 1359 1360 # ifdef CONFIG_64BIT_PHYS_ADDR 1361 if (!cpu_has_64bits) { 1362 /* no i_nop needed */ 1363 i_ll(p, pte, sizeof(pte_t) / 2, ptr); 1364 i_ori(p, pte, pte, hwmode); 1365 i_sc(p, pte, sizeof(pte_t) / 2, ptr); 1366 il_beqz(p, r, pte, label_smp_pgtable_change); 1367 /* no i_nop needed */ 1368 i_lw(p, pte, 0, ptr); 1369 } else 1370 i_nop(p); 1371 # else 1372 i_nop(p); 1373 # endif 1374 #else 1375 # ifdef CONFIG_64BIT_PHYS_ADDR 1376 if (cpu_has_64bits) 1377 i_sd(p, pte, 0, ptr); 1378 else 1379 # endif 1380 i_SW(p, pte, 0, ptr); 1381 1382 # ifdef CONFIG_64BIT_PHYS_ADDR 1383 if (!cpu_has_64bits) { 1384 i_lw(p, pte, sizeof(pte_t) / 2, ptr); 1385 i_ori(p, pte, pte, hwmode); 1386 i_sw(p, pte, sizeof(pte_t) / 2, ptr); 1387 i_lw(p, pte, 0, ptr); 1388 } 1389 # endif 1390 #endif 1391 } 1392 1393 /* 1394 * Check if PTE is present, if not then jump to LABEL. PTR points to 1395 * the page table where this PTE is located, PTE will be re-loaded 1396 * with it's original value. 1397 */ 1398 static void __init 1399 build_pte_present(u32 **p, struct label **l, struct reloc **r, 1400 unsigned int pte, unsigned int ptr, enum label_id lid) 1401 { 1402 i_andi(p, pte, pte, _PAGE_PRESENT | _PAGE_READ); 1403 i_xori(p, pte, pte, _PAGE_PRESENT | _PAGE_READ); 1404 il_bnez(p, r, pte, lid); 1405 iPTE_LW(p, l, pte, ptr); 1406 } 1407 1408 /* Make PTE valid, store result in PTR. */ 1409 static void __init 1410 build_make_valid(u32 **p, struct reloc **r, unsigned int pte, 1411 unsigned int ptr) 1412 { 1413 unsigned int mode = _PAGE_VALID | _PAGE_ACCESSED; 1414 1415 iPTE_SW(p, r, pte, ptr, mode); 1416 } 1417 1418 /* 1419 * Check if PTE can be written to, if not branch to LABEL. Regardless 1420 * restore PTE with value from PTR when done. 1421 */ 1422 static void __init 1423 build_pte_writable(u32 **p, struct label **l, struct reloc **r, 1424 unsigned int pte, unsigned int ptr, enum label_id lid) 1425 { 1426 i_andi(p, pte, pte, _PAGE_PRESENT | _PAGE_WRITE); 1427 i_xori(p, pte, pte, _PAGE_PRESENT | _PAGE_WRITE); 1428 il_bnez(p, r, pte, lid); 1429 iPTE_LW(p, l, pte, ptr); 1430 } 1431 1432 /* Make PTE writable, update software status bits as well, then store 1433 * at PTR. 1434 */ 1435 static void __init 1436 build_make_write(u32 **p, struct reloc **r, unsigned int pte, 1437 unsigned int ptr) 1438 { 1439 unsigned int mode = (_PAGE_ACCESSED | _PAGE_MODIFIED | _PAGE_VALID 1440 | _PAGE_DIRTY); 1441 1442 iPTE_SW(p, r, pte, ptr, mode); 1443 } 1444 1445 /* 1446 * Check if PTE can be modified, if not branch to LABEL. Regardless 1447 * restore PTE with value from PTR when done. 1448 */ 1449 static void __init 1450 build_pte_modifiable(u32 **p, struct label **l, struct reloc **r, 1451 unsigned int pte, unsigned int ptr, enum label_id lid) 1452 { 1453 i_andi(p, pte, pte, _PAGE_WRITE); 1454 il_beqz(p, r, pte, lid); 1455 iPTE_LW(p, l, pte, ptr); 1456 } 1457 1458 /* 1459 * R3000 style TLB load/store/modify handlers. 1460 */ 1461 1462 /* 1463 * This places the pte into ENTRYLO0 and writes it with tlbwi. 1464 * Then it returns. 1465 */ 1466 static void __init 1467 build_r3000_pte_reload_tlbwi(u32 **p, unsigned int pte, unsigned int tmp) 1468 { 1469 i_mtc0(p, pte, C0_ENTRYLO0); /* cp0 delay */ 1470 i_mfc0(p, tmp, C0_EPC); /* cp0 delay */ 1471 i_tlbwi(p); 1472 i_jr(p, tmp); 1473 i_rfe(p); /* branch delay */ 1474 } 1475 1476 /* 1477 * This places the pte into ENTRYLO0 and writes it with tlbwi 1478 * or tlbwr as appropriate. This is because the index register 1479 * may have the probe fail bit set as a result of a trap on a 1480 * kseg2 access, i.e. without refill. Then it returns. 1481 */ 1482 static void __init 1483 build_r3000_tlb_reload_write(u32 **p, struct label **l, struct reloc **r, 1484 unsigned int pte, unsigned int tmp) 1485 { 1486 i_mfc0(p, tmp, C0_INDEX); 1487 i_mtc0(p, pte, C0_ENTRYLO0); /* cp0 delay */ 1488 il_bltz(p, r, tmp, label_r3000_write_probe_fail); /* cp0 delay */ 1489 i_mfc0(p, tmp, C0_EPC); /* branch delay */ 1490 i_tlbwi(p); /* cp0 delay */ 1491 i_jr(p, tmp); 1492 i_rfe(p); /* branch delay */ 1493 l_r3000_write_probe_fail(l, *p); 1494 i_tlbwr(p); /* cp0 delay */ 1495 i_jr(p, tmp); 1496 i_rfe(p); /* branch delay */ 1497 } 1498 1499 static void __init 1500 build_r3000_tlbchange_handler_head(u32 **p, unsigned int pte, 1501 unsigned int ptr) 1502 { 1503 long pgdc = (long)pgd_current; 1504 1505 i_mfc0(p, pte, C0_BADVADDR); 1506 i_lui(p, ptr, rel_hi(pgdc)); /* cp0 delay */ 1507 i_lw(p, ptr, rel_lo(pgdc), ptr); 1508 i_srl(p, pte, pte, 22); /* load delay */ 1509 i_sll(p, pte, pte, 2); 1510 i_addu(p, ptr, ptr, pte); 1511 i_mfc0(p, pte, C0_CONTEXT); 1512 i_lw(p, ptr, 0, ptr); /* cp0 delay */ 1513 i_andi(p, pte, pte, 0xffc); /* load delay */ 1514 i_addu(p, ptr, ptr, pte); 1515 i_lw(p, pte, 0, ptr); 1516 i_tlbp(p); /* load delay */ 1517 } 1518 1519 static void __init build_r3000_tlb_load_handler(void) 1520 { 1521 u32 *p = handle_tlbl; 1522 struct label *l = labels; 1523 struct reloc *r = relocs; 1524 1525 memset(handle_tlbl, 0, sizeof(handle_tlbl)); 1526 memset(labels, 0, sizeof(labels)); 1527 memset(relocs, 0, sizeof(relocs)); 1528 1529 build_r3000_tlbchange_handler_head(&p, K0, K1); 1530 build_pte_present(&p, &l, &r, K0, K1, label_nopage_tlbl); 1531 i_nop(&p); /* load delay */ 1532 build_make_valid(&p, &r, K0, K1); 1533 build_r3000_tlb_reload_write(&p, &l, &r, K0, K1); 1534 1535 l_nopage_tlbl(&l, p); 1536 i_j(&p, (unsigned long)tlb_do_page_fault_0 & 0x0fffffff); 1537 i_nop(&p); 1538 1539 if ((p - handle_tlbl) > FASTPATH_SIZE) 1540 panic("TLB load handler fastpath space exceeded"); 1541 1542 resolve_relocs(relocs, labels); 1543 printk("Synthesized TLB load handler fastpath (%u instructions).\n", 1544 (unsigned int)(p - handle_tlbl)); 1545 1546 #ifdef DEBUG_TLB 1547 { 1548 int i; 1549 1550 for (i = 0; i < (p - handle_tlbl); i++) 1551 printk("%08x\n", handle_tlbl[i]); 1552 } 1553 #endif 1554 } 1555 1556 static void __init build_r3000_tlb_store_handler(void) 1557 { 1558 u32 *p = handle_tlbs; 1559 struct label *l = labels; 1560 struct reloc *r = relocs; 1561 1562 memset(handle_tlbs, 0, sizeof(handle_tlbs)); 1563 memset(labels, 0, sizeof(labels)); 1564 memset(relocs, 0, sizeof(relocs)); 1565 1566 build_r3000_tlbchange_handler_head(&p, K0, K1); 1567 build_pte_writable(&p, &l, &r, K0, K1, label_nopage_tlbs); 1568 i_nop(&p); /* load delay */ 1569 build_make_write(&p, &r, K0, K1); 1570 build_r3000_tlb_reload_write(&p, &l, &r, K0, K1); 1571 1572 l_nopage_tlbs(&l, p); 1573 i_j(&p, (unsigned long)tlb_do_page_fault_1 & 0x0fffffff); 1574 i_nop(&p); 1575 1576 if ((p - handle_tlbs) > FASTPATH_SIZE) 1577 panic("TLB store handler fastpath space exceeded"); 1578 1579 resolve_relocs(relocs, labels); 1580 printk("Synthesized TLB store handler fastpath (%u instructions).\n", 1581 (unsigned int)(p - handle_tlbs)); 1582 1583 #ifdef DEBUG_TLB 1584 { 1585 int i; 1586 1587 for (i = 0; i < (p - handle_tlbs); i++) 1588 printk("%08x\n", handle_tlbs[i]); 1589 } 1590 #endif 1591 } 1592 1593 static void __init build_r3000_tlb_modify_handler(void) 1594 { 1595 u32 *p = handle_tlbm; 1596 struct label *l = labels; 1597 struct reloc *r = relocs; 1598 1599 memset(handle_tlbm, 0, sizeof(handle_tlbm)); 1600 memset(labels, 0, sizeof(labels)); 1601 memset(relocs, 0, sizeof(relocs)); 1602 1603 build_r3000_tlbchange_handler_head(&p, K0, K1); 1604 build_pte_modifiable(&p, &l, &r, K0, K1, label_nopage_tlbm); 1605 i_nop(&p); /* load delay */ 1606 build_make_write(&p, &r, K0, K1); 1607 build_r3000_pte_reload_tlbwi(&p, K0, K1); 1608 1609 l_nopage_tlbm(&l, p); 1610 i_j(&p, (unsigned long)tlb_do_page_fault_1 & 0x0fffffff); 1611 i_nop(&p); 1612 1613 if ((p - handle_tlbm) > FASTPATH_SIZE) 1614 panic("TLB modify handler fastpath space exceeded"); 1615 1616 resolve_relocs(relocs, labels); 1617 printk("Synthesized TLB modify handler fastpath (%u instructions).\n", 1618 (unsigned int)(p - handle_tlbm)); 1619 1620 #ifdef DEBUG_TLB 1621 { 1622 int i; 1623 1624 for (i = 0; i < (p - handle_tlbm); i++) 1625 printk("%08x\n", handle_tlbm[i]); 1626 } 1627 #endif 1628 } 1629 1630 /* 1631 * R4000 style TLB load/store/modify handlers. 1632 */ 1633 static void __init 1634 build_r4000_tlbchange_handler_head(u32 **p, struct label **l, 1635 struct reloc **r, unsigned int pte, 1636 unsigned int ptr) 1637 { 1638 #ifdef CONFIG_64BIT 1639 build_get_pmde64(p, l, r, pte, ptr); /* get pmd in ptr */ 1640 #else 1641 build_get_pgde32(p, pte, ptr); /* get pgd in ptr */ 1642 #endif 1643 1644 i_MFC0(p, pte, C0_BADVADDR); 1645 i_LW(p, ptr, 0, ptr); 1646 i_SRL(p, pte, pte, PAGE_SHIFT + PTE_ORDER - PTE_T_LOG2); 1647 i_andi(p, pte, pte, (PTRS_PER_PTE - 1) << PTE_T_LOG2); 1648 i_ADDU(p, ptr, ptr, pte); 1649 1650 #ifdef CONFIG_SMP 1651 l_smp_pgtable_change(l, *p); 1652 # endif 1653 iPTE_LW(p, l, pte, ptr); /* get even pte */ 1654 build_tlb_probe_entry(p); 1655 } 1656 1657 static void __init 1658 build_r4000_tlbchange_handler_tail(u32 **p, struct label **l, 1659 struct reloc **r, unsigned int tmp, 1660 unsigned int ptr) 1661 { 1662 i_ori(p, ptr, ptr, sizeof(pte_t)); 1663 i_xori(p, ptr, ptr, sizeof(pte_t)); 1664 build_update_entries(p, tmp, ptr); 1665 build_tlb_write_entry(p, l, r, tlb_indexed); 1666 l_leave(l, *p); 1667 i_eret(p); /* return from trap */ 1668 1669 #ifdef CONFIG_64BIT 1670 build_get_pgd_vmalloc64(p, l, r, tmp, ptr); 1671 #endif 1672 } 1673 1674 static void __init build_r4000_tlb_load_handler(void) 1675 { 1676 u32 *p = handle_tlbl; 1677 struct label *l = labels; 1678 struct reloc *r = relocs; 1679 1680 memset(handle_tlbl, 0, sizeof(handle_tlbl)); 1681 memset(labels, 0, sizeof(labels)); 1682 memset(relocs, 0, sizeof(relocs)); 1683 1684 if (bcm1250_m3_war()) { 1685 i_MFC0(&p, K0, C0_BADVADDR); 1686 i_MFC0(&p, K1, C0_ENTRYHI); 1687 i_xor(&p, K0, K0, K1); 1688 i_SRL(&p, K0, K0, PAGE_SHIFT + 1); 1689 il_bnez(&p, &r, K0, label_leave); 1690 /* No need for i_nop */ 1691 } 1692 1693 build_r4000_tlbchange_handler_head(&p, &l, &r, K0, K1); 1694 build_pte_present(&p, &l, &r, K0, K1, label_nopage_tlbl); 1695 build_make_valid(&p, &r, K0, K1); 1696 build_r4000_tlbchange_handler_tail(&p, &l, &r, K0, K1); 1697 1698 l_nopage_tlbl(&l, p); 1699 i_j(&p, (unsigned long)tlb_do_page_fault_0 & 0x0fffffff); 1700 i_nop(&p); 1701 1702 if ((p - handle_tlbl) > FASTPATH_SIZE) 1703 panic("TLB load handler fastpath space exceeded"); 1704 1705 resolve_relocs(relocs, labels); 1706 printk("Synthesized TLB load handler fastpath (%u instructions).\n", 1707 (unsigned int)(p - handle_tlbl)); 1708 1709 #ifdef DEBUG_TLB 1710 { 1711 int i; 1712 1713 for (i = 0; i < (p - handle_tlbl); i++) 1714 printk("%08x\n", handle_tlbl[i]); 1715 } 1716 #endif 1717 } 1718 1719 static void __init build_r4000_tlb_store_handler(void) 1720 { 1721 u32 *p = handle_tlbs; 1722 struct label *l = labels; 1723 struct reloc *r = relocs; 1724 1725 memset(handle_tlbs, 0, sizeof(handle_tlbs)); 1726 memset(labels, 0, sizeof(labels)); 1727 memset(relocs, 0, sizeof(relocs)); 1728 1729 build_r4000_tlbchange_handler_head(&p, &l, &r, K0, K1); 1730 build_pte_writable(&p, &l, &r, K0, K1, label_nopage_tlbs); 1731 build_make_write(&p, &r, K0, K1); 1732 build_r4000_tlbchange_handler_tail(&p, &l, &r, K0, K1); 1733 1734 l_nopage_tlbs(&l, p); 1735 i_j(&p, (unsigned long)tlb_do_page_fault_1 & 0x0fffffff); 1736 i_nop(&p); 1737 1738 if ((p - handle_tlbs) > FASTPATH_SIZE) 1739 panic("TLB store handler fastpath space exceeded"); 1740 1741 resolve_relocs(relocs, labels); 1742 printk("Synthesized TLB store handler fastpath (%u instructions).\n", 1743 (unsigned int)(p - handle_tlbs)); 1744 1745 #ifdef DEBUG_TLB 1746 { 1747 int i; 1748 1749 for (i = 0; i < (p - handle_tlbs); i++) 1750 printk("%08x\n", handle_tlbs[i]); 1751 } 1752 #endif 1753 } 1754 1755 static void __init build_r4000_tlb_modify_handler(void) 1756 { 1757 u32 *p = handle_tlbm; 1758 struct label *l = labels; 1759 struct reloc *r = relocs; 1760 1761 memset(handle_tlbm, 0, sizeof(handle_tlbm)); 1762 memset(labels, 0, sizeof(labels)); 1763 memset(relocs, 0, sizeof(relocs)); 1764 1765 build_r4000_tlbchange_handler_head(&p, &l, &r, K0, K1); 1766 build_pte_modifiable(&p, &l, &r, K0, K1, label_nopage_tlbm); 1767 /* Present and writable bits set, set accessed and dirty bits. */ 1768 build_make_write(&p, &r, K0, K1); 1769 build_r4000_tlbchange_handler_tail(&p, &l, &r, K0, K1); 1770 1771 l_nopage_tlbm(&l, p); 1772 i_j(&p, (unsigned long)tlb_do_page_fault_1 & 0x0fffffff); 1773 i_nop(&p); 1774 1775 if ((p - handle_tlbm) > FASTPATH_SIZE) 1776 panic("TLB modify handler fastpath space exceeded"); 1777 1778 resolve_relocs(relocs, labels); 1779 printk("Synthesized TLB modify handler fastpath (%u instructions).\n", 1780 (unsigned int)(p - handle_tlbm)); 1781 1782 #ifdef DEBUG_TLB 1783 { 1784 int i; 1785 1786 for (i = 0; i < (p - handle_tlbm); i++) 1787 printk("%08x\n", handle_tlbm[i]); 1788 } 1789 #endif 1790 } 1791 1792 void __init build_tlb_refill_handler(void) 1793 { 1794 /* 1795 * The refill handler is generated per-CPU, multi-node systems 1796 * may have local storage for it. The other handlers are only 1797 * needed once. 1798 */ 1799 static int run_once = 0; 1800 1801 switch (current_cpu_data.cputype) { 1802 case CPU_R2000: 1803 case CPU_R3000: 1804 case CPU_R3000A: 1805 case CPU_R3081E: 1806 case CPU_TX3912: 1807 case CPU_TX3922: 1808 case CPU_TX3927: 1809 build_r3000_tlb_refill_handler(); 1810 if (!run_once) { 1811 build_r3000_tlb_load_handler(); 1812 build_r3000_tlb_store_handler(); 1813 build_r3000_tlb_modify_handler(); 1814 run_once++; 1815 } 1816 break; 1817 1818 case CPU_R6000: 1819 case CPU_R6000A: 1820 panic("No R6000 TLB refill handler yet"); 1821 break; 1822 1823 case CPU_R8000: 1824 panic("No R8000 TLB refill handler yet"); 1825 break; 1826 1827 default: 1828 build_r4000_tlb_refill_handler(); 1829 if (!run_once) { 1830 build_r4000_tlb_load_handler(); 1831 build_r4000_tlb_store_handler(); 1832 build_r4000_tlb_modify_handler(); 1833 run_once++; 1834 } 1835 } 1836 } 1837 1838 void __init flush_tlb_handlers(void) 1839 { 1840 flush_icache_range((unsigned long)handle_tlbl, 1841 (unsigned long)handle_tlbl + sizeof(handle_tlbl)); 1842 flush_icache_range((unsigned long)handle_tlbs, 1843 (unsigned long)handle_tlbs + sizeof(handle_tlbs)); 1844 flush_icache_range((unsigned long)handle_tlbm, 1845 (unsigned long)handle_tlbm + sizeof(handle_tlbm)); 1846 } 1847