1 /* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * Synthesize TLB refill handlers at runtime. 7 * 8 * Copyright (C) 2004,2005 by Thiemo Seufer 9 * Copyright (C) 2005 Maciej W. Rozycki 10 * Copyright (C) 2006 Ralf Baechle (ralf@linux-mips.org) 11 * 12 * ... and the days got worse and worse and now you see 13 * I've gone completly out of my mind. 14 * 15 * They're coming to take me a away haha 16 * they're coming to take me a away hoho hihi haha 17 * to the funny farm where code is beautiful all the time ... 18 * 19 * (Condolences to Napoleon XIV) 20 */ 21 22 #include <stdarg.h> 23 24 #include <linux/mm.h> 25 #include <linux/kernel.h> 26 #include <linux/types.h> 27 #include <linux/string.h> 28 #include <linux/init.h> 29 30 #include <asm/pgtable.h> 31 #include <asm/cacheflush.h> 32 #include <asm/mmu_context.h> 33 #include <asm/inst.h> 34 #include <asm/elf.h> 35 #include <asm/smp.h> 36 #include <asm/war.h> 37 38 /* #define DEBUG_TLB */ 39 40 static __init int __attribute__((unused)) r45k_bvahwbug(void) 41 { 42 /* XXX: We should probe for the presence of this bug, but we don't. */ 43 return 0; 44 } 45 46 static __init int __attribute__((unused)) r4k_250MHZhwbug(void) 47 { 48 /* XXX: We should probe for the presence of this bug, but we don't. */ 49 return 0; 50 } 51 52 static __init int __attribute__((unused)) bcm1250_m3_war(void) 53 { 54 return BCM1250_M3_WAR; 55 } 56 57 static __init int __attribute__((unused)) r10000_llsc_war(void) 58 { 59 return R10000_LLSC_WAR; 60 } 61 62 /* 63 * A little micro-assembler, intended for TLB refill handler 64 * synthesizing. It is intentionally kept simple, does only support 65 * a subset of instructions, and does not try to hide pipeline effects 66 * like branch delay slots. 67 */ 68 69 enum fields 70 { 71 RS = 0x001, 72 RT = 0x002, 73 RD = 0x004, 74 RE = 0x008, 75 SIMM = 0x010, 76 UIMM = 0x020, 77 BIMM = 0x040, 78 JIMM = 0x080, 79 FUNC = 0x100, 80 SET = 0x200 81 }; 82 83 #define OP_MASK 0x2f 84 #define OP_SH 26 85 #define RS_MASK 0x1f 86 #define RS_SH 21 87 #define RT_MASK 0x1f 88 #define RT_SH 16 89 #define RD_MASK 0x1f 90 #define RD_SH 11 91 #define RE_MASK 0x1f 92 #define RE_SH 6 93 #define IMM_MASK 0xffff 94 #define IMM_SH 0 95 #define JIMM_MASK 0x3ffffff 96 #define JIMM_SH 0 97 #define FUNC_MASK 0x2f 98 #define FUNC_SH 0 99 #define SET_MASK 0x7 100 #define SET_SH 0 101 102 enum opcode { 103 insn_invalid, 104 insn_addu, insn_addiu, insn_and, insn_andi, insn_beq, 105 insn_beql, insn_bgez, insn_bgezl, insn_bltz, insn_bltzl, 106 insn_bne, insn_daddu, insn_daddiu, insn_dmfc0, insn_dmtc0, 107 insn_dsll, insn_dsll32, insn_dsra, insn_dsrl, 108 insn_dsubu, insn_eret, insn_j, insn_jal, insn_jr, insn_ld, 109 insn_ll, insn_lld, insn_lui, insn_lw, insn_mfc0, insn_mtc0, 110 insn_ori, insn_rfe, insn_sc, insn_scd, insn_sd, insn_sll, 111 insn_sra, insn_srl, insn_subu, insn_sw, insn_tlbp, insn_tlbwi, 112 insn_tlbwr, insn_xor, insn_xori 113 }; 114 115 struct insn { 116 enum opcode opcode; 117 u32 match; 118 enum fields fields; 119 }; 120 121 /* This macro sets the non-variable bits of an instruction. */ 122 #define M(a, b, c, d, e, f) \ 123 ((a) << OP_SH \ 124 | (b) << RS_SH \ 125 | (c) << RT_SH \ 126 | (d) << RD_SH \ 127 | (e) << RE_SH \ 128 | (f) << FUNC_SH) 129 130 static __initdata struct insn insn_table[] = { 131 { insn_addiu, M(addiu_op,0,0,0,0,0), RS | RT | SIMM }, 132 { insn_addu, M(spec_op,0,0,0,0,addu_op), RS | RT | RD }, 133 { insn_and, M(spec_op,0,0,0,0,and_op), RS | RT | RD }, 134 { insn_andi, M(andi_op,0,0,0,0,0), RS | RT | UIMM }, 135 { insn_beq, M(beq_op,0,0,0,0,0), RS | RT | BIMM }, 136 { insn_beql, M(beql_op,0,0,0,0,0), RS | RT | BIMM }, 137 { insn_bgez, M(bcond_op,0,bgez_op,0,0,0), RS | BIMM }, 138 { insn_bgezl, M(bcond_op,0,bgezl_op,0,0,0), RS | BIMM }, 139 { insn_bltz, M(bcond_op,0,bltz_op,0,0,0), RS | BIMM }, 140 { insn_bltzl, M(bcond_op,0,bltzl_op,0,0,0), RS | BIMM }, 141 { insn_bne, M(bne_op,0,0,0,0,0), RS | RT | BIMM }, 142 { insn_daddiu, M(daddiu_op,0,0,0,0,0), RS | RT | SIMM }, 143 { insn_daddu, M(spec_op,0,0,0,0,daddu_op), RS | RT | RD }, 144 { insn_dmfc0, M(cop0_op,dmfc_op,0,0,0,0), RT | RD | SET}, 145 { insn_dmtc0, M(cop0_op,dmtc_op,0,0,0,0), RT | RD | SET}, 146 { insn_dsll, M(spec_op,0,0,0,0,dsll_op), RT | RD | RE }, 147 { insn_dsll32, M(spec_op,0,0,0,0,dsll32_op), RT | RD | RE }, 148 { insn_dsra, M(spec_op,0,0,0,0,dsra_op), RT | RD | RE }, 149 { insn_dsrl, M(spec_op,0,0,0,0,dsrl_op), RT | RD | RE }, 150 { insn_dsubu, M(spec_op,0,0,0,0,dsubu_op), RS | RT | RD }, 151 { insn_eret, M(cop0_op,cop_op,0,0,0,eret_op), 0 }, 152 { insn_j, M(j_op,0,0,0,0,0), JIMM }, 153 { insn_jal, M(jal_op,0,0,0,0,0), JIMM }, 154 { insn_jr, M(spec_op,0,0,0,0,jr_op), RS }, 155 { insn_ld, M(ld_op,0,0,0,0,0), RS | RT | SIMM }, 156 { insn_ll, M(ll_op,0,0,0,0,0), RS | RT | SIMM }, 157 { insn_lld, M(lld_op,0,0,0,0,0), RS | RT | SIMM }, 158 { insn_lui, M(lui_op,0,0,0,0,0), RT | SIMM }, 159 { insn_lw, M(lw_op,0,0,0,0,0), RS | RT | SIMM }, 160 { insn_mfc0, M(cop0_op,mfc_op,0,0,0,0), RT | RD | SET}, 161 { insn_mtc0, M(cop0_op,mtc_op,0,0,0,0), RT | RD | SET}, 162 { insn_ori, M(ori_op,0,0,0,0,0), RS | RT | UIMM }, 163 { insn_rfe, M(cop0_op,cop_op,0,0,0,rfe_op), 0 }, 164 { insn_sc, M(sc_op,0,0,0,0,0), RS | RT | SIMM }, 165 { insn_scd, M(scd_op,0,0,0,0,0), RS | RT | SIMM }, 166 { insn_sd, M(sd_op,0,0,0,0,0), RS | RT | SIMM }, 167 { insn_sll, M(spec_op,0,0,0,0,sll_op), RT | RD | RE }, 168 { insn_sra, M(spec_op,0,0,0,0,sra_op), RT | RD | RE }, 169 { insn_srl, M(spec_op,0,0,0,0,srl_op), RT | RD | RE }, 170 { insn_subu, M(spec_op,0,0,0,0,subu_op), RS | RT | RD }, 171 { insn_sw, M(sw_op,0,0,0,0,0), RS | RT | SIMM }, 172 { insn_tlbp, M(cop0_op,cop_op,0,0,0,tlbp_op), 0 }, 173 { insn_tlbwi, M(cop0_op,cop_op,0,0,0,tlbwi_op), 0 }, 174 { insn_tlbwr, M(cop0_op,cop_op,0,0,0,tlbwr_op), 0 }, 175 { insn_xor, M(spec_op,0,0,0,0,xor_op), RS | RT | RD }, 176 { insn_xori, M(xori_op,0,0,0,0,0), RS | RT | UIMM }, 177 { insn_invalid, 0, 0 } 178 }; 179 180 #undef M 181 182 static __init u32 build_rs(u32 arg) 183 { 184 if (arg & ~RS_MASK) 185 printk(KERN_WARNING "TLB synthesizer field overflow\n"); 186 187 return (arg & RS_MASK) << RS_SH; 188 } 189 190 static __init u32 build_rt(u32 arg) 191 { 192 if (arg & ~RT_MASK) 193 printk(KERN_WARNING "TLB synthesizer field overflow\n"); 194 195 return (arg & RT_MASK) << RT_SH; 196 } 197 198 static __init u32 build_rd(u32 arg) 199 { 200 if (arg & ~RD_MASK) 201 printk(KERN_WARNING "TLB synthesizer field overflow\n"); 202 203 return (arg & RD_MASK) << RD_SH; 204 } 205 206 static __init u32 build_re(u32 arg) 207 { 208 if (arg & ~RE_MASK) 209 printk(KERN_WARNING "TLB synthesizer field overflow\n"); 210 211 return (arg & RE_MASK) << RE_SH; 212 } 213 214 static __init u32 build_simm(s32 arg) 215 { 216 if (arg > 0x7fff || arg < -0x8000) 217 printk(KERN_WARNING "TLB synthesizer field overflow\n"); 218 219 return arg & 0xffff; 220 } 221 222 static __init u32 build_uimm(u32 arg) 223 { 224 if (arg & ~IMM_MASK) 225 printk(KERN_WARNING "TLB synthesizer field overflow\n"); 226 227 return arg & IMM_MASK; 228 } 229 230 static __init u32 build_bimm(s32 arg) 231 { 232 if (arg > 0x1ffff || arg < -0x20000) 233 printk(KERN_WARNING "TLB synthesizer field overflow\n"); 234 235 if (arg & 0x3) 236 printk(KERN_WARNING "Invalid TLB synthesizer branch target\n"); 237 238 return ((arg < 0) ? (1 << 15) : 0) | ((arg >> 2) & 0x7fff); 239 } 240 241 static __init u32 build_jimm(u32 arg) 242 { 243 if (arg & ~((JIMM_MASK) << 2)) 244 printk(KERN_WARNING "TLB synthesizer field overflow\n"); 245 246 return (arg >> 2) & JIMM_MASK; 247 } 248 249 static __init u32 build_func(u32 arg) 250 { 251 if (arg & ~FUNC_MASK) 252 printk(KERN_WARNING "TLB synthesizer field overflow\n"); 253 254 return arg & FUNC_MASK; 255 } 256 257 static __init u32 build_set(u32 arg) 258 { 259 if (arg & ~SET_MASK) 260 printk(KERN_WARNING "TLB synthesizer field overflow\n"); 261 262 return arg & SET_MASK; 263 } 264 265 /* 266 * The order of opcode arguments is implicitly left to right, 267 * starting with RS and ending with FUNC or IMM. 268 */ 269 static void __init build_insn(u32 **buf, enum opcode opc, ...) 270 { 271 struct insn *ip = NULL; 272 unsigned int i; 273 va_list ap; 274 u32 op; 275 276 for (i = 0; insn_table[i].opcode != insn_invalid; i++) 277 if (insn_table[i].opcode == opc) { 278 ip = &insn_table[i]; 279 break; 280 } 281 282 if (!ip) 283 panic("Unsupported TLB synthesizer instruction %d", opc); 284 285 op = ip->match; 286 va_start(ap, opc); 287 if (ip->fields & RS) op |= build_rs(va_arg(ap, u32)); 288 if (ip->fields & RT) op |= build_rt(va_arg(ap, u32)); 289 if (ip->fields & RD) op |= build_rd(va_arg(ap, u32)); 290 if (ip->fields & RE) op |= build_re(va_arg(ap, u32)); 291 if (ip->fields & SIMM) op |= build_simm(va_arg(ap, s32)); 292 if (ip->fields & UIMM) op |= build_uimm(va_arg(ap, u32)); 293 if (ip->fields & BIMM) op |= build_bimm(va_arg(ap, s32)); 294 if (ip->fields & JIMM) op |= build_jimm(va_arg(ap, u32)); 295 if (ip->fields & FUNC) op |= build_func(va_arg(ap, u32)); 296 if (ip->fields & SET) op |= build_set(va_arg(ap, u32)); 297 va_end(ap); 298 299 **buf = op; 300 (*buf)++; 301 } 302 303 #define I_u1u2u3(op) \ 304 static inline void __init i##op(u32 **buf, unsigned int a, \ 305 unsigned int b, unsigned int c) \ 306 { \ 307 build_insn(buf, insn##op, a, b, c); \ 308 } 309 310 #define I_u2u1u3(op) \ 311 static inline void __init i##op(u32 **buf, unsigned int a, \ 312 unsigned int b, unsigned int c) \ 313 { \ 314 build_insn(buf, insn##op, b, a, c); \ 315 } 316 317 #define I_u3u1u2(op) \ 318 static inline void __init i##op(u32 **buf, unsigned int a, \ 319 unsigned int b, unsigned int c) \ 320 { \ 321 build_insn(buf, insn##op, b, c, a); \ 322 } 323 324 #define I_u1u2s3(op) \ 325 static inline void __init i##op(u32 **buf, unsigned int a, \ 326 unsigned int b, signed int c) \ 327 { \ 328 build_insn(buf, insn##op, a, b, c); \ 329 } 330 331 #define I_u2s3u1(op) \ 332 static inline void __init i##op(u32 **buf, unsigned int a, \ 333 signed int b, unsigned int c) \ 334 { \ 335 build_insn(buf, insn##op, c, a, b); \ 336 } 337 338 #define I_u2u1s3(op) \ 339 static inline void __init i##op(u32 **buf, unsigned int a, \ 340 unsigned int b, signed int c) \ 341 { \ 342 build_insn(buf, insn##op, b, a, c); \ 343 } 344 345 #define I_u1u2(op) \ 346 static inline void __init i##op(u32 **buf, unsigned int a, \ 347 unsigned int b) \ 348 { \ 349 build_insn(buf, insn##op, a, b); \ 350 } 351 352 #define I_u1s2(op) \ 353 static inline void __init i##op(u32 **buf, unsigned int a, \ 354 signed int b) \ 355 { \ 356 build_insn(buf, insn##op, a, b); \ 357 } 358 359 #define I_u1(op) \ 360 static inline void __init i##op(u32 **buf, unsigned int a) \ 361 { \ 362 build_insn(buf, insn##op, a); \ 363 } 364 365 #define I_0(op) \ 366 static inline void __init i##op(u32 **buf) \ 367 { \ 368 build_insn(buf, insn##op); \ 369 } 370 371 I_u2u1s3(_addiu); 372 I_u3u1u2(_addu); 373 I_u2u1u3(_andi); 374 I_u3u1u2(_and); 375 I_u1u2s3(_beq); 376 I_u1u2s3(_beql); 377 I_u1s2(_bgez); 378 I_u1s2(_bgezl); 379 I_u1s2(_bltz); 380 I_u1s2(_bltzl); 381 I_u1u2s3(_bne); 382 I_u1u2u3(_dmfc0); 383 I_u1u2u3(_dmtc0); 384 I_u2u1s3(_daddiu); 385 I_u3u1u2(_daddu); 386 I_u2u1u3(_dsll); 387 I_u2u1u3(_dsll32); 388 I_u2u1u3(_dsra); 389 I_u2u1u3(_dsrl); 390 I_u3u1u2(_dsubu); 391 I_0(_eret); 392 I_u1(_j); 393 I_u1(_jal); 394 I_u1(_jr); 395 I_u2s3u1(_ld); 396 I_u2s3u1(_ll); 397 I_u2s3u1(_lld); 398 I_u1s2(_lui); 399 I_u2s3u1(_lw); 400 I_u1u2u3(_mfc0); 401 I_u1u2u3(_mtc0); 402 I_u2u1u3(_ori); 403 I_0(_rfe); 404 I_u2s3u1(_sc); 405 I_u2s3u1(_scd); 406 I_u2s3u1(_sd); 407 I_u2u1u3(_sll); 408 I_u2u1u3(_sra); 409 I_u2u1u3(_srl); 410 I_u3u1u2(_subu); 411 I_u2s3u1(_sw); 412 I_0(_tlbp); 413 I_0(_tlbwi); 414 I_0(_tlbwr); 415 I_u3u1u2(_xor) 416 I_u2u1u3(_xori); 417 418 /* 419 * handling labels 420 */ 421 422 enum label_id { 423 label_invalid, 424 label_second_part, 425 label_leave, 426 label_vmalloc, 427 label_vmalloc_done, 428 label_tlbw_hazard, 429 label_split, 430 label_nopage_tlbl, 431 label_nopage_tlbs, 432 label_nopage_tlbm, 433 label_smp_pgtable_change, 434 label_r3000_write_probe_fail, 435 }; 436 437 struct label { 438 u32 *addr; 439 enum label_id lab; 440 }; 441 442 static __init void build_label(struct label **lab, u32 *addr, 443 enum label_id l) 444 { 445 (*lab)->addr = addr; 446 (*lab)->lab = l; 447 (*lab)++; 448 } 449 450 #define L_LA(lb) \ 451 static inline void l##lb(struct label **lab, u32 *addr) \ 452 { \ 453 build_label(lab, addr, label##lb); \ 454 } 455 456 L_LA(_second_part) 457 L_LA(_leave) 458 L_LA(_vmalloc) 459 L_LA(_vmalloc_done) 460 L_LA(_tlbw_hazard) 461 L_LA(_split) 462 L_LA(_nopage_tlbl) 463 L_LA(_nopage_tlbs) 464 L_LA(_nopage_tlbm) 465 L_LA(_smp_pgtable_change) 466 L_LA(_r3000_write_probe_fail) 467 468 /* convenience macros for instructions */ 469 #ifdef CONFIG_64BIT 470 # define i_LW(buf, rs, rt, off) i_ld(buf, rs, rt, off) 471 # define i_SW(buf, rs, rt, off) i_sd(buf, rs, rt, off) 472 # define i_SLL(buf, rs, rt, sh) i_dsll(buf, rs, rt, sh) 473 # define i_SRA(buf, rs, rt, sh) i_dsra(buf, rs, rt, sh) 474 # define i_SRL(buf, rs, rt, sh) i_dsrl(buf, rs, rt, sh) 475 # define i_MFC0(buf, rt, rd...) i_dmfc0(buf, rt, rd) 476 # define i_MTC0(buf, rt, rd...) i_dmtc0(buf, rt, rd) 477 # define i_ADDIU(buf, rs, rt, val) i_daddiu(buf, rs, rt, val) 478 # define i_ADDU(buf, rs, rt, rd) i_daddu(buf, rs, rt, rd) 479 # define i_SUBU(buf, rs, rt, rd) i_dsubu(buf, rs, rt, rd) 480 # define i_LL(buf, rs, rt, off) i_lld(buf, rs, rt, off) 481 # define i_SC(buf, rs, rt, off) i_scd(buf, rs, rt, off) 482 #else 483 # define i_LW(buf, rs, rt, off) i_lw(buf, rs, rt, off) 484 # define i_SW(buf, rs, rt, off) i_sw(buf, rs, rt, off) 485 # define i_SLL(buf, rs, rt, sh) i_sll(buf, rs, rt, sh) 486 # define i_SRA(buf, rs, rt, sh) i_sra(buf, rs, rt, sh) 487 # define i_SRL(buf, rs, rt, sh) i_srl(buf, rs, rt, sh) 488 # define i_MFC0(buf, rt, rd...) i_mfc0(buf, rt, rd) 489 # define i_MTC0(buf, rt, rd...) i_mtc0(buf, rt, rd) 490 # define i_ADDIU(buf, rs, rt, val) i_addiu(buf, rs, rt, val) 491 # define i_ADDU(buf, rs, rt, rd) i_addu(buf, rs, rt, rd) 492 # define i_SUBU(buf, rs, rt, rd) i_subu(buf, rs, rt, rd) 493 # define i_LL(buf, rs, rt, off) i_ll(buf, rs, rt, off) 494 # define i_SC(buf, rs, rt, off) i_sc(buf, rs, rt, off) 495 #endif 496 497 #define i_b(buf, off) i_beq(buf, 0, 0, off) 498 #define i_beqz(buf, rs, off) i_beq(buf, rs, 0, off) 499 #define i_beqzl(buf, rs, off) i_beql(buf, rs, 0, off) 500 #define i_bnez(buf, rs, off) i_bne(buf, rs, 0, off) 501 #define i_bnezl(buf, rs, off) i_bnel(buf, rs, 0, off) 502 #define i_move(buf, a, b) i_ADDU(buf, a, 0, b) 503 #define i_nop(buf) i_sll(buf, 0, 0, 0) 504 #define i_ssnop(buf) i_sll(buf, 0, 0, 1) 505 #define i_ehb(buf) i_sll(buf, 0, 0, 3) 506 507 #ifdef CONFIG_64BIT 508 static __init int __attribute__((unused)) in_compat_space_p(long addr) 509 { 510 /* Is this address in 32bit compat space? */ 511 return (((addr) & 0xffffffff00000000L) == 0xffffffff00000000L); 512 } 513 514 static __init int __attribute__((unused)) rel_highest(long val) 515 { 516 return ((((val + 0x800080008000L) >> 48) & 0xffff) ^ 0x8000) - 0x8000; 517 } 518 519 static __init int __attribute__((unused)) rel_higher(long val) 520 { 521 return ((((val + 0x80008000L) >> 32) & 0xffff) ^ 0x8000) - 0x8000; 522 } 523 #endif 524 525 static __init int rel_hi(long val) 526 { 527 return ((((val + 0x8000L) >> 16) & 0xffff) ^ 0x8000) - 0x8000; 528 } 529 530 static __init int rel_lo(long val) 531 { 532 return ((val & 0xffff) ^ 0x8000) - 0x8000; 533 } 534 535 static __init void i_LA_mostly(u32 **buf, unsigned int rs, long addr) 536 { 537 #ifdef CONFIG_64BIT 538 if (!in_compat_space_p(addr)) { 539 i_lui(buf, rs, rel_highest(addr)); 540 if (rel_higher(addr)) 541 i_daddiu(buf, rs, rs, rel_higher(addr)); 542 if (rel_hi(addr)) { 543 i_dsll(buf, rs, rs, 16); 544 i_daddiu(buf, rs, rs, rel_hi(addr)); 545 i_dsll(buf, rs, rs, 16); 546 } else 547 i_dsll32(buf, rs, rs, 0); 548 } else 549 #endif 550 i_lui(buf, rs, rel_hi(addr)); 551 } 552 553 static __init void __attribute__((unused)) i_LA(u32 **buf, unsigned int rs, 554 long addr) 555 { 556 i_LA_mostly(buf, rs, addr); 557 if (rel_lo(addr)) 558 i_ADDIU(buf, rs, rs, rel_lo(addr)); 559 } 560 561 /* 562 * handle relocations 563 */ 564 565 struct reloc { 566 u32 *addr; 567 unsigned int type; 568 enum label_id lab; 569 }; 570 571 static __init void r_mips_pc16(struct reloc **rel, u32 *addr, 572 enum label_id l) 573 { 574 (*rel)->addr = addr; 575 (*rel)->type = R_MIPS_PC16; 576 (*rel)->lab = l; 577 (*rel)++; 578 } 579 580 static inline void __resolve_relocs(struct reloc *rel, struct label *lab) 581 { 582 long laddr = (long)lab->addr; 583 long raddr = (long)rel->addr; 584 585 switch (rel->type) { 586 case R_MIPS_PC16: 587 *rel->addr |= build_bimm(laddr - (raddr + 4)); 588 break; 589 590 default: 591 panic("Unsupported TLB synthesizer relocation %d", 592 rel->type); 593 } 594 } 595 596 static __init void resolve_relocs(struct reloc *rel, struct label *lab) 597 { 598 struct label *l; 599 600 for (; rel->lab != label_invalid; rel++) 601 for (l = lab; l->lab != label_invalid; l++) 602 if (rel->lab == l->lab) 603 __resolve_relocs(rel, l); 604 } 605 606 static __init void move_relocs(struct reloc *rel, u32 *first, u32 *end, 607 long off) 608 { 609 for (; rel->lab != label_invalid; rel++) 610 if (rel->addr >= first && rel->addr < end) 611 rel->addr += off; 612 } 613 614 static __init void move_labels(struct label *lab, u32 *first, u32 *end, 615 long off) 616 { 617 for (; lab->lab != label_invalid; lab++) 618 if (lab->addr >= first && lab->addr < end) 619 lab->addr += off; 620 } 621 622 static __init void copy_handler(struct reloc *rel, struct label *lab, 623 u32 *first, u32 *end, u32 *target) 624 { 625 long off = (long)(target - first); 626 627 memcpy(target, first, (end - first) * sizeof(u32)); 628 629 move_relocs(rel, first, end, off); 630 move_labels(lab, first, end, off); 631 } 632 633 static __init int __attribute__((unused)) insn_has_bdelay(struct reloc *rel, 634 u32 *addr) 635 { 636 for (; rel->lab != label_invalid; rel++) { 637 if (rel->addr == addr 638 && (rel->type == R_MIPS_PC16 639 || rel->type == R_MIPS_26)) 640 return 1; 641 } 642 643 return 0; 644 } 645 646 /* convenience functions for labeled branches */ 647 static void __init __attribute__((unused)) 648 il_bltz(u32 **p, struct reloc **r, unsigned int reg, enum label_id l) 649 { 650 r_mips_pc16(r, *p, l); 651 i_bltz(p, reg, 0); 652 } 653 654 static void __init __attribute__((unused)) il_b(u32 **p, struct reloc **r, 655 enum label_id l) 656 { 657 r_mips_pc16(r, *p, l); 658 i_b(p, 0); 659 } 660 661 static void __init il_beqz(u32 **p, struct reloc **r, unsigned int reg, 662 enum label_id l) 663 { 664 r_mips_pc16(r, *p, l); 665 i_beqz(p, reg, 0); 666 } 667 668 static void __init __attribute__((unused)) 669 il_beqzl(u32 **p, struct reloc **r, unsigned int reg, enum label_id l) 670 { 671 r_mips_pc16(r, *p, l); 672 i_beqzl(p, reg, 0); 673 } 674 675 static void __init il_bnez(u32 **p, struct reloc **r, unsigned int reg, 676 enum label_id l) 677 { 678 r_mips_pc16(r, *p, l); 679 i_bnez(p, reg, 0); 680 } 681 682 static void __init il_bgezl(u32 **p, struct reloc **r, unsigned int reg, 683 enum label_id l) 684 { 685 r_mips_pc16(r, *p, l); 686 i_bgezl(p, reg, 0); 687 } 688 689 /* The only general purpose registers allowed in TLB handlers. */ 690 #define K0 26 691 #define K1 27 692 693 /* Some CP0 registers */ 694 #define C0_INDEX 0, 0 695 #define C0_ENTRYLO0 2, 0 696 #define C0_TCBIND 2, 2 697 #define C0_ENTRYLO1 3, 0 698 #define C0_CONTEXT 4, 0 699 #define C0_BADVADDR 8, 0 700 #define C0_ENTRYHI 10, 0 701 #define C0_EPC 14, 0 702 #define C0_XCONTEXT 20, 0 703 704 #ifdef CONFIG_64BIT 705 # define GET_CONTEXT(buf, reg) i_MFC0(buf, reg, C0_XCONTEXT) 706 #else 707 # define GET_CONTEXT(buf, reg) i_MFC0(buf, reg, C0_CONTEXT) 708 #endif 709 710 /* The worst case length of the handler is around 18 instructions for 711 * R3000-style TLBs and up to 63 instructions for R4000-style TLBs. 712 * Maximum space available is 32 instructions for R3000 and 64 713 * instructions for R4000. 714 * 715 * We deliberately chose a buffer size of 128, so we won't scribble 716 * over anything important on overflow before we panic. 717 */ 718 static __initdata u32 tlb_handler[128]; 719 720 /* simply assume worst case size for labels and relocs */ 721 static __initdata struct label labels[128]; 722 static __initdata struct reloc relocs[128]; 723 724 /* 725 * The R3000 TLB handler is simple. 726 */ 727 static void __init build_r3000_tlb_refill_handler(void) 728 { 729 long pgdc = (long)pgd_current; 730 u32 *p; 731 732 memset(tlb_handler, 0, sizeof(tlb_handler)); 733 p = tlb_handler; 734 735 i_mfc0(&p, K0, C0_BADVADDR); 736 i_lui(&p, K1, rel_hi(pgdc)); /* cp0 delay */ 737 i_lw(&p, K1, rel_lo(pgdc), K1); 738 i_srl(&p, K0, K0, 22); /* load delay */ 739 i_sll(&p, K0, K0, 2); 740 i_addu(&p, K1, K1, K0); 741 i_mfc0(&p, K0, C0_CONTEXT); 742 i_lw(&p, K1, 0, K1); /* cp0 delay */ 743 i_andi(&p, K0, K0, 0xffc); /* load delay */ 744 i_addu(&p, K1, K1, K0); 745 i_lw(&p, K0, 0, K1); 746 i_nop(&p); /* load delay */ 747 i_mtc0(&p, K0, C0_ENTRYLO0); 748 i_mfc0(&p, K1, C0_EPC); /* cp0 delay */ 749 i_tlbwr(&p); /* cp0 delay */ 750 i_jr(&p, K1); 751 i_rfe(&p); /* branch delay */ 752 753 if (p > tlb_handler + 32) 754 panic("TLB refill handler space exceeded"); 755 756 printk("Synthesized TLB refill handler (%u instructions).\n", 757 (unsigned int)(p - tlb_handler)); 758 #ifdef DEBUG_TLB 759 { 760 int i; 761 762 for (i = 0; i < (p - tlb_handler); i++) 763 printk("%08x\n", tlb_handler[i]); 764 } 765 #endif 766 767 memcpy((void *)ebase, tlb_handler, 0x80); 768 } 769 770 /* 771 * The R4000 TLB handler is much more complicated. We have two 772 * consecutive handler areas with 32 instructions space each. 773 * Since they aren't used at the same time, we can overflow in the 774 * other one.To keep things simple, we first assume linear space, 775 * then we relocate it to the final handler layout as needed. 776 */ 777 static __initdata u32 final_handler[64]; 778 779 /* 780 * Hazards 781 * 782 * From the IDT errata for the QED RM5230 (Nevada), processor revision 1.0: 783 * 2. A timing hazard exists for the TLBP instruction. 784 * 785 * stalling_instruction 786 * TLBP 787 * 788 * The JTLB is being read for the TLBP throughout the stall generated by the 789 * previous instruction. This is not really correct as the stalling instruction 790 * can modify the address used to access the JTLB. The failure symptom is that 791 * the TLBP instruction will use an address created for the stalling instruction 792 * and not the address held in C0_ENHI and thus report the wrong results. 793 * 794 * The software work-around is to not allow the instruction preceding the TLBP 795 * to stall - make it an NOP or some other instruction guaranteed not to stall. 796 * 797 * Errata 2 will not be fixed. This errata is also on the R5000. 798 * 799 * As if we MIPS hackers wouldn't know how to nop pipelines happy ... 800 */ 801 static __init void __attribute__((unused)) build_tlb_probe_entry(u32 **p) 802 { 803 switch (current_cpu_data.cputype) { 804 /* Found by experiment: R4600 v2.0 needs this, too. */ 805 case CPU_R4600: 806 case CPU_R5000: 807 case CPU_R5000A: 808 case CPU_NEVADA: 809 i_nop(p); 810 i_tlbp(p); 811 break; 812 813 default: 814 i_tlbp(p); 815 break; 816 } 817 } 818 819 /* 820 * Write random or indexed TLB entry, and care about the hazards from 821 * the preceeding mtc0 and for the following eret. 822 */ 823 enum tlb_write_entry { tlb_random, tlb_indexed }; 824 825 static __init void build_tlb_write_entry(u32 **p, struct label **l, 826 struct reloc **r, 827 enum tlb_write_entry wmode) 828 { 829 void(*tlbw)(u32 **) = NULL; 830 831 switch (wmode) { 832 case tlb_random: tlbw = i_tlbwr; break; 833 case tlb_indexed: tlbw = i_tlbwi; break; 834 } 835 836 switch (current_cpu_data.cputype) { 837 case CPU_R4000PC: 838 case CPU_R4000SC: 839 case CPU_R4000MC: 840 case CPU_R4400PC: 841 case CPU_R4400SC: 842 case CPU_R4400MC: 843 /* 844 * This branch uses up a mtc0 hazard nop slot and saves 845 * two nops after the tlbw instruction. 846 */ 847 il_bgezl(p, r, 0, label_tlbw_hazard); 848 tlbw(p); 849 l_tlbw_hazard(l, *p); 850 i_nop(p); 851 break; 852 853 case CPU_R4600: 854 case CPU_R4700: 855 case CPU_R5000: 856 case CPU_R5000A: 857 i_nop(p); 858 tlbw(p); 859 i_nop(p); 860 break; 861 862 case CPU_R4300: 863 case CPU_5KC: 864 case CPU_TX49XX: 865 case CPU_AU1000: 866 case CPU_AU1100: 867 case CPU_AU1500: 868 case CPU_AU1550: 869 case CPU_AU1200: 870 case CPU_PR4450: 871 i_nop(p); 872 tlbw(p); 873 break; 874 875 case CPU_R10000: 876 case CPU_R12000: 877 case CPU_R14000: 878 case CPU_4KC: 879 case CPU_SB1: 880 case CPU_SB1A: 881 case CPU_4KSC: 882 case CPU_20KC: 883 case CPU_25KF: 884 tlbw(p); 885 break; 886 887 case CPU_NEVADA: 888 i_nop(p); /* QED specifies 2 nops hazard */ 889 /* 890 * This branch uses up a mtc0 hazard nop slot and saves 891 * a nop after the tlbw instruction. 892 */ 893 il_bgezl(p, r, 0, label_tlbw_hazard); 894 tlbw(p); 895 l_tlbw_hazard(l, *p); 896 break; 897 898 case CPU_RM7000: 899 i_nop(p); 900 i_nop(p); 901 i_nop(p); 902 i_nop(p); 903 tlbw(p); 904 break; 905 906 case CPU_4KEC: 907 case CPU_24K: 908 case CPU_34K: 909 case CPU_74K: 910 i_ehb(p); 911 tlbw(p); 912 break; 913 914 case CPU_RM9000: 915 /* 916 * When the JTLB is updated by tlbwi or tlbwr, a subsequent 917 * use of the JTLB for instructions should not occur for 4 918 * cpu cycles and use for data translations should not occur 919 * for 3 cpu cycles. 920 */ 921 i_ssnop(p); 922 i_ssnop(p); 923 i_ssnop(p); 924 i_ssnop(p); 925 tlbw(p); 926 i_ssnop(p); 927 i_ssnop(p); 928 i_ssnop(p); 929 i_ssnop(p); 930 break; 931 932 case CPU_VR4111: 933 case CPU_VR4121: 934 case CPU_VR4122: 935 case CPU_VR4181: 936 case CPU_VR4181A: 937 i_nop(p); 938 i_nop(p); 939 tlbw(p); 940 i_nop(p); 941 i_nop(p); 942 break; 943 944 case CPU_VR4131: 945 case CPU_VR4133: 946 case CPU_R5432: 947 i_nop(p); 948 i_nop(p); 949 tlbw(p); 950 break; 951 952 default: 953 panic("No TLB refill handler yet (CPU type: %d)", 954 current_cpu_data.cputype); 955 break; 956 } 957 } 958 959 #ifdef CONFIG_64BIT 960 /* 961 * TMP and PTR are scratch. 962 * TMP will be clobbered, PTR will hold the pmd entry. 963 */ 964 static __init void 965 build_get_pmde64(u32 **p, struct label **l, struct reloc **r, 966 unsigned int tmp, unsigned int ptr) 967 { 968 long pgdc = (long)pgd_current; 969 970 /* 971 * The vmalloc handling is not in the hotpath. 972 */ 973 i_dmfc0(p, tmp, C0_BADVADDR); 974 il_bltz(p, r, tmp, label_vmalloc); 975 /* No i_nop needed here, since the next insn doesn't touch TMP. */ 976 977 #ifdef CONFIG_SMP 978 # ifdef CONFIG_MIPS_MT_SMTC 979 /* 980 * SMTC uses TCBind value as "CPU" index 981 */ 982 i_mfc0(p, ptr, C0_TCBIND); 983 i_dsrl(p, ptr, ptr, 19); 984 # else 985 /* 986 * 64 bit SMP running in XKPHYS has smp_processor_id() << 3 987 * stored in CONTEXT. 988 */ 989 i_dmfc0(p, ptr, C0_CONTEXT); 990 i_dsrl(p, ptr, ptr, 23); 991 #endif 992 i_LA_mostly(p, tmp, pgdc); 993 i_daddu(p, ptr, ptr, tmp); 994 i_dmfc0(p, tmp, C0_BADVADDR); 995 i_ld(p, ptr, rel_lo(pgdc), ptr); 996 #else 997 i_LA_mostly(p, ptr, pgdc); 998 i_ld(p, ptr, rel_lo(pgdc), ptr); 999 #endif 1000 1001 l_vmalloc_done(l, *p); 1002 i_dsrl(p, tmp, tmp, PGDIR_SHIFT-3); /* get pgd offset in bytes */ 1003 i_andi(p, tmp, tmp, (PTRS_PER_PGD - 1)<<3); 1004 i_daddu(p, ptr, ptr, tmp); /* add in pgd offset */ 1005 i_dmfc0(p, tmp, C0_BADVADDR); /* get faulting address */ 1006 i_ld(p, ptr, 0, ptr); /* get pmd pointer */ 1007 i_dsrl(p, tmp, tmp, PMD_SHIFT-3); /* get pmd offset in bytes */ 1008 i_andi(p, tmp, tmp, (PTRS_PER_PMD - 1)<<3); 1009 i_daddu(p, ptr, ptr, tmp); /* add in pmd offset */ 1010 } 1011 1012 /* 1013 * BVADDR is the faulting address, PTR is scratch. 1014 * PTR will hold the pgd for vmalloc. 1015 */ 1016 static __init void 1017 build_get_pgd_vmalloc64(u32 **p, struct label **l, struct reloc **r, 1018 unsigned int bvaddr, unsigned int ptr) 1019 { 1020 long swpd = (long)swapper_pg_dir; 1021 1022 l_vmalloc(l, *p); 1023 i_LA(p, ptr, VMALLOC_START); 1024 i_dsubu(p, bvaddr, bvaddr, ptr); 1025 1026 if (in_compat_space_p(swpd) && !rel_lo(swpd)) { 1027 il_b(p, r, label_vmalloc_done); 1028 i_lui(p, ptr, rel_hi(swpd)); 1029 } else { 1030 i_LA_mostly(p, ptr, swpd); 1031 il_b(p, r, label_vmalloc_done); 1032 i_daddiu(p, ptr, ptr, rel_lo(swpd)); 1033 } 1034 } 1035 1036 #else /* !CONFIG_64BIT */ 1037 1038 /* 1039 * TMP and PTR are scratch. 1040 * TMP will be clobbered, PTR will hold the pgd entry. 1041 */ 1042 static __init void __attribute__((unused)) 1043 build_get_pgde32(u32 **p, unsigned int tmp, unsigned int ptr) 1044 { 1045 long pgdc = (long)pgd_current; 1046 1047 /* 32 bit SMP has smp_processor_id() stored in CONTEXT. */ 1048 #ifdef CONFIG_SMP 1049 #ifdef CONFIG_MIPS_MT_SMTC 1050 /* 1051 * SMTC uses TCBind value as "CPU" index 1052 */ 1053 i_mfc0(p, ptr, C0_TCBIND); 1054 i_LA_mostly(p, tmp, pgdc); 1055 i_srl(p, ptr, ptr, 19); 1056 #else 1057 /* 1058 * smp_processor_id() << 3 is stored in CONTEXT. 1059 */ 1060 i_mfc0(p, ptr, C0_CONTEXT); 1061 i_LA_mostly(p, tmp, pgdc); 1062 i_srl(p, ptr, ptr, 23); 1063 #endif 1064 i_addu(p, ptr, tmp, ptr); 1065 #else 1066 i_LA_mostly(p, ptr, pgdc); 1067 #endif 1068 i_mfc0(p, tmp, C0_BADVADDR); /* get faulting address */ 1069 i_lw(p, ptr, rel_lo(pgdc), ptr); 1070 i_srl(p, tmp, tmp, PGDIR_SHIFT); /* get pgd only bits */ 1071 i_sll(p, tmp, tmp, PGD_T_LOG2); 1072 i_addu(p, ptr, ptr, tmp); /* add in pgd offset */ 1073 } 1074 1075 #endif /* !CONFIG_64BIT */ 1076 1077 static __init void build_adjust_context(u32 **p, unsigned int ctx) 1078 { 1079 unsigned int shift = 4 - (PTE_T_LOG2 + 1); 1080 unsigned int mask = (PTRS_PER_PTE / 2 - 1) << (PTE_T_LOG2 + 1); 1081 1082 switch (current_cpu_data.cputype) { 1083 case CPU_VR41XX: 1084 case CPU_VR4111: 1085 case CPU_VR4121: 1086 case CPU_VR4122: 1087 case CPU_VR4131: 1088 case CPU_VR4181: 1089 case CPU_VR4181A: 1090 case CPU_VR4133: 1091 shift += 2; 1092 break; 1093 1094 default: 1095 break; 1096 } 1097 1098 if (shift) 1099 i_SRL(p, ctx, ctx, shift); 1100 i_andi(p, ctx, ctx, mask); 1101 } 1102 1103 static __init void build_get_ptep(u32 **p, unsigned int tmp, unsigned int ptr) 1104 { 1105 /* 1106 * Bug workaround for the Nevada. It seems as if under certain 1107 * circumstances the move from cp0_context might produce a 1108 * bogus result when the mfc0 instruction and its consumer are 1109 * in a different cacheline or a load instruction, probably any 1110 * memory reference, is between them. 1111 */ 1112 switch (current_cpu_data.cputype) { 1113 case CPU_NEVADA: 1114 i_LW(p, ptr, 0, ptr); 1115 GET_CONTEXT(p, tmp); /* get context reg */ 1116 break; 1117 1118 default: 1119 GET_CONTEXT(p, tmp); /* get context reg */ 1120 i_LW(p, ptr, 0, ptr); 1121 break; 1122 } 1123 1124 build_adjust_context(p, tmp); 1125 i_ADDU(p, ptr, ptr, tmp); /* add in offset */ 1126 } 1127 1128 static __init void build_update_entries(u32 **p, unsigned int tmp, 1129 unsigned int ptep) 1130 { 1131 /* 1132 * 64bit address support (36bit on a 32bit CPU) in a 32bit 1133 * Kernel is a special case. Only a few CPUs use it. 1134 */ 1135 #ifdef CONFIG_64BIT_PHYS_ADDR 1136 if (cpu_has_64bits) { 1137 i_ld(p, tmp, 0, ptep); /* get even pte */ 1138 i_ld(p, ptep, sizeof(pte_t), ptep); /* get odd pte */ 1139 i_dsrl(p, tmp, tmp, 6); /* convert to entrylo0 */ 1140 i_mtc0(p, tmp, C0_ENTRYLO0); /* load it */ 1141 i_dsrl(p, ptep, ptep, 6); /* convert to entrylo1 */ 1142 i_mtc0(p, ptep, C0_ENTRYLO1); /* load it */ 1143 } else { 1144 int pte_off_even = sizeof(pte_t) / 2; 1145 int pte_off_odd = pte_off_even + sizeof(pte_t); 1146 1147 /* The pte entries are pre-shifted */ 1148 i_lw(p, tmp, pte_off_even, ptep); /* get even pte */ 1149 i_mtc0(p, tmp, C0_ENTRYLO0); /* load it */ 1150 i_lw(p, ptep, pte_off_odd, ptep); /* get odd pte */ 1151 i_mtc0(p, ptep, C0_ENTRYLO1); /* load it */ 1152 } 1153 #else 1154 i_LW(p, tmp, 0, ptep); /* get even pte */ 1155 i_LW(p, ptep, sizeof(pte_t), ptep); /* get odd pte */ 1156 if (r45k_bvahwbug()) 1157 build_tlb_probe_entry(p); 1158 i_SRL(p, tmp, tmp, 6); /* convert to entrylo0 */ 1159 if (r4k_250MHZhwbug()) 1160 i_mtc0(p, 0, C0_ENTRYLO0); 1161 i_mtc0(p, tmp, C0_ENTRYLO0); /* load it */ 1162 i_SRL(p, ptep, ptep, 6); /* convert to entrylo1 */ 1163 if (r45k_bvahwbug()) 1164 i_mfc0(p, tmp, C0_INDEX); 1165 if (r4k_250MHZhwbug()) 1166 i_mtc0(p, 0, C0_ENTRYLO1); 1167 i_mtc0(p, ptep, C0_ENTRYLO1); /* load it */ 1168 #endif 1169 } 1170 1171 static void __init build_r4000_tlb_refill_handler(void) 1172 { 1173 u32 *p = tlb_handler; 1174 struct label *l = labels; 1175 struct reloc *r = relocs; 1176 u32 *f; 1177 unsigned int final_len; 1178 1179 memset(tlb_handler, 0, sizeof(tlb_handler)); 1180 memset(labels, 0, sizeof(labels)); 1181 memset(relocs, 0, sizeof(relocs)); 1182 memset(final_handler, 0, sizeof(final_handler)); 1183 1184 /* 1185 * create the plain linear handler 1186 */ 1187 if (bcm1250_m3_war()) { 1188 i_MFC0(&p, K0, C0_BADVADDR); 1189 i_MFC0(&p, K1, C0_ENTRYHI); 1190 i_xor(&p, K0, K0, K1); 1191 i_SRL(&p, K0, K0, PAGE_SHIFT + 1); 1192 il_bnez(&p, &r, K0, label_leave); 1193 /* No need for i_nop */ 1194 } 1195 1196 #ifdef CONFIG_64BIT 1197 build_get_pmde64(&p, &l, &r, K0, K1); /* get pmd in K1 */ 1198 #else 1199 build_get_pgde32(&p, K0, K1); /* get pgd in K1 */ 1200 #endif 1201 1202 build_get_ptep(&p, K0, K1); 1203 build_update_entries(&p, K0, K1); 1204 build_tlb_write_entry(&p, &l, &r, tlb_random); 1205 l_leave(&l, p); 1206 i_eret(&p); /* return from trap */ 1207 1208 #ifdef CONFIG_64BIT 1209 build_get_pgd_vmalloc64(&p, &l, &r, K0, K1); 1210 #endif 1211 1212 /* 1213 * Overflow check: For the 64bit handler, we need at least one 1214 * free instruction slot for the wrap-around branch. In worst 1215 * case, if the intended insertion point is a delay slot, we 1216 * need three, with the the second nop'ed and the third being 1217 * unused. 1218 */ 1219 #ifdef CONFIG_32BIT 1220 if ((p - tlb_handler) > 64) 1221 panic("TLB refill handler space exceeded"); 1222 #else 1223 if (((p - tlb_handler) > 63) 1224 || (((p - tlb_handler) > 61) 1225 && insn_has_bdelay(relocs, tlb_handler + 29))) 1226 panic("TLB refill handler space exceeded"); 1227 #endif 1228 1229 /* 1230 * Now fold the handler in the TLB refill handler space. 1231 */ 1232 #ifdef CONFIG_32BIT 1233 f = final_handler; 1234 /* Simplest case, just copy the handler. */ 1235 copy_handler(relocs, labels, tlb_handler, p, f); 1236 final_len = p - tlb_handler; 1237 #else /* CONFIG_64BIT */ 1238 f = final_handler + 32; 1239 if ((p - tlb_handler) <= 32) { 1240 /* Just copy the handler. */ 1241 copy_handler(relocs, labels, tlb_handler, p, f); 1242 final_len = p - tlb_handler; 1243 } else { 1244 u32 *split = tlb_handler + 30; 1245 1246 /* 1247 * Find the split point. 1248 */ 1249 if (insn_has_bdelay(relocs, split - 1)) 1250 split--; 1251 1252 /* Copy first part of the handler. */ 1253 copy_handler(relocs, labels, tlb_handler, split, f); 1254 f += split - tlb_handler; 1255 1256 /* Insert branch. */ 1257 l_split(&l, final_handler); 1258 il_b(&f, &r, label_split); 1259 if (insn_has_bdelay(relocs, split)) 1260 i_nop(&f); 1261 else { 1262 copy_handler(relocs, labels, split, split + 1, f); 1263 move_labels(labels, f, f + 1, -1); 1264 f++; 1265 split++; 1266 } 1267 1268 /* Copy the rest of the handler. */ 1269 copy_handler(relocs, labels, split, p, final_handler); 1270 final_len = (f - (final_handler + 32)) + (p - split); 1271 } 1272 #endif /* CONFIG_64BIT */ 1273 1274 resolve_relocs(relocs, labels); 1275 printk("Synthesized TLB refill handler (%u instructions).\n", 1276 final_len); 1277 1278 #ifdef DEBUG_TLB 1279 { 1280 int i; 1281 1282 f = final_handler; 1283 #ifdef CONFIG_64BIT 1284 if (final_len > 32) 1285 final_len = 64; 1286 else 1287 f = final_handler + 32; 1288 #endif /* CONFIG_64BIT */ 1289 for (i = 0; i < final_len; i++) 1290 printk("%08x\n", f[i]); 1291 } 1292 #endif 1293 1294 memcpy((void *)ebase, final_handler, 0x100); 1295 } 1296 1297 /* 1298 * TLB load/store/modify handlers. 1299 * 1300 * Only the fastpath gets synthesized at runtime, the slowpath for 1301 * do_page_fault remains normal asm. 1302 */ 1303 extern void tlb_do_page_fault_0(void); 1304 extern void tlb_do_page_fault_1(void); 1305 1306 #define __tlb_handler_align \ 1307 __attribute__((__aligned__(1 << CONFIG_MIPS_L1_CACHE_SHIFT))) 1308 1309 /* 1310 * 128 instructions for the fastpath handler is generous and should 1311 * never be exceeded. 1312 */ 1313 #define FASTPATH_SIZE 128 1314 1315 u32 __tlb_handler_align handle_tlbl[FASTPATH_SIZE]; 1316 u32 __tlb_handler_align handle_tlbs[FASTPATH_SIZE]; 1317 u32 __tlb_handler_align handle_tlbm[FASTPATH_SIZE]; 1318 1319 static void __init 1320 iPTE_LW(u32 **p, struct label **l, unsigned int pte, unsigned int ptr) 1321 { 1322 #ifdef CONFIG_SMP 1323 # ifdef CONFIG_64BIT_PHYS_ADDR 1324 if (cpu_has_64bits) 1325 i_lld(p, pte, 0, ptr); 1326 else 1327 # endif 1328 i_LL(p, pte, 0, ptr); 1329 #else 1330 # ifdef CONFIG_64BIT_PHYS_ADDR 1331 if (cpu_has_64bits) 1332 i_ld(p, pte, 0, ptr); 1333 else 1334 # endif 1335 i_LW(p, pte, 0, ptr); 1336 #endif 1337 } 1338 1339 static void __init 1340 iPTE_SW(u32 **p, struct reloc **r, unsigned int pte, unsigned int ptr, 1341 unsigned int mode) 1342 { 1343 #ifdef CONFIG_64BIT_PHYS_ADDR 1344 unsigned int hwmode = mode & (_PAGE_VALID | _PAGE_DIRTY); 1345 #endif 1346 1347 i_ori(p, pte, pte, mode); 1348 #ifdef CONFIG_SMP 1349 # ifdef CONFIG_64BIT_PHYS_ADDR 1350 if (cpu_has_64bits) 1351 i_scd(p, pte, 0, ptr); 1352 else 1353 # endif 1354 i_SC(p, pte, 0, ptr); 1355 1356 if (r10000_llsc_war()) 1357 il_beqzl(p, r, pte, label_smp_pgtable_change); 1358 else 1359 il_beqz(p, r, pte, label_smp_pgtable_change); 1360 1361 # ifdef CONFIG_64BIT_PHYS_ADDR 1362 if (!cpu_has_64bits) { 1363 /* no i_nop needed */ 1364 i_ll(p, pte, sizeof(pte_t) / 2, ptr); 1365 i_ori(p, pte, pte, hwmode); 1366 i_sc(p, pte, sizeof(pte_t) / 2, ptr); 1367 il_beqz(p, r, pte, label_smp_pgtable_change); 1368 /* no i_nop needed */ 1369 i_lw(p, pte, 0, ptr); 1370 } else 1371 i_nop(p); 1372 # else 1373 i_nop(p); 1374 # endif 1375 #else 1376 # ifdef CONFIG_64BIT_PHYS_ADDR 1377 if (cpu_has_64bits) 1378 i_sd(p, pte, 0, ptr); 1379 else 1380 # endif 1381 i_SW(p, pte, 0, ptr); 1382 1383 # ifdef CONFIG_64BIT_PHYS_ADDR 1384 if (!cpu_has_64bits) { 1385 i_lw(p, pte, sizeof(pte_t) / 2, ptr); 1386 i_ori(p, pte, pte, hwmode); 1387 i_sw(p, pte, sizeof(pte_t) / 2, ptr); 1388 i_lw(p, pte, 0, ptr); 1389 } 1390 # endif 1391 #endif 1392 } 1393 1394 /* 1395 * Check if PTE is present, if not then jump to LABEL. PTR points to 1396 * the page table where this PTE is located, PTE will be re-loaded 1397 * with it's original value. 1398 */ 1399 static void __init 1400 build_pte_present(u32 **p, struct label **l, struct reloc **r, 1401 unsigned int pte, unsigned int ptr, enum label_id lid) 1402 { 1403 i_andi(p, pte, pte, _PAGE_PRESENT | _PAGE_READ); 1404 i_xori(p, pte, pte, _PAGE_PRESENT | _PAGE_READ); 1405 il_bnez(p, r, pte, lid); 1406 iPTE_LW(p, l, pte, ptr); 1407 } 1408 1409 /* Make PTE valid, store result in PTR. */ 1410 static void __init 1411 build_make_valid(u32 **p, struct reloc **r, unsigned int pte, 1412 unsigned int ptr) 1413 { 1414 unsigned int mode = _PAGE_VALID | _PAGE_ACCESSED; 1415 1416 iPTE_SW(p, r, pte, ptr, mode); 1417 } 1418 1419 /* 1420 * Check if PTE can be written to, if not branch to LABEL. Regardless 1421 * restore PTE with value from PTR when done. 1422 */ 1423 static void __init 1424 build_pte_writable(u32 **p, struct label **l, struct reloc **r, 1425 unsigned int pte, unsigned int ptr, enum label_id lid) 1426 { 1427 i_andi(p, pte, pte, _PAGE_PRESENT | _PAGE_WRITE); 1428 i_xori(p, pte, pte, _PAGE_PRESENT | _PAGE_WRITE); 1429 il_bnez(p, r, pte, lid); 1430 iPTE_LW(p, l, pte, ptr); 1431 } 1432 1433 /* Make PTE writable, update software status bits as well, then store 1434 * at PTR. 1435 */ 1436 static void __init 1437 build_make_write(u32 **p, struct reloc **r, unsigned int pte, 1438 unsigned int ptr) 1439 { 1440 unsigned int mode = (_PAGE_ACCESSED | _PAGE_MODIFIED | _PAGE_VALID 1441 | _PAGE_DIRTY); 1442 1443 iPTE_SW(p, r, pte, ptr, mode); 1444 } 1445 1446 /* 1447 * Check if PTE can be modified, if not branch to LABEL. Regardless 1448 * restore PTE with value from PTR when done. 1449 */ 1450 static void __init 1451 build_pte_modifiable(u32 **p, struct label **l, struct reloc **r, 1452 unsigned int pte, unsigned int ptr, enum label_id lid) 1453 { 1454 i_andi(p, pte, pte, _PAGE_WRITE); 1455 il_beqz(p, r, pte, lid); 1456 iPTE_LW(p, l, pte, ptr); 1457 } 1458 1459 /* 1460 * R3000 style TLB load/store/modify handlers. 1461 */ 1462 1463 /* 1464 * This places the pte into ENTRYLO0 and writes it with tlbwi. 1465 * Then it returns. 1466 */ 1467 static void __init 1468 build_r3000_pte_reload_tlbwi(u32 **p, unsigned int pte, unsigned int tmp) 1469 { 1470 i_mtc0(p, pte, C0_ENTRYLO0); /* cp0 delay */ 1471 i_mfc0(p, tmp, C0_EPC); /* cp0 delay */ 1472 i_tlbwi(p); 1473 i_jr(p, tmp); 1474 i_rfe(p); /* branch delay */ 1475 } 1476 1477 /* 1478 * This places the pte into ENTRYLO0 and writes it with tlbwi 1479 * or tlbwr as appropriate. This is because the index register 1480 * may have the probe fail bit set as a result of a trap on a 1481 * kseg2 access, i.e. without refill. Then it returns. 1482 */ 1483 static void __init 1484 build_r3000_tlb_reload_write(u32 **p, struct label **l, struct reloc **r, 1485 unsigned int pte, unsigned int tmp) 1486 { 1487 i_mfc0(p, tmp, C0_INDEX); 1488 i_mtc0(p, pte, C0_ENTRYLO0); /* cp0 delay */ 1489 il_bltz(p, r, tmp, label_r3000_write_probe_fail); /* cp0 delay */ 1490 i_mfc0(p, tmp, C0_EPC); /* branch delay */ 1491 i_tlbwi(p); /* cp0 delay */ 1492 i_jr(p, tmp); 1493 i_rfe(p); /* branch delay */ 1494 l_r3000_write_probe_fail(l, *p); 1495 i_tlbwr(p); /* cp0 delay */ 1496 i_jr(p, tmp); 1497 i_rfe(p); /* branch delay */ 1498 } 1499 1500 static void __init 1501 build_r3000_tlbchange_handler_head(u32 **p, unsigned int pte, 1502 unsigned int ptr) 1503 { 1504 long pgdc = (long)pgd_current; 1505 1506 i_mfc0(p, pte, C0_BADVADDR); 1507 i_lui(p, ptr, rel_hi(pgdc)); /* cp0 delay */ 1508 i_lw(p, ptr, rel_lo(pgdc), ptr); 1509 i_srl(p, pte, pte, 22); /* load delay */ 1510 i_sll(p, pte, pte, 2); 1511 i_addu(p, ptr, ptr, pte); 1512 i_mfc0(p, pte, C0_CONTEXT); 1513 i_lw(p, ptr, 0, ptr); /* cp0 delay */ 1514 i_andi(p, pte, pte, 0xffc); /* load delay */ 1515 i_addu(p, ptr, ptr, pte); 1516 i_lw(p, pte, 0, ptr); 1517 i_tlbp(p); /* load delay */ 1518 } 1519 1520 static void __init build_r3000_tlb_load_handler(void) 1521 { 1522 u32 *p = handle_tlbl; 1523 struct label *l = labels; 1524 struct reloc *r = relocs; 1525 1526 memset(handle_tlbl, 0, sizeof(handle_tlbl)); 1527 memset(labels, 0, sizeof(labels)); 1528 memset(relocs, 0, sizeof(relocs)); 1529 1530 build_r3000_tlbchange_handler_head(&p, K0, K1); 1531 build_pte_present(&p, &l, &r, K0, K1, label_nopage_tlbl); 1532 i_nop(&p); /* load delay */ 1533 build_make_valid(&p, &r, K0, K1); 1534 build_r3000_tlb_reload_write(&p, &l, &r, K0, K1); 1535 1536 l_nopage_tlbl(&l, p); 1537 i_j(&p, (unsigned long)tlb_do_page_fault_0 & 0x0fffffff); 1538 i_nop(&p); 1539 1540 if ((p - handle_tlbl) > FASTPATH_SIZE) 1541 panic("TLB load handler fastpath space exceeded"); 1542 1543 resolve_relocs(relocs, labels); 1544 printk("Synthesized TLB load handler fastpath (%u instructions).\n", 1545 (unsigned int)(p - handle_tlbl)); 1546 1547 #ifdef DEBUG_TLB 1548 { 1549 int i; 1550 1551 for (i = 0; i < (p - handle_tlbl); i++) 1552 printk("%08x\n", handle_tlbl[i]); 1553 } 1554 #endif 1555 } 1556 1557 static void __init build_r3000_tlb_store_handler(void) 1558 { 1559 u32 *p = handle_tlbs; 1560 struct label *l = labels; 1561 struct reloc *r = relocs; 1562 1563 memset(handle_tlbs, 0, sizeof(handle_tlbs)); 1564 memset(labels, 0, sizeof(labels)); 1565 memset(relocs, 0, sizeof(relocs)); 1566 1567 build_r3000_tlbchange_handler_head(&p, K0, K1); 1568 build_pte_writable(&p, &l, &r, K0, K1, label_nopage_tlbs); 1569 i_nop(&p); /* load delay */ 1570 build_make_write(&p, &r, K0, K1); 1571 build_r3000_tlb_reload_write(&p, &l, &r, K0, K1); 1572 1573 l_nopage_tlbs(&l, p); 1574 i_j(&p, (unsigned long)tlb_do_page_fault_1 & 0x0fffffff); 1575 i_nop(&p); 1576 1577 if ((p - handle_tlbs) > FASTPATH_SIZE) 1578 panic("TLB store handler fastpath space exceeded"); 1579 1580 resolve_relocs(relocs, labels); 1581 printk("Synthesized TLB store handler fastpath (%u instructions).\n", 1582 (unsigned int)(p - handle_tlbs)); 1583 1584 #ifdef DEBUG_TLB 1585 { 1586 int i; 1587 1588 for (i = 0; i < (p - handle_tlbs); i++) 1589 printk("%08x\n", handle_tlbs[i]); 1590 } 1591 #endif 1592 } 1593 1594 static void __init build_r3000_tlb_modify_handler(void) 1595 { 1596 u32 *p = handle_tlbm; 1597 struct label *l = labels; 1598 struct reloc *r = relocs; 1599 1600 memset(handle_tlbm, 0, sizeof(handle_tlbm)); 1601 memset(labels, 0, sizeof(labels)); 1602 memset(relocs, 0, sizeof(relocs)); 1603 1604 build_r3000_tlbchange_handler_head(&p, K0, K1); 1605 build_pte_modifiable(&p, &l, &r, K0, K1, label_nopage_tlbm); 1606 i_nop(&p); /* load delay */ 1607 build_make_write(&p, &r, K0, K1); 1608 build_r3000_pte_reload_tlbwi(&p, K0, K1); 1609 1610 l_nopage_tlbm(&l, p); 1611 i_j(&p, (unsigned long)tlb_do_page_fault_1 & 0x0fffffff); 1612 i_nop(&p); 1613 1614 if ((p - handle_tlbm) > FASTPATH_SIZE) 1615 panic("TLB modify handler fastpath space exceeded"); 1616 1617 resolve_relocs(relocs, labels); 1618 printk("Synthesized TLB modify handler fastpath (%u instructions).\n", 1619 (unsigned int)(p - handle_tlbm)); 1620 1621 #ifdef DEBUG_TLB 1622 { 1623 int i; 1624 1625 for (i = 0; i < (p - handle_tlbm); i++) 1626 printk("%08x\n", handle_tlbm[i]); 1627 } 1628 #endif 1629 } 1630 1631 /* 1632 * R4000 style TLB load/store/modify handlers. 1633 */ 1634 static void __init 1635 build_r4000_tlbchange_handler_head(u32 **p, struct label **l, 1636 struct reloc **r, unsigned int pte, 1637 unsigned int ptr) 1638 { 1639 #ifdef CONFIG_64BIT 1640 build_get_pmde64(p, l, r, pte, ptr); /* get pmd in ptr */ 1641 #else 1642 build_get_pgde32(p, pte, ptr); /* get pgd in ptr */ 1643 #endif 1644 1645 i_MFC0(p, pte, C0_BADVADDR); 1646 i_LW(p, ptr, 0, ptr); 1647 i_SRL(p, pte, pte, PAGE_SHIFT + PTE_ORDER - PTE_T_LOG2); 1648 i_andi(p, pte, pte, (PTRS_PER_PTE - 1) << PTE_T_LOG2); 1649 i_ADDU(p, ptr, ptr, pte); 1650 1651 #ifdef CONFIG_SMP 1652 l_smp_pgtable_change(l, *p); 1653 # endif 1654 iPTE_LW(p, l, pte, ptr); /* get even pte */ 1655 build_tlb_probe_entry(p); 1656 } 1657 1658 static void __init 1659 build_r4000_tlbchange_handler_tail(u32 **p, struct label **l, 1660 struct reloc **r, unsigned int tmp, 1661 unsigned int ptr) 1662 { 1663 i_ori(p, ptr, ptr, sizeof(pte_t)); 1664 i_xori(p, ptr, ptr, sizeof(pte_t)); 1665 build_update_entries(p, tmp, ptr); 1666 build_tlb_write_entry(p, l, r, tlb_indexed); 1667 l_leave(l, *p); 1668 i_eret(p); /* return from trap */ 1669 1670 #ifdef CONFIG_64BIT 1671 build_get_pgd_vmalloc64(p, l, r, tmp, ptr); 1672 #endif 1673 } 1674 1675 static void __init build_r4000_tlb_load_handler(void) 1676 { 1677 u32 *p = handle_tlbl; 1678 struct label *l = labels; 1679 struct reloc *r = relocs; 1680 1681 memset(handle_tlbl, 0, sizeof(handle_tlbl)); 1682 memset(labels, 0, sizeof(labels)); 1683 memset(relocs, 0, sizeof(relocs)); 1684 1685 if (bcm1250_m3_war()) { 1686 i_MFC0(&p, K0, C0_BADVADDR); 1687 i_MFC0(&p, K1, C0_ENTRYHI); 1688 i_xor(&p, K0, K0, K1); 1689 i_SRL(&p, K0, K0, PAGE_SHIFT + 1); 1690 il_bnez(&p, &r, K0, label_leave); 1691 /* No need for i_nop */ 1692 } 1693 1694 build_r4000_tlbchange_handler_head(&p, &l, &r, K0, K1); 1695 build_pte_present(&p, &l, &r, K0, K1, label_nopage_tlbl); 1696 build_make_valid(&p, &r, K0, K1); 1697 build_r4000_tlbchange_handler_tail(&p, &l, &r, K0, K1); 1698 1699 l_nopage_tlbl(&l, p); 1700 i_j(&p, (unsigned long)tlb_do_page_fault_0 & 0x0fffffff); 1701 i_nop(&p); 1702 1703 if ((p - handle_tlbl) > FASTPATH_SIZE) 1704 panic("TLB load handler fastpath space exceeded"); 1705 1706 resolve_relocs(relocs, labels); 1707 printk("Synthesized TLB load handler fastpath (%u instructions).\n", 1708 (unsigned int)(p - handle_tlbl)); 1709 1710 #ifdef DEBUG_TLB 1711 { 1712 int i; 1713 1714 for (i = 0; i < (p - handle_tlbl); i++) 1715 printk("%08x\n", handle_tlbl[i]); 1716 } 1717 #endif 1718 } 1719 1720 static void __init build_r4000_tlb_store_handler(void) 1721 { 1722 u32 *p = handle_tlbs; 1723 struct label *l = labels; 1724 struct reloc *r = relocs; 1725 1726 memset(handle_tlbs, 0, sizeof(handle_tlbs)); 1727 memset(labels, 0, sizeof(labels)); 1728 memset(relocs, 0, sizeof(relocs)); 1729 1730 build_r4000_tlbchange_handler_head(&p, &l, &r, K0, K1); 1731 build_pte_writable(&p, &l, &r, K0, K1, label_nopage_tlbs); 1732 build_make_write(&p, &r, K0, K1); 1733 build_r4000_tlbchange_handler_tail(&p, &l, &r, K0, K1); 1734 1735 l_nopage_tlbs(&l, p); 1736 i_j(&p, (unsigned long)tlb_do_page_fault_1 & 0x0fffffff); 1737 i_nop(&p); 1738 1739 if ((p - handle_tlbs) > FASTPATH_SIZE) 1740 panic("TLB store handler fastpath space exceeded"); 1741 1742 resolve_relocs(relocs, labels); 1743 printk("Synthesized TLB store handler fastpath (%u instructions).\n", 1744 (unsigned int)(p - handle_tlbs)); 1745 1746 #ifdef DEBUG_TLB 1747 { 1748 int i; 1749 1750 for (i = 0; i < (p - handle_tlbs); i++) 1751 printk("%08x\n", handle_tlbs[i]); 1752 } 1753 #endif 1754 } 1755 1756 static void __init build_r4000_tlb_modify_handler(void) 1757 { 1758 u32 *p = handle_tlbm; 1759 struct label *l = labels; 1760 struct reloc *r = relocs; 1761 1762 memset(handle_tlbm, 0, sizeof(handle_tlbm)); 1763 memset(labels, 0, sizeof(labels)); 1764 memset(relocs, 0, sizeof(relocs)); 1765 1766 build_r4000_tlbchange_handler_head(&p, &l, &r, K0, K1); 1767 build_pte_modifiable(&p, &l, &r, K0, K1, label_nopage_tlbm); 1768 /* Present and writable bits set, set accessed and dirty bits. */ 1769 build_make_write(&p, &r, K0, K1); 1770 build_r4000_tlbchange_handler_tail(&p, &l, &r, K0, K1); 1771 1772 l_nopage_tlbm(&l, p); 1773 i_j(&p, (unsigned long)tlb_do_page_fault_1 & 0x0fffffff); 1774 i_nop(&p); 1775 1776 if ((p - handle_tlbm) > FASTPATH_SIZE) 1777 panic("TLB modify handler fastpath space exceeded"); 1778 1779 resolve_relocs(relocs, labels); 1780 printk("Synthesized TLB modify handler fastpath (%u instructions).\n", 1781 (unsigned int)(p - handle_tlbm)); 1782 1783 #ifdef DEBUG_TLB 1784 { 1785 int i; 1786 1787 for (i = 0; i < (p - handle_tlbm); i++) 1788 printk("%08x\n", handle_tlbm[i]); 1789 } 1790 #endif 1791 } 1792 1793 void __init build_tlb_refill_handler(void) 1794 { 1795 /* 1796 * The refill handler is generated per-CPU, multi-node systems 1797 * may have local storage for it. The other handlers are only 1798 * needed once. 1799 */ 1800 static int run_once = 0; 1801 1802 switch (current_cpu_data.cputype) { 1803 case CPU_R2000: 1804 case CPU_R3000: 1805 case CPU_R3000A: 1806 case CPU_R3081E: 1807 case CPU_TX3912: 1808 case CPU_TX3922: 1809 case CPU_TX3927: 1810 build_r3000_tlb_refill_handler(); 1811 if (!run_once) { 1812 build_r3000_tlb_load_handler(); 1813 build_r3000_tlb_store_handler(); 1814 build_r3000_tlb_modify_handler(); 1815 run_once++; 1816 } 1817 break; 1818 1819 case CPU_R6000: 1820 case CPU_R6000A: 1821 panic("No R6000 TLB refill handler yet"); 1822 break; 1823 1824 case CPU_R8000: 1825 panic("No R8000 TLB refill handler yet"); 1826 break; 1827 1828 default: 1829 build_r4000_tlb_refill_handler(); 1830 if (!run_once) { 1831 build_r4000_tlb_load_handler(); 1832 build_r4000_tlb_store_handler(); 1833 build_r4000_tlb_modify_handler(); 1834 run_once++; 1835 } 1836 } 1837 } 1838 1839 void __init flush_tlb_handlers(void) 1840 { 1841 flush_icache_range((unsigned long)handle_tlbl, 1842 (unsigned long)handle_tlbl + sizeof(handle_tlbl)); 1843 flush_icache_range((unsigned long)handle_tlbs, 1844 (unsigned long)handle_tlbs + sizeof(handle_tlbs)); 1845 flush_icache_range((unsigned long)handle_tlbm, 1846 (unsigned long)handle_tlbm + sizeof(handle_tlbm)); 1847 } 1848