1 /* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * Synthesize TLB refill handlers at runtime. 7 * 8 * Copyright (C) 2004, 2005, 2006, 2008 Thiemo Seufer 9 * Copyright (C) 2005, 2007 Maciej W. Rozycki 10 * Copyright (C) 2006 Ralf Baechle (ralf@linux-mips.org) 11 * 12 * ... and the days got worse and worse and now you see 13 * I've gone completly out of my mind. 14 * 15 * They're coming to take me a away haha 16 * they're coming to take me a away hoho hihi haha 17 * to the funny farm where code is beautiful all the time ... 18 * 19 * (Condolences to Napoleon XIV) 20 */ 21 22 #include <linux/kernel.h> 23 #include <linux/types.h> 24 #include <linux/string.h> 25 #include <linux/init.h> 26 27 #include <asm/mmu_context.h> 28 #include <asm/war.h> 29 30 #include "uasm.h" 31 32 static inline int r45k_bvahwbug(void) 33 { 34 /* XXX: We should probe for the presence of this bug, but we don't. */ 35 return 0; 36 } 37 38 static inline int r4k_250MHZhwbug(void) 39 { 40 /* XXX: We should probe for the presence of this bug, but we don't. */ 41 return 0; 42 } 43 44 static inline int __maybe_unused bcm1250_m3_war(void) 45 { 46 return BCM1250_M3_WAR; 47 } 48 49 static inline int __maybe_unused r10000_llsc_war(void) 50 { 51 return R10000_LLSC_WAR; 52 } 53 54 /* 55 * Found by experiment: At least some revisions of the 4kc throw under 56 * some circumstances a machine check exception, triggered by invalid 57 * values in the index register. Delaying the tlbp instruction until 58 * after the next branch, plus adding an additional nop in front of 59 * tlbwi/tlbwr avoids the invalid index register values. Nobody knows 60 * why; it's not an issue caused by the core RTL. 61 * 62 */ 63 static int __cpuinit m4kc_tlbp_war(void) 64 { 65 return (current_cpu_data.processor_id & 0xffff00) == 66 (PRID_COMP_MIPS | PRID_IMP_4KC); 67 } 68 69 /* Handle labels (which must be positive integers). */ 70 enum label_id { 71 label_second_part = 1, 72 label_leave, 73 #ifdef MODULE_START 74 label_module_alloc, 75 #endif 76 label_vmalloc, 77 label_vmalloc_done, 78 label_tlbw_hazard, 79 label_split, 80 label_nopage_tlbl, 81 label_nopage_tlbs, 82 label_nopage_tlbm, 83 label_smp_pgtable_change, 84 label_r3000_write_probe_fail, 85 }; 86 87 UASM_L_LA(_second_part) 88 UASM_L_LA(_leave) 89 #ifdef MODULE_START 90 UASM_L_LA(_module_alloc) 91 #endif 92 UASM_L_LA(_vmalloc) 93 UASM_L_LA(_vmalloc_done) 94 UASM_L_LA(_tlbw_hazard) 95 UASM_L_LA(_split) 96 UASM_L_LA(_nopage_tlbl) 97 UASM_L_LA(_nopage_tlbs) 98 UASM_L_LA(_nopage_tlbm) 99 UASM_L_LA(_smp_pgtable_change) 100 UASM_L_LA(_r3000_write_probe_fail) 101 102 /* 103 * For debug purposes. 104 */ 105 static inline void dump_handler(const u32 *handler, int count) 106 { 107 int i; 108 109 pr_debug("\t.set push\n"); 110 pr_debug("\t.set noreorder\n"); 111 112 for (i = 0; i < count; i++) 113 pr_debug("\t%p\t.word 0x%08x\n", &handler[i], handler[i]); 114 115 pr_debug("\t.set pop\n"); 116 } 117 118 /* The only general purpose registers allowed in TLB handlers. */ 119 #define K0 26 120 #define K1 27 121 122 /* Some CP0 registers */ 123 #define C0_INDEX 0, 0 124 #define C0_ENTRYLO0 2, 0 125 #define C0_TCBIND 2, 2 126 #define C0_ENTRYLO1 3, 0 127 #define C0_CONTEXT 4, 0 128 #define C0_BADVADDR 8, 0 129 #define C0_ENTRYHI 10, 0 130 #define C0_EPC 14, 0 131 #define C0_XCONTEXT 20, 0 132 133 #ifdef CONFIG_64BIT 134 # define GET_CONTEXT(buf, reg) UASM_i_MFC0(buf, reg, C0_XCONTEXT) 135 #else 136 # define GET_CONTEXT(buf, reg) UASM_i_MFC0(buf, reg, C0_CONTEXT) 137 #endif 138 139 /* The worst case length of the handler is around 18 instructions for 140 * R3000-style TLBs and up to 63 instructions for R4000-style TLBs. 141 * Maximum space available is 32 instructions for R3000 and 64 142 * instructions for R4000. 143 * 144 * We deliberately chose a buffer size of 128, so we won't scribble 145 * over anything important on overflow before we panic. 146 */ 147 static u32 tlb_handler[128] __cpuinitdata; 148 149 /* simply assume worst case size for labels and relocs */ 150 static struct uasm_label labels[128] __cpuinitdata; 151 static struct uasm_reloc relocs[128] __cpuinitdata; 152 153 /* 154 * The R3000 TLB handler is simple. 155 */ 156 static void __cpuinit build_r3000_tlb_refill_handler(void) 157 { 158 long pgdc = (long)pgd_current; 159 u32 *p; 160 161 memset(tlb_handler, 0, sizeof(tlb_handler)); 162 p = tlb_handler; 163 164 uasm_i_mfc0(&p, K0, C0_BADVADDR); 165 uasm_i_lui(&p, K1, uasm_rel_hi(pgdc)); /* cp0 delay */ 166 uasm_i_lw(&p, K1, uasm_rel_lo(pgdc), K1); 167 uasm_i_srl(&p, K0, K0, 22); /* load delay */ 168 uasm_i_sll(&p, K0, K0, 2); 169 uasm_i_addu(&p, K1, K1, K0); 170 uasm_i_mfc0(&p, K0, C0_CONTEXT); 171 uasm_i_lw(&p, K1, 0, K1); /* cp0 delay */ 172 uasm_i_andi(&p, K0, K0, 0xffc); /* load delay */ 173 uasm_i_addu(&p, K1, K1, K0); 174 uasm_i_lw(&p, K0, 0, K1); 175 uasm_i_nop(&p); /* load delay */ 176 uasm_i_mtc0(&p, K0, C0_ENTRYLO0); 177 uasm_i_mfc0(&p, K1, C0_EPC); /* cp0 delay */ 178 uasm_i_tlbwr(&p); /* cp0 delay */ 179 uasm_i_jr(&p, K1); 180 uasm_i_rfe(&p); /* branch delay */ 181 182 if (p > tlb_handler + 32) 183 panic("TLB refill handler space exceeded"); 184 185 pr_debug("Wrote TLB refill handler (%u instructions).\n", 186 (unsigned int)(p - tlb_handler)); 187 188 memcpy((void *)ebase, tlb_handler, 0x80); 189 190 dump_handler((u32 *)ebase, 32); 191 } 192 193 /* 194 * The R4000 TLB handler is much more complicated. We have two 195 * consecutive handler areas with 32 instructions space each. 196 * Since they aren't used at the same time, we can overflow in the 197 * other one.To keep things simple, we first assume linear space, 198 * then we relocate it to the final handler layout as needed. 199 */ 200 static u32 final_handler[64] __cpuinitdata; 201 202 /* 203 * Hazards 204 * 205 * From the IDT errata for the QED RM5230 (Nevada), processor revision 1.0: 206 * 2. A timing hazard exists for the TLBP instruction. 207 * 208 * stalling_instruction 209 * TLBP 210 * 211 * The JTLB is being read for the TLBP throughout the stall generated by the 212 * previous instruction. This is not really correct as the stalling instruction 213 * can modify the address used to access the JTLB. The failure symptom is that 214 * the TLBP instruction will use an address created for the stalling instruction 215 * and not the address held in C0_ENHI and thus report the wrong results. 216 * 217 * The software work-around is to not allow the instruction preceding the TLBP 218 * to stall - make it an NOP or some other instruction guaranteed not to stall. 219 * 220 * Errata 2 will not be fixed. This errata is also on the R5000. 221 * 222 * As if we MIPS hackers wouldn't know how to nop pipelines happy ... 223 */ 224 static void __cpuinit __maybe_unused build_tlb_probe_entry(u32 **p) 225 { 226 switch (current_cpu_type()) { 227 /* Found by experiment: R4600 v2.0/R4700 needs this, too. */ 228 case CPU_R4600: 229 case CPU_R4700: 230 case CPU_R5000: 231 case CPU_R5000A: 232 case CPU_NEVADA: 233 uasm_i_nop(p); 234 uasm_i_tlbp(p); 235 break; 236 237 default: 238 uasm_i_tlbp(p); 239 break; 240 } 241 } 242 243 /* 244 * Write random or indexed TLB entry, and care about the hazards from 245 * the preceeding mtc0 and for the following eret. 246 */ 247 enum tlb_write_entry { tlb_random, tlb_indexed }; 248 249 static void __cpuinit build_tlb_write_entry(u32 **p, struct uasm_label **l, 250 struct uasm_reloc **r, 251 enum tlb_write_entry wmode) 252 { 253 void(*tlbw)(u32 **) = NULL; 254 255 switch (wmode) { 256 case tlb_random: tlbw = uasm_i_tlbwr; break; 257 case tlb_indexed: tlbw = uasm_i_tlbwi; break; 258 } 259 260 if (cpu_has_mips_r2) { 261 uasm_i_ehb(p); 262 tlbw(p); 263 return; 264 } 265 266 switch (current_cpu_type()) { 267 case CPU_R4000PC: 268 case CPU_R4000SC: 269 case CPU_R4000MC: 270 case CPU_R4400PC: 271 case CPU_R4400SC: 272 case CPU_R4400MC: 273 /* 274 * This branch uses up a mtc0 hazard nop slot and saves 275 * two nops after the tlbw instruction. 276 */ 277 uasm_il_bgezl(p, r, 0, label_tlbw_hazard); 278 tlbw(p); 279 uasm_l_tlbw_hazard(l, *p); 280 uasm_i_nop(p); 281 break; 282 283 case CPU_R4600: 284 case CPU_R4700: 285 case CPU_R5000: 286 case CPU_R5000A: 287 uasm_i_nop(p); 288 tlbw(p); 289 uasm_i_nop(p); 290 break; 291 292 case CPU_R4300: 293 case CPU_5KC: 294 case CPU_TX49XX: 295 case CPU_AU1000: 296 case CPU_AU1100: 297 case CPU_AU1500: 298 case CPU_AU1550: 299 case CPU_AU1200: 300 case CPU_AU1210: 301 case CPU_AU1250: 302 case CPU_PR4450: 303 uasm_i_nop(p); 304 tlbw(p); 305 break; 306 307 case CPU_R10000: 308 case CPU_R12000: 309 case CPU_R14000: 310 case CPU_4KC: 311 case CPU_4KEC: 312 case CPU_SB1: 313 case CPU_SB1A: 314 case CPU_4KSC: 315 case CPU_20KC: 316 case CPU_25KF: 317 case CPU_BCM3302: 318 case CPU_BCM4710: 319 case CPU_LOONGSON2: 320 case CPU_CAVIUM_OCTEON: 321 case CPU_R5500: 322 if (m4kc_tlbp_war()) 323 uasm_i_nop(p); 324 tlbw(p); 325 break; 326 327 case CPU_NEVADA: 328 uasm_i_nop(p); /* QED specifies 2 nops hazard */ 329 /* 330 * This branch uses up a mtc0 hazard nop slot and saves 331 * a nop after the tlbw instruction. 332 */ 333 uasm_il_bgezl(p, r, 0, label_tlbw_hazard); 334 tlbw(p); 335 uasm_l_tlbw_hazard(l, *p); 336 break; 337 338 case CPU_RM7000: 339 uasm_i_nop(p); 340 uasm_i_nop(p); 341 uasm_i_nop(p); 342 uasm_i_nop(p); 343 tlbw(p); 344 break; 345 346 case CPU_RM9000: 347 /* 348 * When the JTLB is updated by tlbwi or tlbwr, a subsequent 349 * use of the JTLB for instructions should not occur for 4 350 * cpu cycles and use for data translations should not occur 351 * for 3 cpu cycles. 352 */ 353 uasm_i_ssnop(p); 354 uasm_i_ssnop(p); 355 uasm_i_ssnop(p); 356 uasm_i_ssnop(p); 357 tlbw(p); 358 uasm_i_ssnop(p); 359 uasm_i_ssnop(p); 360 uasm_i_ssnop(p); 361 uasm_i_ssnop(p); 362 break; 363 364 case CPU_VR4111: 365 case CPU_VR4121: 366 case CPU_VR4122: 367 case CPU_VR4181: 368 case CPU_VR4181A: 369 uasm_i_nop(p); 370 uasm_i_nop(p); 371 tlbw(p); 372 uasm_i_nop(p); 373 uasm_i_nop(p); 374 break; 375 376 case CPU_VR4131: 377 case CPU_VR4133: 378 case CPU_R5432: 379 uasm_i_nop(p); 380 uasm_i_nop(p); 381 tlbw(p); 382 break; 383 384 default: 385 panic("No TLB refill handler yet (CPU type: %d)", 386 current_cpu_data.cputype); 387 break; 388 } 389 } 390 391 #ifdef CONFIG_64BIT 392 /* 393 * TMP and PTR are scratch. 394 * TMP will be clobbered, PTR will hold the pmd entry. 395 */ 396 static void __cpuinit 397 build_get_pmde64(u32 **p, struct uasm_label **l, struct uasm_reloc **r, 398 unsigned int tmp, unsigned int ptr) 399 { 400 long pgdc = (long)pgd_current; 401 402 /* 403 * The vmalloc handling is not in the hotpath. 404 */ 405 uasm_i_dmfc0(p, tmp, C0_BADVADDR); 406 #ifdef MODULE_START 407 uasm_il_bltz(p, r, tmp, label_module_alloc); 408 #else 409 uasm_il_bltz(p, r, tmp, label_vmalloc); 410 #endif 411 /* No uasm_i_nop needed here, since the next insn doesn't touch TMP. */ 412 413 #ifdef CONFIG_SMP 414 # ifdef CONFIG_MIPS_MT_SMTC 415 /* 416 * SMTC uses TCBind value as "CPU" index 417 */ 418 uasm_i_mfc0(p, ptr, C0_TCBIND); 419 uasm_i_dsrl(p, ptr, ptr, 19); 420 # else 421 /* 422 * 64 bit SMP running in XKPHYS has smp_processor_id() << 3 423 * stored in CONTEXT. 424 */ 425 uasm_i_dmfc0(p, ptr, C0_CONTEXT); 426 uasm_i_dsrl(p, ptr, ptr, 23); 427 #endif 428 UASM_i_LA_mostly(p, tmp, pgdc); 429 uasm_i_daddu(p, ptr, ptr, tmp); 430 uasm_i_dmfc0(p, tmp, C0_BADVADDR); 431 uasm_i_ld(p, ptr, uasm_rel_lo(pgdc), ptr); 432 #else 433 UASM_i_LA_mostly(p, ptr, pgdc); 434 uasm_i_ld(p, ptr, uasm_rel_lo(pgdc), ptr); 435 #endif 436 437 uasm_l_vmalloc_done(l, *p); 438 439 if (PGDIR_SHIFT - 3 < 32) /* get pgd offset in bytes */ 440 uasm_i_dsrl(p, tmp, tmp, PGDIR_SHIFT-3); 441 else 442 uasm_i_dsrl32(p, tmp, tmp, PGDIR_SHIFT - 3 - 32); 443 444 uasm_i_andi(p, tmp, tmp, (PTRS_PER_PGD - 1)<<3); 445 uasm_i_daddu(p, ptr, ptr, tmp); /* add in pgd offset */ 446 uasm_i_dmfc0(p, tmp, C0_BADVADDR); /* get faulting address */ 447 uasm_i_ld(p, ptr, 0, ptr); /* get pmd pointer */ 448 uasm_i_dsrl(p, tmp, tmp, PMD_SHIFT-3); /* get pmd offset in bytes */ 449 uasm_i_andi(p, tmp, tmp, (PTRS_PER_PMD - 1)<<3); 450 uasm_i_daddu(p, ptr, ptr, tmp); /* add in pmd offset */ 451 } 452 453 /* 454 * BVADDR is the faulting address, PTR is scratch. 455 * PTR will hold the pgd for vmalloc. 456 */ 457 static void __cpuinit 458 build_get_pgd_vmalloc64(u32 **p, struct uasm_label **l, struct uasm_reloc **r, 459 unsigned int bvaddr, unsigned int ptr) 460 { 461 long swpd = (long)swapper_pg_dir; 462 463 #ifdef MODULE_START 464 long modd = (long)module_pg_dir; 465 466 uasm_l_module_alloc(l, *p); 467 /* 468 * Assumption: 469 * VMALLOC_START >= 0xc000000000000000UL 470 * MODULE_START >= 0xe000000000000000UL 471 */ 472 UASM_i_SLL(p, ptr, bvaddr, 2); 473 uasm_il_bgez(p, r, ptr, label_vmalloc); 474 475 if (uasm_in_compat_space_p(MODULE_START) && 476 !uasm_rel_lo(MODULE_START)) { 477 uasm_i_lui(p, ptr, uasm_rel_hi(MODULE_START)); /* delay slot */ 478 } else { 479 /* unlikely configuration */ 480 uasm_i_nop(p); /* delay slot */ 481 UASM_i_LA(p, ptr, MODULE_START); 482 } 483 uasm_i_dsubu(p, bvaddr, bvaddr, ptr); 484 485 if (uasm_in_compat_space_p(modd) && !uasm_rel_lo(modd)) { 486 uasm_il_b(p, r, label_vmalloc_done); 487 uasm_i_lui(p, ptr, uasm_rel_hi(modd)); 488 } else { 489 UASM_i_LA_mostly(p, ptr, modd); 490 uasm_il_b(p, r, label_vmalloc_done); 491 if (uasm_in_compat_space_p(modd)) 492 uasm_i_addiu(p, ptr, ptr, uasm_rel_lo(modd)); 493 else 494 uasm_i_daddiu(p, ptr, ptr, uasm_rel_lo(modd)); 495 } 496 497 uasm_l_vmalloc(l, *p); 498 if (uasm_in_compat_space_p(MODULE_START) && 499 !uasm_rel_lo(MODULE_START) && 500 MODULE_START << 32 == VMALLOC_START) 501 uasm_i_dsll32(p, ptr, ptr, 0); /* typical case */ 502 else 503 UASM_i_LA(p, ptr, VMALLOC_START); 504 #else 505 uasm_l_vmalloc(l, *p); 506 UASM_i_LA(p, ptr, VMALLOC_START); 507 #endif 508 uasm_i_dsubu(p, bvaddr, bvaddr, ptr); 509 510 if (uasm_in_compat_space_p(swpd) && !uasm_rel_lo(swpd)) { 511 uasm_il_b(p, r, label_vmalloc_done); 512 uasm_i_lui(p, ptr, uasm_rel_hi(swpd)); 513 } else { 514 UASM_i_LA_mostly(p, ptr, swpd); 515 uasm_il_b(p, r, label_vmalloc_done); 516 if (uasm_in_compat_space_p(swpd)) 517 uasm_i_addiu(p, ptr, ptr, uasm_rel_lo(swpd)); 518 else 519 uasm_i_daddiu(p, ptr, ptr, uasm_rel_lo(swpd)); 520 } 521 } 522 523 #else /* !CONFIG_64BIT */ 524 525 /* 526 * TMP and PTR are scratch. 527 * TMP will be clobbered, PTR will hold the pgd entry. 528 */ 529 static void __cpuinit __maybe_unused 530 build_get_pgde32(u32 **p, unsigned int tmp, unsigned int ptr) 531 { 532 long pgdc = (long)pgd_current; 533 534 /* 32 bit SMP has smp_processor_id() stored in CONTEXT. */ 535 #ifdef CONFIG_SMP 536 #ifdef CONFIG_MIPS_MT_SMTC 537 /* 538 * SMTC uses TCBind value as "CPU" index 539 */ 540 uasm_i_mfc0(p, ptr, C0_TCBIND); 541 UASM_i_LA_mostly(p, tmp, pgdc); 542 uasm_i_srl(p, ptr, ptr, 19); 543 #else 544 /* 545 * smp_processor_id() << 3 is stored in CONTEXT. 546 */ 547 uasm_i_mfc0(p, ptr, C0_CONTEXT); 548 UASM_i_LA_mostly(p, tmp, pgdc); 549 uasm_i_srl(p, ptr, ptr, 23); 550 #endif 551 uasm_i_addu(p, ptr, tmp, ptr); 552 #else 553 UASM_i_LA_mostly(p, ptr, pgdc); 554 #endif 555 uasm_i_mfc0(p, tmp, C0_BADVADDR); /* get faulting address */ 556 uasm_i_lw(p, ptr, uasm_rel_lo(pgdc), ptr); 557 uasm_i_srl(p, tmp, tmp, PGDIR_SHIFT); /* get pgd only bits */ 558 uasm_i_sll(p, tmp, tmp, PGD_T_LOG2); 559 uasm_i_addu(p, ptr, ptr, tmp); /* add in pgd offset */ 560 } 561 562 #endif /* !CONFIG_64BIT */ 563 564 static void __cpuinit build_adjust_context(u32 **p, unsigned int ctx) 565 { 566 unsigned int shift = 4 - (PTE_T_LOG2 + 1) + PAGE_SHIFT - 12; 567 unsigned int mask = (PTRS_PER_PTE / 2 - 1) << (PTE_T_LOG2 + 1); 568 569 switch (current_cpu_type()) { 570 case CPU_VR41XX: 571 case CPU_VR4111: 572 case CPU_VR4121: 573 case CPU_VR4122: 574 case CPU_VR4131: 575 case CPU_VR4181: 576 case CPU_VR4181A: 577 case CPU_VR4133: 578 shift += 2; 579 break; 580 581 default: 582 break; 583 } 584 585 if (shift) 586 UASM_i_SRL(p, ctx, ctx, shift); 587 uasm_i_andi(p, ctx, ctx, mask); 588 } 589 590 static void __cpuinit build_get_ptep(u32 **p, unsigned int tmp, unsigned int ptr) 591 { 592 /* 593 * Bug workaround for the Nevada. It seems as if under certain 594 * circumstances the move from cp0_context might produce a 595 * bogus result when the mfc0 instruction and its consumer are 596 * in a different cacheline or a load instruction, probably any 597 * memory reference, is between them. 598 */ 599 switch (current_cpu_type()) { 600 case CPU_NEVADA: 601 UASM_i_LW(p, ptr, 0, ptr); 602 GET_CONTEXT(p, tmp); /* get context reg */ 603 break; 604 605 default: 606 GET_CONTEXT(p, tmp); /* get context reg */ 607 UASM_i_LW(p, ptr, 0, ptr); 608 break; 609 } 610 611 build_adjust_context(p, tmp); 612 UASM_i_ADDU(p, ptr, ptr, tmp); /* add in offset */ 613 } 614 615 static void __cpuinit build_update_entries(u32 **p, unsigned int tmp, 616 unsigned int ptep) 617 { 618 /* 619 * 64bit address support (36bit on a 32bit CPU) in a 32bit 620 * Kernel is a special case. Only a few CPUs use it. 621 */ 622 #ifdef CONFIG_64BIT_PHYS_ADDR 623 if (cpu_has_64bits) { 624 uasm_i_ld(p, tmp, 0, ptep); /* get even pte */ 625 uasm_i_ld(p, ptep, sizeof(pte_t), ptep); /* get odd pte */ 626 uasm_i_dsrl(p, tmp, tmp, 6); /* convert to entrylo0 */ 627 uasm_i_mtc0(p, tmp, C0_ENTRYLO0); /* load it */ 628 uasm_i_dsrl(p, ptep, ptep, 6); /* convert to entrylo1 */ 629 uasm_i_mtc0(p, ptep, C0_ENTRYLO1); /* load it */ 630 } else { 631 int pte_off_even = sizeof(pte_t) / 2; 632 int pte_off_odd = pte_off_even + sizeof(pte_t); 633 634 /* The pte entries are pre-shifted */ 635 uasm_i_lw(p, tmp, pte_off_even, ptep); /* get even pte */ 636 uasm_i_mtc0(p, tmp, C0_ENTRYLO0); /* load it */ 637 uasm_i_lw(p, ptep, pte_off_odd, ptep); /* get odd pte */ 638 uasm_i_mtc0(p, ptep, C0_ENTRYLO1); /* load it */ 639 } 640 #else 641 UASM_i_LW(p, tmp, 0, ptep); /* get even pte */ 642 UASM_i_LW(p, ptep, sizeof(pte_t), ptep); /* get odd pte */ 643 if (r45k_bvahwbug()) 644 build_tlb_probe_entry(p); 645 UASM_i_SRL(p, tmp, tmp, 6); /* convert to entrylo0 */ 646 if (r4k_250MHZhwbug()) 647 uasm_i_mtc0(p, 0, C0_ENTRYLO0); 648 uasm_i_mtc0(p, tmp, C0_ENTRYLO0); /* load it */ 649 UASM_i_SRL(p, ptep, ptep, 6); /* convert to entrylo1 */ 650 if (r45k_bvahwbug()) 651 uasm_i_mfc0(p, tmp, C0_INDEX); 652 if (r4k_250MHZhwbug()) 653 uasm_i_mtc0(p, 0, C0_ENTRYLO1); 654 uasm_i_mtc0(p, ptep, C0_ENTRYLO1); /* load it */ 655 #endif 656 } 657 658 static void __cpuinit build_r4000_tlb_refill_handler(void) 659 { 660 u32 *p = tlb_handler; 661 struct uasm_label *l = labels; 662 struct uasm_reloc *r = relocs; 663 u32 *f; 664 unsigned int final_len; 665 666 memset(tlb_handler, 0, sizeof(tlb_handler)); 667 memset(labels, 0, sizeof(labels)); 668 memset(relocs, 0, sizeof(relocs)); 669 memset(final_handler, 0, sizeof(final_handler)); 670 671 /* 672 * create the plain linear handler 673 */ 674 if (bcm1250_m3_war()) { 675 UASM_i_MFC0(&p, K0, C0_BADVADDR); 676 UASM_i_MFC0(&p, K1, C0_ENTRYHI); 677 uasm_i_xor(&p, K0, K0, K1); 678 UASM_i_SRL(&p, K0, K0, PAGE_SHIFT + 1); 679 uasm_il_bnez(&p, &r, K0, label_leave); 680 /* No need for uasm_i_nop */ 681 } 682 683 #ifdef CONFIG_64BIT 684 build_get_pmde64(&p, &l, &r, K0, K1); /* get pmd in K1 */ 685 #else 686 build_get_pgde32(&p, K0, K1); /* get pgd in K1 */ 687 #endif 688 689 build_get_ptep(&p, K0, K1); 690 build_update_entries(&p, K0, K1); 691 build_tlb_write_entry(&p, &l, &r, tlb_random); 692 uasm_l_leave(&l, p); 693 uasm_i_eret(&p); /* return from trap */ 694 695 #ifdef CONFIG_64BIT 696 build_get_pgd_vmalloc64(&p, &l, &r, K0, K1); 697 #endif 698 699 /* 700 * Overflow check: For the 64bit handler, we need at least one 701 * free instruction slot for the wrap-around branch. In worst 702 * case, if the intended insertion point is a delay slot, we 703 * need three, with the second nop'ed and the third being 704 * unused. 705 */ 706 /* Loongson2 ebase is different than r4k, we have more space */ 707 #if defined(CONFIG_32BIT) || defined(CONFIG_CPU_LOONGSON2) 708 if ((p - tlb_handler) > 64) 709 panic("TLB refill handler space exceeded"); 710 #else 711 if (((p - tlb_handler) > 63) 712 || (((p - tlb_handler) > 61) 713 && uasm_insn_has_bdelay(relocs, tlb_handler + 29))) 714 panic("TLB refill handler space exceeded"); 715 #endif 716 717 /* 718 * Now fold the handler in the TLB refill handler space. 719 */ 720 #if defined(CONFIG_32BIT) || defined(CONFIG_CPU_LOONGSON2) 721 f = final_handler; 722 /* Simplest case, just copy the handler. */ 723 uasm_copy_handler(relocs, labels, tlb_handler, p, f); 724 final_len = p - tlb_handler; 725 #else /* CONFIG_64BIT */ 726 f = final_handler + 32; 727 if ((p - tlb_handler) <= 32) { 728 /* Just copy the handler. */ 729 uasm_copy_handler(relocs, labels, tlb_handler, p, f); 730 final_len = p - tlb_handler; 731 } else { 732 u32 *split = tlb_handler + 30; 733 734 /* 735 * Find the split point. 736 */ 737 if (uasm_insn_has_bdelay(relocs, split - 1)) 738 split--; 739 740 /* Copy first part of the handler. */ 741 uasm_copy_handler(relocs, labels, tlb_handler, split, f); 742 f += split - tlb_handler; 743 744 /* Insert branch. */ 745 uasm_l_split(&l, final_handler); 746 uasm_il_b(&f, &r, label_split); 747 if (uasm_insn_has_bdelay(relocs, split)) 748 uasm_i_nop(&f); 749 else { 750 uasm_copy_handler(relocs, labels, split, split + 1, f); 751 uasm_move_labels(labels, f, f + 1, -1); 752 f++; 753 split++; 754 } 755 756 /* Copy the rest of the handler. */ 757 uasm_copy_handler(relocs, labels, split, p, final_handler); 758 final_len = (f - (final_handler + 32)) + (p - split); 759 } 760 #endif /* CONFIG_64BIT */ 761 762 uasm_resolve_relocs(relocs, labels); 763 pr_debug("Wrote TLB refill handler (%u instructions).\n", 764 final_len); 765 766 memcpy((void *)ebase, final_handler, 0x100); 767 768 dump_handler((u32 *)ebase, 64); 769 } 770 771 /* 772 * TLB load/store/modify handlers. 773 * 774 * Only the fastpath gets synthesized at runtime, the slowpath for 775 * do_page_fault remains normal asm. 776 */ 777 extern void tlb_do_page_fault_0(void); 778 extern void tlb_do_page_fault_1(void); 779 780 /* 781 * 128 instructions for the fastpath handler is generous and should 782 * never be exceeded. 783 */ 784 #define FASTPATH_SIZE 128 785 786 u32 handle_tlbl[FASTPATH_SIZE] __cacheline_aligned; 787 u32 handle_tlbs[FASTPATH_SIZE] __cacheline_aligned; 788 u32 handle_tlbm[FASTPATH_SIZE] __cacheline_aligned; 789 790 static void __cpuinit 791 iPTE_LW(u32 **p, struct uasm_label **l, unsigned int pte, unsigned int ptr) 792 { 793 #ifdef CONFIG_SMP 794 # ifdef CONFIG_64BIT_PHYS_ADDR 795 if (cpu_has_64bits) 796 uasm_i_lld(p, pte, 0, ptr); 797 else 798 # endif 799 UASM_i_LL(p, pte, 0, ptr); 800 #else 801 # ifdef CONFIG_64BIT_PHYS_ADDR 802 if (cpu_has_64bits) 803 uasm_i_ld(p, pte, 0, ptr); 804 else 805 # endif 806 UASM_i_LW(p, pte, 0, ptr); 807 #endif 808 } 809 810 static void __cpuinit 811 iPTE_SW(u32 **p, struct uasm_reloc **r, unsigned int pte, unsigned int ptr, 812 unsigned int mode) 813 { 814 #ifdef CONFIG_64BIT_PHYS_ADDR 815 unsigned int hwmode = mode & (_PAGE_VALID | _PAGE_DIRTY); 816 #endif 817 818 uasm_i_ori(p, pte, pte, mode); 819 #ifdef CONFIG_SMP 820 # ifdef CONFIG_64BIT_PHYS_ADDR 821 if (cpu_has_64bits) 822 uasm_i_scd(p, pte, 0, ptr); 823 else 824 # endif 825 UASM_i_SC(p, pte, 0, ptr); 826 827 if (r10000_llsc_war()) 828 uasm_il_beqzl(p, r, pte, label_smp_pgtable_change); 829 else 830 uasm_il_beqz(p, r, pte, label_smp_pgtable_change); 831 832 # ifdef CONFIG_64BIT_PHYS_ADDR 833 if (!cpu_has_64bits) { 834 /* no uasm_i_nop needed */ 835 uasm_i_ll(p, pte, sizeof(pte_t) / 2, ptr); 836 uasm_i_ori(p, pte, pte, hwmode); 837 uasm_i_sc(p, pte, sizeof(pte_t) / 2, ptr); 838 uasm_il_beqz(p, r, pte, label_smp_pgtable_change); 839 /* no uasm_i_nop needed */ 840 uasm_i_lw(p, pte, 0, ptr); 841 } else 842 uasm_i_nop(p); 843 # else 844 uasm_i_nop(p); 845 # endif 846 #else 847 # ifdef CONFIG_64BIT_PHYS_ADDR 848 if (cpu_has_64bits) 849 uasm_i_sd(p, pte, 0, ptr); 850 else 851 # endif 852 UASM_i_SW(p, pte, 0, ptr); 853 854 # ifdef CONFIG_64BIT_PHYS_ADDR 855 if (!cpu_has_64bits) { 856 uasm_i_lw(p, pte, sizeof(pte_t) / 2, ptr); 857 uasm_i_ori(p, pte, pte, hwmode); 858 uasm_i_sw(p, pte, sizeof(pte_t) / 2, ptr); 859 uasm_i_lw(p, pte, 0, ptr); 860 } 861 # endif 862 #endif 863 } 864 865 /* 866 * Check if PTE is present, if not then jump to LABEL. PTR points to 867 * the page table where this PTE is located, PTE will be re-loaded 868 * with it's original value. 869 */ 870 static void __cpuinit 871 build_pte_present(u32 **p, struct uasm_label **l, struct uasm_reloc **r, 872 unsigned int pte, unsigned int ptr, enum label_id lid) 873 { 874 uasm_i_andi(p, pte, pte, _PAGE_PRESENT | _PAGE_READ); 875 uasm_i_xori(p, pte, pte, _PAGE_PRESENT | _PAGE_READ); 876 uasm_il_bnez(p, r, pte, lid); 877 iPTE_LW(p, l, pte, ptr); 878 } 879 880 /* Make PTE valid, store result in PTR. */ 881 static void __cpuinit 882 build_make_valid(u32 **p, struct uasm_reloc **r, unsigned int pte, 883 unsigned int ptr) 884 { 885 unsigned int mode = _PAGE_VALID | _PAGE_ACCESSED; 886 887 iPTE_SW(p, r, pte, ptr, mode); 888 } 889 890 /* 891 * Check if PTE can be written to, if not branch to LABEL. Regardless 892 * restore PTE with value from PTR when done. 893 */ 894 static void __cpuinit 895 build_pte_writable(u32 **p, struct uasm_label **l, struct uasm_reloc **r, 896 unsigned int pte, unsigned int ptr, enum label_id lid) 897 { 898 uasm_i_andi(p, pte, pte, _PAGE_PRESENT | _PAGE_WRITE); 899 uasm_i_xori(p, pte, pte, _PAGE_PRESENT | _PAGE_WRITE); 900 uasm_il_bnez(p, r, pte, lid); 901 iPTE_LW(p, l, pte, ptr); 902 } 903 904 /* Make PTE writable, update software status bits as well, then store 905 * at PTR. 906 */ 907 static void __cpuinit 908 build_make_write(u32 **p, struct uasm_reloc **r, unsigned int pte, 909 unsigned int ptr) 910 { 911 unsigned int mode = (_PAGE_ACCESSED | _PAGE_MODIFIED | _PAGE_VALID 912 | _PAGE_DIRTY); 913 914 iPTE_SW(p, r, pte, ptr, mode); 915 } 916 917 /* 918 * Check if PTE can be modified, if not branch to LABEL. Regardless 919 * restore PTE with value from PTR when done. 920 */ 921 static void __cpuinit 922 build_pte_modifiable(u32 **p, struct uasm_label **l, struct uasm_reloc **r, 923 unsigned int pte, unsigned int ptr, enum label_id lid) 924 { 925 uasm_i_andi(p, pte, pte, _PAGE_WRITE); 926 uasm_il_beqz(p, r, pte, lid); 927 iPTE_LW(p, l, pte, ptr); 928 } 929 930 /* 931 * R3000 style TLB load/store/modify handlers. 932 */ 933 934 /* 935 * This places the pte into ENTRYLO0 and writes it with tlbwi. 936 * Then it returns. 937 */ 938 static void __cpuinit 939 build_r3000_pte_reload_tlbwi(u32 **p, unsigned int pte, unsigned int tmp) 940 { 941 uasm_i_mtc0(p, pte, C0_ENTRYLO0); /* cp0 delay */ 942 uasm_i_mfc0(p, tmp, C0_EPC); /* cp0 delay */ 943 uasm_i_tlbwi(p); 944 uasm_i_jr(p, tmp); 945 uasm_i_rfe(p); /* branch delay */ 946 } 947 948 /* 949 * This places the pte into ENTRYLO0 and writes it with tlbwi 950 * or tlbwr as appropriate. This is because the index register 951 * may have the probe fail bit set as a result of a trap on a 952 * kseg2 access, i.e. without refill. Then it returns. 953 */ 954 static void __cpuinit 955 build_r3000_tlb_reload_write(u32 **p, struct uasm_label **l, 956 struct uasm_reloc **r, unsigned int pte, 957 unsigned int tmp) 958 { 959 uasm_i_mfc0(p, tmp, C0_INDEX); 960 uasm_i_mtc0(p, pte, C0_ENTRYLO0); /* cp0 delay */ 961 uasm_il_bltz(p, r, tmp, label_r3000_write_probe_fail); /* cp0 delay */ 962 uasm_i_mfc0(p, tmp, C0_EPC); /* branch delay */ 963 uasm_i_tlbwi(p); /* cp0 delay */ 964 uasm_i_jr(p, tmp); 965 uasm_i_rfe(p); /* branch delay */ 966 uasm_l_r3000_write_probe_fail(l, *p); 967 uasm_i_tlbwr(p); /* cp0 delay */ 968 uasm_i_jr(p, tmp); 969 uasm_i_rfe(p); /* branch delay */ 970 } 971 972 static void __cpuinit 973 build_r3000_tlbchange_handler_head(u32 **p, unsigned int pte, 974 unsigned int ptr) 975 { 976 long pgdc = (long)pgd_current; 977 978 uasm_i_mfc0(p, pte, C0_BADVADDR); 979 uasm_i_lui(p, ptr, uasm_rel_hi(pgdc)); /* cp0 delay */ 980 uasm_i_lw(p, ptr, uasm_rel_lo(pgdc), ptr); 981 uasm_i_srl(p, pte, pte, 22); /* load delay */ 982 uasm_i_sll(p, pte, pte, 2); 983 uasm_i_addu(p, ptr, ptr, pte); 984 uasm_i_mfc0(p, pte, C0_CONTEXT); 985 uasm_i_lw(p, ptr, 0, ptr); /* cp0 delay */ 986 uasm_i_andi(p, pte, pte, 0xffc); /* load delay */ 987 uasm_i_addu(p, ptr, ptr, pte); 988 uasm_i_lw(p, pte, 0, ptr); 989 uasm_i_tlbp(p); /* load delay */ 990 } 991 992 static void __cpuinit build_r3000_tlb_load_handler(void) 993 { 994 u32 *p = handle_tlbl; 995 struct uasm_label *l = labels; 996 struct uasm_reloc *r = relocs; 997 998 memset(handle_tlbl, 0, sizeof(handle_tlbl)); 999 memset(labels, 0, sizeof(labels)); 1000 memset(relocs, 0, sizeof(relocs)); 1001 1002 build_r3000_tlbchange_handler_head(&p, K0, K1); 1003 build_pte_present(&p, &l, &r, K0, K1, label_nopage_tlbl); 1004 uasm_i_nop(&p); /* load delay */ 1005 build_make_valid(&p, &r, K0, K1); 1006 build_r3000_tlb_reload_write(&p, &l, &r, K0, K1); 1007 1008 uasm_l_nopage_tlbl(&l, p); 1009 uasm_i_j(&p, (unsigned long)tlb_do_page_fault_0 & 0x0fffffff); 1010 uasm_i_nop(&p); 1011 1012 if ((p - handle_tlbl) > FASTPATH_SIZE) 1013 panic("TLB load handler fastpath space exceeded"); 1014 1015 uasm_resolve_relocs(relocs, labels); 1016 pr_debug("Wrote TLB load handler fastpath (%u instructions).\n", 1017 (unsigned int)(p - handle_tlbl)); 1018 1019 dump_handler(handle_tlbl, ARRAY_SIZE(handle_tlbl)); 1020 } 1021 1022 static void __cpuinit build_r3000_tlb_store_handler(void) 1023 { 1024 u32 *p = handle_tlbs; 1025 struct uasm_label *l = labels; 1026 struct uasm_reloc *r = relocs; 1027 1028 memset(handle_tlbs, 0, sizeof(handle_tlbs)); 1029 memset(labels, 0, sizeof(labels)); 1030 memset(relocs, 0, sizeof(relocs)); 1031 1032 build_r3000_tlbchange_handler_head(&p, K0, K1); 1033 build_pte_writable(&p, &l, &r, K0, K1, label_nopage_tlbs); 1034 uasm_i_nop(&p); /* load delay */ 1035 build_make_write(&p, &r, K0, K1); 1036 build_r3000_tlb_reload_write(&p, &l, &r, K0, K1); 1037 1038 uasm_l_nopage_tlbs(&l, p); 1039 uasm_i_j(&p, (unsigned long)tlb_do_page_fault_1 & 0x0fffffff); 1040 uasm_i_nop(&p); 1041 1042 if ((p - handle_tlbs) > FASTPATH_SIZE) 1043 panic("TLB store handler fastpath space exceeded"); 1044 1045 uasm_resolve_relocs(relocs, labels); 1046 pr_debug("Wrote TLB store handler fastpath (%u instructions).\n", 1047 (unsigned int)(p - handle_tlbs)); 1048 1049 dump_handler(handle_tlbs, ARRAY_SIZE(handle_tlbs)); 1050 } 1051 1052 static void __cpuinit build_r3000_tlb_modify_handler(void) 1053 { 1054 u32 *p = handle_tlbm; 1055 struct uasm_label *l = labels; 1056 struct uasm_reloc *r = relocs; 1057 1058 memset(handle_tlbm, 0, sizeof(handle_tlbm)); 1059 memset(labels, 0, sizeof(labels)); 1060 memset(relocs, 0, sizeof(relocs)); 1061 1062 build_r3000_tlbchange_handler_head(&p, K0, K1); 1063 build_pte_modifiable(&p, &l, &r, K0, K1, label_nopage_tlbm); 1064 uasm_i_nop(&p); /* load delay */ 1065 build_make_write(&p, &r, K0, K1); 1066 build_r3000_pte_reload_tlbwi(&p, K0, K1); 1067 1068 uasm_l_nopage_tlbm(&l, p); 1069 uasm_i_j(&p, (unsigned long)tlb_do_page_fault_1 & 0x0fffffff); 1070 uasm_i_nop(&p); 1071 1072 if ((p - handle_tlbm) > FASTPATH_SIZE) 1073 panic("TLB modify handler fastpath space exceeded"); 1074 1075 uasm_resolve_relocs(relocs, labels); 1076 pr_debug("Wrote TLB modify handler fastpath (%u instructions).\n", 1077 (unsigned int)(p - handle_tlbm)); 1078 1079 dump_handler(handle_tlbm, ARRAY_SIZE(handle_tlbm)); 1080 } 1081 1082 /* 1083 * R4000 style TLB load/store/modify handlers. 1084 */ 1085 static void __cpuinit 1086 build_r4000_tlbchange_handler_head(u32 **p, struct uasm_label **l, 1087 struct uasm_reloc **r, unsigned int pte, 1088 unsigned int ptr) 1089 { 1090 #ifdef CONFIG_64BIT 1091 build_get_pmde64(p, l, r, pte, ptr); /* get pmd in ptr */ 1092 #else 1093 build_get_pgde32(p, pte, ptr); /* get pgd in ptr */ 1094 #endif 1095 1096 UASM_i_MFC0(p, pte, C0_BADVADDR); 1097 UASM_i_LW(p, ptr, 0, ptr); 1098 UASM_i_SRL(p, pte, pte, PAGE_SHIFT + PTE_ORDER - PTE_T_LOG2); 1099 uasm_i_andi(p, pte, pte, (PTRS_PER_PTE - 1) << PTE_T_LOG2); 1100 UASM_i_ADDU(p, ptr, ptr, pte); 1101 1102 #ifdef CONFIG_SMP 1103 uasm_l_smp_pgtable_change(l, *p); 1104 #endif 1105 iPTE_LW(p, l, pte, ptr); /* get even pte */ 1106 if (!m4kc_tlbp_war()) 1107 build_tlb_probe_entry(p); 1108 } 1109 1110 static void __cpuinit 1111 build_r4000_tlbchange_handler_tail(u32 **p, struct uasm_label **l, 1112 struct uasm_reloc **r, unsigned int tmp, 1113 unsigned int ptr) 1114 { 1115 uasm_i_ori(p, ptr, ptr, sizeof(pte_t)); 1116 uasm_i_xori(p, ptr, ptr, sizeof(pte_t)); 1117 build_update_entries(p, tmp, ptr); 1118 build_tlb_write_entry(p, l, r, tlb_indexed); 1119 uasm_l_leave(l, *p); 1120 uasm_i_eret(p); /* return from trap */ 1121 1122 #ifdef CONFIG_64BIT 1123 build_get_pgd_vmalloc64(p, l, r, tmp, ptr); 1124 #endif 1125 } 1126 1127 static void __cpuinit build_r4000_tlb_load_handler(void) 1128 { 1129 u32 *p = handle_tlbl; 1130 struct uasm_label *l = labels; 1131 struct uasm_reloc *r = relocs; 1132 1133 memset(handle_tlbl, 0, sizeof(handle_tlbl)); 1134 memset(labels, 0, sizeof(labels)); 1135 memset(relocs, 0, sizeof(relocs)); 1136 1137 if (bcm1250_m3_war()) { 1138 UASM_i_MFC0(&p, K0, C0_BADVADDR); 1139 UASM_i_MFC0(&p, K1, C0_ENTRYHI); 1140 uasm_i_xor(&p, K0, K0, K1); 1141 UASM_i_SRL(&p, K0, K0, PAGE_SHIFT + 1); 1142 uasm_il_bnez(&p, &r, K0, label_leave); 1143 /* No need for uasm_i_nop */ 1144 } 1145 1146 build_r4000_tlbchange_handler_head(&p, &l, &r, K0, K1); 1147 build_pte_present(&p, &l, &r, K0, K1, label_nopage_tlbl); 1148 if (m4kc_tlbp_war()) 1149 build_tlb_probe_entry(&p); 1150 build_make_valid(&p, &r, K0, K1); 1151 build_r4000_tlbchange_handler_tail(&p, &l, &r, K0, K1); 1152 1153 uasm_l_nopage_tlbl(&l, p); 1154 uasm_i_j(&p, (unsigned long)tlb_do_page_fault_0 & 0x0fffffff); 1155 uasm_i_nop(&p); 1156 1157 if ((p - handle_tlbl) > FASTPATH_SIZE) 1158 panic("TLB load handler fastpath space exceeded"); 1159 1160 uasm_resolve_relocs(relocs, labels); 1161 pr_debug("Wrote TLB load handler fastpath (%u instructions).\n", 1162 (unsigned int)(p - handle_tlbl)); 1163 1164 dump_handler(handle_tlbl, ARRAY_SIZE(handle_tlbl)); 1165 } 1166 1167 static void __cpuinit build_r4000_tlb_store_handler(void) 1168 { 1169 u32 *p = handle_tlbs; 1170 struct uasm_label *l = labels; 1171 struct uasm_reloc *r = relocs; 1172 1173 memset(handle_tlbs, 0, sizeof(handle_tlbs)); 1174 memset(labels, 0, sizeof(labels)); 1175 memset(relocs, 0, sizeof(relocs)); 1176 1177 build_r4000_tlbchange_handler_head(&p, &l, &r, K0, K1); 1178 build_pte_writable(&p, &l, &r, K0, K1, label_nopage_tlbs); 1179 if (m4kc_tlbp_war()) 1180 build_tlb_probe_entry(&p); 1181 build_make_write(&p, &r, K0, K1); 1182 build_r4000_tlbchange_handler_tail(&p, &l, &r, K0, K1); 1183 1184 uasm_l_nopage_tlbs(&l, p); 1185 uasm_i_j(&p, (unsigned long)tlb_do_page_fault_1 & 0x0fffffff); 1186 uasm_i_nop(&p); 1187 1188 if ((p - handle_tlbs) > FASTPATH_SIZE) 1189 panic("TLB store handler fastpath space exceeded"); 1190 1191 uasm_resolve_relocs(relocs, labels); 1192 pr_debug("Wrote TLB store handler fastpath (%u instructions).\n", 1193 (unsigned int)(p - handle_tlbs)); 1194 1195 dump_handler(handle_tlbs, ARRAY_SIZE(handle_tlbs)); 1196 } 1197 1198 static void __cpuinit build_r4000_tlb_modify_handler(void) 1199 { 1200 u32 *p = handle_tlbm; 1201 struct uasm_label *l = labels; 1202 struct uasm_reloc *r = relocs; 1203 1204 memset(handle_tlbm, 0, sizeof(handle_tlbm)); 1205 memset(labels, 0, sizeof(labels)); 1206 memset(relocs, 0, sizeof(relocs)); 1207 1208 build_r4000_tlbchange_handler_head(&p, &l, &r, K0, K1); 1209 build_pte_modifiable(&p, &l, &r, K0, K1, label_nopage_tlbm); 1210 if (m4kc_tlbp_war()) 1211 build_tlb_probe_entry(&p); 1212 /* Present and writable bits set, set accessed and dirty bits. */ 1213 build_make_write(&p, &r, K0, K1); 1214 build_r4000_tlbchange_handler_tail(&p, &l, &r, K0, K1); 1215 1216 uasm_l_nopage_tlbm(&l, p); 1217 uasm_i_j(&p, (unsigned long)tlb_do_page_fault_1 & 0x0fffffff); 1218 uasm_i_nop(&p); 1219 1220 if ((p - handle_tlbm) > FASTPATH_SIZE) 1221 panic("TLB modify handler fastpath space exceeded"); 1222 1223 uasm_resolve_relocs(relocs, labels); 1224 pr_debug("Wrote TLB modify handler fastpath (%u instructions).\n", 1225 (unsigned int)(p - handle_tlbm)); 1226 1227 dump_handler(handle_tlbm, ARRAY_SIZE(handle_tlbm)); 1228 } 1229 1230 void __cpuinit build_tlb_refill_handler(void) 1231 { 1232 /* 1233 * The refill handler is generated per-CPU, multi-node systems 1234 * may have local storage for it. The other handlers are only 1235 * needed once. 1236 */ 1237 static int run_once = 0; 1238 1239 switch (current_cpu_type()) { 1240 case CPU_R2000: 1241 case CPU_R3000: 1242 case CPU_R3000A: 1243 case CPU_R3081E: 1244 case CPU_TX3912: 1245 case CPU_TX3922: 1246 case CPU_TX3927: 1247 build_r3000_tlb_refill_handler(); 1248 if (!run_once) { 1249 build_r3000_tlb_load_handler(); 1250 build_r3000_tlb_store_handler(); 1251 build_r3000_tlb_modify_handler(); 1252 run_once++; 1253 } 1254 break; 1255 1256 case CPU_R6000: 1257 case CPU_R6000A: 1258 panic("No R6000 TLB refill handler yet"); 1259 break; 1260 1261 case CPU_R8000: 1262 panic("No R8000 TLB refill handler yet"); 1263 break; 1264 1265 default: 1266 build_r4000_tlb_refill_handler(); 1267 if (!run_once) { 1268 build_r4000_tlb_load_handler(); 1269 build_r4000_tlb_store_handler(); 1270 build_r4000_tlb_modify_handler(); 1271 run_once++; 1272 } 1273 } 1274 } 1275 1276 void __cpuinit flush_tlb_handlers(void) 1277 { 1278 local_flush_icache_range((unsigned long)handle_tlbl, 1279 (unsigned long)handle_tlbl + sizeof(handle_tlbl)); 1280 local_flush_icache_range((unsigned long)handle_tlbs, 1281 (unsigned long)handle_tlbs + sizeof(handle_tlbs)); 1282 local_flush_icache_range((unsigned long)handle_tlbm, 1283 (unsigned long)handle_tlbm + sizeof(handle_tlbm)); 1284 } 1285