1*5b3b1688SDavid Daney/* 2*5b3b1688SDavid Daney * This file is subject to the terms and conditions of the GNU General Public 3*5b3b1688SDavid Daney * License. See the file "COPYING" in the main directory of this archive 4*5b3b1688SDavid Daney * for more details. 5*5b3b1688SDavid Daney * 6*5b3b1688SDavid Daney * Copyright (C) 2006 Cavium Networks 7*5b3b1688SDavid Daney * Cache error handler 8*5b3b1688SDavid Daney */ 9*5b3b1688SDavid Daney 10*5b3b1688SDavid Daney#include <asm/asm.h> 11*5b3b1688SDavid Daney#include <asm/regdef.h> 12*5b3b1688SDavid Daney#include <asm/mipsregs.h> 13*5b3b1688SDavid Daney#include <asm/stackframe.h> 14*5b3b1688SDavid Daney 15*5b3b1688SDavid Daney/* 16*5b3b1688SDavid Daney * Handle cache error. Indicate to the second level handler whether 17*5b3b1688SDavid Daney * the exception is recoverable. 18*5b3b1688SDavid Daney */ 19*5b3b1688SDavid Daney LEAF(except_vec2_octeon) 20*5b3b1688SDavid Daney 21*5b3b1688SDavid Daney .set push 22*5b3b1688SDavid Daney .set mips64r2 23*5b3b1688SDavid Daney .set noreorder 24*5b3b1688SDavid Daney .set noat 25*5b3b1688SDavid Daney 26*5b3b1688SDavid Daney 27*5b3b1688SDavid Daney /* due to an errata we need to read the COP0 CacheErr (Dcache) 28*5b3b1688SDavid Daney * before any cache/DRAM access */ 29*5b3b1688SDavid Daney 30*5b3b1688SDavid Daney rdhwr k0, $0 /* get core_id */ 31*5b3b1688SDavid Daney PTR_LA k1, cache_err_dcache 32*5b3b1688SDavid Daney sll k0, k0, 3 33*5b3b1688SDavid Daney PTR_ADDU k1, k0, k1 /* k1 = &cache_err_dcache[core_id] */ 34*5b3b1688SDavid Daney 35*5b3b1688SDavid Daney dmfc0 k0, CP0_CACHEERR, 1 36*5b3b1688SDavid Daney sd k0, (k1) 37*5b3b1688SDavid Daney dmtc0 $0, CP0_CACHEERR, 1 38*5b3b1688SDavid Daney 39*5b3b1688SDavid Daney /* check whether this is a nested exception */ 40*5b3b1688SDavid Daney mfc0 k1, CP0_STATUS 41*5b3b1688SDavid Daney andi k1, k1, ST0_EXL 42*5b3b1688SDavid Daney beqz k1, 1f 43*5b3b1688SDavid Daney nop 44*5b3b1688SDavid Daney j cache_parity_error_octeon_non_recoverable 45*5b3b1688SDavid Daney nop 46*5b3b1688SDavid Daney 47*5b3b1688SDavid Daney /* exception is recoverable */ 48*5b3b1688SDavid Daney1: j handle_cache_err 49*5b3b1688SDavid Daney nop 50*5b3b1688SDavid Daney 51*5b3b1688SDavid Daney .set pop 52*5b3b1688SDavid Daney END(except_vec2_octeon) 53*5b3b1688SDavid Daney 54*5b3b1688SDavid Daney /* We need to jump to handle_cache_err so that the previous handler 55*5b3b1688SDavid Daney * can fit within 0x80 bytes. We also move from 0xFFFFFFFFAXXXXXXX 56*5b3b1688SDavid Daney * space (uncached) to the 0xFFFFFFFF8XXXXXXX space (cached). */ 57*5b3b1688SDavid Daney LEAF(handle_cache_err) 58*5b3b1688SDavid Daney .set push 59*5b3b1688SDavid Daney .set noreorder 60*5b3b1688SDavid Daney .set noat 61*5b3b1688SDavid Daney 62*5b3b1688SDavid Daney SAVE_ALL 63*5b3b1688SDavid Daney KMODE 64*5b3b1688SDavid Daney jal cache_parity_error_octeon_recoverable 65*5b3b1688SDavid Daney nop 66*5b3b1688SDavid Daney j ret_from_exception 67*5b3b1688SDavid Daney nop 68*5b3b1688SDavid Daney 69*5b3b1688SDavid Daney .set pop 70*5b3b1688SDavid Daney END(handle_cache_err) 71