1 /* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * Copyright (C) 1996 David S. Miller (davem@davemloft.net) 7 * Copyright (C) 1997, 1998, 1999, 2000, 2001, 2002 Ralf Baechle (ralf@gnu.org) 8 * Copyright (C) 1999, 2000 Silicon Graphics, Inc. 9 */ 10 #include <linux/hardirq.h> 11 #include <linux/init.h> 12 #include <linux/highmem.h> 13 #include <linux/kernel.h> 14 #include <linux/linkage.h> 15 #include <linux/sched.h> 16 #include <linux/smp.h> 17 #include <linux/mm.h> 18 #include <linux/module.h> 19 #include <linux/bitops.h> 20 21 #include <asm/bcache.h> 22 #include <asm/bootinfo.h> 23 #include <asm/cache.h> 24 #include <asm/cacheops.h> 25 #include <asm/cpu.h> 26 #include <asm/cpu-features.h> 27 #include <asm/io.h> 28 #include <asm/page.h> 29 #include <asm/pgtable.h> 30 #include <asm/r4kcache.h> 31 #include <asm/sections.h> 32 #include <asm/mmu_context.h> 33 #include <asm/war.h> 34 #include <asm/cacheflush.h> /* for run_uncached() */ 35 #include <asm/traps.h> 36 37 /* 38 * Special Variant of smp_call_function for use by cache functions: 39 * 40 * o No return value 41 * o collapses to normal function call on UP kernels 42 * o collapses to normal function call on systems with a single shared 43 * primary cache. 44 * o doesn't disable interrupts on the local CPU 45 */ 46 static inline void r4k_on_each_cpu(void (*func) (void *info), void *info) 47 { 48 preempt_disable(); 49 50 #if !defined(CONFIG_MIPS_MT_SMP) && !defined(CONFIG_MIPS_MT_SMTC) 51 smp_call_function(func, info, 1); 52 #endif 53 func(info); 54 preempt_enable(); 55 } 56 57 #if defined(CONFIG_MIPS_CMP) 58 #define cpu_has_safe_index_cacheops 0 59 #else 60 #define cpu_has_safe_index_cacheops 1 61 #endif 62 63 /* 64 * Must die. 65 */ 66 static unsigned long icache_size __read_mostly; 67 static unsigned long dcache_size __read_mostly; 68 static unsigned long scache_size __read_mostly; 69 70 /* 71 * Dummy cache handling routines for machines without boardcaches 72 */ 73 static void cache_noop(void) {} 74 75 static struct bcache_ops no_sc_ops = { 76 .bc_enable = (void *)cache_noop, 77 .bc_disable = (void *)cache_noop, 78 .bc_wback_inv = (void *)cache_noop, 79 .bc_inv = (void *)cache_noop 80 }; 81 82 struct bcache_ops *bcops = &no_sc_ops; 83 84 #define cpu_is_r4600_v1_x() ((read_c0_prid() & 0xfffffff0) == 0x00002010) 85 #define cpu_is_r4600_v2_x() ((read_c0_prid() & 0xfffffff0) == 0x00002020) 86 87 #define R4600_HIT_CACHEOP_WAR_IMPL \ 88 do { \ 89 if (R4600_V2_HIT_CACHEOP_WAR && cpu_is_r4600_v2_x()) \ 90 *(volatile unsigned long *)CKSEG1; \ 91 if (R4600_V1_HIT_CACHEOP_WAR) \ 92 __asm__ __volatile__("nop;nop;nop;nop"); \ 93 } while (0) 94 95 static void (*r4k_blast_dcache_page)(unsigned long addr); 96 97 static inline void r4k_blast_dcache_page_dc32(unsigned long addr) 98 { 99 R4600_HIT_CACHEOP_WAR_IMPL; 100 blast_dcache32_page(addr); 101 } 102 103 static inline void r4k_blast_dcache_page_dc64(unsigned long addr) 104 { 105 R4600_HIT_CACHEOP_WAR_IMPL; 106 blast_dcache64_page(addr); 107 } 108 109 static void __cpuinit r4k_blast_dcache_page_setup(void) 110 { 111 unsigned long dc_lsize = cpu_dcache_line_size(); 112 113 if (dc_lsize == 0) 114 r4k_blast_dcache_page = (void *)cache_noop; 115 else if (dc_lsize == 16) 116 r4k_blast_dcache_page = blast_dcache16_page; 117 else if (dc_lsize == 32) 118 r4k_blast_dcache_page = r4k_blast_dcache_page_dc32; 119 else if (dc_lsize == 64) 120 r4k_blast_dcache_page = r4k_blast_dcache_page_dc64; 121 } 122 123 static void (* r4k_blast_dcache_page_indexed)(unsigned long addr); 124 125 static void __cpuinit r4k_blast_dcache_page_indexed_setup(void) 126 { 127 unsigned long dc_lsize = cpu_dcache_line_size(); 128 129 if (dc_lsize == 0) 130 r4k_blast_dcache_page_indexed = (void *)cache_noop; 131 else if (dc_lsize == 16) 132 r4k_blast_dcache_page_indexed = blast_dcache16_page_indexed; 133 else if (dc_lsize == 32) 134 r4k_blast_dcache_page_indexed = blast_dcache32_page_indexed; 135 else if (dc_lsize == 64) 136 r4k_blast_dcache_page_indexed = blast_dcache64_page_indexed; 137 } 138 139 static void (* r4k_blast_dcache)(void); 140 141 static void __cpuinit r4k_blast_dcache_setup(void) 142 { 143 unsigned long dc_lsize = cpu_dcache_line_size(); 144 145 if (dc_lsize == 0) 146 r4k_blast_dcache = (void *)cache_noop; 147 else if (dc_lsize == 16) 148 r4k_blast_dcache = blast_dcache16; 149 else if (dc_lsize == 32) 150 r4k_blast_dcache = blast_dcache32; 151 else if (dc_lsize == 64) 152 r4k_blast_dcache = blast_dcache64; 153 } 154 155 /* force code alignment (used for TX49XX_ICACHE_INDEX_INV_WAR) */ 156 #define JUMP_TO_ALIGN(order) \ 157 __asm__ __volatile__( \ 158 "b\t1f\n\t" \ 159 ".align\t" #order "\n\t" \ 160 "1:\n\t" \ 161 ) 162 #define CACHE32_UNROLL32_ALIGN JUMP_TO_ALIGN(10) /* 32 * 32 = 1024 */ 163 #define CACHE32_UNROLL32_ALIGN2 JUMP_TO_ALIGN(11) 164 165 static inline void blast_r4600_v1_icache32(void) 166 { 167 unsigned long flags; 168 169 local_irq_save(flags); 170 blast_icache32(); 171 local_irq_restore(flags); 172 } 173 174 static inline void tx49_blast_icache32(void) 175 { 176 unsigned long start = INDEX_BASE; 177 unsigned long end = start + current_cpu_data.icache.waysize; 178 unsigned long ws_inc = 1UL << current_cpu_data.icache.waybit; 179 unsigned long ws_end = current_cpu_data.icache.ways << 180 current_cpu_data.icache.waybit; 181 unsigned long ws, addr; 182 183 CACHE32_UNROLL32_ALIGN2; 184 /* I'm in even chunk. blast odd chunks */ 185 for (ws = 0; ws < ws_end; ws += ws_inc) 186 for (addr = start + 0x400; addr < end; addr += 0x400 * 2) 187 cache32_unroll32(addr|ws, Index_Invalidate_I); 188 CACHE32_UNROLL32_ALIGN; 189 /* I'm in odd chunk. blast even chunks */ 190 for (ws = 0; ws < ws_end; ws += ws_inc) 191 for (addr = start; addr < end; addr += 0x400 * 2) 192 cache32_unroll32(addr|ws, Index_Invalidate_I); 193 } 194 195 static inline void blast_icache32_r4600_v1_page_indexed(unsigned long page) 196 { 197 unsigned long flags; 198 199 local_irq_save(flags); 200 blast_icache32_page_indexed(page); 201 local_irq_restore(flags); 202 } 203 204 static inline void tx49_blast_icache32_page_indexed(unsigned long page) 205 { 206 unsigned long indexmask = current_cpu_data.icache.waysize - 1; 207 unsigned long start = INDEX_BASE + (page & indexmask); 208 unsigned long end = start + PAGE_SIZE; 209 unsigned long ws_inc = 1UL << current_cpu_data.icache.waybit; 210 unsigned long ws_end = current_cpu_data.icache.ways << 211 current_cpu_data.icache.waybit; 212 unsigned long ws, addr; 213 214 CACHE32_UNROLL32_ALIGN2; 215 /* I'm in even chunk. blast odd chunks */ 216 for (ws = 0; ws < ws_end; ws += ws_inc) 217 for (addr = start + 0x400; addr < end; addr += 0x400 * 2) 218 cache32_unroll32(addr|ws, Index_Invalidate_I); 219 CACHE32_UNROLL32_ALIGN; 220 /* I'm in odd chunk. blast even chunks */ 221 for (ws = 0; ws < ws_end; ws += ws_inc) 222 for (addr = start; addr < end; addr += 0x400 * 2) 223 cache32_unroll32(addr|ws, Index_Invalidate_I); 224 } 225 226 static void (* r4k_blast_icache_page)(unsigned long addr); 227 228 static void __cpuinit r4k_blast_icache_page_setup(void) 229 { 230 unsigned long ic_lsize = cpu_icache_line_size(); 231 232 if (ic_lsize == 0) 233 r4k_blast_icache_page = (void *)cache_noop; 234 else if (ic_lsize == 16) 235 r4k_blast_icache_page = blast_icache16_page; 236 else if (ic_lsize == 32) 237 r4k_blast_icache_page = blast_icache32_page; 238 else if (ic_lsize == 64) 239 r4k_blast_icache_page = blast_icache64_page; 240 } 241 242 243 static void (* r4k_blast_icache_page_indexed)(unsigned long addr); 244 245 static void __cpuinit r4k_blast_icache_page_indexed_setup(void) 246 { 247 unsigned long ic_lsize = cpu_icache_line_size(); 248 249 if (ic_lsize == 0) 250 r4k_blast_icache_page_indexed = (void *)cache_noop; 251 else if (ic_lsize == 16) 252 r4k_blast_icache_page_indexed = blast_icache16_page_indexed; 253 else if (ic_lsize == 32) { 254 if (R4600_V1_INDEX_ICACHEOP_WAR && cpu_is_r4600_v1_x()) 255 r4k_blast_icache_page_indexed = 256 blast_icache32_r4600_v1_page_indexed; 257 else if (TX49XX_ICACHE_INDEX_INV_WAR) 258 r4k_blast_icache_page_indexed = 259 tx49_blast_icache32_page_indexed; 260 else 261 r4k_blast_icache_page_indexed = 262 blast_icache32_page_indexed; 263 } else if (ic_lsize == 64) 264 r4k_blast_icache_page_indexed = blast_icache64_page_indexed; 265 } 266 267 static void (* r4k_blast_icache)(void); 268 269 static void __cpuinit r4k_blast_icache_setup(void) 270 { 271 unsigned long ic_lsize = cpu_icache_line_size(); 272 273 if (ic_lsize == 0) 274 r4k_blast_icache = (void *)cache_noop; 275 else if (ic_lsize == 16) 276 r4k_blast_icache = blast_icache16; 277 else if (ic_lsize == 32) { 278 if (R4600_V1_INDEX_ICACHEOP_WAR && cpu_is_r4600_v1_x()) 279 r4k_blast_icache = blast_r4600_v1_icache32; 280 else if (TX49XX_ICACHE_INDEX_INV_WAR) 281 r4k_blast_icache = tx49_blast_icache32; 282 else 283 r4k_blast_icache = blast_icache32; 284 } else if (ic_lsize == 64) 285 r4k_blast_icache = blast_icache64; 286 } 287 288 static void (* r4k_blast_scache_page)(unsigned long addr); 289 290 static void __cpuinit r4k_blast_scache_page_setup(void) 291 { 292 unsigned long sc_lsize = cpu_scache_line_size(); 293 294 if (scache_size == 0) 295 r4k_blast_scache_page = (void *)cache_noop; 296 else if (sc_lsize == 16) 297 r4k_blast_scache_page = blast_scache16_page; 298 else if (sc_lsize == 32) 299 r4k_blast_scache_page = blast_scache32_page; 300 else if (sc_lsize == 64) 301 r4k_blast_scache_page = blast_scache64_page; 302 else if (sc_lsize == 128) 303 r4k_blast_scache_page = blast_scache128_page; 304 } 305 306 static void (* r4k_blast_scache_page_indexed)(unsigned long addr); 307 308 static void __cpuinit r4k_blast_scache_page_indexed_setup(void) 309 { 310 unsigned long sc_lsize = cpu_scache_line_size(); 311 312 if (scache_size == 0) 313 r4k_blast_scache_page_indexed = (void *)cache_noop; 314 else if (sc_lsize == 16) 315 r4k_blast_scache_page_indexed = blast_scache16_page_indexed; 316 else if (sc_lsize == 32) 317 r4k_blast_scache_page_indexed = blast_scache32_page_indexed; 318 else if (sc_lsize == 64) 319 r4k_blast_scache_page_indexed = blast_scache64_page_indexed; 320 else if (sc_lsize == 128) 321 r4k_blast_scache_page_indexed = blast_scache128_page_indexed; 322 } 323 324 static void (* r4k_blast_scache)(void); 325 326 static void __cpuinit r4k_blast_scache_setup(void) 327 { 328 unsigned long sc_lsize = cpu_scache_line_size(); 329 330 if (scache_size == 0) 331 r4k_blast_scache = (void *)cache_noop; 332 else if (sc_lsize == 16) 333 r4k_blast_scache = blast_scache16; 334 else if (sc_lsize == 32) 335 r4k_blast_scache = blast_scache32; 336 else if (sc_lsize == 64) 337 r4k_blast_scache = blast_scache64; 338 else if (sc_lsize == 128) 339 r4k_blast_scache = blast_scache128; 340 } 341 342 static inline void local_r4k___flush_cache_all(void * args) 343 { 344 #if defined(CONFIG_CPU_LOONGSON2) 345 r4k_blast_scache(); 346 return; 347 #endif 348 r4k_blast_dcache(); 349 r4k_blast_icache(); 350 351 switch (current_cpu_type()) { 352 case CPU_R4000SC: 353 case CPU_R4000MC: 354 case CPU_R4400SC: 355 case CPU_R4400MC: 356 case CPU_R10000: 357 case CPU_R12000: 358 case CPU_R14000: 359 r4k_blast_scache(); 360 } 361 } 362 363 static void r4k___flush_cache_all(void) 364 { 365 r4k_on_each_cpu(local_r4k___flush_cache_all, NULL); 366 } 367 368 static inline int has_valid_asid(const struct mm_struct *mm) 369 { 370 #if defined(CONFIG_MIPS_MT_SMP) || defined(CONFIG_MIPS_MT_SMTC) 371 int i; 372 373 for_each_online_cpu(i) 374 if (cpu_context(i, mm)) 375 return 1; 376 377 return 0; 378 #else 379 return cpu_context(smp_processor_id(), mm); 380 #endif 381 } 382 383 static void r4k__flush_cache_vmap(void) 384 { 385 r4k_blast_dcache(); 386 } 387 388 static void r4k__flush_cache_vunmap(void) 389 { 390 r4k_blast_dcache(); 391 } 392 393 static inline void local_r4k_flush_cache_range(void * args) 394 { 395 struct vm_area_struct *vma = args; 396 int exec = vma->vm_flags & VM_EXEC; 397 398 if (!(has_valid_asid(vma->vm_mm))) 399 return; 400 401 r4k_blast_dcache(); 402 if (exec) 403 r4k_blast_icache(); 404 } 405 406 static void r4k_flush_cache_range(struct vm_area_struct *vma, 407 unsigned long start, unsigned long end) 408 { 409 int exec = vma->vm_flags & VM_EXEC; 410 411 if (cpu_has_dc_aliases || (exec && !cpu_has_ic_fills_f_dc)) 412 r4k_on_each_cpu(local_r4k_flush_cache_range, vma); 413 } 414 415 static inline void local_r4k_flush_cache_mm(void * args) 416 { 417 struct mm_struct *mm = args; 418 419 if (!has_valid_asid(mm)) 420 return; 421 422 /* 423 * Kludge alert. For obscure reasons R4000SC and R4400SC go nuts if we 424 * only flush the primary caches but R10000 and R12000 behave sane ... 425 * R4000SC and R4400SC indexed S-cache ops also invalidate primary 426 * caches, so we can bail out early. 427 */ 428 if (current_cpu_type() == CPU_R4000SC || 429 current_cpu_type() == CPU_R4000MC || 430 current_cpu_type() == CPU_R4400SC || 431 current_cpu_type() == CPU_R4400MC) { 432 r4k_blast_scache(); 433 return; 434 } 435 436 r4k_blast_dcache(); 437 } 438 439 static void r4k_flush_cache_mm(struct mm_struct *mm) 440 { 441 if (!cpu_has_dc_aliases) 442 return; 443 444 r4k_on_each_cpu(local_r4k_flush_cache_mm, mm); 445 } 446 447 struct flush_cache_page_args { 448 struct vm_area_struct *vma; 449 unsigned long addr; 450 unsigned long pfn; 451 }; 452 453 static inline void local_r4k_flush_cache_page(void *args) 454 { 455 struct flush_cache_page_args *fcp_args = args; 456 struct vm_area_struct *vma = fcp_args->vma; 457 unsigned long addr = fcp_args->addr; 458 struct page *page = pfn_to_page(fcp_args->pfn); 459 int exec = vma->vm_flags & VM_EXEC; 460 struct mm_struct *mm = vma->vm_mm; 461 int map_coherent = 0; 462 pgd_t *pgdp; 463 pud_t *pudp; 464 pmd_t *pmdp; 465 pte_t *ptep; 466 void *vaddr; 467 468 /* 469 * If ownes no valid ASID yet, cannot possibly have gotten 470 * this page into the cache. 471 */ 472 if (!has_valid_asid(mm)) 473 return; 474 475 addr &= PAGE_MASK; 476 pgdp = pgd_offset(mm, addr); 477 pudp = pud_offset(pgdp, addr); 478 pmdp = pmd_offset(pudp, addr); 479 ptep = pte_offset(pmdp, addr); 480 481 /* 482 * If the page isn't marked valid, the page cannot possibly be 483 * in the cache. 484 */ 485 if (!(pte_present(*ptep))) 486 return; 487 488 if ((mm == current->active_mm) && (pte_val(*ptep) & _PAGE_VALID)) 489 vaddr = NULL; 490 else { 491 /* 492 * Use kmap_coherent or kmap_atomic to do flushes for 493 * another ASID than the current one. 494 */ 495 map_coherent = (cpu_has_dc_aliases && 496 page_mapped(page) && !Page_dcache_dirty(page)); 497 if (map_coherent) 498 vaddr = kmap_coherent(page, addr); 499 else 500 vaddr = kmap_atomic(page); 501 addr = (unsigned long)vaddr; 502 } 503 504 if (cpu_has_dc_aliases || (exec && !cpu_has_ic_fills_f_dc)) { 505 r4k_blast_dcache_page(addr); 506 if (exec && !cpu_icache_snoops_remote_store) 507 r4k_blast_scache_page(addr); 508 } 509 if (exec) { 510 if (vaddr && cpu_has_vtag_icache && mm == current->active_mm) { 511 int cpu = smp_processor_id(); 512 513 if (cpu_context(cpu, mm) != 0) 514 drop_mmu_context(mm, cpu); 515 } else 516 r4k_blast_icache_page(addr); 517 } 518 519 if (vaddr) { 520 if (map_coherent) 521 kunmap_coherent(); 522 else 523 kunmap_atomic(vaddr); 524 } 525 } 526 527 static void r4k_flush_cache_page(struct vm_area_struct *vma, 528 unsigned long addr, unsigned long pfn) 529 { 530 struct flush_cache_page_args args; 531 532 args.vma = vma; 533 args.addr = addr; 534 args.pfn = pfn; 535 536 r4k_on_each_cpu(local_r4k_flush_cache_page, &args); 537 } 538 539 static inline void local_r4k_flush_data_cache_page(void * addr) 540 { 541 r4k_blast_dcache_page((unsigned long) addr); 542 } 543 544 static void r4k_flush_data_cache_page(unsigned long addr) 545 { 546 if (in_atomic()) 547 local_r4k_flush_data_cache_page((void *)addr); 548 else 549 r4k_on_each_cpu(local_r4k_flush_data_cache_page, (void *) addr); 550 } 551 552 struct flush_icache_range_args { 553 unsigned long start; 554 unsigned long end; 555 }; 556 557 static inline void local_r4k_flush_icache_range(unsigned long start, unsigned long end) 558 { 559 if (!cpu_has_ic_fills_f_dc) { 560 if (end - start >= dcache_size) { 561 r4k_blast_dcache(); 562 } else { 563 R4600_HIT_CACHEOP_WAR_IMPL; 564 protected_blast_dcache_range(start, end); 565 } 566 } 567 568 if (end - start > icache_size) 569 r4k_blast_icache(); 570 else 571 protected_blast_icache_range(start, end); 572 } 573 574 static inline void local_r4k_flush_icache_range_ipi(void *args) 575 { 576 struct flush_icache_range_args *fir_args = args; 577 unsigned long start = fir_args->start; 578 unsigned long end = fir_args->end; 579 580 local_r4k_flush_icache_range(start, end); 581 } 582 583 static void r4k_flush_icache_range(unsigned long start, unsigned long end) 584 { 585 struct flush_icache_range_args args; 586 587 args.start = start; 588 args.end = end; 589 590 r4k_on_each_cpu(local_r4k_flush_icache_range_ipi, &args); 591 instruction_hazard(); 592 } 593 594 #ifdef CONFIG_DMA_NONCOHERENT 595 596 static void r4k_dma_cache_wback_inv(unsigned long addr, unsigned long size) 597 { 598 /* Catch bad driver code */ 599 BUG_ON(size == 0); 600 601 if (cpu_has_inclusive_pcaches) { 602 if (size >= scache_size) 603 r4k_blast_scache(); 604 else 605 blast_scache_range(addr, addr + size); 606 __sync(); 607 return; 608 } 609 610 /* 611 * Either no secondary cache or the available caches don't have the 612 * subset property so we have to flush the primary caches 613 * explicitly 614 */ 615 if (cpu_has_safe_index_cacheops && size >= dcache_size) { 616 r4k_blast_dcache(); 617 } else { 618 R4600_HIT_CACHEOP_WAR_IMPL; 619 blast_dcache_range(addr, addr + size); 620 } 621 622 bc_wback_inv(addr, size); 623 __sync(); 624 } 625 626 static void r4k_dma_cache_inv(unsigned long addr, unsigned long size) 627 { 628 /* Catch bad driver code */ 629 BUG_ON(size == 0); 630 631 if (cpu_has_inclusive_pcaches) { 632 if (size >= scache_size) 633 r4k_blast_scache(); 634 else { 635 /* 636 * There is no clearly documented alignment requirement 637 * for the cache instruction on MIPS processors and 638 * some processors, among them the RM5200 and RM7000 639 * QED processors will throw an address error for cache 640 * hit ops with insufficient alignment. Solved by 641 * aligning the address to cache line size. 642 */ 643 blast_inv_scache_range(addr, addr + size); 644 } 645 __sync(); 646 return; 647 } 648 649 if (cpu_has_safe_index_cacheops && size >= dcache_size) { 650 r4k_blast_dcache(); 651 } else { 652 R4600_HIT_CACHEOP_WAR_IMPL; 653 blast_inv_dcache_range(addr, addr + size); 654 } 655 656 bc_inv(addr, size); 657 __sync(); 658 } 659 #endif /* CONFIG_DMA_NONCOHERENT */ 660 661 /* 662 * While we're protected against bad userland addresses we don't care 663 * very much about what happens in that case. Usually a segmentation 664 * fault will dump the process later on anyway ... 665 */ 666 static void local_r4k_flush_cache_sigtramp(void * arg) 667 { 668 unsigned long ic_lsize = cpu_icache_line_size(); 669 unsigned long dc_lsize = cpu_dcache_line_size(); 670 unsigned long sc_lsize = cpu_scache_line_size(); 671 unsigned long addr = (unsigned long) arg; 672 673 R4600_HIT_CACHEOP_WAR_IMPL; 674 if (dc_lsize) 675 protected_writeback_dcache_line(addr & ~(dc_lsize - 1)); 676 if (!cpu_icache_snoops_remote_store && scache_size) 677 protected_writeback_scache_line(addr & ~(sc_lsize - 1)); 678 if (ic_lsize) 679 protected_flush_icache_line(addr & ~(ic_lsize - 1)); 680 if (MIPS4K_ICACHE_REFILL_WAR) { 681 __asm__ __volatile__ ( 682 ".set push\n\t" 683 ".set noat\n\t" 684 ".set mips3\n\t" 685 #ifdef CONFIG_32BIT 686 "la $at,1f\n\t" 687 #endif 688 #ifdef CONFIG_64BIT 689 "dla $at,1f\n\t" 690 #endif 691 "cache %0,($at)\n\t" 692 "nop; nop; nop\n" 693 "1:\n\t" 694 ".set pop" 695 : 696 : "i" (Hit_Invalidate_I)); 697 } 698 if (MIPS_CACHE_SYNC_WAR) 699 __asm__ __volatile__ ("sync"); 700 } 701 702 static void r4k_flush_cache_sigtramp(unsigned long addr) 703 { 704 r4k_on_each_cpu(local_r4k_flush_cache_sigtramp, (void *) addr); 705 } 706 707 static void r4k_flush_icache_all(void) 708 { 709 if (cpu_has_vtag_icache) 710 r4k_blast_icache(); 711 } 712 713 struct flush_kernel_vmap_range_args { 714 unsigned long vaddr; 715 int size; 716 }; 717 718 static inline void local_r4k_flush_kernel_vmap_range(void *args) 719 { 720 struct flush_kernel_vmap_range_args *vmra = args; 721 unsigned long vaddr = vmra->vaddr; 722 int size = vmra->size; 723 724 /* 725 * Aliases only affect the primary caches so don't bother with 726 * S-caches or T-caches. 727 */ 728 if (cpu_has_safe_index_cacheops && size >= dcache_size) 729 r4k_blast_dcache(); 730 else { 731 R4600_HIT_CACHEOP_WAR_IMPL; 732 blast_dcache_range(vaddr, vaddr + size); 733 } 734 } 735 736 static void r4k_flush_kernel_vmap_range(unsigned long vaddr, int size) 737 { 738 struct flush_kernel_vmap_range_args args; 739 740 args.vaddr = (unsigned long) vaddr; 741 args.size = size; 742 743 r4k_on_each_cpu(local_r4k_flush_kernel_vmap_range, &args); 744 } 745 746 static inline void rm7k_erratum31(void) 747 { 748 const unsigned long ic_lsize = 32; 749 unsigned long addr; 750 751 /* RM7000 erratum #31. The icache is screwed at startup. */ 752 write_c0_taglo(0); 753 write_c0_taghi(0); 754 755 for (addr = INDEX_BASE; addr <= INDEX_BASE + 4096; addr += ic_lsize) { 756 __asm__ __volatile__ ( 757 ".set push\n\t" 758 ".set noreorder\n\t" 759 ".set mips3\n\t" 760 "cache\t%1, 0(%0)\n\t" 761 "cache\t%1, 0x1000(%0)\n\t" 762 "cache\t%1, 0x2000(%0)\n\t" 763 "cache\t%1, 0x3000(%0)\n\t" 764 "cache\t%2, 0(%0)\n\t" 765 "cache\t%2, 0x1000(%0)\n\t" 766 "cache\t%2, 0x2000(%0)\n\t" 767 "cache\t%2, 0x3000(%0)\n\t" 768 "cache\t%1, 0(%0)\n\t" 769 "cache\t%1, 0x1000(%0)\n\t" 770 "cache\t%1, 0x2000(%0)\n\t" 771 "cache\t%1, 0x3000(%0)\n\t" 772 ".set pop\n" 773 : 774 : "r" (addr), "i" (Index_Store_Tag_I), "i" (Fill)); 775 } 776 } 777 778 static inline void alias_74k_erratum(struct cpuinfo_mips *c) 779 { 780 /* 781 * Early versions of the 74K do not update the cache tags on a 782 * vtag miss/ptag hit which can occur in the case of KSEG0/KUSEG 783 * aliases. In this case it is better to treat the cache as always 784 * having aliases. 785 */ 786 if ((c->processor_id & 0xff) <= PRID_REV_ENCODE_332(2, 4, 0)) 787 c->dcache.flags |= MIPS_CACHE_VTAG; 788 if ((c->processor_id & 0xff) == PRID_REV_ENCODE_332(2, 4, 0)) 789 write_c0_config6(read_c0_config6() | MIPS_CONF6_SYND); 790 if (((c->processor_id & 0xff00) == PRID_IMP_1074K) && 791 ((c->processor_id & 0xff) <= PRID_REV_ENCODE_332(1, 1, 0))) { 792 c->dcache.flags |= MIPS_CACHE_VTAG; 793 write_c0_config6(read_c0_config6() | MIPS_CONF6_SYND); 794 } 795 } 796 797 static char *way_string[] __cpuinitdata = { NULL, "direct mapped", "2-way", 798 "3-way", "4-way", "5-way", "6-way", "7-way", "8-way" 799 }; 800 801 static void __cpuinit probe_pcache(void) 802 { 803 struct cpuinfo_mips *c = ¤t_cpu_data; 804 unsigned int config = read_c0_config(); 805 unsigned int prid = read_c0_prid(); 806 unsigned long config1; 807 unsigned int lsize; 808 809 switch (c->cputype) { 810 case CPU_R4600: /* QED style two way caches? */ 811 case CPU_R4700: 812 case CPU_R5000: 813 case CPU_NEVADA: 814 icache_size = 1 << (12 + ((config & CONF_IC) >> 9)); 815 c->icache.linesz = 16 << ((config & CONF_IB) >> 5); 816 c->icache.ways = 2; 817 c->icache.waybit = __ffs(icache_size/2); 818 819 dcache_size = 1 << (12 + ((config & CONF_DC) >> 6)); 820 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4); 821 c->dcache.ways = 2; 822 c->dcache.waybit= __ffs(dcache_size/2); 823 824 c->options |= MIPS_CPU_CACHE_CDEX_P; 825 break; 826 827 case CPU_R5432: 828 case CPU_R5500: 829 icache_size = 1 << (12 + ((config & CONF_IC) >> 9)); 830 c->icache.linesz = 16 << ((config & CONF_IB) >> 5); 831 c->icache.ways = 2; 832 c->icache.waybit= 0; 833 834 dcache_size = 1 << (12 + ((config & CONF_DC) >> 6)); 835 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4); 836 c->dcache.ways = 2; 837 c->dcache.waybit = 0; 838 839 c->options |= MIPS_CPU_CACHE_CDEX_P | MIPS_CPU_PREFETCH; 840 break; 841 842 case CPU_TX49XX: 843 icache_size = 1 << (12 + ((config & CONF_IC) >> 9)); 844 c->icache.linesz = 16 << ((config & CONF_IB) >> 5); 845 c->icache.ways = 4; 846 c->icache.waybit= 0; 847 848 dcache_size = 1 << (12 + ((config & CONF_DC) >> 6)); 849 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4); 850 c->dcache.ways = 4; 851 c->dcache.waybit = 0; 852 853 c->options |= MIPS_CPU_CACHE_CDEX_P; 854 c->options |= MIPS_CPU_PREFETCH; 855 break; 856 857 case CPU_R4000PC: 858 case CPU_R4000SC: 859 case CPU_R4000MC: 860 case CPU_R4400PC: 861 case CPU_R4400SC: 862 case CPU_R4400MC: 863 case CPU_R4300: 864 icache_size = 1 << (12 + ((config & CONF_IC) >> 9)); 865 c->icache.linesz = 16 << ((config & CONF_IB) >> 5); 866 c->icache.ways = 1; 867 c->icache.waybit = 0; /* doesn't matter */ 868 869 dcache_size = 1 << (12 + ((config & CONF_DC) >> 6)); 870 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4); 871 c->dcache.ways = 1; 872 c->dcache.waybit = 0; /* does not matter */ 873 874 c->options |= MIPS_CPU_CACHE_CDEX_P; 875 break; 876 877 case CPU_R10000: 878 case CPU_R12000: 879 case CPU_R14000: 880 icache_size = 1 << (12 + ((config & R10K_CONF_IC) >> 29)); 881 c->icache.linesz = 64; 882 c->icache.ways = 2; 883 c->icache.waybit = 0; 884 885 dcache_size = 1 << (12 + ((config & R10K_CONF_DC) >> 26)); 886 c->dcache.linesz = 32; 887 c->dcache.ways = 2; 888 c->dcache.waybit = 0; 889 890 c->options |= MIPS_CPU_PREFETCH; 891 break; 892 893 case CPU_VR4133: 894 write_c0_config(config & ~VR41_CONF_P4K); 895 case CPU_VR4131: 896 /* Workaround for cache instruction bug of VR4131 */ 897 if (c->processor_id == 0x0c80U || c->processor_id == 0x0c81U || 898 c->processor_id == 0x0c82U) { 899 config |= 0x00400000U; 900 if (c->processor_id == 0x0c80U) 901 config |= VR41_CONF_BP; 902 write_c0_config(config); 903 } else 904 c->options |= MIPS_CPU_CACHE_CDEX_P; 905 906 icache_size = 1 << (10 + ((config & CONF_IC) >> 9)); 907 c->icache.linesz = 16 << ((config & CONF_IB) >> 5); 908 c->icache.ways = 2; 909 c->icache.waybit = __ffs(icache_size/2); 910 911 dcache_size = 1 << (10 + ((config & CONF_DC) >> 6)); 912 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4); 913 c->dcache.ways = 2; 914 c->dcache.waybit = __ffs(dcache_size/2); 915 break; 916 917 case CPU_VR41XX: 918 case CPU_VR4111: 919 case CPU_VR4121: 920 case CPU_VR4122: 921 case CPU_VR4181: 922 case CPU_VR4181A: 923 icache_size = 1 << (10 + ((config & CONF_IC) >> 9)); 924 c->icache.linesz = 16 << ((config & CONF_IB) >> 5); 925 c->icache.ways = 1; 926 c->icache.waybit = 0; /* doesn't matter */ 927 928 dcache_size = 1 << (10 + ((config & CONF_DC) >> 6)); 929 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4); 930 c->dcache.ways = 1; 931 c->dcache.waybit = 0; /* does not matter */ 932 933 c->options |= MIPS_CPU_CACHE_CDEX_P; 934 break; 935 936 case CPU_RM7000: 937 rm7k_erratum31(); 938 939 icache_size = 1 << (12 + ((config & CONF_IC) >> 9)); 940 c->icache.linesz = 16 << ((config & CONF_IB) >> 5); 941 c->icache.ways = 4; 942 c->icache.waybit = __ffs(icache_size / c->icache.ways); 943 944 dcache_size = 1 << (12 + ((config & CONF_DC) >> 6)); 945 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4); 946 c->dcache.ways = 4; 947 c->dcache.waybit = __ffs(dcache_size / c->dcache.ways); 948 949 c->options |= MIPS_CPU_CACHE_CDEX_P; 950 c->options |= MIPS_CPU_PREFETCH; 951 break; 952 953 case CPU_LOONGSON2: 954 icache_size = 1 << (12 + ((config & CONF_IC) >> 9)); 955 c->icache.linesz = 16 << ((config & CONF_IB) >> 5); 956 if (prid & 0x3) 957 c->icache.ways = 4; 958 else 959 c->icache.ways = 2; 960 c->icache.waybit = 0; 961 962 dcache_size = 1 << (12 + ((config & CONF_DC) >> 6)); 963 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4); 964 if (prid & 0x3) 965 c->dcache.ways = 4; 966 else 967 c->dcache.ways = 2; 968 c->dcache.waybit = 0; 969 break; 970 971 default: 972 if (!(config & MIPS_CONF_M)) 973 panic("Don't know how to probe P-caches on this cpu."); 974 975 /* 976 * So we seem to be a MIPS32 or MIPS64 CPU 977 * So let's probe the I-cache ... 978 */ 979 config1 = read_c0_config1(); 980 981 if ((lsize = ((config1 >> 19) & 7))) 982 c->icache.linesz = 2 << lsize; 983 else 984 c->icache.linesz = lsize; 985 c->icache.sets = 32 << (((config1 >> 22) + 1) & 7); 986 c->icache.ways = 1 + ((config1 >> 16) & 7); 987 988 icache_size = c->icache.sets * 989 c->icache.ways * 990 c->icache.linesz; 991 c->icache.waybit = __ffs(icache_size/c->icache.ways); 992 993 if (config & 0x8) /* VI bit */ 994 c->icache.flags |= MIPS_CACHE_VTAG; 995 996 /* 997 * Now probe the MIPS32 / MIPS64 data cache. 998 */ 999 c->dcache.flags = 0; 1000 1001 if ((lsize = ((config1 >> 10) & 7))) 1002 c->dcache.linesz = 2 << lsize; 1003 else 1004 c->dcache.linesz= lsize; 1005 c->dcache.sets = 32 << (((config1 >> 13) + 1) & 7); 1006 c->dcache.ways = 1 + ((config1 >> 7) & 7); 1007 1008 dcache_size = c->dcache.sets * 1009 c->dcache.ways * 1010 c->dcache.linesz; 1011 c->dcache.waybit = __ffs(dcache_size/c->dcache.ways); 1012 1013 c->options |= MIPS_CPU_PREFETCH; 1014 break; 1015 } 1016 1017 /* 1018 * Processor configuration sanity check for the R4000SC erratum 1019 * #5. With page sizes larger than 32kB there is no possibility 1020 * to get a VCE exception anymore so we don't care about this 1021 * misconfiguration. The case is rather theoretical anyway; 1022 * presumably no vendor is shipping his hardware in the "bad" 1023 * configuration. 1024 */ 1025 if ((prid & 0xff00) == PRID_IMP_R4000 && (prid & 0xff) < 0x40 && 1026 !(config & CONF_SC) && c->icache.linesz != 16 && 1027 PAGE_SIZE <= 0x8000) 1028 panic("Improper R4000SC processor configuration detected"); 1029 1030 /* compute a couple of other cache variables */ 1031 c->icache.waysize = icache_size / c->icache.ways; 1032 c->dcache.waysize = dcache_size / c->dcache.ways; 1033 1034 c->icache.sets = c->icache.linesz ? 1035 icache_size / (c->icache.linesz * c->icache.ways) : 0; 1036 c->dcache.sets = c->dcache.linesz ? 1037 dcache_size / (c->dcache.linesz * c->dcache.ways) : 0; 1038 1039 /* 1040 * R10000 and R12000 P-caches are odd in a positive way. They're 32kB 1041 * 2-way virtually indexed so normally would suffer from aliases. So 1042 * normally they'd suffer from aliases but magic in the hardware deals 1043 * with that for us so we don't need to take care ourselves. 1044 */ 1045 switch (c->cputype) { 1046 case CPU_20KC: 1047 case CPU_25KF: 1048 case CPU_SB1: 1049 case CPU_SB1A: 1050 case CPU_XLR: 1051 c->dcache.flags |= MIPS_CACHE_PINDEX; 1052 break; 1053 1054 case CPU_R10000: 1055 case CPU_R12000: 1056 case CPU_R14000: 1057 break; 1058 1059 case CPU_M14KC: 1060 case CPU_24K: 1061 case CPU_34K: 1062 case CPU_74K: 1063 case CPU_1004K: 1064 if (c->cputype == CPU_74K) 1065 alias_74k_erratum(c); 1066 if ((read_c0_config7() & (1 << 16))) { 1067 /* effectively physically indexed dcache, 1068 thus no virtual aliases. */ 1069 c->dcache.flags |= MIPS_CACHE_PINDEX; 1070 break; 1071 } 1072 default: 1073 if (c->dcache.waysize > PAGE_SIZE) 1074 c->dcache.flags |= MIPS_CACHE_ALIASES; 1075 } 1076 1077 switch (c->cputype) { 1078 case CPU_20KC: 1079 /* 1080 * Some older 20Kc chips doesn't have the 'VI' bit in 1081 * the config register. 1082 */ 1083 c->icache.flags |= MIPS_CACHE_VTAG; 1084 break; 1085 1086 case CPU_ALCHEMY: 1087 c->icache.flags |= MIPS_CACHE_IC_F_DC; 1088 break; 1089 } 1090 1091 #ifdef CONFIG_CPU_LOONGSON2 1092 /* 1093 * LOONGSON2 has 4 way icache, but when using indexed cache op, 1094 * one op will act on all 4 ways 1095 */ 1096 c->icache.ways = 1; 1097 #endif 1098 1099 printk("Primary instruction cache %ldkB, %s, %s, linesize %d bytes.\n", 1100 icache_size >> 10, 1101 c->icache.flags & MIPS_CACHE_VTAG ? "VIVT" : "VIPT", 1102 way_string[c->icache.ways], c->icache.linesz); 1103 1104 printk("Primary data cache %ldkB, %s, %s, %s, linesize %d bytes\n", 1105 dcache_size >> 10, way_string[c->dcache.ways], 1106 (c->dcache.flags & MIPS_CACHE_PINDEX) ? "PIPT" : "VIPT", 1107 (c->dcache.flags & MIPS_CACHE_ALIASES) ? 1108 "cache aliases" : "no aliases", 1109 c->dcache.linesz); 1110 } 1111 1112 /* 1113 * If you even _breathe_ on this function, look at the gcc output and make sure 1114 * it does not pop things on and off the stack for the cache sizing loop that 1115 * executes in KSEG1 space or else you will crash and burn badly. You have 1116 * been warned. 1117 */ 1118 static int __cpuinit probe_scache(void) 1119 { 1120 unsigned long flags, addr, begin, end, pow2; 1121 unsigned int config = read_c0_config(); 1122 struct cpuinfo_mips *c = ¤t_cpu_data; 1123 1124 if (config & CONF_SC) 1125 return 0; 1126 1127 begin = (unsigned long) &_stext; 1128 begin &= ~((4 * 1024 * 1024) - 1); 1129 end = begin + (4 * 1024 * 1024); 1130 1131 /* 1132 * This is such a bitch, you'd think they would make it easy to do 1133 * this. Away you daemons of stupidity! 1134 */ 1135 local_irq_save(flags); 1136 1137 /* Fill each size-multiple cache line with a valid tag. */ 1138 pow2 = (64 * 1024); 1139 for (addr = begin; addr < end; addr = (begin + pow2)) { 1140 unsigned long *p = (unsigned long *) addr; 1141 __asm__ __volatile__("nop" : : "r" (*p)); /* whee... */ 1142 pow2 <<= 1; 1143 } 1144 1145 /* Load first line with zero (therefore invalid) tag. */ 1146 write_c0_taglo(0); 1147 write_c0_taghi(0); 1148 __asm__ __volatile__("nop; nop; nop; nop;"); /* avoid the hazard */ 1149 cache_op(Index_Store_Tag_I, begin); 1150 cache_op(Index_Store_Tag_D, begin); 1151 cache_op(Index_Store_Tag_SD, begin); 1152 1153 /* Now search for the wrap around point. */ 1154 pow2 = (128 * 1024); 1155 for (addr = begin + (128 * 1024); addr < end; addr = begin + pow2) { 1156 cache_op(Index_Load_Tag_SD, addr); 1157 __asm__ __volatile__("nop; nop; nop; nop;"); /* hazard... */ 1158 if (!read_c0_taglo()) 1159 break; 1160 pow2 <<= 1; 1161 } 1162 local_irq_restore(flags); 1163 addr -= begin; 1164 1165 scache_size = addr; 1166 c->scache.linesz = 16 << ((config & R4K_CONF_SB) >> 22); 1167 c->scache.ways = 1; 1168 c->dcache.waybit = 0; /* does not matter */ 1169 1170 return 1; 1171 } 1172 1173 #if defined(CONFIG_CPU_LOONGSON2) 1174 static void __init loongson2_sc_init(void) 1175 { 1176 struct cpuinfo_mips *c = ¤t_cpu_data; 1177 1178 scache_size = 512*1024; 1179 c->scache.linesz = 32; 1180 c->scache.ways = 4; 1181 c->scache.waybit = 0; 1182 c->scache.waysize = scache_size / (c->scache.ways); 1183 c->scache.sets = scache_size / (c->scache.linesz * c->scache.ways); 1184 pr_info("Unified secondary cache %ldkB %s, linesize %d bytes.\n", 1185 scache_size >> 10, way_string[c->scache.ways], c->scache.linesz); 1186 1187 c->options |= MIPS_CPU_INCLUSIVE_CACHES; 1188 } 1189 #endif 1190 1191 extern int r5k_sc_init(void); 1192 extern int rm7k_sc_init(void); 1193 extern int mips_sc_init(void); 1194 1195 static void __cpuinit setup_scache(void) 1196 { 1197 struct cpuinfo_mips *c = ¤t_cpu_data; 1198 unsigned int config = read_c0_config(); 1199 int sc_present = 0; 1200 1201 /* 1202 * Do the probing thing on R4000SC and R4400SC processors. Other 1203 * processors don't have a S-cache that would be relevant to the 1204 * Linux memory management. 1205 */ 1206 switch (c->cputype) { 1207 case CPU_R4000SC: 1208 case CPU_R4000MC: 1209 case CPU_R4400SC: 1210 case CPU_R4400MC: 1211 sc_present = run_uncached(probe_scache); 1212 if (sc_present) 1213 c->options |= MIPS_CPU_CACHE_CDEX_S; 1214 break; 1215 1216 case CPU_R10000: 1217 case CPU_R12000: 1218 case CPU_R14000: 1219 scache_size = 0x80000 << ((config & R10K_CONF_SS) >> 16); 1220 c->scache.linesz = 64 << ((config >> 13) & 1); 1221 c->scache.ways = 2; 1222 c->scache.waybit= 0; 1223 sc_present = 1; 1224 break; 1225 1226 case CPU_R5000: 1227 case CPU_NEVADA: 1228 #ifdef CONFIG_R5000_CPU_SCACHE 1229 r5k_sc_init(); 1230 #endif 1231 return; 1232 1233 case CPU_RM7000: 1234 #ifdef CONFIG_RM7000_CPU_SCACHE 1235 rm7k_sc_init(); 1236 #endif 1237 return; 1238 1239 #if defined(CONFIG_CPU_LOONGSON2) 1240 case CPU_LOONGSON2: 1241 loongson2_sc_init(); 1242 return; 1243 #endif 1244 case CPU_XLP: 1245 /* don't need to worry about L2, fully coherent */ 1246 return; 1247 1248 default: 1249 if (c->isa_level == MIPS_CPU_ISA_M32R1 || 1250 c->isa_level == MIPS_CPU_ISA_M32R2 || 1251 c->isa_level == MIPS_CPU_ISA_M64R1 || 1252 c->isa_level == MIPS_CPU_ISA_M64R2) { 1253 #ifdef CONFIG_MIPS_CPU_SCACHE 1254 if (mips_sc_init ()) { 1255 scache_size = c->scache.ways * c->scache.sets * c->scache.linesz; 1256 printk("MIPS secondary cache %ldkB, %s, linesize %d bytes.\n", 1257 scache_size >> 10, 1258 way_string[c->scache.ways], c->scache.linesz); 1259 } 1260 #else 1261 if (!(c->scache.flags & MIPS_CACHE_NOT_PRESENT)) 1262 panic("Dunno how to handle MIPS32 / MIPS64 second level cache"); 1263 #endif 1264 return; 1265 } 1266 sc_present = 0; 1267 } 1268 1269 if (!sc_present) 1270 return; 1271 1272 /* compute a couple of other cache variables */ 1273 c->scache.waysize = scache_size / c->scache.ways; 1274 1275 c->scache.sets = scache_size / (c->scache.linesz * c->scache.ways); 1276 1277 printk("Unified secondary cache %ldkB %s, linesize %d bytes.\n", 1278 scache_size >> 10, way_string[c->scache.ways], c->scache.linesz); 1279 1280 c->options |= MIPS_CPU_INCLUSIVE_CACHES; 1281 } 1282 1283 void au1x00_fixup_config_od(void) 1284 { 1285 /* 1286 * c0_config.od (bit 19) was write only (and read as 0) 1287 * on the early revisions of Alchemy SOCs. It disables the bus 1288 * transaction overlapping and needs to be set to fix various errata. 1289 */ 1290 switch (read_c0_prid()) { 1291 case 0x00030100: /* Au1000 DA */ 1292 case 0x00030201: /* Au1000 HA */ 1293 case 0x00030202: /* Au1000 HB */ 1294 case 0x01030200: /* Au1500 AB */ 1295 /* 1296 * Au1100 errata actually keeps silence about this bit, so we set it 1297 * just in case for those revisions that require it to be set according 1298 * to the (now gone) cpu table. 1299 */ 1300 case 0x02030200: /* Au1100 AB */ 1301 case 0x02030201: /* Au1100 BA */ 1302 case 0x02030202: /* Au1100 BC */ 1303 set_c0_config(1 << 19); 1304 break; 1305 } 1306 } 1307 1308 /* CP0 hazard avoidance. */ 1309 #define NXP_BARRIER() \ 1310 __asm__ __volatile__( \ 1311 ".set noreorder\n\t" \ 1312 "nop; nop; nop; nop; nop; nop;\n\t" \ 1313 ".set reorder\n\t") 1314 1315 static void nxp_pr4450_fixup_config(void) 1316 { 1317 unsigned long config0; 1318 1319 config0 = read_c0_config(); 1320 1321 /* clear all three cache coherency fields */ 1322 config0 &= ~(0x7 | (7 << 25) | (7 << 28)); 1323 config0 |= (((_page_cachable_default >> _CACHE_SHIFT) << 0) | 1324 ((_page_cachable_default >> _CACHE_SHIFT) << 25) | 1325 ((_page_cachable_default >> _CACHE_SHIFT) << 28)); 1326 write_c0_config(config0); 1327 NXP_BARRIER(); 1328 } 1329 1330 static int __cpuinitdata cca = -1; 1331 1332 static int __init cca_setup(char *str) 1333 { 1334 get_option(&str, &cca); 1335 1336 return 0; 1337 } 1338 1339 early_param("cca", cca_setup); 1340 1341 static void __cpuinit coherency_setup(void) 1342 { 1343 if (cca < 0 || cca > 7) 1344 cca = read_c0_config() & CONF_CM_CMASK; 1345 _page_cachable_default = cca << _CACHE_SHIFT; 1346 1347 pr_debug("Using cache attribute %d\n", cca); 1348 change_c0_config(CONF_CM_CMASK, cca); 1349 1350 /* 1351 * c0_status.cu=0 specifies that updates by the sc instruction use 1352 * the coherency mode specified by the TLB; 1 means cachable 1353 * coherent update on write will be used. Not all processors have 1354 * this bit and; some wire it to zero, others like Toshiba had the 1355 * silly idea of putting something else there ... 1356 */ 1357 switch (current_cpu_type()) { 1358 case CPU_R4000PC: 1359 case CPU_R4000SC: 1360 case CPU_R4000MC: 1361 case CPU_R4400PC: 1362 case CPU_R4400SC: 1363 case CPU_R4400MC: 1364 clear_c0_config(CONF_CU); 1365 break; 1366 /* 1367 * We need to catch the early Alchemy SOCs with 1368 * the write-only co_config.od bit and set it back to one on: 1369 * Au1000 rev DA, HA, HB; Au1100 AB, BA, BC, Au1500 AB 1370 */ 1371 case CPU_ALCHEMY: 1372 au1x00_fixup_config_od(); 1373 break; 1374 1375 case PRID_IMP_PR4450: 1376 nxp_pr4450_fixup_config(); 1377 break; 1378 } 1379 } 1380 1381 #if defined(CONFIG_DMA_NONCOHERENT) 1382 1383 static int __cpuinitdata coherentio; 1384 1385 static int __init setcoherentio(char *str) 1386 { 1387 coherentio = 1; 1388 1389 return 0; 1390 } 1391 1392 early_param("coherentio", setcoherentio); 1393 #endif 1394 1395 static void __cpuinit r4k_cache_error_setup(void) 1396 { 1397 extern char __weak except_vec2_generic; 1398 extern char __weak except_vec2_sb1; 1399 struct cpuinfo_mips *c = ¤t_cpu_data; 1400 1401 switch (c->cputype) { 1402 case CPU_SB1: 1403 case CPU_SB1A: 1404 set_uncached_handler(0x100, &except_vec2_sb1, 0x80); 1405 break; 1406 1407 default: 1408 set_uncached_handler(0x100, &except_vec2_generic, 0x80); 1409 break; 1410 } 1411 } 1412 1413 void __cpuinit r4k_cache_init(void) 1414 { 1415 extern void build_clear_page(void); 1416 extern void build_copy_page(void); 1417 struct cpuinfo_mips *c = ¤t_cpu_data; 1418 1419 probe_pcache(); 1420 setup_scache(); 1421 1422 r4k_blast_dcache_page_setup(); 1423 r4k_blast_dcache_page_indexed_setup(); 1424 r4k_blast_dcache_setup(); 1425 r4k_blast_icache_page_setup(); 1426 r4k_blast_icache_page_indexed_setup(); 1427 r4k_blast_icache_setup(); 1428 r4k_blast_scache_page_setup(); 1429 r4k_blast_scache_page_indexed_setup(); 1430 r4k_blast_scache_setup(); 1431 1432 /* 1433 * Some MIPS32 and MIPS64 processors have physically indexed caches. 1434 * This code supports virtually indexed processors and will be 1435 * unnecessarily inefficient on physically indexed processors. 1436 */ 1437 if (c->dcache.linesz) 1438 shm_align_mask = max_t( unsigned long, 1439 c->dcache.sets * c->dcache.linesz - 1, 1440 PAGE_SIZE - 1); 1441 else 1442 shm_align_mask = PAGE_SIZE-1; 1443 1444 __flush_cache_vmap = r4k__flush_cache_vmap; 1445 __flush_cache_vunmap = r4k__flush_cache_vunmap; 1446 1447 flush_cache_all = cache_noop; 1448 __flush_cache_all = r4k___flush_cache_all; 1449 flush_cache_mm = r4k_flush_cache_mm; 1450 flush_cache_page = r4k_flush_cache_page; 1451 flush_cache_range = r4k_flush_cache_range; 1452 1453 __flush_kernel_vmap_range = r4k_flush_kernel_vmap_range; 1454 1455 flush_cache_sigtramp = r4k_flush_cache_sigtramp; 1456 flush_icache_all = r4k_flush_icache_all; 1457 local_flush_data_cache_page = local_r4k_flush_data_cache_page; 1458 flush_data_cache_page = r4k_flush_data_cache_page; 1459 flush_icache_range = r4k_flush_icache_range; 1460 local_flush_icache_range = local_r4k_flush_icache_range; 1461 1462 #if defined(CONFIG_DMA_NONCOHERENT) 1463 if (coherentio) { 1464 _dma_cache_wback_inv = (void *)cache_noop; 1465 _dma_cache_wback = (void *)cache_noop; 1466 _dma_cache_inv = (void *)cache_noop; 1467 } else { 1468 _dma_cache_wback_inv = r4k_dma_cache_wback_inv; 1469 _dma_cache_wback = r4k_dma_cache_wback_inv; 1470 _dma_cache_inv = r4k_dma_cache_inv; 1471 } 1472 #endif 1473 1474 build_clear_page(); 1475 build_copy_page(); 1476 #if !defined(CONFIG_MIPS_CMP) 1477 local_r4k___flush_cache_all(NULL); 1478 #endif 1479 coherency_setup(); 1480 board_cache_error_setup = r4k_cache_error_setup; 1481 } 1482