1 /* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * Copyright (C) 1996 David S. Miller (davem@davemloft.net) 7 * Copyright (C) 1997, 1998, 1999, 2000, 2001, 2002 Ralf Baechle (ralf@gnu.org) 8 * Copyright (C) 1999, 2000 Silicon Graphics, Inc. 9 */ 10 #include <linux/cpu_pm.h> 11 #include <linux/hardirq.h> 12 #include <linux/init.h> 13 #include <linux/highmem.h> 14 #include <linux/kernel.h> 15 #include <linux/linkage.h> 16 #include <linux/preempt.h> 17 #include <linux/sched.h> 18 #include <linux/smp.h> 19 #include <linux/mm.h> 20 #include <linux/export.h> 21 #include <linux/bitops.h> 22 23 #include <asm/bcache.h> 24 #include <asm/bootinfo.h> 25 #include <asm/cache.h> 26 #include <asm/cacheops.h> 27 #include <asm/cpu.h> 28 #include <asm/cpu-features.h> 29 #include <asm/cpu-type.h> 30 #include <asm/io.h> 31 #include <asm/page.h> 32 #include <asm/pgtable.h> 33 #include <asm/r4kcache.h> 34 #include <asm/sections.h> 35 #include <asm/mmu_context.h> 36 #include <asm/war.h> 37 #include <asm/cacheflush.h> /* for run_uncached() */ 38 #include <asm/traps.h> 39 #include <asm/dma-coherence.h> 40 #include <asm/mips-cps.h> 41 42 /* 43 * Bits describing what cache ops an SMP callback function may perform. 44 * 45 * R4K_HIT - Virtual user or kernel address based cache operations. The 46 * active_mm must be checked before using user addresses, falling 47 * back to kmap. 48 * R4K_INDEX - Index based cache operations. 49 */ 50 51 #define R4K_HIT BIT(0) 52 #define R4K_INDEX BIT(1) 53 54 /** 55 * r4k_op_needs_ipi() - Decide if a cache op needs to be done on every core. 56 * @type: Type of cache operations (R4K_HIT or R4K_INDEX). 57 * 58 * Decides whether a cache op needs to be performed on every core in the system. 59 * This may change depending on the @type of cache operation, as well as the set 60 * of online CPUs, so preemption should be disabled by the caller to prevent CPU 61 * hotplug from changing the result. 62 * 63 * Returns: 1 if the cache operation @type should be done on every core in 64 * the system. 65 * 0 if the cache operation @type is globalized and only needs to 66 * be performed on a simple CPU. 67 */ 68 static inline bool r4k_op_needs_ipi(unsigned int type) 69 { 70 /* The MIPS Coherence Manager (CM) globalizes address-based cache ops */ 71 if (type == R4K_HIT && mips_cm_present()) 72 return false; 73 74 /* 75 * Hardware doesn't globalize the required cache ops, so SMP calls may 76 * be needed, but only if there are foreign CPUs (non-siblings with 77 * separate caches). 78 */ 79 /* cpu_foreign_map[] undeclared when !CONFIG_SMP */ 80 #ifdef CONFIG_SMP 81 return !cpumask_empty(&cpu_foreign_map[0]); 82 #else 83 return false; 84 #endif 85 } 86 87 /* 88 * Special Variant of smp_call_function for use by cache functions: 89 * 90 * o No return value 91 * o collapses to normal function call on UP kernels 92 * o collapses to normal function call on systems with a single shared 93 * primary cache. 94 * o doesn't disable interrupts on the local CPU 95 */ 96 static inline void r4k_on_each_cpu(unsigned int type, 97 void (*func)(void *info), void *info) 98 { 99 preempt_disable(); 100 if (r4k_op_needs_ipi(type)) 101 smp_call_function_many(&cpu_foreign_map[smp_processor_id()], 102 func, info, 1); 103 func(info); 104 preempt_enable(); 105 } 106 107 /* 108 * Must die. 109 */ 110 static unsigned long icache_size __read_mostly; 111 static unsigned long dcache_size __read_mostly; 112 static unsigned long vcache_size __read_mostly; 113 static unsigned long scache_size __read_mostly; 114 115 /* 116 * Dummy cache handling routines for machines without boardcaches 117 */ 118 static void cache_noop(void) {} 119 120 static struct bcache_ops no_sc_ops = { 121 .bc_enable = (void *)cache_noop, 122 .bc_disable = (void *)cache_noop, 123 .bc_wback_inv = (void *)cache_noop, 124 .bc_inv = (void *)cache_noop 125 }; 126 127 struct bcache_ops *bcops = &no_sc_ops; 128 129 #define cpu_is_r4600_v1_x() ((read_c0_prid() & 0xfffffff0) == 0x00002010) 130 #define cpu_is_r4600_v2_x() ((read_c0_prid() & 0xfffffff0) == 0x00002020) 131 132 #define R4600_HIT_CACHEOP_WAR_IMPL \ 133 do { \ 134 if (R4600_V2_HIT_CACHEOP_WAR && cpu_is_r4600_v2_x()) \ 135 *(volatile unsigned long *)CKSEG1; \ 136 if (R4600_V1_HIT_CACHEOP_WAR) \ 137 __asm__ __volatile__("nop;nop;nop;nop"); \ 138 } while (0) 139 140 static void (*r4k_blast_dcache_page)(unsigned long addr); 141 142 static inline void r4k_blast_dcache_page_dc32(unsigned long addr) 143 { 144 R4600_HIT_CACHEOP_WAR_IMPL; 145 blast_dcache32_page(addr); 146 } 147 148 static inline void r4k_blast_dcache_page_dc64(unsigned long addr) 149 { 150 blast_dcache64_page(addr); 151 } 152 153 static inline void r4k_blast_dcache_page_dc128(unsigned long addr) 154 { 155 blast_dcache128_page(addr); 156 } 157 158 static void r4k_blast_dcache_page_setup(void) 159 { 160 unsigned long dc_lsize = cpu_dcache_line_size(); 161 162 switch (dc_lsize) { 163 case 0: 164 r4k_blast_dcache_page = (void *)cache_noop; 165 break; 166 case 16: 167 r4k_blast_dcache_page = blast_dcache16_page; 168 break; 169 case 32: 170 r4k_blast_dcache_page = r4k_blast_dcache_page_dc32; 171 break; 172 case 64: 173 r4k_blast_dcache_page = r4k_blast_dcache_page_dc64; 174 break; 175 case 128: 176 r4k_blast_dcache_page = r4k_blast_dcache_page_dc128; 177 break; 178 default: 179 break; 180 } 181 } 182 183 #ifndef CONFIG_EVA 184 #define r4k_blast_dcache_user_page r4k_blast_dcache_page 185 #else 186 187 static void (*r4k_blast_dcache_user_page)(unsigned long addr); 188 189 static void r4k_blast_dcache_user_page_setup(void) 190 { 191 unsigned long dc_lsize = cpu_dcache_line_size(); 192 193 if (dc_lsize == 0) 194 r4k_blast_dcache_user_page = (void *)cache_noop; 195 else if (dc_lsize == 16) 196 r4k_blast_dcache_user_page = blast_dcache16_user_page; 197 else if (dc_lsize == 32) 198 r4k_blast_dcache_user_page = blast_dcache32_user_page; 199 else if (dc_lsize == 64) 200 r4k_blast_dcache_user_page = blast_dcache64_user_page; 201 } 202 203 #endif 204 205 static void (* r4k_blast_dcache_page_indexed)(unsigned long addr); 206 207 static void r4k_blast_dcache_page_indexed_setup(void) 208 { 209 unsigned long dc_lsize = cpu_dcache_line_size(); 210 211 if (dc_lsize == 0) 212 r4k_blast_dcache_page_indexed = (void *)cache_noop; 213 else if (dc_lsize == 16) 214 r4k_blast_dcache_page_indexed = blast_dcache16_page_indexed; 215 else if (dc_lsize == 32) 216 r4k_blast_dcache_page_indexed = blast_dcache32_page_indexed; 217 else if (dc_lsize == 64) 218 r4k_blast_dcache_page_indexed = blast_dcache64_page_indexed; 219 else if (dc_lsize == 128) 220 r4k_blast_dcache_page_indexed = blast_dcache128_page_indexed; 221 } 222 223 void (* r4k_blast_dcache)(void); 224 EXPORT_SYMBOL(r4k_blast_dcache); 225 226 static void r4k_blast_dcache_setup(void) 227 { 228 unsigned long dc_lsize = cpu_dcache_line_size(); 229 230 if (dc_lsize == 0) 231 r4k_blast_dcache = (void *)cache_noop; 232 else if (dc_lsize == 16) 233 r4k_blast_dcache = blast_dcache16; 234 else if (dc_lsize == 32) 235 r4k_blast_dcache = blast_dcache32; 236 else if (dc_lsize == 64) 237 r4k_blast_dcache = blast_dcache64; 238 else if (dc_lsize == 128) 239 r4k_blast_dcache = blast_dcache128; 240 } 241 242 /* force code alignment (used for TX49XX_ICACHE_INDEX_INV_WAR) */ 243 #define JUMP_TO_ALIGN(order) \ 244 __asm__ __volatile__( \ 245 "b\t1f\n\t" \ 246 ".align\t" #order "\n\t" \ 247 "1:\n\t" \ 248 ) 249 #define CACHE32_UNROLL32_ALIGN JUMP_TO_ALIGN(10) /* 32 * 32 = 1024 */ 250 #define CACHE32_UNROLL32_ALIGN2 JUMP_TO_ALIGN(11) 251 252 static inline void blast_r4600_v1_icache32(void) 253 { 254 unsigned long flags; 255 256 local_irq_save(flags); 257 blast_icache32(); 258 local_irq_restore(flags); 259 } 260 261 static inline void tx49_blast_icache32(void) 262 { 263 unsigned long start = INDEX_BASE; 264 unsigned long end = start + current_cpu_data.icache.waysize; 265 unsigned long ws_inc = 1UL << current_cpu_data.icache.waybit; 266 unsigned long ws_end = current_cpu_data.icache.ways << 267 current_cpu_data.icache.waybit; 268 unsigned long ws, addr; 269 270 CACHE32_UNROLL32_ALIGN2; 271 /* I'm in even chunk. blast odd chunks */ 272 for (ws = 0; ws < ws_end; ws += ws_inc) 273 for (addr = start + 0x400; addr < end; addr += 0x400 * 2) 274 cache32_unroll32(addr|ws, Index_Invalidate_I); 275 CACHE32_UNROLL32_ALIGN; 276 /* I'm in odd chunk. blast even chunks */ 277 for (ws = 0; ws < ws_end; ws += ws_inc) 278 for (addr = start; addr < end; addr += 0x400 * 2) 279 cache32_unroll32(addr|ws, Index_Invalidate_I); 280 } 281 282 static inline void blast_icache32_r4600_v1_page_indexed(unsigned long page) 283 { 284 unsigned long flags; 285 286 local_irq_save(flags); 287 blast_icache32_page_indexed(page); 288 local_irq_restore(flags); 289 } 290 291 static inline void tx49_blast_icache32_page_indexed(unsigned long page) 292 { 293 unsigned long indexmask = current_cpu_data.icache.waysize - 1; 294 unsigned long start = INDEX_BASE + (page & indexmask); 295 unsigned long end = start + PAGE_SIZE; 296 unsigned long ws_inc = 1UL << current_cpu_data.icache.waybit; 297 unsigned long ws_end = current_cpu_data.icache.ways << 298 current_cpu_data.icache.waybit; 299 unsigned long ws, addr; 300 301 CACHE32_UNROLL32_ALIGN2; 302 /* I'm in even chunk. blast odd chunks */ 303 for (ws = 0; ws < ws_end; ws += ws_inc) 304 for (addr = start + 0x400; addr < end; addr += 0x400 * 2) 305 cache32_unroll32(addr|ws, Index_Invalidate_I); 306 CACHE32_UNROLL32_ALIGN; 307 /* I'm in odd chunk. blast even chunks */ 308 for (ws = 0; ws < ws_end; ws += ws_inc) 309 for (addr = start; addr < end; addr += 0x400 * 2) 310 cache32_unroll32(addr|ws, Index_Invalidate_I); 311 } 312 313 static void (* r4k_blast_icache_page)(unsigned long addr); 314 315 static void r4k_blast_icache_page_setup(void) 316 { 317 unsigned long ic_lsize = cpu_icache_line_size(); 318 319 if (ic_lsize == 0) 320 r4k_blast_icache_page = (void *)cache_noop; 321 else if (ic_lsize == 16) 322 r4k_blast_icache_page = blast_icache16_page; 323 else if (ic_lsize == 32 && current_cpu_type() == CPU_LOONGSON2) 324 r4k_blast_icache_page = loongson2_blast_icache32_page; 325 else if (ic_lsize == 32) 326 r4k_blast_icache_page = blast_icache32_page; 327 else if (ic_lsize == 64) 328 r4k_blast_icache_page = blast_icache64_page; 329 else if (ic_lsize == 128) 330 r4k_blast_icache_page = blast_icache128_page; 331 } 332 333 #ifndef CONFIG_EVA 334 #define r4k_blast_icache_user_page r4k_blast_icache_page 335 #else 336 337 static void (*r4k_blast_icache_user_page)(unsigned long addr); 338 339 static void r4k_blast_icache_user_page_setup(void) 340 { 341 unsigned long ic_lsize = cpu_icache_line_size(); 342 343 if (ic_lsize == 0) 344 r4k_blast_icache_user_page = (void *)cache_noop; 345 else if (ic_lsize == 16) 346 r4k_blast_icache_user_page = blast_icache16_user_page; 347 else if (ic_lsize == 32) 348 r4k_blast_icache_user_page = blast_icache32_user_page; 349 else if (ic_lsize == 64) 350 r4k_blast_icache_user_page = blast_icache64_user_page; 351 } 352 353 #endif 354 355 static void (* r4k_blast_icache_page_indexed)(unsigned long addr); 356 357 static void r4k_blast_icache_page_indexed_setup(void) 358 { 359 unsigned long ic_lsize = cpu_icache_line_size(); 360 361 if (ic_lsize == 0) 362 r4k_blast_icache_page_indexed = (void *)cache_noop; 363 else if (ic_lsize == 16) 364 r4k_blast_icache_page_indexed = blast_icache16_page_indexed; 365 else if (ic_lsize == 32) { 366 if (R4600_V1_INDEX_ICACHEOP_WAR && cpu_is_r4600_v1_x()) 367 r4k_blast_icache_page_indexed = 368 blast_icache32_r4600_v1_page_indexed; 369 else if (TX49XX_ICACHE_INDEX_INV_WAR) 370 r4k_blast_icache_page_indexed = 371 tx49_blast_icache32_page_indexed; 372 else if (current_cpu_type() == CPU_LOONGSON2) 373 r4k_blast_icache_page_indexed = 374 loongson2_blast_icache32_page_indexed; 375 else 376 r4k_blast_icache_page_indexed = 377 blast_icache32_page_indexed; 378 } else if (ic_lsize == 64) 379 r4k_blast_icache_page_indexed = blast_icache64_page_indexed; 380 } 381 382 void (* r4k_blast_icache)(void); 383 EXPORT_SYMBOL(r4k_blast_icache); 384 385 static void r4k_blast_icache_setup(void) 386 { 387 unsigned long ic_lsize = cpu_icache_line_size(); 388 389 if (ic_lsize == 0) 390 r4k_blast_icache = (void *)cache_noop; 391 else if (ic_lsize == 16) 392 r4k_blast_icache = blast_icache16; 393 else if (ic_lsize == 32) { 394 if (R4600_V1_INDEX_ICACHEOP_WAR && cpu_is_r4600_v1_x()) 395 r4k_blast_icache = blast_r4600_v1_icache32; 396 else if (TX49XX_ICACHE_INDEX_INV_WAR) 397 r4k_blast_icache = tx49_blast_icache32; 398 else if (current_cpu_type() == CPU_LOONGSON2) 399 r4k_blast_icache = loongson2_blast_icache32; 400 else 401 r4k_blast_icache = blast_icache32; 402 } else if (ic_lsize == 64) 403 r4k_blast_icache = blast_icache64; 404 else if (ic_lsize == 128) 405 r4k_blast_icache = blast_icache128; 406 } 407 408 static void (* r4k_blast_scache_page)(unsigned long addr); 409 410 static void r4k_blast_scache_page_setup(void) 411 { 412 unsigned long sc_lsize = cpu_scache_line_size(); 413 414 if (scache_size == 0) 415 r4k_blast_scache_page = (void *)cache_noop; 416 else if (sc_lsize == 16) 417 r4k_blast_scache_page = blast_scache16_page; 418 else if (sc_lsize == 32) 419 r4k_blast_scache_page = blast_scache32_page; 420 else if (sc_lsize == 64) 421 r4k_blast_scache_page = blast_scache64_page; 422 else if (sc_lsize == 128) 423 r4k_blast_scache_page = blast_scache128_page; 424 } 425 426 static void (* r4k_blast_scache_page_indexed)(unsigned long addr); 427 428 static void r4k_blast_scache_page_indexed_setup(void) 429 { 430 unsigned long sc_lsize = cpu_scache_line_size(); 431 432 if (scache_size == 0) 433 r4k_blast_scache_page_indexed = (void *)cache_noop; 434 else if (sc_lsize == 16) 435 r4k_blast_scache_page_indexed = blast_scache16_page_indexed; 436 else if (sc_lsize == 32) 437 r4k_blast_scache_page_indexed = blast_scache32_page_indexed; 438 else if (sc_lsize == 64) 439 r4k_blast_scache_page_indexed = blast_scache64_page_indexed; 440 else if (sc_lsize == 128) 441 r4k_blast_scache_page_indexed = blast_scache128_page_indexed; 442 } 443 444 static void (* r4k_blast_scache)(void); 445 446 static void r4k_blast_scache_setup(void) 447 { 448 unsigned long sc_lsize = cpu_scache_line_size(); 449 450 if (scache_size == 0) 451 r4k_blast_scache = (void *)cache_noop; 452 else if (sc_lsize == 16) 453 r4k_blast_scache = blast_scache16; 454 else if (sc_lsize == 32) 455 r4k_blast_scache = blast_scache32; 456 else if (sc_lsize == 64) 457 r4k_blast_scache = blast_scache64; 458 else if (sc_lsize == 128) 459 r4k_blast_scache = blast_scache128; 460 } 461 462 static inline void local_r4k___flush_cache_all(void * args) 463 { 464 switch (current_cpu_type()) { 465 case CPU_LOONGSON2: 466 case CPU_LOONGSON3: 467 case CPU_R4000SC: 468 case CPU_R4000MC: 469 case CPU_R4400SC: 470 case CPU_R4400MC: 471 case CPU_R10000: 472 case CPU_R12000: 473 case CPU_R14000: 474 case CPU_R16000: 475 /* 476 * These caches are inclusive caches, that is, if something 477 * is not cached in the S-cache, we know it also won't be 478 * in one of the primary caches. 479 */ 480 r4k_blast_scache(); 481 break; 482 483 case CPU_BMIPS5000: 484 r4k_blast_scache(); 485 __sync(); 486 break; 487 488 default: 489 r4k_blast_dcache(); 490 r4k_blast_icache(); 491 break; 492 } 493 } 494 495 static void r4k___flush_cache_all(void) 496 { 497 r4k_on_each_cpu(R4K_INDEX, local_r4k___flush_cache_all, NULL); 498 } 499 500 /** 501 * has_valid_asid() - Determine if an mm already has an ASID. 502 * @mm: Memory map. 503 * @type: R4K_HIT or R4K_INDEX, type of cache op. 504 * 505 * Determines whether @mm already has an ASID on any of the CPUs which cache ops 506 * of type @type within an r4k_on_each_cpu() call will affect. If 507 * r4k_on_each_cpu() does an SMP call to a single VPE in each core, then the 508 * scope of the operation is confined to sibling CPUs, otherwise all online CPUs 509 * will need to be checked. 510 * 511 * Must be called in non-preemptive context. 512 * 513 * Returns: 1 if the CPUs affected by @type cache ops have an ASID for @mm. 514 * 0 otherwise. 515 */ 516 static inline int has_valid_asid(const struct mm_struct *mm, unsigned int type) 517 { 518 unsigned int i; 519 const cpumask_t *mask = cpu_present_mask; 520 521 /* cpu_sibling_map[] undeclared when !CONFIG_SMP */ 522 #ifdef CONFIG_SMP 523 /* 524 * If r4k_on_each_cpu does SMP calls, it does them to a single VPE in 525 * each foreign core, so we only need to worry about siblings. 526 * Otherwise we need to worry about all present CPUs. 527 */ 528 if (r4k_op_needs_ipi(type)) 529 mask = &cpu_sibling_map[smp_processor_id()]; 530 #endif 531 for_each_cpu(i, mask) 532 if (cpu_context(i, mm)) 533 return 1; 534 return 0; 535 } 536 537 static void r4k__flush_cache_vmap(void) 538 { 539 r4k_blast_dcache(); 540 } 541 542 static void r4k__flush_cache_vunmap(void) 543 { 544 r4k_blast_dcache(); 545 } 546 547 /* 548 * Note: flush_tlb_range() assumes flush_cache_range() sufficiently flushes 549 * whole caches when vma is executable. 550 */ 551 static inline void local_r4k_flush_cache_range(void * args) 552 { 553 struct vm_area_struct *vma = args; 554 int exec = vma->vm_flags & VM_EXEC; 555 556 if (!has_valid_asid(vma->vm_mm, R4K_INDEX)) 557 return; 558 559 /* 560 * If dcache can alias, we must blast it since mapping is changing. 561 * If executable, we must ensure any dirty lines are written back far 562 * enough to be visible to icache. 563 */ 564 if (cpu_has_dc_aliases || (exec && !cpu_has_ic_fills_f_dc)) 565 r4k_blast_dcache(); 566 /* If executable, blast stale lines from icache */ 567 if (exec) 568 r4k_blast_icache(); 569 } 570 571 static void r4k_flush_cache_range(struct vm_area_struct *vma, 572 unsigned long start, unsigned long end) 573 { 574 int exec = vma->vm_flags & VM_EXEC; 575 576 if (cpu_has_dc_aliases || exec) 577 r4k_on_each_cpu(R4K_INDEX, local_r4k_flush_cache_range, vma); 578 } 579 580 static inline void local_r4k_flush_cache_mm(void * args) 581 { 582 struct mm_struct *mm = args; 583 584 if (!has_valid_asid(mm, R4K_INDEX)) 585 return; 586 587 /* 588 * Kludge alert. For obscure reasons R4000SC and R4400SC go nuts if we 589 * only flush the primary caches but R1x000 behave sane ... 590 * R4000SC and R4400SC indexed S-cache ops also invalidate primary 591 * caches, so we can bail out early. 592 */ 593 if (current_cpu_type() == CPU_R4000SC || 594 current_cpu_type() == CPU_R4000MC || 595 current_cpu_type() == CPU_R4400SC || 596 current_cpu_type() == CPU_R4400MC) { 597 r4k_blast_scache(); 598 return; 599 } 600 601 r4k_blast_dcache(); 602 } 603 604 static void r4k_flush_cache_mm(struct mm_struct *mm) 605 { 606 if (!cpu_has_dc_aliases) 607 return; 608 609 r4k_on_each_cpu(R4K_INDEX, local_r4k_flush_cache_mm, mm); 610 } 611 612 struct flush_cache_page_args { 613 struct vm_area_struct *vma; 614 unsigned long addr; 615 unsigned long pfn; 616 }; 617 618 static inline void local_r4k_flush_cache_page(void *args) 619 { 620 struct flush_cache_page_args *fcp_args = args; 621 struct vm_area_struct *vma = fcp_args->vma; 622 unsigned long addr = fcp_args->addr; 623 struct page *page = pfn_to_page(fcp_args->pfn); 624 int exec = vma->vm_flags & VM_EXEC; 625 struct mm_struct *mm = vma->vm_mm; 626 int map_coherent = 0; 627 pgd_t *pgdp; 628 pud_t *pudp; 629 pmd_t *pmdp; 630 pte_t *ptep; 631 void *vaddr; 632 633 /* 634 * If owns no valid ASID yet, cannot possibly have gotten 635 * this page into the cache. 636 */ 637 if (!has_valid_asid(mm, R4K_HIT)) 638 return; 639 640 addr &= PAGE_MASK; 641 pgdp = pgd_offset(mm, addr); 642 pudp = pud_offset(pgdp, addr); 643 pmdp = pmd_offset(pudp, addr); 644 ptep = pte_offset(pmdp, addr); 645 646 /* 647 * If the page isn't marked valid, the page cannot possibly be 648 * in the cache. 649 */ 650 if (!(pte_present(*ptep))) 651 return; 652 653 if ((mm == current->active_mm) && (pte_val(*ptep) & _PAGE_VALID)) 654 vaddr = NULL; 655 else { 656 /* 657 * Use kmap_coherent or kmap_atomic to do flushes for 658 * another ASID than the current one. 659 */ 660 map_coherent = (cpu_has_dc_aliases && 661 page_mapcount(page) && 662 !Page_dcache_dirty(page)); 663 if (map_coherent) 664 vaddr = kmap_coherent(page, addr); 665 else 666 vaddr = kmap_atomic(page); 667 addr = (unsigned long)vaddr; 668 } 669 670 if (cpu_has_dc_aliases || (exec && !cpu_has_ic_fills_f_dc)) { 671 vaddr ? r4k_blast_dcache_page(addr) : 672 r4k_blast_dcache_user_page(addr); 673 if (exec && !cpu_icache_snoops_remote_store) 674 r4k_blast_scache_page(addr); 675 } 676 if (exec) { 677 if (vaddr && cpu_has_vtag_icache && mm == current->active_mm) { 678 int cpu = smp_processor_id(); 679 680 if (cpu_context(cpu, mm) != 0) 681 drop_mmu_context(mm, cpu); 682 } else 683 vaddr ? r4k_blast_icache_page(addr) : 684 r4k_blast_icache_user_page(addr); 685 } 686 687 if (vaddr) { 688 if (map_coherent) 689 kunmap_coherent(); 690 else 691 kunmap_atomic(vaddr); 692 } 693 } 694 695 static void r4k_flush_cache_page(struct vm_area_struct *vma, 696 unsigned long addr, unsigned long pfn) 697 { 698 struct flush_cache_page_args args; 699 700 args.vma = vma; 701 args.addr = addr; 702 args.pfn = pfn; 703 704 r4k_on_each_cpu(R4K_HIT, local_r4k_flush_cache_page, &args); 705 } 706 707 static inline void local_r4k_flush_data_cache_page(void * addr) 708 { 709 r4k_blast_dcache_page((unsigned long) addr); 710 } 711 712 static void r4k_flush_data_cache_page(unsigned long addr) 713 { 714 if (in_atomic()) 715 local_r4k_flush_data_cache_page((void *)addr); 716 else 717 r4k_on_each_cpu(R4K_HIT, local_r4k_flush_data_cache_page, 718 (void *) addr); 719 } 720 721 struct flush_icache_range_args { 722 unsigned long start; 723 unsigned long end; 724 unsigned int type; 725 bool user; 726 }; 727 728 static inline void __local_r4k_flush_icache_range(unsigned long start, 729 unsigned long end, 730 unsigned int type, 731 bool user) 732 { 733 if (!cpu_has_ic_fills_f_dc) { 734 if (type == R4K_INDEX || 735 (type & R4K_INDEX && end - start >= dcache_size)) { 736 r4k_blast_dcache(); 737 } else { 738 R4600_HIT_CACHEOP_WAR_IMPL; 739 if (user) 740 protected_blast_dcache_range(start, end); 741 else 742 blast_dcache_range(start, end); 743 } 744 } 745 746 if (type == R4K_INDEX || 747 (type & R4K_INDEX && end - start > icache_size)) 748 r4k_blast_icache(); 749 else { 750 switch (boot_cpu_type()) { 751 case CPU_LOONGSON2: 752 protected_loongson2_blast_icache_range(start, end); 753 break; 754 755 default: 756 if (user) 757 protected_blast_icache_range(start, end); 758 else 759 blast_icache_range(start, end); 760 break; 761 } 762 } 763 } 764 765 static inline void local_r4k_flush_icache_range(unsigned long start, 766 unsigned long end) 767 { 768 __local_r4k_flush_icache_range(start, end, R4K_HIT | R4K_INDEX, false); 769 } 770 771 static inline void local_r4k_flush_icache_user_range(unsigned long start, 772 unsigned long end) 773 { 774 __local_r4k_flush_icache_range(start, end, R4K_HIT | R4K_INDEX, true); 775 } 776 777 static inline void local_r4k_flush_icache_range_ipi(void *args) 778 { 779 struct flush_icache_range_args *fir_args = args; 780 unsigned long start = fir_args->start; 781 unsigned long end = fir_args->end; 782 unsigned int type = fir_args->type; 783 bool user = fir_args->user; 784 785 __local_r4k_flush_icache_range(start, end, type, user); 786 } 787 788 static void __r4k_flush_icache_range(unsigned long start, unsigned long end, 789 bool user) 790 { 791 struct flush_icache_range_args args; 792 unsigned long size, cache_size; 793 794 args.start = start; 795 args.end = end; 796 args.type = R4K_HIT | R4K_INDEX; 797 args.user = user; 798 799 /* 800 * Indexed cache ops require an SMP call. 801 * Consider if that can or should be avoided. 802 */ 803 preempt_disable(); 804 if (r4k_op_needs_ipi(R4K_INDEX) && !r4k_op_needs_ipi(R4K_HIT)) { 805 /* 806 * If address-based cache ops don't require an SMP call, then 807 * use them exclusively for small flushes. 808 */ 809 size = end - start; 810 cache_size = icache_size; 811 if (!cpu_has_ic_fills_f_dc) { 812 size *= 2; 813 cache_size += dcache_size; 814 } 815 if (size <= cache_size) 816 args.type &= ~R4K_INDEX; 817 } 818 r4k_on_each_cpu(args.type, local_r4k_flush_icache_range_ipi, &args); 819 preempt_enable(); 820 instruction_hazard(); 821 } 822 823 static void r4k_flush_icache_range(unsigned long start, unsigned long end) 824 { 825 return __r4k_flush_icache_range(start, end, false); 826 } 827 828 static void r4k_flush_icache_user_range(unsigned long start, unsigned long end) 829 { 830 return __r4k_flush_icache_range(start, end, true); 831 } 832 833 #if defined(CONFIG_DMA_NONCOHERENT) || defined(CONFIG_DMA_MAYBE_COHERENT) 834 835 static void r4k_dma_cache_wback_inv(unsigned long addr, unsigned long size) 836 { 837 /* Catch bad driver code */ 838 BUG_ON(size == 0); 839 840 preempt_disable(); 841 if (cpu_has_inclusive_pcaches) { 842 if (size >= scache_size) 843 r4k_blast_scache(); 844 else 845 blast_scache_range(addr, addr + size); 846 preempt_enable(); 847 __sync(); 848 return; 849 } 850 851 /* 852 * Either no secondary cache or the available caches don't have the 853 * subset property so we have to flush the primary caches 854 * explicitly. 855 * If we would need IPI to perform an INDEX-type operation, then 856 * we have to use the HIT-type alternative as IPI cannot be used 857 * here due to interrupts possibly being disabled. 858 */ 859 if (!r4k_op_needs_ipi(R4K_INDEX) && size >= dcache_size) { 860 r4k_blast_dcache(); 861 } else { 862 R4600_HIT_CACHEOP_WAR_IMPL; 863 blast_dcache_range(addr, addr + size); 864 } 865 preempt_enable(); 866 867 bc_wback_inv(addr, size); 868 __sync(); 869 } 870 871 static void r4k_dma_cache_inv(unsigned long addr, unsigned long size) 872 { 873 /* Catch bad driver code */ 874 BUG_ON(size == 0); 875 876 preempt_disable(); 877 if (cpu_has_inclusive_pcaches) { 878 if (size >= scache_size) 879 r4k_blast_scache(); 880 else { 881 /* 882 * There is no clearly documented alignment requirement 883 * for the cache instruction on MIPS processors and 884 * some processors, among them the RM5200 and RM7000 885 * QED processors will throw an address error for cache 886 * hit ops with insufficient alignment. Solved by 887 * aligning the address to cache line size. 888 */ 889 blast_inv_scache_range(addr, addr + size); 890 } 891 preempt_enable(); 892 __sync(); 893 return; 894 } 895 896 if (!r4k_op_needs_ipi(R4K_INDEX) && size >= dcache_size) { 897 r4k_blast_dcache(); 898 } else { 899 R4600_HIT_CACHEOP_WAR_IMPL; 900 blast_inv_dcache_range(addr, addr + size); 901 } 902 preempt_enable(); 903 904 bc_inv(addr, size); 905 __sync(); 906 } 907 #endif /* CONFIG_DMA_NONCOHERENT || CONFIG_DMA_MAYBE_COHERENT */ 908 909 struct flush_cache_sigtramp_args { 910 struct mm_struct *mm; 911 struct page *page; 912 unsigned long addr; 913 }; 914 915 /* 916 * While we're protected against bad userland addresses we don't care 917 * very much about what happens in that case. Usually a segmentation 918 * fault will dump the process later on anyway ... 919 */ 920 static void local_r4k_flush_cache_sigtramp(void *args) 921 { 922 struct flush_cache_sigtramp_args *fcs_args = args; 923 unsigned long addr = fcs_args->addr; 924 struct page *page = fcs_args->page; 925 struct mm_struct *mm = fcs_args->mm; 926 int map_coherent = 0; 927 void *vaddr; 928 929 unsigned long ic_lsize = cpu_icache_line_size(); 930 unsigned long dc_lsize = cpu_dcache_line_size(); 931 unsigned long sc_lsize = cpu_scache_line_size(); 932 933 /* 934 * If owns no valid ASID yet, cannot possibly have gotten 935 * this page into the cache. 936 */ 937 if (!has_valid_asid(mm, R4K_HIT)) 938 return; 939 940 if (mm == current->active_mm) { 941 vaddr = NULL; 942 } else { 943 /* 944 * Use kmap_coherent or kmap_atomic to do flushes for 945 * another ASID than the current one. 946 */ 947 map_coherent = (cpu_has_dc_aliases && 948 page_mapcount(page) && 949 !Page_dcache_dirty(page)); 950 if (map_coherent) 951 vaddr = kmap_coherent(page, addr); 952 else 953 vaddr = kmap_atomic(page); 954 addr = (unsigned long)vaddr + (addr & ~PAGE_MASK); 955 } 956 957 R4600_HIT_CACHEOP_WAR_IMPL; 958 if (!cpu_has_ic_fills_f_dc) { 959 if (dc_lsize) 960 vaddr ? flush_dcache_line(addr & ~(dc_lsize - 1)) 961 : protected_writeback_dcache_line( 962 addr & ~(dc_lsize - 1)); 963 if (!cpu_icache_snoops_remote_store && scache_size) 964 vaddr ? flush_scache_line(addr & ~(sc_lsize - 1)) 965 : protected_writeback_scache_line( 966 addr & ~(sc_lsize - 1)); 967 } 968 if (ic_lsize) 969 vaddr ? flush_icache_line(addr & ~(ic_lsize - 1)) 970 : protected_flush_icache_line(addr & ~(ic_lsize - 1)); 971 972 if (vaddr) { 973 if (map_coherent) 974 kunmap_coherent(); 975 else 976 kunmap_atomic(vaddr); 977 } 978 979 if (MIPS4K_ICACHE_REFILL_WAR) { 980 __asm__ __volatile__ ( 981 ".set push\n\t" 982 ".set noat\n\t" 983 ".set "MIPS_ISA_LEVEL"\n\t" 984 #ifdef CONFIG_32BIT 985 "la $at,1f\n\t" 986 #endif 987 #ifdef CONFIG_64BIT 988 "dla $at,1f\n\t" 989 #endif 990 "cache %0,($at)\n\t" 991 "nop; nop; nop\n" 992 "1:\n\t" 993 ".set pop" 994 : 995 : "i" (Hit_Invalidate_I)); 996 } 997 if (MIPS_CACHE_SYNC_WAR) 998 __asm__ __volatile__ ("sync"); 999 } 1000 1001 static void r4k_flush_cache_sigtramp(unsigned long addr) 1002 { 1003 struct flush_cache_sigtramp_args args; 1004 int npages; 1005 1006 down_read(¤t->mm->mmap_sem); 1007 1008 npages = get_user_pages_fast(addr, 1, 0, &args.page); 1009 if (npages < 1) 1010 goto out; 1011 1012 args.mm = current->mm; 1013 args.addr = addr; 1014 1015 r4k_on_each_cpu(R4K_HIT, local_r4k_flush_cache_sigtramp, &args); 1016 1017 put_page(args.page); 1018 out: 1019 up_read(¤t->mm->mmap_sem); 1020 } 1021 1022 static void r4k_flush_icache_all(void) 1023 { 1024 if (cpu_has_vtag_icache) 1025 r4k_blast_icache(); 1026 } 1027 1028 struct flush_kernel_vmap_range_args { 1029 unsigned long vaddr; 1030 int size; 1031 }; 1032 1033 static inline void local_r4k_flush_kernel_vmap_range_index(void *args) 1034 { 1035 /* 1036 * Aliases only affect the primary caches so don't bother with 1037 * S-caches or T-caches. 1038 */ 1039 r4k_blast_dcache(); 1040 } 1041 1042 static inline void local_r4k_flush_kernel_vmap_range(void *args) 1043 { 1044 struct flush_kernel_vmap_range_args *vmra = args; 1045 unsigned long vaddr = vmra->vaddr; 1046 int size = vmra->size; 1047 1048 /* 1049 * Aliases only affect the primary caches so don't bother with 1050 * S-caches or T-caches. 1051 */ 1052 R4600_HIT_CACHEOP_WAR_IMPL; 1053 blast_dcache_range(vaddr, vaddr + size); 1054 } 1055 1056 static void r4k_flush_kernel_vmap_range(unsigned long vaddr, int size) 1057 { 1058 struct flush_kernel_vmap_range_args args; 1059 1060 args.vaddr = (unsigned long) vaddr; 1061 args.size = size; 1062 1063 if (size >= dcache_size) 1064 r4k_on_each_cpu(R4K_INDEX, 1065 local_r4k_flush_kernel_vmap_range_index, NULL); 1066 else 1067 r4k_on_each_cpu(R4K_HIT, local_r4k_flush_kernel_vmap_range, 1068 &args); 1069 } 1070 1071 static inline void rm7k_erratum31(void) 1072 { 1073 const unsigned long ic_lsize = 32; 1074 unsigned long addr; 1075 1076 /* RM7000 erratum #31. The icache is screwed at startup. */ 1077 write_c0_taglo(0); 1078 write_c0_taghi(0); 1079 1080 for (addr = INDEX_BASE; addr <= INDEX_BASE + 4096; addr += ic_lsize) { 1081 __asm__ __volatile__ ( 1082 ".set push\n\t" 1083 ".set noreorder\n\t" 1084 ".set mips3\n\t" 1085 "cache\t%1, 0(%0)\n\t" 1086 "cache\t%1, 0x1000(%0)\n\t" 1087 "cache\t%1, 0x2000(%0)\n\t" 1088 "cache\t%1, 0x3000(%0)\n\t" 1089 "cache\t%2, 0(%0)\n\t" 1090 "cache\t%2, 0x1000(%0)\n\t" 1091 "cache\t%2, 0x2000(%0)\n\t" 1092 "cache\t%2, 0x3000(%0)\n\t" 1093 "cache\t%1, 0(%0)\n\t" 1094 "cache\t%1, 0x1000(%0)\n\t" 1095 "cache\t%1, 0x2000(%0)\n\t" 1096 "cache\t%1, 0x3000(%0)\n\t" 1097 ".set pop\n" 1098 : 1099 : "r" (addr), "i" (Index_Store_Tag_I), "i" (Fill)); 1100 } 1101 } 1102 1103 static inline int alias_74k_erratum(struct cpuinfo_mips *c) 1104 { 1105 unsigned int imp = c->processor_id & PRID_IMP_MASK; 1106 unsigned int rev = c->processor_id & PRID_REV_MASK; 1107 int present = 0; 1108 1109 /* 1110 * Early versions of the 74K do not update the cache tags on a 1111 * vtag miss/ptag hit which can occur in the case of KSEG0/KUSEG 1112 * aliases. In this case it is better to treat the cache as always 1113 * having aliases. Also disable the synonym tag update feature 1114 * where available. In this case no opportunistic tag update will 1115 * happen where a load causes a virtual address miss but a physical 1116 * address hit during a D-cache look-up. 1117 */ 1118 switch (imp) { 1119 case PRID_IMP_74K: 1120 if (rev <= PRID_REV_ENCODE_332(2, 4, 0)) 1121 present = 1; 1122 if (rev == PRID_REV_ENCODE_332(2, 4, 0)) 1123 write_c0_config6(read_c0_config6() | MIPS_CONF6_SYND); 1124 break; 1125 case PRID_IMP_1074K: 1126 if (rev <= PRID_REV_ENCODE_332(1, 1, 0)) { 1127 present = 1; 1128 write_c0_config6(read_c0_config6() | MIPS_CONF6_SYND); 1129 } 1130 break; 1131 default: 1132 BUG(); 1133 } 1134 1135 return present; 1136 } 1137 1138 static void b5k_instruction_hazard(void) 1139 { 1140 __sync(); 1141 __sync(); 1142 __asm__ __volatile__( 1143 " nop; nop; nop; nop; nop; nop; nop; nop\n" 1144 " nop; nop; nop; nop; nop; nop; nop; nop\n" 1145 " nop; nop; nop; nop; nop; nop; nop; nop\n" 1146 " nop; nop; nop; nop; nop; nop; nop; nop\n" 1147 : : : "memory"); 1148 } 1149 1150 static char *way_string[] = { NULL, "direct mapped", "2-way", 1151 "3-way", "4-way", "5-way", "6-way", "7-way", "8-way", 1152 "9-way", "10-way", "11-way", "12-way", 1153 "13-way", "14-way", "15-way", "16-way", 1154 }; 1155 1156 static void probe_pcache(void) 1157 { 1158 struct cpuinfo_mips *c = ¤t_cpu_data; 1159 unsigned int config = read_c0_config(); 1160 unsigned int prid = read_c0_prid(); 1161 int has_74k_erratum = 0; 1162 unsigned long config1; 1163 unsigned int lsize; 1164 1165 switch (current_cpu_type()) { 1166 case CPU_R4600: /* QED style two way caches? */ 1167 case CPU_R4700: 1168 case CPU_R5000: 1169 case CPU_NEVADA: 1170 icache_size = 1 << (12 + ((config & CONF_IC) >> 9)); 1171 c->icache.linesz = 16 << ((config & CONF_IB) >> 5); 1172 c->icache.ways = 2; 1173 c->icache.waybit = __ffs(icache_size/2); 1174 1175 dcache_size = 1 << (12 + ((config & CONF_DC) >> 6)); 1176 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4); 1177 c->dcache.ways = 2; 1178 c->dcache.waybit= __ffs(dcache_size/2); 1179 1180 c->options |= MIPS_CPU_CACHE_CDEX_P; 1181 break; 1182 1183 case CPU_R5432: 1184 case CPU_R5500: 1185 icache_size = 1 << (12 + ((config & CONF_IC) >> 9)); 1186 c->icache.linesz = 16 << ((config & CONF_IB) >> 5); 1187 c->icache.ways = 2; 1188 c->icache.waybit= 0; 1189 1190 dcache_size = 1 << (12 + ((config & CONF_DC) >> 6)); 1191 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4); 1192 c->dcache.ways = 2; 1193 c->dcache.waybit = 0; 1194 1195 c->options |= MIPS_CPU_CACHE_CDEX_P | MIPS_CPU_PREFETCH; 1196 break; 1197 1198 case CPU_TX49XX: 1199 icache_size = 1 << (12 + ((config & CONF_IC) >> 9)); 1200 c->icache.linesz = 16 << ((config & CONF_IB) >> 5); 1201 c->icache.ways = 4; 1202 c->icache.waybit= 0; 1203 1204 dcache_size = 1 << (12 + ((config & CONF_DC) >> 6)); 1205 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4); 1206 c->dcache.ways = 4; 1207 c->dcache.waybit = 0; 1208 1209 c->options |= MIPS_CPU_CACHE_CDEX_P; 1210 c->options |= MIPS_CPU_PREFETCH; 1211 break; 1212 1213 case CPU_R4000PC: 1214 case CPU_R4000SC: 1215 case CPU_R4000MC: 1216 case CPU_R4400PC: 1217 case CPU_R4400SC: 1218 case CPU_R4400MC: 1219 case CPU_R4300: 1220 icache_size = 1 << (12 + ((config & CONF_IC) >> 9)); 1221 c->icache.linesz = 16 << ((config & CONF_IB) >> 5); 1222 c->icache.ways = 1; 1223 c->icache.waybit = 0; /* doesn't matter */ 1224 1225 dcache_size = 1 << (12 + ((config & CONF_DC) >> 6)); 1226 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4); 1227 c->dcache.ways = 1; 1228 c->dcache.waybit = 0; /* does not matter */ 1229 1230 c->options |= MIPS_CPU_CACHE_CDEX_P; 1231 break; 1232 1233 case CPU_R10000: 1234 case CPU_R12000: 1235 case CPU_R14000: 1236 case CPU_R16000: 1237 icache_size = 1 << (12 + ((config & R10K_CONF_IC) >> 29)); 1238 c->icache.linesz = 64; 1239 c->icache.ways = 2; 1240 c->icache.waybit = 0; 1241 1242 dcache_size = 1 << (12 + ((config & R10K_CONF_DC) >> 26)); 1243 c->dcache.linesz = 32; 1244 c->dcache.ways = 2; 1245 c->dcache.waybit = 0; 1246 1247 c->options |= MIPS_CPU_PREFETCH; 1248 break; 1249 1250 case CPU_VR4133: 1251 write_c0_config(config & ~VR41_CONF_P4K); 1252 case CPU_VR4131: 1253 /* Workaround for cache instruction bug of VR4131 */ 1254 if (c->processor_id == 0x0c80U || c->processor_id == 0x0c81U || 1255 c->processor_id == 0x0c82U) { 1256 config |= 0x00400000U; 1257 if (c->processor_id == 0x0c80U) 1258 config |= VR41_CONF_BP; 1259 write_c0_config(config); 1260 } else 1261 c->options |= MIPS_CPU_CACHE_CDEX_P; 1262 1263 icache_size = 1 << (10 + ((config & CONF_IC) >> 9)); 1264 c->icache.linesz = 16 << ((config & CONF_IB) >> 5); 1265 c->icache.ways = 2; 1266 c->icache.waybit = __ffs(icache_size/2); 1267 1268 dcache_size = 1 << (10 + ((config & CONF_DC) >> 6)); 1269 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4); 1270 c->dcache.ways = 2; 1271 c->dcache.waybit = __ffs(dcache_size/2); 1272 break; 1273 1274 case CPU_VR41XX: 1275 case CPU_VR4111: 1276 case CPU_VR4121: 1277 case CPU_VR4122: 1278 case CPU_VR4181: 1279 case CPU_VR4181A: 1280 icache_size = 1 << (10 + ((config & CONF_IC) >> 9)); 1281 c->icache.linesz = 16 << ((config & CONF_IB) >> 5); 1282 c->icache.ways = 1; 1283 c->icache.waybit = 0; /* doesn't matter */ 1284 1285 dcache_size = 1 << (10 + ((config & CONF_DC) >> 6)); 1286 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4); 1287 c->dcache.ways = 1; 1288 c->dcache.waybit = 0; /* does not matter */ 1289 1290 c->options |= MIPS_CPU_CACHE_CDEX_P; 1291 break; 1292 1293 case CPU_RM7000: 1294 rm7k_erratum31(); 1295 1296 icache_size = 1 << (12 + ((config & CONF_IC) >> 9)); 1297 c->icache.linesz = 16 << ((config & CONF_IB) >> 5); 1298 c->icache.ways = 4; 1299 c->icache.waybit = __ffs(icache_size / c->icache.ways); 1300 1301 dcache_size = 1 << (12 + ((config & CONF_DC) >> 6)); 1302 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4); 1303 c->dcache.ways = 4; 1304 c->dcache.waybit = __ffs(dcache_size / c->dcache.ways); 1305 1306 c->options |= MIPS_CPU_CACHE_CDEX_P; 1307 c->options |= MIPS_CPU_PREFETCH; 1308 break; 1309 1310 case CPU_LOONGSON2: 1311 icache_size = 1 << (12 + ((config & CONF_IC) >> 9)); 1312 c->icache.linesz = 16 << ((config & CONF_IB) >> 5); 1313 if (prid & 0x3) 1314 c->icache.ways = 4; 1315 else 1316 c->icache.ways = 2; 1317 c->icache.waybit = 0; 1318 1319 dcache_size = 1 << (12 + ((config & CONF_DC) >> 6)); 1320 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4); 1321 if (prid & 0x3) 1322 c->dcache.ways = 4; 1323 else 1324 c->dcache.ways = 2; 1325 c->dcache.waybit = 0; 1326 break; 1327 1328 case CPU_LOONGSON3: 1329 config1 = read_c0_config1(); 1330 lsize = (config1 >> 19) & 7; 1331 if (lsize) 1332 c->icache.linesz = 2 << lsize; 1333 else 1334 c->icache.linesz = 0; 1335 c->icache.sets = 64 << ((config1 >> 22) & 7); 1336 c->icache.ways = 1 + ((config1 >> 16) & 7); 1337 icache_size = c->icache.sets * 1338 c->icache.ways * 1339 c->icache.linesz; 1340 c->icache.waybit = 0; 1341 1342 lsize = (config1 >> 10) & 7; 1343 if (lsize) 1344 c->dcache.linesz = 2 << lsize; 1345 else 1346 c->dcache.linesz = 0; 1347 c->dcache.sets = 64 << ((config1 >> 13) & 7); 1348 c->dcache.ways = 1 + ((config1 >> 7) & 7); 1349 dcache_size = c->dcache.sets * 1350 c->dcache.ways * 1351 c->dcache.linesz; 1352 c->dcache.waybit = 0; 1353 if ((prid & PRID_REV_MASK) >= PRID_REV_LOONGSON3A_R2) 1354 c->options |= MIPS_CPU_PREFETCH; 1355 break; 1356 1357 case CPU_CAVIUM_OCTEON3: 1358 /* For now lie about the number of ways. */ 1359 c->icache.linesz = 128; 1360 c->icache.sets = 16; 1361 c->icache.ways = 8; 1362 c->icache.flags |= MIPS_CACHE_VTAG; 1363 icache_size = c->icache.sets * c->icache.ways * c->icache.linesz; 1364 1365 c->dcache.linesz = 128; 1366 c->dcache.ways = 8; 1367 c->dcache.sets = 8; 1368 dcache_size = c->dcache.sets * c->dcache.ways * c->dcache.linesz; 1369 c->options |= MIPS_CPU_PREFETCH; 1370 break; 1371 1372 default: 1373 if (!(config & MIPS_CONF_M)) 1374 panic("Don't know how to probe P-caches on this cpu."); 1375 1376 /* 1377 * So we seem to be a MIPS32 or MIPS64 CPU 1378 * So let's probe the I-cache ... 1379 */ 1380 config1 = read_c0_config1(); 1381 1382 lsize = (config1 >> 19) & 7; 1383 1384 /* IL == 7 is reserved */ 1385 if (lsize == 7) 1386 panic("Invalid icache line size"); 1387 1388 c->icache.linesz = lsize ? 2 << lsize : 0; 1389 1390 c->icache.sets = 32 << (((config1 >> 22) + 1) & 7); 1391 c->icache.ways = 1 + ((config1 >> 16) & 7); 1392 1393 icache_size = c->icache.sets * 1394 c->icache.ways * 1395 c->icache.linesz; 1396 c->icache.waybit = __ffs(icache_size/c->icache.ways); 1397 1398 if (config & MIPS_CONF_VI) 1399 c->icache.flags |= MIPS_CACHE_VTAG; 1400 1401 /* 1402 * Now probe the MIPS32 / MIPS64 data cache. 1403 */ 1404 c->dcache.flags = 0; 1405 1406 lsize = (config1 >> 10) & 7; 1407 1408 /* DL == 7 is reserved */ 1409 if (lsize == 7) 1410 panic("Invalid dcache line size"); 1411 1412 c->dcache.linesz = lsize ? 2 << lsize : 0; 1413 1414 c->dcache.sets = 32 << (((config1 >> 13) + 1) & 7); 1415 c->dcache.ways = 1 + ((config1 >> 7) & 7); 1416 1417 dcache_size = c->dcache.sets * 1418 c->dcache.ways * 1419 c->dcache.linesz; 1420 c->dcache.waybit = __ffs(dcache_size/c->dcache.ways); 1421 1422 c->options |= MIPS_CPU_PREFETCH; 1423 break; 1424 } 1425 1426 /* 1427 * Processor configuration sanity check for the R4000SC erratum 1428 * #5. With page sizes larger than 32kB there is no possibility 1429 * to get a VCE exception anymore so we don't care about this 1430 * misconfiguration. The case is rather theoretical anyway; 1431 * presumably no vendor is shipping his hardware in the "bad" 1432 * configuration. 1433 */ 1434 if ((prid & PRID_IMP_MASK) == PRID_IMP_R4000 && 1435 (prid & PRID_REV_MASK) < PRID_REV_R4400 && 1436 !(config & CONF_SC) && c->icache.linesz != 16 && 1437 PAGE_SIZE <= 0x8000) 1438 panic("Improper R4000SC processor configuration detected"); 1439 1440 /* compute a couple of other cache variables */ 1441 c->icache.waysize = icache_size / c->icache.ways; 1442 c->dcache.waysize = dcache_size / c->dcache.ways; 1443 1444 c->icache.sets = c->icache.linesz ? 1445 icache_size / (c->icache.linesz * c->icache.ways) : 0; 1446 c->dcache.sets = c->dcache.linesz ? 1447 dcache_size / (c->dcache.linesz * c->dcache.ways) : 0; 1448 1449 /* 1450 * R1x000 P-caches are odd in a positive way. They're 32kB 2-way 1451 * virtually indexed so normally would suffer from aliases. So 1452 * normally they'd suffer from aliases but magic in the hardware deals 1453 * with that for us so we don't need to take care ourselves. 1454 */ 1455 switch (current_cpu_type()) { 1456 case CPU_20KC: 1457 case CPU_25KF: 1458 case CPU_I6400: 1459 case CPU_I6500: 1460 case CPU_SB1: 1461 case CPU_SB1A: 1462 case CPU_XLR: 1463 c->dcache.flags |= MIPS_CACHE_PINDEX; 1464 break; 1465 1466 case CPU_R10000: 1467 case CPU_R12000: 1468 case CPU_R14000: 1469 case CPU_R16000: 1470 break; 1471 1472 case CPU_74K: 1473 case CPU_1074K: 1474 has_74k_erratum = alias_74k_erratum(c); 1475 /* Fall through. */ 1476 case CPU_M14KC: 1477 case CPU_M14KEC: 1478 case CPU_24K: 1479 case CPU_34K: 1480 case CPU_1004K: 1481 case CPU_INTERAPTIV: 1482 case CPU_P5600: 1483 case CPU_PROAPTIV: 1484 case CPU_M5150: 1485 case CPU_QEMU_GENERIC: 1486 case CPU_P6600: 1487 case CPU_M6250: 1488 if (!(read_c0_config7() & MIPS_CONF7_IAR) && 1489 (c->icache.waysize > PAGE_SIZE)) 1490 c->icache.flags |= MIPS_CACHE_ALIASES; 1491 if (!has_74k_erratum && (read_c0_config7() & MIPS_CONF7_AR)) { 1492 /* 1493 * Effectively physically indexed dcache, 1494 * thus no virtual aliases. 1495 */ 1496 c->dcache.flags |= MIPS_CACHE_PINDEX; 1497 break; 1498 } 1499 default: 1500 if (has_74k_erratum || c->dcache.waysize > PAGE_SIZE) 1501 c->dcache.flags |= MIPS_CACHE_ALIASES; 1502 } 1503 1504 /* Physically indexed caches don't suffer from virtual aliasing */ 1505 if (c->dcache.flags & MIPS_CACHE_PINDEX) 1506 c->dcache.flags &= ~MIPS_CACHE_ALIASES; 1507 1508 switch (current_cpu_type()) { 1509 case CPU_20KC: 1510 /* 1511 * Some older 20Kc chips doesn't have the 'VI' bit in 1512 * the config register. 1513 */ 1514 c->icache.flags |= MIPS_CACHE_VTAG; 1515 break; 1516 1517 case CPU_ALCHEMY: 1518 case CPU_I6400: 1519 case CPU_I6500: 1520 c->icache.flags |= MIPS_CACHE_IC_F_DC; 1521 break; 1522 1523 case CPU_BMIPS5000: 1524 c->icache.flags |= MIPS_CACHE_IC_F_DC; 1525 /* Cache aliases are handled in hardware; allow HIGHMEM */ 1526 c->dcache.flags &= ~MIPS_CACHE_ALIASES; 1527 break; 1528 1529 case CPU_LOONGSON2: 1530 /* 1531 * LOONGSON2 has 4 way icache, but when using indexed cache op, 1532 * one op will act on all 4 ways 1533 */ 1534 c->icache.ways = 1; 1535 } 1536 1537 printk("Primary instruction cache %ldkB, %s, %s, linesize %d bytes.\n", 1538 icache_size >> 10, 1539 c->icache.flags & MIPS_CACHE_VTAG ? "VIVT" : "VIPT", 1540 way_string[c->icache.ways], c->icache.linesz); 1541 1542 printk("Primary data cache %ldkB, %s, %s, %s, linesize %d bytes\n", 1543 dcache_size >> 10, way_string[c->dcache.ways], 1544 (c->dcache.flags & MIPS_CACHE_PINDEX) ? "PIPT" : "VIPT", 1545 (c->dcache.flags & MIPS_CACHE_ALIASES) ? 1546 "cache aliases" : "no aliases", 1547 c->dcache.linesz); 1548 } 1549 1550 static void probe_vcache(void) 1551 { 1552 struct cpuinfo_mips *c = ¤t_cpu_data; 1553 unsigned int config2, lsize; 1554 1555 if (current_cpu_type() != CPU_LOONGSON3) 1556 return; 1557 1558 config2 = read_c0_config2(); 1559 if ((lsize = ((config2 >> 20) & 15))) 1560 c->vcache.linesz = 2 << lsize; 1561 else 1562 c->vcache.linesz = lsize; 1563 1564 c->vcache.sets = 64 << ((config2 >> 24) & 15); 1565 c->vcache.ways = 1 + ((config2 >> 16) & 15); 1566 1567 vcache_size = c->vcache.sets * c->vcache.ways * c->vcache.linesz; 1568 1569 c->vcache.waybit = 0; 1570 c->vcache.waysize = vcache_size / c->vcache.ways; 1571 1572 pr_info("Unified victim cache %ldkB %s, linesize %d bytes.\n", 1573 vcache_size >> 10, way_string[c->vcache.ways], c->vcache.linesz); 1574 } 1575 1576 /* 1577 * If you even _breathe_ on this function, look at the gcc output and make sure 1578 * it does not pop things on and off the stack for the cache sizing loop that 1579 * executes in KSEG1 space or else you will crash and burn badly. You have 1580 * been warned. 1581 */ 1582 static int probe_scache(void) 1583 { 1584 unsigned long flags, addr, begin, end, pow2; 1585 unsigned int config = read_c0_config(); 1586 struct cpuinfo_mips *c = ¤t_cpu_data; 1587 1588 if (config & CONF_SC) 1589 return 0; 1590 1591 begin = (unsigned long) &_stext; 1592 begin &= ~((4 * 1024 * 1024) - 1); 1593 end = begin + (4 * 1024 * 1024); 1594 1595 /* 1596 * This is such a bitch, you'd think they would make it easy to do 1597 * this. Away you daemons of stupidity! 1598 */ 1599 local_irq_save(flags); 1600 1601 /* Fill each size-multiple cache line with a valid tag. */ 1602 pow2 = (64 * 1024); 1603 for (addr = begin; addr < end; addr = (begin + pow2)) { 1604 unsigned long *p = (unsigned long *) addr; 1605 __asm__ __volatile__("nop" : : "r" (*p)); /* whee... */ 1606 pow2 <<= 1; 1607 } 1608 1609 /* Load first line with zero (therefore invalid) tag. */ 1610 write_c0_taglo(0); 1611 write_c0_taghi(0); 1612 __asm__ __volatile__("nop; nop; nop; nop;"); /* avoid the hazard */ 1613 cache_op(Index_Store_Tag_I, begin); 1614 cache_op(Index_Store_Tag_D, begin); 1615 cache_op(Index_Store_Tag_SD, begin); 1616 1617 /* Now search for the wrap around point. */ 1618 pow2 = (128 * 1024); 1619 for (addr = begin + (128 * 1024); addr < end; addr = begin + pow2) { 1620 cache_op(Index_Load_Tag_SD, addr); 1621 __asm__ __volatile__("nop; nop; nop; nop;"); /* hazard... */ 1622 if (!read_c0_taglo()) 1623 break; 1624 pow2 <<= 1; 1625 } 1626 local_irq_restore(flags); 1627 addr -= begin; 1628 1629 scache_size = addr; 1630 c->scache.linesz = 16 << ((config & R4K_CONF_SB) >> 22); 1631 c->scache.ways = 1; 1632 c->scache.waybit = 0; /* does not matter */ 1633 1634 return 1; 1635 } 1636 1637 static void __init loongson2_sc_init(void) 1638 { 1639 struct cpuinfo_mips *c = ¤t_cpu_data; 1640 1641 scache_size = 512*1024; 1642 c->scache.linesz = 32; 1643 c->scache.ways = 4; 1644 c->scache.waybit = 0; 1645 c->scache.waysize = scache_size / (c->scache.ways); 1646 c->scache.sets = scache_size / (c->scache.linesz * c->scache.ways); 1647 pr_info("Unified secondary cache %ldkB %s, linesize %d bytes.\n", 1648 scache_size >> 10, way_string[c->scache.ways], c->scache.linesz); 1649 1650 c->options |= MIPS_CPU_INCLUSIVE_CACHES; 1651 } 1652 1653 static void __init loongson3_sc_init(void) 1654 { 1655 struct cpuinfo_mips *c = ¤t_cpu_data; 1656 unsigned int config2, lsize; 1657 1658 config2 = read_c0_config2(); 1659 lsize = (config2 >> 4) & 15; 1660 if (lsize) 1661 c->scache.linesz = 2 << lsize; 1662 else 1663 c->scache.linesz = 0; 1664 c->scache.sets = 64 << ((config2 >> 8) & 15); 1665 c->scache.ways = 1 + (config2 & 15); 1666 1667 scache_size = c->scache.sets * 1668 c->scache.ways * 1669 c->scache.linesz; 1670 /* Loongson-3 has 4 cores, 1MB scache for each. scaches are shared */ 1671 scache_size *= 4; 1672 c->scache.waybit = 0; 1673 c->scache.waysize = scache_size / c->scache.ways; 1674 pr_info("Unified secondary cache %ldkB %s, linesize %d bytes.\n", 1675 scache_size >> 10, way_string[c->scache.ways], c->scache.linesz); 1676 if (scache_size) 1677 c->options |= MIPS_CPU_INCLUSIVE_CACHES; 1678 return; 1679 } 1680 1681 extern int r5k_sc_init(void); 1682 extern int rm7k_sc_init(void); 1683 extern int mips_sc_init(void); 1684 1685 static void setup_scache(void) 1686 { 1687 struct cpuinfo_mips *c = ¤t_cpu_data; 1688 unsigned int config = read_c0_config(); 1689 int sc_present = 0; 1690 1691 /* 1692 * Do the probing thing on R4000SC and R4400SC processors. Other 1693 * processors don't have a S-cache that would be relevant to the 1694 * Linux memory management. 1695 */ 1696 switch (current_cpu_type()) { 1697 case CPU_R4000SC: 1698 case CPU_R4000MC: 1699 case CPU_R4400SC: 1700 case CPU_R4400MC: 1701 sc_present = run_uncached(probe_scache); 1702 if (sc_present) 1703 c->options |= MIPS_CPU_CACHE_CDEX_S; 1704 break; 1705 1706 case CPU_R10000: 1707 case CPU_R12000: 1708 case CPU_R14000: 1709 case CPU_R16000: 1710 scache_size = 0x80000 << ((config & R10K_CONF_SS) >> 16); 1711 c->scache.linesz = 64 << ((config >> 13) & 1); 1712 c->scache.ways = 2; 1713 c->scache.waybit= 0; 1714 sc_present = 1; 1715 break; 1716 1717 case CPU_R5000: 1718 case CPU_NEVADA: 1719 #ifdef CONFIG_R5000_CPU_SCACHE 1720 r5k_sc_init(); 1721 #endif 1722 return; 1723 1724 case CPU_RM7000: 1725 #ifdef CONFIG_RM7000_CPU_SCACHE 1726 rm7k_sc_init(); 1727 #endif 1728 return; 1729 1730 case CPU_LOONGSON2: 1731 loongson2_sc_init(); 1732 return; 1733 1734 case CPU_LOONGSON3: 1735 loongson3_sc_init(); 1736 return; 1737 1738 case CPU_CAVIUM_OCTEON3: 1739 case CPU_XLP: 1740 /* don't need to worry about L2, fully coherent */ 1741 return; 1742 1743 default: 1744 if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M32R2 | 1745 MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R1 | 1746 MIPS_CPU_ISA_M64R2 | MIPS_CPU_ISA_M64R6)) { 1747 #ifdef CONFIG_MIPS_CPU_SCACHE 1748 if (mips_sc_init ()) { 1749 scache_size = c->scache.ways * c->scache.sets * c->scache.linesz; 1750 printk("MIPS secondary cache %ldkB, %s, linesize %d bytes.\n", 1751 scache_size >> 10, 1752 way_string[c->scache.ways], c->scache.linesz); 1753 } 1754 #else 1755 if (!(c->scache.flags & MIPS_CACHE_NOT_PRESENT)) 1756 panic("Dunno how to handle MIPS32 / MIPS64 second level cache"); 1757 #endif 1758 return; 1759 } 1760 sc_present = 0; 1761 } 1762 1763 if (!sc_present) 1764 return; 1765 1766 /* compute a couple of other cache variables */ 1767 c->scache.waysize = scache_size / c->scache.ways; 1768 1769 c->scache.sets = scache_size / (c->scache.linesz * c->scache.ways); 1770 1771 printk("Unified secondary cache %ldkB %s, linesize %d bytes.\n", 1772 scache_size >> 10, way_string[c->scache.ways], c->scache.linesz); 1773 1774 c->options |= MIPS_CPU_INCLUSIVE_CACHES; 1775 } 1776 1777 void au1x00_fixup_config_od(void) 1778 { 1779 /* 1780 * c0_config.od (bit 19) was write only (and read as 0) 1781 * on the early revisions of Alchemy SOCs. It disables the bus 1782 * transaction overlapping and needs to be set to fix various errata. 1783 */ 1784 switch (read_c0_prid()) { 1785 case 0x00030100: /* Au1000 DA */ 1786 case 0x00030201: /* Au1000 HA */ 1787 case 0x00030202: /* Au1000 HB */ 1788 case 0x01030200: /* Au1500 AB */ 1789 /* 1790 * Au1100 errata actually keeps silence about this bit, so we set it 1791 * just in case for those revisions that require it to be set according 1792 * to the (now gone) cpu table. 1793 */ 1794 case 0x02030200: /* Au1100 AB */ 1795 case 0x02030201: /* Au1100 BA */ 1796 case 0x02030202: /* Au1100 BC */ 1797 set_c0_config(1 << 19); 1798 break; 1799 } 1800 } 1801 1802 /* CP0 hazard avoidance. */ 1803 #define NXP_BARRIER() \ 1804 __asm__ __volatile__( \ 1805 ".set noreorder\n\t" \ 1806 "nop; nop; nop; nop; nop; nop;\n\t" \ 1807 ".set reorder\n\t") 1808 1809 static void nxp_pr4450_fixup_config(void) 1810 { 1811 unsigned long config0; 1812 1813 config0 = read_c0_config(); 1814 1815 /* clear all three cache coherency fields */ 1816 config0 &= ~(0x7 | (7 << 25) | (7 << 28)); 1817 config0 |= (((_page_cachable_default >> _CACHE_SHIFT) << 0) | 1818 ((_page_cachable_default >> _CACHE_SHIFT) << 25) | 1819 ((_page_cachable_default >> _CACHE_SHIFT) << 28)); 1820 write_c0_config(config0); 1821 NXP_BARRIER(); 1822 } 1823 1824 static int cca = -1; 1825 1826 static int __init cca_setup(char *str) 1827 { 1828 get_option(&str, &cca); 1829 1830 return 0; 1831 } 1832 1833 early_param("cca", cca_setup); 1834 1835 static void coherency_setup(void) 1836 { 1837 if (cca < 0 || cca > 7) 1838 cca = read_c0_config() & CONF_CM_CMASK; 1839 _page_cachable_default = cca << _CACHE_SHIFT; 1840 1841 pr_debug("Using cache attribute %d\n", cca); 1842 change_c0_config(CONF_CM_CMASK, cca); 1843 1844 /* 1845 * c0_status.cu=0 specifies that updates by the sc instruction use 1846 * the coherency mode specified by the TLB; 1 means cachable 1847 * coherent update on write will be used. Not all processors have 1848 * this bit and; some wire it to zero, others like Toshiba had the 1849 * silly idea of putting something else there ... 1850 */ 1851 switch (current_cpu_type()) { 1852 case CPU_R4000PC: 1853 case CPU_R4000SC: 1854 case CPU_R4000MC: 1855 case CPU_R4400PC: 1856 case CPU_R4400SC: 1857 case CPU_R4400MC: 1858 clear_c0_config(CONF_CU); 1859 break; 1860 /* 1861 * We need to catch the early Alchemy SOCs with 1862 * the write-only co_config.od bit and set it back to one on: 1863 * Au1000 rev DA, HA, HB; Au1100 AB, BA, BC, Au1500 AB 1864 */ 1865 case CPU_ALCHEMY: 1866 au1x00_fixup_config_od(); 1867 break; 1868 1869 case PRID_IMP_PR4450: 1870 nxp_pr4450_fixup_config(); 1871 break; 1872 } 1873 } 1874 1875 static void r4k_cache_error_setup(void) 1876 { 1877 extern char __weak except_vec2_generic; 1878 extern char __weak except_vec2_sb1; 1879 1880 switch (current_cpu_type()) { 1881 case CPU_SB1: 1882 case CPU_SB1A: 1883 set_uncached_handler(0x100, &except_vec2_sb1, 0x80); 1884 break; 1885 1886 default: 1887 set_uncached_handler(0x100, &except_vec2_generic, 0x80); 1888 break; 1889 } 1890 } 1891 1892 void r4k_cache_init(void) 1893 { 1894 extern void build_clear_page(void); 1895 extern void build_copy_page(void); 1896 struct cpuinfo_mips *c = ¤t_cpu_data; 1897 1898 probe_pcache(); 1899 probe_vcache(); 1900 setup_scache(); 1901 1902 r4k_blast_dcache_page_setup(); 1903 r4k_blast_dcache_page_indexed_setup(); 1904 r4k_blast_dcache_setup(); 1905 r4k_blast_icache_page_setup(); 1906 r4k_blast_icache_page_indexed_setup(); 1907 r4k_blast_icache_setup(); 1908 r4k_blast_scache_page_setup(); 1909 r4k_blast_scache_page_indexed_setup(); 1910 r4k_blast_scache_setup(); 1911 #ifdef CONFIG_EVA 1912 r4k_blast_dcache_user_page_setup(); 1913 r4k_blast_icache_user_page_setup(); 1914 #endif 1915 1916 /* 1917 * Some MIPS32 and MIPS64 processors have physically indexed caches. 1918 * This code supports virtually indexed processors and will be 1919 * unnecessarily inefficient on physically indexed processors. 1920 */ 1921 if (c->dcache.linesz && cpu_has_dc_aliases) 1922 shm_align_mask = max_t( unsigned long, 1923 c->dcache.sets * c->dcache.linesz - 1, 1924 PAGE_SIZE - 1); 1925 else 1926 shm_align_mask = PAGE_SIZE-1; 1927 1928 __flush_cache_vmap = r4k__flush_cache_vmap; 1929 __flush_cache_vunmap = r4k__flush_cache_vunmap; 1930 1931 flush_cache_all = cache_noop; 1932 __flush_cache_all = r4k___flush_cache_all; 1933 flush_cache_mm = r4k_flush_cache_mm; 1934 flush_cache_page = r4k_flush_cache_page; 1935 flush_cache_range = r4k_flush_cache_range; 1936 1937 __flush_kernel_vmap_range = r4k_flush_kernel_vmap_range; 1938 1939 flush_cache_sigtramp = r4k_flush_cache_sigtramp; 1940 flush_icache_all = r4k_flush_icache_all; 1941 local_flush_data_cache_page = local_r4k_flush_data_cache_page; 1942 flush_data_cache_page = r4k_flush_data_cache_page; 1943 flush_icache_range = r4k_flush_icache_range; 1944 local_flush_icache_range = local_r4k_flush_icache_range; 1945 __flush_icache_user_range = r4k_flush_icache_user_range; 1946 __local_flush_icache_user_range = local_r4k_flush_icache_user_range; 1947 1948 #if defined(CONFIG_DMA_NONCOHERENT) || defined(CONFIG_DMA_MAYBE_COHERENT) 1949 # if defined(CONFIG_DMA_PERDEV_COHERENT) 1950 if (0) { 1951 # else 1952 if ((coherentio == IO_COHERENCE_ENABLED) || 1953 ((coherentio == IO_COHERENCE_DEFAULT) && hw_coherentio)) { 1954 # endif 1955 _dma_cache_wback_inv = (void *)cache_noop; 1956 _dma_cache_wback = (void *)cache_noop; 1957 _dma_cache_inv = (void *)cache_noop; 1958 } else { 1959 _dma_cache_wback_inv = r4k_dma_cache_wback_inv; 1960 _dma_cache_wback = r4k_dma_cache_wback_inv; 1961 _dma_cache_inv = r4k_dma_cache_inv; 1962 } 1963 #endif 1964 1965 build_clear_page(); 1966 build_copy_page(); 1967 1968 /* 1969 * We want to run CMP kernels on core with and without coherent 1970 * caches. Therefore, do not use CONFIG_MIPS_CMP to decide whether 1971 * or not to flush caches. 1972 */ 1973 local_r4k___flush_cache_all(NULL); 1974 1975 coherency_setup(); 1976 board_cache_error_setup = r4k_cache_error_setup; 1977 1978 /* 1979 * Per-CPU overrides 1980 */ 1981 switch (current_cpu_type()) { 1982 case CPU_BMIPS4350: 1983 case CPU_BMIPS4380: 1984 /* No IPI is needed because all CPUs share the same D$ */ 1985 flush_data_cache_page = r4k_blast_dcache_page; 1986 break; 1987 case CPU_BMIPS5000: 1988 /* We lose our superpowers if L2 is disabled */ 1989 if (c->scache.flags & MIPS_CACHE_NOT_PRESENT) 1990 break; 1991 1992 /* I$ fills from D$ just by emptying the write buffers */ 1993 flush_cache_page = (void *)b5k_instruction_hazard; 1994 flush_cache_range = (void *)b5k_instruction_hazard; 1995 flush_cache_sigtramp = (void *)b5k_instruction_hazard; 1996 local_flush_data_cache_page = (void *)b5k_instruction_hazard; 1997 flush_data_cache_page = (void *)b5k_instruction_hazard; 1998 flush_icache_range = (void *)b5k_instruction_hazard; 1999 local_flush_icache_range = (void *)b5k_instruction_hazard; 2000 2001 2002 /* Optimization: an L2 flush implicitly flushes the L1 */ 2003 current_cpu_data.options |= MIPS_CPU_INCLUSIVE_CACHES; 2004 break; 2005 case CPU_LOONGSON3: 2006 /* Loongson-3 maintains cache coherency by hardware */ 2007 __flush_cache_all = cache_noop; 2008 __flush_cache_vmap = cache_noop; 2009 __flush_cache_vunmap = cache_noop; 2010 __flush_kernel_vmap_range = (void *)cache_noop; 2011 flush_cache_mm = (void *)cache_noop; 2012 flush_cache_page = (void *)cache_noop; 2013 flush_cache_range = (void *)cache_noop; 2014 flush_cache_sigtramp = (void *)cache_noop; 2015 flush_icache_all = (void *)cache_noop; 2016 flush_data_cache_page = (void *)cache_noop; 2017 local_flush_data_cache_page = (void *)cache_noop; 2018 break; 2019 } 2020 } 2021 2022 static int r4k_cache_pm_notifier(struct notifier_block *self, unsigned long cmd, 2023 void *v) 2024 { 2025 switch (cmd) { 2026 case CPU_PM_ENTER_FAILED: 2027 case CPU_PM_EXIT: 2028 coherency_setup(); 2029 break; 2030 } 2031 2032 return NOTIFY_OK; 2033 } 2034 2035 static struct notifier_block r4k_cache_pm_notifier_block = { 2036 .notifier_call = r4k_cache_pm_notifier, 2037 }; 2038 2039 int __init r4k_cache_init_pm(void) 2040 { 2041 return cpu_pm_register_notifier(&r4k_cache_pm_notifier_block); 2042 } 2043 arch_initcall(r4k_cache_init_pm); 2044