1 #include <asm/branch.h> 2 #include <asm/cacheflush.h> 3 #include <asm/fpu_emulator.h> 4 #include <asm/inst.h> 5 #include <asm/mipsregs.h> 6 #include <asm/uaccess.h> 7 8 #include "ieee754.h" 9 10 /* 11 * Emulate the arbritrary instruction ir at xcp->cp0_epc. Required when 12 * we have to emulate the instruction in a COP1 branch delay slot. Do 13 * not change cp0_epc due to the instruction 14 * 15 * According to the spec: 16 * 1) it shouldn't be a branch :-) 17 * 2) it can be a COP instruction :-( 18 * 3) if we are tring to run a protected memory space we must take 19 * special care on memory access instructions :-( 20 */ 21 22 /* 23 * "Trampoline" return routine to catch exception following 24 * execution of delay-slot instruction execution. 25 */ 26 27 struct emuframe { 28 mips_instruction emul; 29 mips_instruction badinst; 30 mips_instruction cookie; 31 unsigned long epc; 32 }; 33 34 int mips_dsemul(struct pt_regs *regs, mips_instruction ir, unsigned long cpc) 35 { 36 struct emuframe __user *fr; 37 int err; 38 39 if ((get_isa16_mode(regs->cp0_epc) && ((ir >> 16) == MM_NOP16)) || 40 (ir == 0)) { 41 /* NOP is easy */ 42 regs->cp0_epc = cpc; 43 clear_delay_slot(regs); 44 return 0; 45 } 46 47 pr_debug("dsemul %lx %lx\n", regs->cp0_epc, cpc); 48 49 /* 50 * The strategy is to push the instruction onto the user stack 51 * and put a trap after it which we can catch and jump to 52 * the required address any alternative apart from full 53 * instruction emulation!!. 54 * 55 * Algorithmics used a system call instruction, and 56 * borrowed that vector. MIPS/Linux version is a bit 57 * more heavyweight in the interests of portability and 58 * multiprocessor support. For Linux we generate a 59 * an unaligned access and force an address error exception. 60 * 61 * For embedded systems (stand-alone) we prefer to use a 62 * non-existing CP1 instruction. This prevents us from emulating 63 * branches, but gives us a cleaner interface to the exception 64 * handler (single entry point). 65 */ 66 67 /* Ensure that the two instructions are in the same cache line */ 68 fr = (struct emuframe __user *) 69 ((regs->regs[29] - sizeof(struct emuframe)) & ~0x7); 70 71 /* Verify that the stack pointer is not competely insane */ 72 if (unlikely(!access_ok(VERIFY_WRITE, fr, sizeof(struct emuframe)))) 73 return SIGBUS; 74 75 if (get_isa16_mode(regs->cp0_epc)) { 76 err = __put_user(ir >> 16, (u16 __user *)(&fr->emul)); 77 err |= __put_user(ir & 0xffff, (u16 __user *)((long)(&fr->emul) + 2)); 78 err |= __put_user(BREAK_MATH >> 16, (u16 __user *)(&fr->badinst)); 79 err |= __put_user(BREAK_MATH & 0xffff, (u16 __user *)((long)(&fr->badinst) + 2)); 80 } else { 81 err = __put_user(ir, &fr->emul); 82 err |= __put_user((mips_instruction)BREAK_MATH, &fr->badinst); 83 } 84 85 err |= __put_user((mips_instruction)BD_COOKIE, &fr->cookie); 86 err |= __put_user(cpc, &fr->epc); 87 88 if (unlikely(err)) { 89 MIPS_FPU_EMU_INC_STATS(errors); 90 return SIGBUS; 91 } 92 93 regs->cp0_epc = ((unsigned long) &fr->emul) | 94 get_isa16_mode(regs->cp0_epc); 95 96 flush_cache_sigtramp((unsigned long)&fr->emul); 97 98 return 0; 99 } 100 101 int do_dsemulret(struct pt_regs *xcp) 102 { 103 struct emuframe __user *fr; 104 unsigned long epc; 105 u32 insn, cookie; 106 int err = 0; 107 u16 instr[2]; 108 109 fr = (struct emuframe __user *) 110 (msk_isa16_mode(xcp->cp0_epc) - sizeof(mips_instruction)); 111 112 /* 113 * If we can't even access the area, something is very wrong, but we'll 114 * leave that to the default handling 115 */ 116 if (!access_ok(VERIFY_READ, fr, sizeof(struct emuframe))) 117 return 0; 118 119 /* 120 * Do some sanity checking on the stackframe: 121 * 122 * - Is the instruction pointed to by the EPC an BREAK_MATH? 123 * - Is the following memory word the BD_COOKIE? 124 */ 125 if (get_isa16_mode(xcp->cp0_epc)) { 126 err = __get_user(instr[0], (u16 __user *)(&fr->badinst)); 127 err |= __get_user(instr[1], (u16 __user *)((long)(&fr->badinst) + 2)); 128 insn = (instr[0] << 16) | instr[1]; 129 } else { 130 err = __get_user(insn, &fr->badinst); 131 } 132 err |= __get_user(cookie, &fr->cookie); 133 134 if (unlikely(err || (insn != BREAK_MATH) || (cookie != BD_COOKIE))) { 135 MIPS_FPU_EMU_INC_STATS(errors); 136 return 0; 137 } 138 139 /* 140 * At this point, we are satisfied that it's a BD emulation trap. Yes, 141 * a user might have deliberately put two malformed and useless 142 * instructions in a row in his program, in which case he's in for a 143 * nasty surprise - the next instruction will be treated as a 144 * continuation address! Alas, this seems to be the only way that we 145 * can handle signals, recursion, and longjmps() in the context of 146 * emulating the branch delay instruction. 147 */ 148 149 pr_debug("dsemulret\n"); 150 151 if (__get_user(epc, &fr->epc)) { /* Saved EPC */ 152 /* This is not a good situation to be in */ 153 force_sig(SIGBUS, current); 154 155 return 0; 156 } 157 158 /* Set EPC to return to post-branch instruction */ 159 xcp->cp0_epc = epc; 160 MIPS_FPU_EMU_INC_STATS(ds_emul); 161 return 1; 162 } 163