1 /* 2 * cp1emu.c: a MIPS coprocessor 1 (FPU) instruction emulator 3 * 4 * MIPS floating point support 5 * Copyright (C) 1994-2000 Algorithmics Ltd. 6 * 7 * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com 8 * Copyright (C) 2000 MIPS Technologies, Inc. 9 * 10 * This program is free software; you can distribute it and/or modify it 11 * under the terms of the GNU General Public License (Version 2) as 12 * published by the Free Software Foundation. 13 * 14 * This program is distributed in the hope it will be useful, but WITHOUT 15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 17 * for more details. 18 * 19 * You should have received a copy of the GNU General Public License along 20 * with this program; if not, write to the Free Software Foundation, Inc., 21 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. 22 * 23 * A complete emulator for MIPS coprocessor 1 instructions. This is 24 * required for #float(switch) or #float(trap), where it catches all 25 * COP1 instructions via the "CoProcessor Unusable" exception. 26 * 27 * More surprisingly it is also required for #float(ieee), to help out 28 * the hardware FPU at the boundaries of the IEEE-754 representation 29 * (denormalised values, infinities, underflow, etc). It is made 30 * quite nasty because emulation of some non-COP1 instructions is 31 * required, e.g. in branch delay slots. 32 * 33 * Note if you know that you won't have an FPU, then you'll get much 34 * better performance by compiling with -msoft-float! 35 */ 36 #include <linux/sched.h> 37 #include <linux/debugfs.h> 38 #include <linux/kconfig.h> 39 #include <linux/percpu-defs.h> 40 #include <linux/perf_event.h> 41 42 #include <asm/branch.h> 43 #include <asm/inst.h> 44 #include <asm/ptrace.h> 45 #include <asm/signal.h> 46 #include <asm/uaccess.h> 47 48 #include <asm/cpu-info.h> 49 #include <asm/processor.h> 50 #include <asm/fpu_emulator.h> 51 #include <asm/fpu.h> 52 #include <asm/mips-r2-to-r6-emul.h> 53 54 #include "ieee754.h" 55 56 /* Function which emulates a floating point instruction. */ 57 58 static int fpu_emu(struct pt_regs *, struct mips_fpu_struct *, 59 mips_instruction); 60 61 static int fpux_emu(struct pt_regs *, 62 struct mips_fpu_struct *, mips_instruction, void *__user *); 63 64 /* Control registers */ 65 66 #define FPCREG_RID 0 /* $0 = revision id */ 67 #define FPCREG_FCCR 25 /* $25 = fccr */ 68 #define FPCREG_FEXR 26 /* $26 = fexr */ 69 #define FPCREG_FENR 28 /* $28 = fenr */ 70 #define FPCREG_CSR 31 /* $31 = csr */ 71 72 /* convert condition code register number to csr bit */ 73 const unsigned int fpucondbit[8] = { 74 FPU_CSR_COND, 75 FPU_CSR_COND1, 76 FPU_CSR_COND2, 77 FPU_CSR_COND3, 78 FPU_CSR_COND4, 79 FPU_CSR_COND5, 80 FPU_CSR_COND6, 81 FPU_CSR_COND7 82 }; 83 84 /* (microMIPS) Convert certain microMIPS instructions to MIPS32 format. */ 85 static const int sd_format[] = {16, 17, 0, 0, 0, 0, 0, 0}; 86 static const int sdps_format[] = {16, 17, 22, 0, 0, 0, 0, 0}; 87 static const int dwl_format[] = {17, 20, 21, 0, 0, 0, 0, 0}; 88 static const int swl_format[] = {16, 20, 21, 0, 0, 0, 0, 0}; 89 90 /* 91 * This functions translates a 32-bit microMIPS instruction 92 * into a 32-bit MIPS32 instruction. Returns 0 on success 93 * and SIGILL otherwise. 94 */ 95 static int microMIPS32_to_MIPS32(union mips_instruction *insn_ptr) 96 { 97 union mips_instruction insn = *insn_ptr; 98 union mips_instruction mips32_insn = insn; 99 int func, fmt, op; 100 101 switch (insn.mm_i_format.opcode) { 102 case mm_ldc132_op: 103 mips32_insn.mm_i_format.opcode = ldc1_op; 104 mips32_insn.mm_i_format.rt = insn.mm_i_format.rs; 105 mips32_insn.mm_i_format.rs = insn.mm_i_format.rt; 106 break; 107 case mm_lwc132_op: 108 mips32_insn.mm_i_format.opcode = lwc1_op; 109 mips32_insn.mm_i_format.rt = insn.mm_i_format.rs; 110 mips32_insn.mm_i_format.rs = insn.mm_i_format.rt; 111 break; 112 case mm_sdc132_op: 113 mips32_insn.mm_i_format.opcode = sdc1_op; 114 mips32_insn.mm_i_format.rt = insn.mm_i_format.rs; 115 mips32_insn.mm_i_format.rs = insn.mm_i_format.rt; 116 break; 117 case mm_swc132_op: 118 mips32_insn.mm_i_format.opcode = swc1_op; 119 mips32_insn.mm_i_format.rt = insn.mm_i_format.rs; 120 mips32_insn.mm_i_format.rs = insn.mm_i_format.rt; 121 break; 122 case mm_pool32i_op: 123 /* NOTE: offset is << by 1 if in microMIPS mode. */ 124 if ((insn.mm_i_format.rt == mm_bc1f_op) || 125 (insn.mm_i_format.rt == mm_bc1t_op)) { 126 mips32_insn.fb_format.opcode = cop1_op; 127 mips32_insn.fb_format.bc = bc_op; 128 mips32_insn.fb_format.flag = 129 (insn.mm_i_format.rt == mm_bc1t_op) ? 1 : 0; 130 } else 131 return SIGILL; 132 break; 133 case mm_pool32f_op: 134 switch (insn.mm_fp0_format.func) { 135 case mm_32f_01_op: 136 case mm_32f_11_op: 137 case mm_32f_02_op: 138 case mm_32f_12_op: 139 case mm_32f_41_op: 140 case mm_32f_51_op: 141 case mm_32f_42_op: 142 case mm_32f_52_op: 143 op = insn.mm_fp0_format.func; 144 if (op == mm_32f_01_op) 145 func = madd_s_op; 146 else if (op == mm_32f_11_op) 147 func = madd_d_op; 148 else if (op == mm_32f_02_op) 149 func = nmadd_s_op; 150 else if (op == mm_32f_12_op) 151 func = nmadd_d_op; 152 else if (op == mm_32f_41_op) 153 func = msub_s_op; 154 else if (op == mm_32f_51_op) 155 func = msub_d_op; 156 else if (op == mm_32f_42_op) 157 func = nmsub_s_op; 158 else 159 func = nmsub_d_op; 160 mips32_insn.fp6_format.opcode = cop1x_op; 161 mips32_insn.fp6_format.fr = insn.mm_fp6_format.fr; 162 mips32_insn.fp6_format.ft = insn.mm_fp6_format.ft; 163 mips32_insn.fp6_format.fs = insn.mm_fp6_format.fs; 164 mips32_insn.fp6_format.fd = insn.mm_fp6_format.fd; 165 mips32_insn.fp6_format.func = func; 166 break; 167 case mm_32f_10_op: 168 func = -1; /* Invalid */ 169 op = insn.mm_fp5_format.op & 0x7; 170 if (op == mm_ldxc1_op) 171 func = ldxc1_op; 172 else if (op == mm_sdxc1_op) 173 func = sdxc1_op; 174 else if (op == mm_lwxc1_op) 175 func = lwxc1_op; 176 else if (op == mm_swxc1_op) 177 func = swxc1_op; 178 179 if (func != -1) { 180 mips32_insn.r_format.opcode = cop1x_op; 181 mips32_insn.r_format.rs = 182 insn.mm_fp5_format.base; 183 mips32_insn.r_format.rt = 184 insn.mm_fp5_format.index; 185 mips32_insn.r_format.rd = 0; 186 mips32_insn.r_format.re = insn.mm_fp5_format.fd; 187 mips32_insn.r_format.func = func; 188 } else 189 return SIGILL; 190 break; 191 case mm_32f_40_op: 192 op = -1; /* Invalid */ 193 if (insn.mm_fp2_format.op == mm_fmovt_op) 194 op = 1; 195 else if (insn.mm_fp2_format.op == mm_fmovf_op) 196 op = 0; 197 if (op != -1) { 198 mips32_insn.fp0_format.opcode = cop1_op; 199 mips32_insn.fp0_format.fmt = 200 sdps_format[insn.mm_fp2_format.fmt]; 201 mips32_insn.fp0_format.ft = 202 (insn.mm_fp2_format.cc<<2) + op; 203 mips32_insn.fp0_format.fs = 204 insn.mm_fp2_format.fs; 205 mips32_insn.fp0_format.fd = 206 insn.mm_fp2_format.fd; 207 mips32_insn.fp0_format.func = fmovc_op; 208 } else 209 return SIGILL; 210 break; 211 case mm_32f_60_op: 212 func = -1; /* Invalid */ 213 if (insn.mm_fp0_format.op == mm_fadd_op) 214 func = fadd_op; 215 else if (insn.mm_fp0_format.op == mm_fsub_op) 216 func = fsub_op; 217 else if (insn.mm_fp0_format.op == mm_fmul_op) 218 func = fmul_op; 219 else if (insn.mm_fp0_format.op == mm_fdiv_op) 220 func = fdiv_op; 221 if (func != -1) { 222 mips32_insn.fp0_format.opcode = cop1_op; 223 mips32_insn.fp0_format.fmt = 224 sdps_format[insn.mm_fp0_format.fmt]; 225 mips32_insn.fp0_format.ft = 226 insn.mm_fp0_format.ft; 227 mips32_insn.fp0_format.fs = 228 insn.mm_fp0_format.fs; 229 mips32_insn.fp0_format.fd = 230 insn.mm_fp0_format.fd; 231 mips32_insn.fp0_format.func = func; 232 } else 233 return SIGILL; 234 break; 235 case mm_32f_70_op: 236 func = -1; /* Invalid */ 237 if (insn.mm_fp0_format.op == mm_fmovn_op) 238 func = fmovn_op; 239 else if (insn.mm_fp0_format.op == mm_fmovz_op) 240 func = fmovz_op; 241 if (func != -1) { 242 mips32_insn.fp0_format.opcode = cop1_op; 243 mips32_insn.fp0_format.fmt = 244 sdps_format[insn.mm_fp0_format.fmt]; 245 mips32_insn.fp0_format.ft = 246 insn.mm_fp0_format.ft; 247 mips32_insn.fp0_format.fs = 248 insn.mm_fp0_format.fs; 249 mips32_insn.fp0_format.fd = 250 insn.mm_fp0_format.fd; 251 mips32_insn.fp0_format.func = func; 252 } else 253 return SIGILL; 254 break; 255 case mm_32f_73_op: /* POOL32FXF */ 256 switch (insn.mm_fp1_format.op) { 257 case mm_movf0_op: 258 case mm_movf1_op: 259 case mm_movt0_op: 260 case mm_movt1_op: 261 if ((insn.mm_fp1_format.op & 0x7f) == 262 mm_movf0_op) 263 op = 0; 264 else 265 op = 1; 266 mips32_insn.r_format.opcode = spec_op; 267 mips32_insn.r_format.rs = insn.mm_fp4_format.fs; 268 mips32_insn.r_format.rt = 269 (insn.mm_fp4_format.cc << 2) + op; 270 mips32_insn.r_format.rd = insn.mm_fp4_format.rt; 271 mips32_insn.r_format.re = 0; 272 mips32_insn.r_format.func = movc_op; 273 break; 274 case mm_fcvtd0_op: 275 case mm_fcvtd1_op: 276 case mm_fcvts0_op: 277 case mm_fcvts1_op: 278 if ((insn.mm_fp1_format.op & 0x7f) == 279 mm_fcvtd0_op) { 280 func = fcvtd_op; 281 fmt = swl_format[insn.mm_fp3_format.fmt]; 282 } else { 283 func = fcvts_op; 284 fmt = dwl_format[insn.mm_fp3_format.fmt]; 285 } 286 mips32_insn.fp0_format.opcode = cop1_op; 287 mips32_insn.fp0_format.fmt = fmt; 288 mips32_insn.fp0_format.ft = 0; 289 mips32_insn.fp0_format.fs = 290 insn.mm_fp3_format.fs; 291 mips32_insn.fp0_format.fd = 292 insn.mm_fp3_format.rt; 293 mips32_insn.fp0_format.func = func; 294 break; 295 case mm_fmov0_op: 296 case mm_fmov1_op: 297 case mm_fabs0_op: 298 case mm_fabs1_op: 299 case mm_fneg0_op: 300 case mm_fneg1_op: 301 if ((insn.mm_fp1_format.op & 0x7f) == 302 mm_fmov0_op) 303 func = fmov_op; 304 else if ((insn.mm_fp1_format.op & 0x7f) == 305 mm_fabs0_op) 306 func = fabs_op; 307 else 308 func = fneg_op; 309 mips32_insn.fp0_format.opcode = cop1_op; 310 mips32_insn.fp0_format.fmt = 311 sdps_format[insn.mm_fp3_format.fmt]; 312 mips32_insn.fp0_format.ft = 0; 313 mips32_insn.fp0_format.fs = 314 insn.mm_fp3_format.fs; 315 mips32_insn.fp0_format.fd = 316 insn.mm_fp3_format.rt; 317 mips32_insn.fp0_format.func = func; 318 break; 319 case mm_ffloorl_op: 320 case mm_ffloorw_op: 321 case mm_fceill_op: 322 case mm_fceilw_op: 323 case mm_ftruncl_op: 324 case mm_ftruncw_op: 325 case mm_froundl_op: 326 case mm_froundw_op: 327 case mm_fcvtl_op: 328 case mm_fcvtw_op: 329 if (insn.mm_fp1_format.op == mm_ffloorl_op) 330 func = ffloorl_op; 331 else if (insn.mm_fp1_format.op == mm_ffloorw_op) 332 func = ffloor_op; 333 else if (insn.mm_fp1_format.op == mm_fceill_op) 334 func = fceill_op; 335 else if (insn.mm_fp1_format.op == mm_fceilw_op) 336 func = fceil_op; 337 else if (insn.mm_fp1_format.op == mm_ftruncl_op) 338 func = ftruncl_op; 339 else if (insn.mm_fp1_format.op == mm_ftruncw_op) 340 func = ftrunc_op; 341 else if (insn.mm_fp1_format.op == mm_froundl_op) 342 func = froundl_op; 343 else if (insn.mm_fp1_format.op == mm_froundw_op) 344 func = fround_op; 345 else if (insn.mm_fp1_format.op == mm_fcvtl_op) 346 func = fcvtl_op; 347 else 348 func = fcvtw_op; 349 mips32_insn.fp0_format.opcode = cop1_op; 350 mips32_insn.fp0_format.fmt = 351 sd_format[insn.mm_fp1_format.fmt]; 352 mips32_insn.fp0_format.ft = 0; 353 mips32_insn.fp0_format.fs = 354 insn.mm_fp1_format.fs; 355 mips32_insn.fp0_format.fd = 356 insn.mm_fp1_format.rt; 357 mips32_insn.fp0_format.func = func; 358 break; 359 case mm_frsqrt_op: 360 case mm_fsqrt_op: 361 case mm_frecip_op: 362 if (insn.mm_fp1_format.op == mm_frsqrt_op) 363 func = frsqrt_op; 364 else if (insn.mm_fp1_format.op == mm_fsqrt_op) 365 func = fsqrt_op; 366 else 367 func = frecip_op; 368 mips32_insn.fp0_format.opcode = cop1_op; 369 mips32_insn.fp0_format.fmt = 370 sdps_format[insn.mm_fp1_format.fmt]; 371 mips32_insn.fp0_format.ft = 0; 372 mips32_insn.fp0_format.fs = 373 insn.mm_fp1_format.fs; 374 mips32_insn.fp0_format.fd = 375 insn.mm_fp1_format.rt; 376 mips32_insn.fp0_format.func = func; 377 break; 378 case mm_mfc1_op: 379 case mm_mtc1_op: 380 case mm_cfc1_op: 381 case mm_ctc1_op: 382 case mm_mfhc1_op: 383 case mm_mthc1_op: 384 if (insn.mm_fp1_format.op == mm_mfc1_op) 385 op = mfc_op; 386 else if (insn.mm_fp1_format.op == mm_mtc1_op) 387 op = mtc_op; 388 else if (insn.mm_fp1_format.op == mm_cfc1_op) 389 op = cfc_op; 390 else if (insn.mm_fp1_format.op == mm_ctc1_op) 391 op = ctc_op; 392 else if (insn.mm_fp1_format.op == mm_mfhc1_op) 393 op = mfhc_op; 394 else 395 op = mthc_op; 396 mips32_insn.fp1_format.opcode = cop1_op; 397 mips32_insn.fp1_format.op = op; 398 mips32_insn.fp1_format.rt = 399 insn.mm_fp1_format.rt; 400 mips32_insn.fp1_format.fs = 401 insn.mm_fp1_format.fs; 402 mips32_insn.fp1_format.fd = 0; 403 mips32_insn.fp1_format.func = 0; 404 break; 405 default: 406 return SIGILL; 407 } 408 break; 409 case mm_32f_74_op: /* c.cond.fmt */ 410 mips32_insn.fp0_format.opcode = cop1_op; 411 mips32_insn.fp0_format.fmt = 412 sdps_format[insn.mm_fp4_format.fmt]; 413 mips32_insn.fp0_format.ft = insn.mm_fp4_format.rt; 414 mips32_insn.fp0_format.fs = insn.mm_fp4_format.fs; 415 mips32_insn.fp0_format.fd = insn.mm_fp4_format.cc << 2; 416 mips32_insn.fp0_format.func = 417 insn.mm_fp4_format.cond | MM_MIPS32_COND_FC; 418 break; 419 default: 420 return SIGILL; 421 } 422 break; 423 default: 424 return SIGILL; 425 } 426 427 *insn_ptr = mips32_insn; 428 return 0; 429 } 430 431 /* 432 * Redundant with logic already in kernel/branch.c, 433 * embedded in compute_return_epc. At some point, 434 * a single subroutine should be used across both 435 * modules. 436 */ 437 static int isBranchInstr(struct pt_regs *regs, struct mm_decoded_insn dec_insn, 438 unsigned long *contpc) 439 { 440 union mips_instruction insn = (union mips_instruction)dec_insn.insn; 441 unsigned int fcr31; 442 unsigned int bit = 0; 443 444 switch (insn.i_format.opcode) { 445 case spec_op: 446 switch (insn.r_format.func) { 447 case jalr_op: 448 regs->regs[insn.r_format.rd] = 449 regs->cp0_epc + dec_insn.pc_inc + 450 dec_insn.next_pc_inc; 451 /* Fall through */ 452 case jr_op: 453 /* For R6, JR already emulated in jalr_op */ 454 if (NO_R6EMU && insn.r_format.func == jr_op) 455 break; 456 *contpc = regs->regs[insn.r_format.rs]; 457 return 1; 458 } 459 break; 460 case bcond_op: 461 switch (insn.i_format.rt) { 462 case bltzal_op: 463 case bltzall_op: 464 if (NO_R6EMU && (insn.i_format.rs || 465 insn.i_format.rt == bltzall_op)) 466 break; 467 468 regs->regs[31] = regs->cp0_epc + 469 dec_insn.pc_inc + 470 dec_insn.next_pc_inc; 471 /* Fall through */ 472 case bltzl_op: 473 if (NO_R6EMU) 474 break; 475 case bltz_op: 476 if ((long)regs->regs[insn.i_format.rs] < 0) 477 *contpc = regs->cp0_epc + 478 dec_insn.pc_inc + 479 (insn.i_format.simmediate << 2); 480 else 481 *contpc = regs->cp0_epc + 482 dec_insn.pc_inc + 483 dec_insn.next_pc_inc; 484 return 1; 485 case bgezal_op: 486 case bgezall_op: 487 if (NO_R6EMU && (insn.i_format.rs || 488 insn.i_format.rt == bgezall_op)) 489 break; 490 491 regs->regs[31] = regs->cp0_epc + 492 dec_insn.pc_inc + 493 dec_insn.next_pc_inc; 494 /* Fall through */ 495 case bgezl_op: 496 if (NO_R6EMU) 497 break; 498 case bgez_op: 499 if ((long)regs->regs[insn.i_format.rs] >= 0) 500 *contpc = regs->cp0_epc + 501 dec_insn.pc_inc + 502 (insn.i_format.simmediate << 2); 503 else 504 *contpc = regs->cp0_epc + 505 dec_insn.pc_inc + 506 dec_insn.next_pc_inc; 507 return 1; 508 } 509 break; 510 case jalx_op: 511 set_isa16_mode(bit); 512 case jal_op: 513 regs->regs[31] = regs->cp0_epc + 514 dec_insn.pc_inc + 515 dec_insn.next_pc_inc; 516 /* Fall through */ 517 case j_op: 518 *contpc = regs->cp0_epc + dec_insn.pc_inc; 519 *contpc >>= 28; 520 *contpc <<= 28; 521 *contpc |= (insn.j_format.target << 2); 522 /* Set microMIPS mode bit: XOR for jalx. */ 523 *contpc ^= bit; 524 return 1; 525 case beql_op: 526 if (NO_R6EMU) 527 break; 528 case beq_op: 529 if (regs->regs[insn.i_format.rs] == 530 regs->regs[insn.i_format.rt]) 531 *contpc = regs->cp0_epc + 532 dec_insn.pc_inc + 533 (insn.i_format.simmediate << 2); 534 else 535 *contpc = regs->cp0_epc + 536 dec_insn.pc_inc + 537 dec_insn.next_pc_inc; 538 return 1; 539 case bnel_op: 540 if (NO_R6EMU) 541 break; 542 case bne_op: 543 if (regs->regs[insn.i_format.rs] != 544 regs->regs[insn.i_format.rt]) 545 *contpc = regs->cp0_epc + 546 dec_insn.pc_inc + 547 (insn.i_format.simmediate << 2); 548 else 549 *contpc = regs->cp0_epc + 550 dec_insn.pc_inc + 551 dec_insn.next_pc_inc; 552 return 1; 553 case blezl_op: 554 if (!insn.i_format.rt && NO_R6EMU) 555 break; 556 case blez_op: 557 558 /* 559 * Compact branches for R6 for the 560 * blez and blezl opcodes. 561 * BLEZ | rs = 0 | rt != 0 == BLEZALC 562 * BLEZ | rs = rt != 0 == BGEZALC 563 * BLEZ | rs != 0 | rt != 0 == BGEUC 564 * BLEZL | rs = 0 | rt != 0 == BLEZC 565 * BLEZL | rs = rt != 0 == BGEZC 566 * BLEZL | rs != 0 | rt != 0 == BGEC 567 * 568 * For real BLEZ{,L}, rt is always 0. 569 */ 570 if (cpu_has_mips_r6 && insn.i_format.rt) { 571 if ((insn.i_format.opcode == blez_op) && 572 ((!insn.i_format.rs && insn.i_format.rt) || 573 (insn.i_format.rs == insn.i_format.rt))) 574 regs->regs[31] = regs->cp0_epc + 575 dec_insn.pc_inc; 576 *contpc = regs->cp0_epc + dec_insn.pc_inc + 577 dec_insn.next_pc_inc; 578 579 return 1; 580 } 581 if ((long)regs->regs[insn.i_format.rs] <= 0) 582 *contpc = regs->cp0_epc + 583 dec_insn.pc_inc + 584 (insn.i_format.simmediate << 2); 585 else 586 *contpc = regs->cp0_epc + 587 dec_insn.pc_inc + 588 dec_insn.next_pc_inc; 589 return 1; 590 case bgtzl_op: 591 if (!insn.i_format.rt && NO_R6EMU) 592 break; 593 case bgtz_op: 594 /* 595 * Compact branches for R6 for the 596 * bgtz and bgtzl opcodes. 597 * BGTZ | rs = 0 | rt != 0 == BGTZALC 598 * BGTZ | rs = rt != 0 == BLTZALC 599 * BGTZ | rs != 0 | rt != 0 == BLTUC 600 * BGTZL | rs = 0 | rt != 0 == BGTZC 601 * BGTZL | rs = rt != 0 == BLTZC 602 * BGTZL | rs != 0 | rt != 0 == BLTC 603 * 604 * *ZALC varint for BGTZ &&& rt != 0 605 * For real GTZ{,L}, rt is always 0. 606 */ 607 if (cpu_has_mips_r6 && insn.i_format.rt) { 608 if ((insn.i_format.opcode == blez_op) && 609 ((!insn.i_format.rs && insn.i_format.rt) || 610 (insn.i_format.rs == insn.i_format.rt))) 611 regs->regs[31] = regs->cp0_epc + 612 dec_insn.pc_inc; 613 *contpc = regs->cp0_epc + dec_insn.pc_inc + 614 dec_insn.next_pc_inc; 615 616 return 1; 617 } 618 619 if ((long)regs->regs[insn.i_format.rs] > 0) 620 *contpc = regs->cp0_epc + 621 dec_insn.pc_inc + 622 (insn.i_format.simmediate << 2); 623 else 624 *contpc = regs->cp0_epc + 625 dec_insn.pc_inc + 626 dec_insn.next_pc_inc; 627 return 1; 628 case cbcond0_op: 629 case cbcond1_op: 630 if (!cpu_has_mips_r6) 631 break; 632 if (insn.i_format.rt && !insn.i_format.rs) 633 regs->regs[31] = regs->cp0_epc + 4; 634 *contpc = regs->cp0_epc + dec_insn.pc_inc + 635 dec_insn.next_pc_inc; 636 637 return 1; 638 #ifdef CONFIG_CPU_CAVIUM_OCTEON 639 case lwc2_op: /* This is bbit0 on Octeon */ 640 if ((regs->regs[insn.i_format.rs] & (1ull<<insn.i_format.rt)) == 0) 641 *contpc = regs->cp0_epc + 4 + (insn.i_format.simmediate << 2); 642 else 643 *contpc = regs->cp0_epc + 8; 644 return 1; 645 case ldc2_op: /* This is bbit032 on Octeon */ 646 if ((regs->regs[insn.i_format.rs] & (1ull<<(insn.i_format.rt + 32))) == 0) 647 *contpc = regs->cp0_epc + 4 + (insn.i_format.simmediate << 2); 648 else 649 *contpc = regs->cp0_epc + 8; 650 return 1; 651 case swc2_op: /* This is bbit1 on Octeon */ 652 if (regs->regs[insn.i_format.rs] & (1ull<<insn.i_format.rt)) 653 *contpc = regs->cp0_epc + 4 + (insn.i_format.simmediate << 2); 654 else 655 *contpc = regs->cp0_epc + 8; 656 return 1; 657 case sdc2_op: /* This is bbit132 on Octeon */ 658 if (regs->regs[insn.i_format.rs] & (1ull<<(insn.i_format.rt + 32))) 659 *contpc = regs->cp0_epc + 4 + (insn.i_format.simmediate << 2); 660 else 661 *contpc = regs->cp0_epc + 8; 662 return 1; 663 #else 664 case bc6_op: 665 /* 666 * Only valid for MIPS R6 but we can still end up 667 * here from a broken userland so just tell emulator 668 * this is not a branch and let it break later on. 669 */ 670 if (!cpu_has_mips_r6) 671 break; 672 *contpc = regs->cp0_epc + dec_insn.pc_inc + 673 dec_insn.next_pc_inc; 674 675 return 1; 676 case balc6_op: 677 if (!cpu_has_mips_r6) 678 break; 679 regs->regs[31] = regs->cp0_epc + 4; 680 *contpc = regs->cp0_epc + dec_insn.pc_inc + 681 dec_insn.next_pc_inc; 682 683 return 1; 684 case beqzcjic_op: 685 if (!cpu_has_mips_r6) 686 break; 687 *contpc = regs->cp0_epc + dec_insn.pc_inc + 688 dec_insn.next_pc_inc; 689 690 return 1; 691 case bnezcjialc_op: 692 if (!cpu_has_mips_r6) 693 break; 694 if (!insn.i_format.rs) 695 regs->regs[31] = regs->cp0_epc + 4; 696 *contpc = regs->cp0_epc + dec_insn.pc_inc + 697 dec_insn.next_pc_inc; 698 699 return 1; 700 #endif 701 case cop0_op: 702 case cop1_op: 703 /* Need to check for R6 bc1nez and bc1eqz branches */ 704 if (cpu_has_mips_r6 && 705 ((insn.i_format.rs == bc1eqz_op) || 706 (insn.i_format.rs == bc1nez_op))) { 707 bit = 0; 708 switch (insn.i_format.rs) { 709 case bc1eqz_op: 710 if (get_fpr32(¤t->thread.fpu.fpr[insn.i_format.rt], 0) & 0x1) 711 bit = 1; 712 break; 713 case bc1nez_op: 714 if (!(get_fpr32(¤t->thread.fpu.fpr[insn.i_format.rt], 0) & 0x1)) 715 bit = 1; 716 break; 717 } 718 if (bit) 719 *contpc = regs->cp0_epc + 720 dec_insn.pc_inc + 721 (insn.i_format.simmediate << 2); 722 else 723 *contpc = regs->cp0_epc + 724 dec_insn.pc_inc + 725 dec_insn.next_pc_inc; 726 727 return 1; 728 } 729 /* R2/R6 compatible cop1 instruction. Fall through */ 730 case cop2_op: 731 case cop1x_op: 732 if (insn.i_format.rs == bc_op) { 733 preempt_disable(); 734 if (is_fpu_owner()) 735 fcr31 = read_32bit_cp1_register(CP1_STATUS); 736 else 737 fcr31 = current->thread.fpu.fcr31; 738 preempt_enable(); 739 740 bit = (insn.i_format.rt >> 2); 741 bit += (bit != 0); 742 bit += 23; 743 switch (insn.i_format.rt & 3) { 744 case 0: /* bc1f */ 745 case 2: /* bc1fl */ 746 if (~fcr31 & (1 << bit)) 747 *contpc = regs->cp0_epc + 748 dec_insn.pc_inc + 749 (insn.i_format.simmediate << 2); 750 else 751 *contpc = regs->cp0_epc + 752 dec_insn.pc_inc + 753 dec_insn.next_pc_inc; 754 return 1; 755 case 1: /* bc1t */ 756 case 3: /* bc1tl */ 757 if (fcr31 & (1 << bit)) 758 *contpc = regs->cp0_epc + 759 dec_insn.pc_inc + 760 (insn.i_format.simmediate << 2); 761 else 762 *contpc = regs->cp0_epc + 763 dec_insn.pc_inc + 764 dec_insn.next_pc_inc; 765 return 1; 766 } 767 } 768 break; 769 } 770 return 0; 771 } 772 773 /* 774 * In the Linux kernel, we support selection of FPR format on the 775 * basis of the Status.FR bit. If an FPU is not present, the FR bit 776 * is hardwired to zero, which would imply a 32-bit FPU even for 777 * 64-bit CPUs so we rather look at TIF_32BIT_FPREGS. 778 * FPU emu is slow and bulky and optimizing this function offers fairly 779 * sizeable benefits so we try to be clever and make this function return 780 * a constant whenever possible, that is on 64-bit kernels without O32 781 * compatibility enabled and on 32-bit without 64-bit FPU support. 782 */ 783 static inline int cop1_64bit(struct pt_regs *xcp) 784 { 785 if (config_enabled(CONFIG_64BIT) && !config_enabled(CONFIG_MIPS32_O32)) 786 return 1; 787 else if (config_enabled(CONFIG_32BIT) && 788 !config_enabled(CONFIG_MIPS_O32_FP64_SUPPORT)) 789 return 0; 790 791 return !test_thread_flag(TIF_32BIT_FPREGS); 792 } 793 794 static inline bool hybrid_fprs(void) 795 { 796 return test_thread_flag(TIF_HYBRID_FPREGS); 797 } 798 799 #define SIFROMREG(si, x) \ 800 do { \ 801 if (cop1_64bit(xcp) && !hybrid_fprs()) \ 802 (si) = (int)get_fpr32(&ctx->fpr[x], 0); \ 803 else \ 804 (si) = (int)get_fpr32(&ctx->fpr[(x) & ~1], (x) & 1); \ 805 } while (0) 806 807 #define SITOREG(si, x) \ 808 do { \ 809 if (cop1_64bit(xcp) && !hybrid_fprs()) { \ 810 unsigned i; \ 811 set_fpr32(&ctx->fpr[x], 0, si); \ 812 for (i = 1; i < ARRAY_SIZE(ctx->fpr[x].val32); i++) \ 813 set_fpr32(&ctx->fpr[x], i, 0); \ 814 } else { \ 815 set_fpr32(&ctx->fpr[(x) & ~1], (x) & 1, si); \ 816 } \ 817 } while (0) 818 819 #define SIFROMHREG(si, x) ((si) = (int)get_fpr32(&ctx->fpr[x], 1)) 820 821 #define SITOHREG(si, x) \ 822 do { \ 823 unsigned i; \ 824 set_fpr32(&ctx->fpr[x], 1, si); \ 825 for (i = 2; i < ARRAY_SIZE(ctx->fpr[x].val32); i++) \ 826 set_fpr32(&ctx->fpr[x], i, 0); \ 827 } while (0) 828 829 #define DIFROMREG(di, x) \ 830 ((di) = get_fpr64(&ctx->fpr[(x) & ~(cop1_64bit(xcp) == 0)], 0)) 831 832 #define DITOREG(di, x) \ 833 do { \ 834 unsigned fpr, i; \ 835 fpr = (x) & ~(cop1_64bit(xcp) == 0); \ 836 set_fpr64(&ctx->fpr[fpr], 0, di); \ 837 for (i = 1; i < ARRAY_SIZE(ctx->fpr[x].val64); i++) \ 838 set_fpr64(&ctx->fpr[fpr], i, 0); \ 839 } while (0) 840 841 #define SPFROMREG(sp, x) SIFROMREG((sp).bits, x) 842 #define SPTOREG(sp, x) SITOREG((sp).bits, x) 843 #define DPFROMREG(dp, x) DIFROMREG((dp).bits, x) 844 #define DPTOREG(dp, x) DITOREG((dp).bits, x) 845 846 /* 847 * Emulate a CFC1 instruction. 848 */ 849 static inline void cop1_cfc(struct pt_regs *xcp, struct mips_fpu_struct *ctx, 850 mips_instruction ir) 851 { 852 u32 fcr31 = ctx->fcr31; 853 u32 value = 0; 854 855 switch (MIPSInst_RD(ir)) { 856 case FPCREG_CSR: 857 value = fcr31; 858 pr_debug("%p gpr[%d]<-csr=%08x\n", 859 (void *)xcp->cp0_epc, MIPSInst_RT(ir), value); 860 break; 861 862 case FPCREG_FENR: 863 if (!cpu_has_mips_r) 864 break; 865 value = (fcr31 >> (FPU_CSR_FS_S - MIPS_FENR_FS_S)) & 866 MIPS_FENR_FS; 867 value |= fcr31 & (FPU_CSR_ALL_E | FPU_CSR_RM); 868 pr_debug("%p gpr[%d]<-enr=%08x\n", 869 (void *)xcp->cp0_epc, MIPSInst_RT(ir), value); 870 break; 871 872 case FPCREG_FEXR: 873 if (!cpu_has_mips_r) 874 break; 875 value = fcr31 & (FPU_CSR_ALL_X | FPU_CSR_ALL_S); 876 pr_debug("%p gpr[%d]<-exr=%08x\n", 877 (void *)xcp->cp0_epc, MIPSInst_RT(ir), value); 878 break; 879 880 case FPCREG_FCCR: 881 if (!cpu_has_mips_r) 882 break; 883 value = (fcr31 >> (FPU_CSR_COND_S - MIPS_FCCR_COND0_S)) & 884 MIPS_FCCR_COND0; 885 value |= (fcr31 >> (FPU_CSR_COND1_S - MIPS_FCCR_COND1_S)) & 886 (MIPS_FCCR_CONDX & ~MIPS_FCCR_COND0); 887 pr_debug("%p gpr[%d]<-ccr=%08x\n", 888 (void *)xcp->cp0_epc, MIPSInst_RT(ir), value); 889 break; 890 891 case FPCREG_RID: 892 value = boot_cpu_data.fpu_id; 893 break; 894 895 default: 896 break; 897 } 898 899 if (MIPSInst_RT(ir)) 900 xcp->regs[MIPSInst_RT(ir)] = value; 901 } 902 903 /* 904 * Emulate a CTC1 instruction. 905 */ 906 static inline void cop1_ctc(struct pt_regs *xcp, struct mips_fpu_struct *ctx, 907 mips_instruction ir) 908 { 909 u32 fcr31 = ctx->fcr31; 910 u32 value; 911 u32 mask; 912 913 if (MIPSInst_RT(ir) == 0) 914 value = 0; 915 else 916 value = xcp->regs[MIPSInst_RT(ir)]; 917 918 switch (MIPSInst_RD(ir)) { 919 case FPCREG_CSR: 920 pr_debug("%p gpr[%d]->csr=%08x\n", 921 (void *)xcp->cp0_epc, MIPSInst_RT(ir), value); 922 923 /* Preserve read-only bits. */ 924 mask = boot_cpu_data.fpu_msk31; 925 fcr31 = (value & ~mask) | (fcr31 & mask); 926 break; 927 928 case FPCREG_FENR: 929 if (!cpu_has_mips_r) 930 break; 931 pr_debug("%p gpr[%d]->enr=%08x\n", 932 (void *)xcp->cp0_epc, MIPSInst_RT(ir), value); 933 fcr31 &= ~(FPU_CSR_FS | FPU_CSR_ALL_E | FPU_CSR_RM); 934 fcr31 |= (value << (FPU_CSR_FS_S - MIPS_FENR_FS_S)) & 935 FPU_CSR_FS; 936 fcr31 |= value & (FPU_CSR_ALL_E | FPU_CSR_RM); 937 break; 938 939 case FPCREG_FEXR: 940 if (!cpu_has_mips_r) 941 break; 942 pr_debug("%p gpr[%d]->exr=%08x\n", 943 (void *)xcp->cp0_epc, MIPSInst_RT(ir), value); 944 fcr31 &= ~(FPU_CSR_ALL_X | FPU_CSR_ALL_S); 945 fcr31 |= value & (FPU_CSR_ALL_X | FPU_CSR_ALL_S); 946 break; 947 948 case FPCREG_FCCR: 949 if (!cpu_has_mips_r) 950 break; 951 pr_debug("%p gpr[%d]->ccr=%08x\n", 952 (void *)xcp->cp0_epc, MIPSInst_RT(ir), value); 953 fcr31 &= ~(FPU_CSR_CONDX | FPU_CSR_COND); 954 fcr31 |= (value << (FPU_CSR_COND_S - MIPS_FCCR_COND0_S)) & 955 FPU_CSR_COND; 956 fcr31 |= (value << (FPU_CSR_COND1_S - MIPS_FCCR_COND1_S)) & 957 FPU_CSR_CONDX; 958 break; 959 960 default: 961 break; 962 } 963 964 ctx->fcr31 = fcr31; 965 } 966 967 /* 968 * Emulate the single floating point instruction pointed at by EPC. 969 * Two instructions if the instruction is in a branch delay slot. 970 */ 971 972 static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_struct *ctx, 973 struct mm_decoded_insn dec_insn, void *__user *fault_addr) 974 { 975 unsigned long contpc = xcp->cp0_epc + dec_insn.pc_inc; 976 unsigned int cond, cbit; 977 mips_instruction ir; 978 int likely, pc_inc; 979 u32 __user *wva; 980 u64 __user *dva; 981 u32 wval; 982 u64 dval; 983 int sig; 984 985 /* 986 * These are giving gcc a gentle hint about what to expect in 987 * dec_inst in order to do better optimization. 988 */ 989 if (!cpu_has_mmips && dec_insn.micro_mips_mode) 990 unreachable(); 991 992 /* XXX NEC Vr54xx bug workaround */ 993 if (delay_slot(xcp)) { 994 if (dec_insn.micro_mips_mode) { 995 if (!mm_isBranchInstr(xcp, dec_insn, &contpc)) 996 clear_delay_slot(xcp); 997 } else { 998 if (!isBranchInstr(xcp, dec_insn, &contpc)) 999 clear_delay_slot(xcp); 1000 } 1001 } 1002 1003 if (delay_slot(xcp)) { 1004 /* 1005 * The instruction to be emulated is in a branch delay slot 1006 * which means that we have to emulate the branch instruction 1007 * BEFORE we do the cop1 instruction. 1008 * 1009 * This branch could be a COP1 branch, but in that case we 1010 * would have had a trap for that instruction, and would not 1011 * come through this route. 1012 * 1013 * Linux MIPS branch emulator operates on context, updating the 1014 * cp0_epc. 1015 */ 1016 ir = dec_insn.next_insn; /* process delay slot instr */ 1017 pc_inc = dec_insn.next_pc_inc; 1018 } else { 1019 ir = dec_insn.insn; /* process current instr */ 1020 pc_inc = dec_insn.pc_inc; 1021 } 1022 1023 /* 1024 * Since microMIPS FPU instructios are a subset of MIPS32 FPU 1025 * instructions, we want to convert microMIPS FPU instructions 1026 * into MIPS32 instructions so that we could reuse all of the 1027 * FPU emulation code. 1028 * 1029 * NOTE: We cannot do this for branch instructions since they 1030 * are not a subset. Example: Cannot emulate a 16-bit 1031 * aligned target address with a MIPS32 instruction. 1032 */ 1033 if (dec_insn.micro_mips_mode) { 1034 /* 1035 * If next instruction is a 16-bit instruction, then it 1036 * it cannot be a FPU instruction. This could happen 1037 * since we can be called for non-FPU instructions. 1038 */ 1039 if ((pc_inc == 2) || 1040 (microMIPS32_to_MIPS32((union mips_instruction *)&ir) 1041 == SIGILL)) 1042 return SIGILL; 1043 } 1044 1045 emul: 1046 perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 1, xcp, 0); 1047 MIPS_FPU_EMU_INC_STATS(emulated); 1048 switch (MIPSInst_OPCODE(ir)) { 1049 case ldc1_op: 1050 dva = (u64 __user *) (xcp->regs[MIPSInst_RS(ir)] + 1051 MIPSInst_SIMM(ir)); 1052 MIPS_FPU_EMU_INC_STATS(loads); 1053 1054 if (!access_ok(VERIFY_READ, dva, sizeof(u64))) { 1055 MIPS_FPU_EMU_INC_STATS(errors); 1056 *fault_addr = dva; 1057 return SIGBUS; 1058 } 1059 if (__get_user(dval, dva)) { 1060 MIPS_FPU_EMU_INC_STATS(errors); 1061 *fault_addr = dva; 1062 return SIGSEGV; 1063 } 1064 DITOREG(dval, MIPSInst_RT(ir)); 1065 break; 1066 1067 case sdc1_op: 1068 dva = (u64 __user *) (xcp->regs[MIPSInst_RS(ir)] + 1069 MIPSInst_SIMM(ir)); 1070 MIPS_FPU_EMU_INC_STATS(stores); 1071 DIFROMREG(dval, MIPSInst_RT(ir)); 1072 if (!access_ok(VERIFY_WRITE, dva, sizeof(u64))) { 1073 MIPS_FPU_EMU_INC_STATS(errors); 1074 *fault_addr = dva; 1075 return SIGBUS; 1076 } 1077 if (__put_user(dval, dva)) { 1078 MIPS_FPU_EMU_INC_STATS(errors); 1079 *fault_addr = dva; 1080 return SIGSEGV; 1081 } 1082 break; 1083 1084 case lwc1_op: 1085 wva = (u32 __user *) (xcp->regs[MIPSInst_RS(ir)] + 1086 MIPSInst_SIMM(ir)); 1087 MIPS_FPU_EMU_INC_STATS(loads); 1088 if (!access_ok(VERIFY_READ, wva, sizeof(u32))) { 1089 MIPS_FPU_EMU_INC_STATS(errors); 1090 *fault_addr = wva; 1091 return SIGBUS; 1092 } 1093 if (__get_user(wval, wva)) { 1094 MIPS_FPU_EMU_INC_STATS(errors); 1095 *fault_addr = wva; 1096 return SIGSEGV; 1097 } 1098 SITOREG(wval, MIPSInst_RT(ir)); 1099 break; 1100 1101 case swc1_op: 1102 wva = (u32 __user *) (xcp->regs[MIPSInst_RS(ir)] + 1103 MIPSInst_SIMM(ir)); 1104 MIPS_FPU_EMU_INC_STATS(stores); 1105 SIFROMREG(wval, MIPSInst_RT(ir)); 1106 if (!access_ok(VERIFY_WRITE, wva, sizeof(u32))) { 1107 MIPS_FPU_EMU_INC_STATS(errors); 1108 *fault_addr = wva; 1109 return SIGBUS; 1110 } 1111 if (__put_user(wval, wva)) { 1112 MIPS_FPU_EMU_INC_STATS(errors); 1113 *fault_addr = wva; 1114 return SIGSEGV; 1115 } 1116 break; 1117 1118 case cop1_op: 1119 switch (MIPSInst_RS(ir)) { 1120 case dmfc_op: 1121 if (!cpu_has_mips_3_4_5 && !cpu_has_mips64) 1122 return SIGILL; 1123 1124 /* copregister fs -> gpr[rt] */ 1125 if (MIPSInst_RT(ir) != 0) { 1126 DIFROMREG(xcp->regs[MIPSInst_RT(ir)], 1127 MIPSInst_RD(ir)); 1128 } 1129 break; 1130 1131 case dmtc_op: 1132 if (!cpu_has_mips_3_4_5 && !cpu_has_mips64) 1133 return SIGILL; 1134 1135 /* copregister fs <- rt */ 1136 DITOREG(xcp->regs[MIPSInst_RT(ir)], MIPSInst_RD(ir)); 1137 break; 1138 1139 case mfhc_op: 1140 if (!cpu_has_mips_r2) 1141 goto sigill; 1142 1143 /* copregister rd -> gpr[rt] */ 1144 if (MIPSInst_RT(ir) != 0) { 1145 SIFROMHREG(xcp->regs[MIPSInst_RT(ir)], 1146 MIPSInst_RD(ir)); 1147 } 1148 break; 1149 1150 case mthc_op: 1151 if (!cpu_has_mips_r2) 1152 goto sigill; 1153 1154 /* copregister rd <- gpr[rt] */ 1155 SITOHREG(xcp->regs[MIPSInst_RT(ir)], MIPSInst_RD(ir)); 1156 break; 1157 1158 case mfc_op: 1159 /* copregister rd -> gpr[rt] */ 1160 if (MIPSInst_RT(ir) != 0) { 1161 SIFROMREG(xcp->regs[MIPSInst_RT(ir)], 1162 MIPSInst_RD(ir)); 1163 } 1164 break; 1165 1166 case mtc_op: 1167 /* copregister rd <- rt */ 1168 SITOREG(xcp->regs[MIPSInst_RT(ir)], MIPSInst_RD(ir)); 1169 break; 1170 1171 case cfc_op: 1172 /* cop control register rd -> gpr[rt] */ 1173 cop1_cfc(xcp, ctx, ir); 1174 break; 1175 1176 case ctc_op: 1177 /* copregister rd <- rt */ 1178 cop1_ctc(xcp, ctx, ir); 1179 if ((ctx->fcr31 >> 5) & ctx->fcr31 & FPU_CSR_ALL_E) { 1180 return SIGFPE; 1181 } 1182 break; 1183 1184 case bc_op: 1185 if (delay_slot(xcp)) 1186 return SIGILL; 1187 1188 if (cpu_has_mips_4_5_r) 1189 cbit = fpucondbit[MIPSInst_RT(ir) >> 2]; 1190 else 1191 cbit = FPU_CSR_COND; 1192 cond = ctx->fcr31 & cbit; 1193 1194 likely = 0; 1195 switch (MIPSInst_RT(ir) & 3) { 1196 case bcfl_op: 1197 if (cpu_has_mips_2_3_4_5_r) 1198 likely = 1; 1199 /* Fall through */ 1200 case bcf_op: 1201 cond = !cond; 1202 break; 1203 case bctl_op: 1204 if (cpu_has_mips_2_3_4_5_r) 1205 likely = 1; 1206 /* Fall through */ 1207 case bct_op: 1208 break; 1209 } 1210 1211 set_delay_slot(xcp); 1212 if (cond) { 1213 /* 1214 * Branch taken: emulate dslot instruction 1215 */ 1216 unsigned long bcpc; 1217 1218 /* 1219 * Remember EPC at the branch to point back 1220 * at so that any delay-slot instruction 1221 * signal is not silently ignored. 1222 */ 1223 bcpc = xcp->cp0_epc; 1224 xcp->cp0_epc += dec_insn.pc_inc; 1225 1226 contpc = MIPSInst_SIMM(ir); 1227 ir = dec_insn.next_insn; 1228 if (dec_insn.micro_mips_mode) { 1229 contpc = (xcp->cp0_epc + (contpc << 1)); 1230 1231 /* If 16-bit instruction, not FPU. */ 1232 if ((dec_insn.next_pc_inc == 2) || 1233 (microMIPS32_to_MIPS32((union mips_instruction *)&ir) == SIGILL)) { 1234 1235 /* 1236 * Since this instruction will 1237 * be put on the stack with 1238 * 32-bit words, get around 1239 * this problem by putting a 1240 * NOP16 as the second one. 1241 */ 1242 if (dec_insn.next_pc_inc == 2) 1243 ir = (ir & (~0xffff)) | MM_NOP16; 1244 1245 /* 1246 * Single step the non-CP1 1247 * instruction in the dslot. 1248 */ 1249 sig = mips_dsemul(xcp, ir, 1250 contpc); 1251 if (sig) 1252 xcp->cp0_epc = bcpc; 1253 /* 1254 * SIGILL forces out of 1255 * the emulation loop. 1256 */ 1257 return sig ? sig : SIGILL; 1258 } 1259 } else 1260 contpc = (xcp->cp0_epc + (contpc << 2)); 1261 1262 switch (MIPSInst_OPCODE(ir)) { 1263 case lwc1_op: 1264 case swc1_op: 1265 goto emul; 1266 1267 case ldc1_op: 1268 case sdc1_op: 1269 if (cpu_has_mips_2_3_4_5_r) 1270 goto emul; 1271 1272 goto bc_sigill; 1273 1274 case cop1_op: 1275 goto emul; 1276 1277 case cop1x_op: 1278 if (cpu_has_mips_4_5_64_r2_r6) 1279 /* its one of ours */ 1280 goto emul; 1281 1282 goto bc_sigill; 1283 1284 case spec_op: 1285 switch (MIPSInst_FUNC(ir)) { 1286 case movc_op: 1287 if (cpu_has_mips_4_5_r) 1288 goto emul; 1289 1290 goto bc_sigill; 1291 } 1292 break; 1293 1294 bc_sigill: 1295 xcp->cp0_epc = bcpc; 1296 return SIGILL; 1297 } 1298 1299 /* 1300 * Single step the non-cp1 1301 * instruction in the dslot 1302 */ 1303 sig = mips_dsemul(xcp, ir, contpc); 1304 if (sig) 1305 xcp->cp0_epc = bcpc; 1306 /* SIGILL forces out of the emulation loop. */ 1307 return sig ? sig : SIGILL; 1308 } else if (likely) { /* branch not taken */ 1309 /* 1310 * branch likely nullifies 1311 * dslot if not taken 1312 */ 1313 xcp->cp0_epc += dec_insn.pc_inc; 1314 contpc += dec_insn.pc_inc; 1315 /* 1316 * else continue & execute 1317 * dslot as normal insn 1318 */ 1319 } 1320 break; 1321 1322 default: 1323 if (!(MIPSInst_RS(ir) & 0x10)) 1324 return SIGILL; 1325 1326 /* a real fpu computation instruction */ 1327 if ((sig = fpu_emu(xcp, ctx, ir))) 1328 return sig; 1329 } 1330 break; 1331 1332 case cop1x_op: 1333 if (!cpu_has_mips_4_5_64_r2_r6) 1334 return SIGILL; 1335 1336 sig = fpux_emu(xcp, ctx, ir, fault_addr); 1337 if (sig) 1338 return sig; 1339 break; 1340 1341 case spec_op: 1342 if (!cpu_has_mips_4_5_r) 1343 return SIGILL; 1344 1345 if (MIPSInst_FUNC(ir) != movc_op) 1346 return SIGILL; 1347 cond = fpucondbit[MIPSInst_RT(ir) >> 2]; 1348 if (((ctx->fcr31 & cond) != 0) == ((MIPSInst_RT(ir) & 1) != 0)) 1349 xcp->regs[MIPSInst_RD(ir)] = 1350 xcp->regs[MIPSInst_RS(ir)]; 1351 break; 1352 default: 1353 sigill: 1354 return SIGILL; 1355 } 1356 1357 /* we did it !! */ 1358 xcp->cp0_epc = contpc; 1359 clear_delay_slot(xcp); 1360 1361 return 0; 1362 } 1363 1364 /* 1365 * Conversion table from MIPS compare ops 48-63 1366 * cond = ieee754dp_cmp(x,y,IEEE754_UN,sig); 1367 */ 1368 static const unsigned char cmptab[8] = { 1369 0, /* cmp_0 (sig) cmp_sf */ 1370 IEEE754_CUN, /* cmp_un (sig) cmp_ngle */ 1371 IEEE754_CEQ, /* cmp_eq (sig) cmp_seq */ 1372 IEEE754_CEQ | IEEE754_CUN, /* cmp_ueq (sig) cmp_ngl */ 1373 IEEE754_CLT, /* cmp_olt (sig) cmp_lt */ 1374 IEEE754_CLT | IEEE754_CUN, /* cmp_ult (sig) cmp_nge */ 1375 IEEE754_CLT | IEEE754_CEQ, /* cmp_ole (sig) cmp_le */ 1376 IEEE754_CLT | IEEE754_CEQ | IEEE754_CUN, /* cmp_ule (sig) cmp_ngt */ 1377 }; 1378 1379 1380 /* 1381 * Additional MIPS4 instructions 1382 */ 1383 1384 #define DEF3OP(name, p, f1, f2, f3) \ 1385 static union ieee754##p fpemu_##p##_##name(union ieee754##p r, \ 1386 union ieee754##p s, union ieee754##p t) \ 1387 { \ 1388 struct _ieee754_csr ieee754_csr_save; \ 1389 s = f1(s, t); \ 1390 ieee754_csr_save = ieee754_csr; \ 1391 s = f2(s, r); \ 1392 ieee754_csr_save.cx |= ieee754_csr.cx; \ 1393 ieee754_csr_save.sx |= ieee754_csr.sx; \ 1394 s = f3(s); \ 1395 ieee754_csr.cx |= ieee754_csr_save.cx; \ 1396 ieee754_csr.sx |= ieee754_csr_save.sx; \ 1397 return s; \ 1398 } 1399 1400 static union ieee754dp fpemu_dp_recip(union ieee754dp d) 1401 { 1402 return ieee754dp_div(ieee754dp_one(0), d); 1403 } 1404 1405 static union ieee754dp fpemu_dp_rsqrt(union ieee754dp d) 1406 { 1407 return ieee754dp_div(ieee754dp_one(0), ieee754dp_sqrt(d)); 1408 } 1409 1410 static union ieee754sp fpemu_sp_recip(union ieee754sp s) 1411 { 1412 return ieee754sp_div(ieee754sp_one(0), s); 1413 } 1414 1415 static union ieee754sp fpemu_sp_rsqrt(union ieee754sp s) 1416 { 1417 return ieee754sp_div(ieee754sp_one(0), ieee754sp_sqrt(s)); 1418 } 1419 1420 DEF3OP(madd, sp, ieee754sp_mul, ieee754sp_add, ); 1421 DEF3OP(msub, sp, ieee754sp_mul, ieee754sp_sub, ); 1422 DEF3OP(nmadd, sp, ieee754sp_mul, ieee754sp_add, ieee754sp_neg); 1423 DEF3OP(nmsub, sp, ieee754sp_mul, ieee754sp_sub, ieee754sp_neg); 1424 DEF3OP(madd, dp, ieee754dp_mul, ieee754dp_add, ); 1425 DEF3OP(msub, dp, ieee754dp_mul, ieee754dp_sub, ); 1426 DEF3OP(nmadd, dp, ieee754dp_mul, ieee754dp_add, ieee754dp_neg); 1427 DEF3OP(nmsub, dp, ieee754dp_mul, ieee754dp_sub, ieee754dp_neg); 1428 1429 static int fpux_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx, 1430 mips_instruction ir, void *__user *fault_addr) 1431 { 1432 unsigned rcsr = 0; /* resulting csr */ 1433 1434 MIPS_FPU_EMU_INC_STATS(cp1xops); 1435 1436 switch (MIPSInst_FMA_FFMT(ir)) { 1437 case s_fmt:{ /* 0 */ 1438 1439 union ieee754sp(*handler) (union ieee754sp, union ieee754sp, union ieee754sp); 1440 union ieee754sp fd, fr, fs, ft; 1441 u32 __user *va; 1442 u32 val; 1443 1444 switch (MIPSInst_FUNC(ir)) { 1445 case lwxc1_op: 1446 va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] + 1447 xcp->regs[MIPSInst_FT(ir)]); 1448 1449 MIPS_FPU_EMU_INC_STATS(loads); 1450 if (!access_ok(VERIFY_READ, va, sizeof(u32))) { 1451 MIPS_FPU_EMU_INC_STATS(errors); 1452 *fault_addr = va; 1453 return SIGBUS; 1454 } 1455 if (__get_user(val, va)) { 1456 MIPS_FPU_EMU_INC_STATS(errors); 1457 *fault_addr = va; 1458 return SIGSEGV; 1459 } 1460 SITOREG(val, MIPSInst_FD(ir)); 1461 break; 1462 1463 case swxc1_op: 1464 va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] + 1465 xcp->regs[MIPSInst_FT(ir)]); 1466 1467 MIPS_FPU_EMU_INC_STATS(stores); 1468 1469 SIFROMREG(val, MIPSInst_FS(ir)); 1470 if (!access_ok(VERIFY_WRITE, va, sizeof(u32))) { 1471 MIPS_FPU_EMU_INC_STATS(errors); 1472 *fault_addr = va; 1473 return SIGBUS; 1474 } 1475 if (put_user(val, va)) { 1476 MIPS_FPU_EMU_INC_STATS(errors); 1477 *fault_addr = va; 1478 return SIGSEGV; 1479 } 1480 break; 1481 1482 case madd_s_op: 1483 handler = fpemu_sp_madd; 1484 goto scoptop; 1485 case msub_s_op: 1486 handler = fpemu_sp_msub; 1487 goto scoptop; 1488 case nmadd_s_op: 1489 handler = fpemu_sp_nmadd; 1490 goto scoptop; 1491 case nmsub_s_op: 1492 handler = fpemu_sp_nmsub; 1493 goto scoptop; 1494 1495 scoptop: 1496 SPFROMREG(fr, MIPSInst_FR(ir)); 1497 SPFROMREG(fs, MIPSInst_FS(ir)); 1498 SPFROMREG(ft, MIPSInst_FT(ir)); 1499 fd = (*handler) (fr, fs, ft); 1500 SPTOREG(fd, MIPSInst_FD(ir)); 1501 1502 copcsr: 1503 if (ieee754_cxtest(IEEE754_INEXACT)) { 1504 MIPS_FPU_EMU_INC_STATS(ieee754_inexact); 1505 rcsr |= FPU_CSR_INE_X | FPU_CSR_INE_S; 1506 } 1507 if (ieee754_cxtest(IEEE754_UNDERFLOW)) { 1508 MIPS_FPU_EMU_INC_STATS(ieee754_underflow); 1509 rcsr |= FPU_CSR_UDF_X | FPU_CSR_UDF_S; 1510 } 1511 if (ieee754_cxtest(IEEE754_OVERFLOW)) { 1512 MIPS_FPU_EMU_INC_STATS(ieee754_overflow); 1513 rcsr |= FPU_CSR_OVF_X | FPU_CSR_OVF_S; 1514 } 1515 if (ieee754_cxtest(IEEE754_INVALID_OPERATION)) { 1516 MIPS_FPU_EMU_INC_STATS(ieee754_invalidop); 1517 rcsr |= FPU_CSR_INV_X | FPU_CSR_INV_S; 1518 } 1519 1520 ctx->fcr31 = (ctx->fcr31 & ~FPU_CSR_ALL_X) | rcsr; 1521 if ((ctx->fcr31 >> 5) & ctx->fcr31 & FPU_CSR_ALL_E) { 1522 /*printk ("SIGFPE: FPU csr = %08x\n", 1523 ctx->fcr31); */ 1524 return SIGFPE; 1525 } 1526 1527 break; 1528 1529 default: 1530 return SIGILL; 1531 } 1532 break; 1533 } 1534 1535 case d_fmt:{ /* 1 */ 1536 union ieee754dp(*handler) (union ieee754dp, union ieee754dp, union ieee754dp); 1537 union ieee754dp fd, fr, fs, ft; 1538 u64 __user *va; 1539 u64 val; 1540 1541 switch (MIPSInst_FUNC(ir)) { 1542 case ldxc1_op: 1543 va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] + 1544 xcp->regs[MIPSInst_FT(ir)]); 1545 1546 MIPS_FPU_EMU_INC_STATS(loads); 1547 if (!access_ok(VERIFY_READ, va, sizeof(u64))) { 1548 MIPS_FPU_EMU_INC_STATS(errors); 1549 *fault_addr = va; 1550 return SIGBUS; 1551 } 1552 if (__get_user(val, va)) { 1553 MIPS_FPU_EMU_INC_STATS(errors); 1554 *fault_addr = va; 1555 return SIGSEGV; 1556 } 1557 DITOREG(val, MIPSInst_FD(ir)); 1558 break; 1559 1560 case sdxc1_op: 1561 va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] + 1562 xcp->regs[MIPSInst_FT(ir)]); 1563 1564 MIPS_FPU_EMU_INC_STATS(stores); 1565 DIFROMREG(val, MIPSInst_FS(ir)); 1566 if (!access_ok(VERIFY_WRITE, va, sizeof(u64))) { 1567 MIPS_FPU_EMU_INC_STATS(errors); 1568 *fault_addr = va; 1569 return SIGBUS; 1570 } 1571 if (__put_user(val, va)) { 1572 MIPS_FPU_EMU_INC_STATS(errors); 1573 *fault_addr = va; 1574 return SIGSEGV; 1575 } 1576 break; 1577 1578 case madd_d_op: 1579 handler = fpemu_dp_madd; 1580 goto dcoptop; 1581 case msub_d_op: 1582 handler = fpemu_dp_msub; 1583 goto dcoptop; 1584 case nmadd_d_op: 1585 handler = fpemu_dp_nmadd; 1586 goto dcoptop; 1587 case nmsub_d_op: 1588 handler = fpemu_dp_nmsub; 1589 goto dcoptop; 1590 1591 dcoptop: 1592 DPFROMREG(fr, MIPSInst_FR(ir)); 1593 DPFROMREG(fs, MIPSInst_FS(ir)); 1594 DPFROMREG(ft, MIPSInst_FT(ir)); 1595 fd = (*handler) (fr, fs, ft); 1596 DPTOREG(fd, MIPSInst_FD(ir)); 1597 goto copcsr; 1598 1599 default: 1600 return SIGILL; 1601 } 1602 break; 1603 } 1604 1605 case 0x3: 1606 if (MIPSInst_FUNC(ir) != pfetch_op) 1607 return SIGILL; 1608 1609 /* ignore prefx operation */ 1610 break; 1611 1612 default: 1613 return SIGILL; 1614 } 1615 1616 return 0; 1617 } 1618 1619 1620 1621 /* 1622 * Emulate a single COP1 arithmetic instruction. 1623 */ 1624 static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx, 1625 mips_instruction ir) 1626 { 1627 int rfmt; /* resulting format */ 1628 unsigned rcsr = 0; /* resulting csr */ 1629 unsigned int oldrm; 1630 unsigned int cbit; 1631 unsigned cond; 1632 union { 1633 union ieee754dp d; 1634 union ieee754sp s; 1635 int w; 1636 s64 l; 1637 } rv; /* resulting value */ 1638 u64 bits; 1639 1640 MIPS_FPU_EMU_INC_STATS(cp1ops); 1641 switch (rfmt = (MIPSInst_FFMT(ir) & 0xf)) { 1642 case s_fmt: { /* 0 */ 1643 union { 1644 union ieee754sp(*b) (union ieee754sp, union ieee754sp); 1645 union ieee754sp(*u) (union ieee754sp); 1646 } handler; 1647 union ieee754sp fs, ft; 1648 1649 switch (MIPSInst_FUNC(ir)) { 1650 /* binary ops */ 1651 case fadd_op: 1652 handler.b = ieee754sp_add; 1653 goto scopbop; 1654 case fsub_op: 1655 handler.b = ieee754sp_sub; 1656 goto scopbop; 1657 case fmul_op: 1658 handler.b = ieee754sp_mul; 1659 goto scopbop; 1660 case fdiv_op: 1661 handler.b = ieee754sp_div; 1662 goto scopbop; 1663 1664 /* unary ops */ 1665 case fsqrt_op: 1666 if (!cpu_has_mips_2_3_4_5_r) 1667 return SIGILL; 1668 1669 handler.u = ieee754sp_sqrt; 1670 goto scopuop; 1671 1672 /* 1673 * Note that on some MIPS IV implementations such as the 1674 * R5000 and R8000 the FSQRT and FRECIP instructions do not 1675 * achieve full IEEE-754 accuracy - however this emulator does. 1676 */ 1677 case frsqrt_op: 1678 if (!cpu_has_mips_4_5_64_r2_r6) 1679 return SIGILL; 1680 1681 handler.u = fpemu_sp_rsqrt; 1682 goto scopuop; 1683 1684 case frecip_op: 1685 if (!cpu_has_mips_4_5_64_r2_r6) 1686 return SIGILL; 1687 1688 handler.u = fpemu_sp_recip; 1689 goto scopuop; 1690 1691 case fmovc_op: 1692 if (!cpu_has_mips_4_5_r) 1693 return SIGILL; 1694 1695 cond = fpucondbit[MIPSInst_FT(ir) >> 2]; 1696 if (((ctx->fcr31 & cond) != 0) != 1697 ((MIPSInst_FT(ir) & 1) != 0)) 1698 return 0; 1699 SPFROMREG(rv.s, MIPSInst_FS(ir)); 1700 break; 1701 1702 case fmovz_op: 1703 if (!cpu_has_mips_4_5_r) 1704 return SIGILL; 1705 1706 if (xcp->regs[MIPSInst_FT(ir)] != 0) 1707 return 0; 1708 SPFROMREG(rv.s, MIPSInst_FS(ir)); 1709 break; 1710 1711 case fmovn_op: 1712 if (!cpu_has_mips_4_5_r) 1713 return SIGILL; 1714 1715 if (xcp->regs[MIPSInst_FT(ir)] == 0) 1716 return 0; 1717 SPFROMREG(rv.s, MIPSInst_FS(ir)); 1718 break; 1719 1720 case fabs_op: 1721 handler.u = ieee754sp_abs; 1722 goto scopuop; 1723 1724 case fneg_op: 1725 handler.u = ieee754sp_neg; 1726 goto scopuop; 1727 1728 case fmov_op: 1729 /* an easy one */ 1730 SPFROMREG(rv.s, MIPSInst_FS(ir)); 1731 goto copcsr; 1732 1733 /* binary op on handler */ 1734 scopbop: 1735 SPFROMREG(fs, MIPSInst_FS(ir)); 1736 SPFROMREG(ft, MIPSInst_FT(ir)); 1737 1738 rv.s = (*handler.b) (fs, ft); 1739 goto copcsr; 1740 scopuop: 1741 SPFROMREG(fs, MIPSInst_FS(ir)); 1742 rv.s = (*handler.u) (fs); 1743 goto copcsr; 1744 copcsr: 1745 if (ieee754_cxtest(IEEE754_INEXACT)) { 1746 MIPS_FPU_EMU_INC_STATS(ieee754_inexact); 1747 rcsr |= FPU_CSR_INE_X | FPU_CSR_INE_S; 1748 } 1749 if (ieee754_cxtest(IEEE754_UNDERFLOW)) { 1750 MIPS_FPU_EMU_INC_STATS(ieee754_underflow); 1751 rcsr |= FPU_CSR_UDF_X | FPU_CSR_UDF_S; 1752 } 1753 if (ieee754_cxtest(IEEE754_OVERFLOW)) { 1754 MIPS_FPU_EMU_INC_STATS(ieee754_overflow); 1755 rcsr |= FPU_CSR_OVF_X | FPU_CSR_OVF_S; 1756 } 1757 if (ieee754_cxtest(IEEE754_ZERO_DIVIDE)) { 1758 MIPS_FPU_EMU_INC_STATS(ieee754_zerodiv); 1759 rcsr |= FPU_CSR_DIV_X | FPU_CSR_DIV_S; 1760 } 1761 if (ieee754_cxtest(IEEE754_INVALID_OPERATION)) { 1762 MIPS_FPU_EMU_INC_STATS(ieee754_invalidop); 1763 rcsr |= FPU_CSR_INV_X | FPU_CSR_INV_S; 1764 } 1765 break; 1766 1767 /* unary conv ops */ 1768 case fcvts_op: 1769 return SIGILL; /* not defined */ 1770 1771 case fcvtd_op: 1772 SPFROMREG(fs, MIPSInst_FS(ir)); 1773 rv.d = ieee754dp_fsp(fs); 1774 rfmt = d_fmt; 1775 goto copcsr; 1776 1777 case fcvtw_op: 1778 SPFROMREG(fs, MIPSInst_FS(ir)); 1779 rv.w = ieee754sp_tint(fs); 1780 rfmt = w_fmt; 1781 goto copcsr; 1782 1783 case fround_op: 1784 case ftrunc_op: 1785 case fceil_op: 1786 case ffloor_op: 1787 if (!cpu_has_mips_2_3_4_5_r) 1788 return SIGILL; 1789 1790 oldrm = ieee754_csr.rm; 1791 SPFROMREG(fs, MIPSInst_FS(ir)); 1792 ieee754_csr.rm = MIPSInst_FUNC(ir); 1793 rv.w = ieee754sp_tint(fs); 1794 ieee754_csr.rm = oldrm; 1795 rfmt = w_fmt; 1796 goto copcsr; 1797 1798 case fcvtl_op: 1799 if (!cpu_has_mips_3_4_5_64_r2_r6) 1800 return SIGILL; 1801 1802 SPFROMREG(fs, MIPSInst_FS(ir)); 1803 rv.l = ieee754sp_tlong(fs); 1804 rfmt = l_fmt; 1805 goto copcsr; 1806 1807 case froundl_op: 1808 case ftruncl_op: 1809 case fceill_op: 1810 case ffloorl_op: 1811 if (!cpu_has_mips_3_4_5_64_r2_r6) 1812 return SIGILL; 1813 1814 oldrm = ieee754_csr.rm; 1815 SPFROMREG(fs, MIPSInst_FS(ir)); 1816 ieee754_csr.rm = MIPSInst_FUNC(ir); 1817 rv.l = ieee754sp_tlong(fs); 1818 ieee754_csr.rm = oldrm; 1819 rfmt = l_fmt; 1820 goto copcsr; 1821 1822 default: 1823 if (MIPSInst_FUNC(ir) >= fcmp_op) { 1824 unsigned cmpop = MIPSInst_FUNC(ir) - fcmp_op; 1825 union ieee754sp fs, ft; 1826 1827 SPFROMREG(fs, MIPSInst_FS(ir)); 1828 SPFROMREG(ft, MIPSInst_FT(ir)); 1829 rv.w = ieee754sp_cmp(fs, ft, 1830 cmptab[cmpop & 0x7], cmpop & 0x8); 1831 rfmt = -1; 1832 if ((cmpop & 0x8) && ieee754_cxtest 1833 (IEEE754_INVALID_OPERATION)) 1834 rcsr = FPU_CSR_INV_X | FPU_CSR_INV_S; 1835 else 1836 goto copcsr; 1837 1838 } else 1839 return SIGILL; 1840 break; 1841 } 1842 break; 1843 } 1844 1845 case d_fmt: { 1846 union ieee754dp fs, ft; 1847 union { 1848 union ieee754dp(*b) (union ieee754dp, union ieee754dp); 1849 union ieee754dp(*u) (union ieee754dp); 1850 } handler; 1851 1852 switch (MIPSInst_FUNC(ir)) { 1853 /* binary ops */ 1854 case fadd_op: 1855 handler.b = ieee754dp_add; 1856 goto dcopbop; 1857 case fsub_op: 1858 handler.b = ieee754dp_sub; 1859 goto dcopbop; 1860 case fmul_op: 1861 handler.b = ieee754dp_mul; 1862 goto dcopbop; 1863 case fdiv_op: 1864 handler.b = ieee754dp_div; 1865 goto dcopbop; 1866 1867 /* unary ops */ 1868 case fsqrt_op: 1869 if (!cpu_has_mips_2_3_4_5_r) 1870 return SIGILL; 1871 1872 handler.u = ieee754dp_sqrt; 1873 goto dcopuop; 1874 /* 1875 * Note that on some MIPS IV implementations such as the 1876 * R5000 and R8000 the FSQRT and FRECIP instructions do not 1877 * achieve full IEEE-754 accuracy - however this emulator does. 1878 */ 1879 case frsqrt_op: 1880 if (!cpu_has_mips_4_5_64_r2_r6) 1881 return SIGILL; 1882 1883 handler.u = fpemu_dp_rsqrt; 1884 goto dcopuop; 1885 case frecip_op: 1886 if (!cpu_has_mips_4_5_64_r2_r6) 1887 return SIGILL; 1888 1889 handler.u = fpemu_dp_recip; 1890 goto dcopuop; 1891 case fmovc_op: 1892 if (!cpu_has_mips_4_5_r) 1893 return SIGILL; 1894 1895 cond = fpucondbit[MIPSInst_FT(ir) >> 2]; 1896 if (((ctx->fcr31 & cond) != 0) != 1897 ((MIPSInst_FT(ir) & 1) != 0)) 1898 return 0; 1899 DPFROMREG(rv.d, MIPSInst_FS(ir)); 1900 break; 1901 case fmovz_op: 1902 if (!cpu_has_mips_4_5_r) 1903 return SIGILL; 1904 1905 if (xcp->regs[MIPSInst_FT(ir)] != 0) 1906 return 0; 1907 DPFROMREG(rv.d, MIPSInst_FS(ir)); 1908 break; 1909 case fmovn_op: 1910 if (!cpu_has_mips_4_5_r) 1911 return SIGILL; 1912 1913 if (xcp->regs[MIPSInst_FT(ir)] == 0) 1914 return 0; 1915 DPFROMREG(rv.d, MIPSInst_FS(ir)); 1916 break; 1917 case fabs_op: 1918 handler.u = ieee754dp_abs; 1919 goto dcopuop; 1920 1921 case fneg_op: 1922 handler.u = ieee754dp_neg; 1923 goto dcopuop; 1924 1925 case fmov_op: 1926 /* an easy one */ 1927 DPFROMREG(rv.d, MIPSInst_FS(ir)); 1928 goto copcsr; 1929 1930 /* binary op on handler */ 1931 dcopbop: 1932 DPFROMREG(fs, MIPSInst_FS(ir)); 1933 DPFROMREG(ft, MIPSInst_FT(ir)); 1934 1935 rv.d = (*handler.b) (fs, ft); 1936 goto copcsr; 1937 dcopuop: 1938 DPFROMREG(fs, MIPSInst_FS(ir)); 1939 rv.d = (*handler.u) (fs); 1940 goto copcsr; 1941 1942 /* 1943 * unary conv ops 1944 */ 1945 case fcvts_op: 1946 DPFROMREG(fs, MIPSInst_FS(ir)); 1947 rv.s = ieee754sp_fdp(fs); 1948 rfmt = s_fmt; 1949 goto copcsr; 1950 1951 case fcvtd_op: 1952 return SIGILL; /* not defined */ 1953 1954 case fcvtw_op: 1955 DPFROMREG(fs, MIPSInst_FS(ir)); 1956 rv.w = ieee754dp_tint(fs); /* wrong */ 1957 rfmt = w_fmt; 1958 goto copcsr; 1959 1960 case fround_op: 1961 case ftrunc_op: 1962 case fceil_op: 1963 case ffloor_op: 1964 if (!cpu_has_mips_2_3_4_5_r) 1965 return SIGILL; 1966 1967 oldrm = ieee754_csr.rm; 1968 DPFROMREG(fs, MIPSInst_FS(ir)); 1969 ieee754_csr.rm = MIPSInst_FUNC(ir); 1970 rv.w = ieee754dp_tint(fs); 1971 ieee754_csr.rm = oldrm; 1972 rfmt = w_fmt; 1973 goto copcsr; 1974 1975 case fcvtl_op: 1976 if (!cpu_has_mips_3_4_5_64_r2_r6) 1977 return SIGILL; 1978 1979 DPFROMREG(fs, MIPSInst_FS(ir)); 1980 rv.l = ieee754dp_tlong(fs); 1981 rfmt = l_fmt; 1982 goto copcsr; 1983 1984 case froundl_op: 1985 case ftruncl_op: 1986 case fceill_op: 1987 case ffloorl_op: 1988 if (!cpu_has_mips_3_4_5_64_r2_r6) 1989 return SIGILL; 1990 1991 oldrm = ieee754_csr.rm; 1992 DPFROMREG(fs, MIPSInst_FS(ir)); 1993 ieee754_csr.rm = MIPSInst_FUNC(ir); 1994 rv.l = ieee754dp_tlong(fs); 1995 ieee754_csr.rm = oldrm; 1996 rfmt = l_fmt; 1997 goto copcsr; 1998 1999 default: 2000 if (MIPSInst_FUNC(ir) >= fcmp_op) { 2001 unsigned cmpop = MIPSInst_FUNC(ir) - fcmp_op; 2002 union ieee754dp fs, ft; 2003 2004 DPFROMREG(fs, MIPSInst_FS(ir)); 2005 DPFROMREG(ft, MIPSInst_FT(ir)); 2006 rv.w = ieee754dp_cmp(fs, ft, 2007 cmptab[cmpop & 0x7], cmpop & 0x8); 2008 rfmt = -1; 2009 if ((cmpop & 0x8) 2010 && 2011 ieee754_cxtest 2012 (IEEE754_INVALID_OPERATION)) 2013 rcsr = FPU_CSR_INV_X | FPU_CSR_INV_S; 2014 else 2015 goto copcsr; 2016 2017 } 2018 else { 2019 return SIGILL; 2020 } 2021 break; 2022 } 2023 break; 2024 2025 case w_fmt: 2026 switch (MIPSInst_FUNC(ir)) { 2027 case fcvts_op: 2028 /* convert word to single precision real */ 2029 SPFROMREG(fs, MIPSInst_FS(ir)); 2030 rv.s = ieee754sp_fint(fs.bits); 2031 rfmt = s_fmt; 2032 goto copcsr; 2033 case fcvtd_op: 2034 /* convert word to double precision real */ 2035 SPFROMREG(fs, MIPSInst_FS(ir)); 2036 rv.d = ieee754dp_fint(fs.bits); 2037 rfmt = d_fmt; 2038 goto copcsr; 2039 default: 2040 return SIGILL; 2041 } 2042 break; 2043 } 2044 2045 case l_fmt: 2046 2047 if (!cpu_has_mips_3_4_5_64_r2_r6) 2048 return SIGILL; 2049 2050 DIFROMREG(bits, MIPSInst_FS(ir)); 2051 2052 switch (MIPSInst_FUNC(ir)) { 2053 case fcvts_op: 2054 /* convert long to single precision real */ 2055 rv.s = ieee754sp_flong(bits); 2056 rfmt = s_fmt; 2057 goto copcsr; 2058 case fcvtd_op: 2059 /* convert long to double precision real */ 2060 rv.d = ieee754dp_flong(bits); 2061 rfmt = d_fmt; 2062 goto copcsr; 2063 default: 2064 return SIGILL; 2065 } 2066 break; 2067 2068 default: 2069 return SIGILL; 2070 } 2071 2072 /* 2073 * Update the fpu CSR register for this operation. 2074 * If an exception is required, generate a tidy SIGFPE exception, 2075 * without updating the result register. 2076 * Note: cause exception bits do not accumulate, they are rewritten 2077 * for each op; only the flag/sticky bits accumulate. 2078 */ 2079 ctx->fcr31 = (ctx->fcr31 & ~FPU_CSR_ALL_X) | rcsr; 2080 if ((ctx->fcr31 >> 5) & ctx->fcr31 & FPU_CSR_ALL_E) { 2081 /*printk ("SIGFPE: FPU csr = %08x\n",ctx->fcr31); */ 2082 return SIGFPE; 2083 } 2084 2085 /* 2086 * Now we can safely write the result back to the register file. 2087 */ 2088 switch (rfmt) { 2089 case -1: 2090 2091 if (cpu_has_mips_4_5_r) 2092 cbit = fpucondbit[MIPSInst_FD(ir) >> 2]; 2093 else 2094 cbit = FPU_CSR_COND; 2095 if (rv.w) 2096 ctx->fcr31 |= cbit; 2097 else 2098 ctx->fcr31 &= ~cbit; 2099 break; 2100 2101 case d_fmt: 2102 DPTOREG(rv.d, MIPSInst_FD(ir)); 2103 break; 2104 case s_fmt: 2105 SPTOREG(rv.s, MIPSInst_FD(ir)); 2106 break; 2107 case w_fmt: 2108 SITOREG(rv.w, MIPSInst_FD(ir)); 2109 break; 2110 case l_fmt: 2111 if (!cpu_has_mips_3_4_5_64_r2_r6) 2112 return SIGILL; 2113 2114 DITOREG(rv.l, MIPSInst_FD(ir)); 2115 break; 2116 default: 2117 return SIGILL; 2118 } 2119 2120 return 0; 2121 } 2122 2123 int fpu_emulator_cop1Handler(struct pt_regs *xcp, struct mips_fpu_struct *ctx, 2124 int has_fpu, void *__user *fault_addr) 2125 { 2126 unsigned long oldepc, prevepc; 2127 struct mm_decoded_insn dec_insn; 2128 u16 instr[4]; 2129 u16 *instr_ptr; 2130 int sig = 0; 2131 2132 oldepc = xcp->cp0_epc; 2133 do { 2134 prevepc = xcp->cp0_epc; 2135 2136 if (get_isa16_mode(prevepc) && cpu_has_mmips) { 2137 /* 2138 * Get next 2 microMIPS instructions and convert them 2139 * into 32-bit instructions. 2140 */ 2141 if ((get_user(instr[0], (u16 __user *)msk_isa16_mode(xcp->cp0_epc))) || 2142 (get_user(instr[1], (u16 __user *)msk_isa16_mode(xcp->cp0_epc + 2))) || 2143 (get_user(instr[2], (u16 __user *)msk_isa16_mode(xcp->cp0_epc + 4))) || 2144 (get_user(instr[3], (u16 __user *)msk_isa16_mode(xcp->cp0_epc + 6)))) { 2145 MIPS_FPU_EMU_INC_STATS(errors); 2146 return SIGBUS; 2147 } 2148 instr_ptr = instr; 2149 2150 /* Get first instruction. */ 2151 if (mm_insn_16bit(*instr_ptr)) { 2152 /* Duplicate the half-word. */ 2153 dec_insn.insn = (*instr_ptr << 16) | 2154 (*instr_ptr); 2155 /* 16-bit instruction. */ 2156 dec_insn.pc_inc = 2; 2157 instr_ptr += 1; 2158 } else { 2159 dec_insn.insn = (*instr_ptr << 16) | 2160 *(instr_ptr+1); 2161 /* 32-bit instruction. */ 2162 dec_insn.pc_inc = 4; 2163 instr_ptr += 2; 2164 } 2165 /* Get second instruction. */ 2166 if (mm_insn_16bit(*instr_ptr)) { 2167 /* Duplicate the half-word. */ 2168 dec_insn.next_insn = (*instr_ptr << 16) | 2169 (*instr_ptr); 2170 /* 16-bit instruction. */ 2171 dec_insn.next_pc_inc = 2; 2172 } else { 2173 dec_insn.next_insn = (*instr_ptr << 16) | 2174 *(instr_ptr+1); 2175 /* 32-bit instruction. */ 2176 dec_insn.next_pc_inc = 4; 2177 } 2178 dec_insn.micro_mips_mode = 1; 2179 } else { 2180 if ((get_user(dec_insn.insn, 2181 (mips_instruction __user *) xcp->cp0_epc)) || 2182 (get_user(dec_insn.next_insn, 2183 (mips_instruction __user *)(xcp->cp0_epc+4)))) { 2184 MIPS_FPU_EMU_INC_STATS(errors); 2185 return SIGBUS; 2186 } 2187 dec_insn.pc_inc = 4; 2188 dec_insn.next_pc_inc = 4; 2189 dec_insn.micro_mips_mode = 0; 2190 } 2191 2192 if ((dec_insn.insn == 0) || 2193 ((dec_insn.pc_inc == 2) && 2194 ((dec_insn.insn & 0xffff) == MM_NOP16))) 2195 xcp->cp0_epc += dec_insn.pc_inc; /* Skip NOPs */ 2196 else { 2197 /* 2198 * The 'ieee754_csr' is an alias of ctx->fcr31. 2199 * No need to copy ctx->fcr31 to ieee754_csr. 2200 */ 2201 sig = cop1Emulate(xcp, ctx, dec_insn, fault_addr); 2202 } 2203 2204 if (has_fpu) 2205 break; 2206 if (sig) 2207 break; 2208 2209 cond_resched(); 2210 } while (xcp->cp0_epc > prevepc); 2211 2212 /* SIGILL indicates a non-fpu instruction */ 2213 if (sig == SIGILL && xcp->cp0_epc != oldepc) 2214 /* but if EPC has advanced, then ignore it */ 2215 sig = 0; 2216 2217 return sig; 2218 } 2219