1 /* 2 * cp1emu.c: a MIPS coprocessor 1 (FPU) instruction emulator 3 * 4 * MIPS floating point support 5 * Copyright (C) 1994-2000 Algorithmics Ltd. 6 * 7 * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com 8 * Copyright (C) 2000 MIPS Technologies, Inc. 9 * 10 * This program is free software; you can distribute it and/or modify it 11 * under the terms of the GNU General Public License (Version 2) as 12 * published by the Free Software Foundation. 13 * 14 * This program is distributed in the hope it will be useful, but WITHOUT 15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 17 * for more details. 18 * 19 * You should have received a copy of the GNU General Public License along 20 * with this program; if not, write to the Free Software Foundation, Inc., 21 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. 22 * 23 * A complete emulator for MIPS coprocessor 1 instructions. This is 24 * required for #float(switch) or #float(trap), where it catches all 25 * COP1 instructions via the "CoProcessor Unusable" exception. 26 * 27 * More surprisingly it is also required for #float(ieee), to help out 28 * the hardware FPU at the boundaries of the IEEE-754 representation 29 * (denormalised values, infinities, underflow, etc). It is made 30 * quite nasty because emulation of some non-COP1 instructions is 31 * required, e.g. in branch delay slots. 32 * 33 * Note if you know that you won't have an FPU, then you'll get much 34 * better performance by compiling with -msoft-float! 35 */ 36 #include <linux/sched.h> 37 #include <linux/debugfs.h> 38 #include <linux/kconfig.h> 39 #include <linux/percpu-defs.h> 40 #include <linux/perf_event.h> 41 42 #include <asm/branch.h> 43 #include <asm/inst.h> 44 #include <asm/ptrace.h> 45 #include <asm/signal.h> 46 #include <asm/uaccess.h> 47 48 #include <asm/processor.h> 49 #include <asm/fpu_emulator.h> 50 #include <asm/fpu.h> 51 #include <asm/mips-r2-to-r6-emul.h> 52 53 #include "ieee754.h" 54 55 /* Function which emulates a floating point instruction. */ 56 57 static int fpu_emu(struct pt_regs *, struct mips_fpu_struct *, 58 mips_instruction); 59 60 static int fpux_emu(struct pt_regs *, 61 struct mips_fpu_struct *, mips_instruction, void *__user *); 62 63 /* Control registers */ 64 65 #define FPCREG_RID 0 /* $0 = revision id */ 66 #define FPCREG_CSR 31 /* $31 = csr */ 67 68 /* Determine rounding mode from the RM bits of the FCSR */ 69 #define modeindex(v) ((v) & FPU_CSR_RM) 70 71 /* convert condition code register number to csr bit */ 72 const unsigned int fpucondbit[8] = { 73 FPU_CSR_COND0, 74 FPU_CSR_COND1, 75 FPU_CSR_COND2, 76 FPU_CSR_COND3, 77 FPU_CSR_COND4, 78 FPU_CSR_COND5, 79 FPU_CSR_COND6, 80 FPU_CSR_COND7 81 }; 82 83 /* (microMIPS) Convert certain microMIPS instructions to MIPS32 format. */ 84 static const int sd_format[] = {16, 17, 0, 0, 0, 0, 0, 0}; 85 static const int sdps_format[] = {16, 17, 22, 0, 0, 0, 0, 0}; 86 static const int dwl_format[] = {17, 20, 21, 0, 0, 0, 0, 0}; 87 static const int swl_format[] = {16, 20, 21, 0, 0, 0, 0, 0}; 88 89 /* 90 * This functions translates a 32-bit microMIPS instruction 91 * into a 32-bit MIPS32 instruction. Returns 0 on success 92 * and SIGILL otherwise. 93 */ 94 static int microMIPS32_to_MIPS32(union mips_instruction *insn_ptr) 95 { 96 union mips_instruction insn = *insn_ptr; 97 union mips_instruction mips32_insn = insn; 98 int func, fmt, op; 99 100 switch (insn.mm_i_format.opcode) { 101 case mm_ldc132_op: 102 mips32_insn.mm_i_format.opcode = ldc1_op; 103 mips32_insn.mm_i_format.rt = insn.mm_i_format.rs; 104 mips32_insn.mm_i_format.rs = insn.mm_i_format.rt; 105 break; 106 case mm_lwc132_op: 107 mips32_insn.mm_i_format.opcode = lwc1_op; 108 mips32_insn.mm_i_format.rt = insn.mm_i_format.rs; 109 mips32_insn.mm_i_format.rs = insn.mm_i_format.rt; 110 break; 111 case mm_sdc132_op: 112 mips32_insn.mm_i_format.opcode = sdc1_op; 113 mips32_insn.mm_i_format.rt = insn.mm_i_format.rs; 114 mips32_insn.mm_i_format.rs = insn.mm_i_format.rt; 115 break; 116 case mm_swc132_op: 117 mips32_insn.mm_i_format.opcode = swc1_op; 118 mips32_insn.mm_i_format.rt = insn.mm_i_format.rs; 119 mips32_insn.mm_i_format.rs = insn.mm_i_format.rt; 120 break; 121 case mm_pool32i_op: 122 /* NOTE: offset is << by 1 if in microMIPS mode. */ 123 if ((insn.mm_i_format.rt == mm_bc1f_op) || 124 (insn.mm_i_format.rt == mm_bc1t_op)) { 125 mips32_insn.fb_format.opcode = cop1_op; 126 mips32_insn.fb_format.bc = bc_op; 127 mips32_insn.fb_format.flag = 128 (insn.mm_i_format.rt == mm_bc1t_op) ? 1 : 0; 129 } else 130 return SIGILL; 131 break; 132 case mm_pool32f_op: 133 switch (insn.mm_fp0_format.func) { 134 case mm_32f_01_op: 135 case mm_32f_11_op: 136 case mm_32f_02_op: 137 case mm_32f_12_op: 138 case mm_32f_41_op: 139 case mm_32f_51_op: 140 case mm_32f_42_op: 141 case mm_32f_52_op: 142 op = insn.mm_fp0_format.func; 143 if (op == mm_32f_01_op) 144 func = madd_s_op; 145 else if (op == mm_32f_11_op) 146 func = madd_d_op; 147 else if (op == mm_32f_02_op) 148 func = nmadd_s_op; 149 else if (op == mm_32f_12_op) 150 func = nmadd_d_op; 151 else if (op == mm_32f_41_op) 152 func = msub_s_op; 153 else if (op == mm_32f_51_op) 154 func = msub_d_op; 155 else if (op == mm_32f_42_op) 156 func = nmsub_s_op; 157 else 158 func = nmsub_d_op; 159 mips32_insn.fp6_format.opcode = cop1x_op; 160 mips32_insn.fp6_format.fr = insn.mm_fp6_format.fr; 161 mips32_insn.fp6_format.ft = insn.mm_fp6_format.ft; 162 mips32_insn.fp6_format.fs = insn.mm_fp6_format.fs; 163 mips32_insn.fp6_format.fd = insn.mm_fp6_format.fd; 164 mips32_insn.fp6_format.func = func; 165 break; 166 case mm_32f_10_op: 167 func = -1; /* Invalid */ 168 op = insn.mm_fp5_format.op & 0x7; 169 if (op == mm_ldxc1_op) 170 func = ldxc1_op; 171 else if (op == mm_sdxc1_op) 172 func = sdxc1_op; 173 else if (op == mm_lwxc1_op) 174 func = lwxc1_op; 175 else if (op == mm_swxc1_op) 176 func = swxc1_op; 177 178 if (func != -1) { 179 mips32_insn.r_format.opcode = cop1x_op; 180 mips32_insn.r_format.rs = 181 insn.mm_fp5_format.base; 182 mips32_insn.r_format.rt = 183 insn.mm_fp5_format.index; 184 mips32_insn.r_format.rd = 0; 185 mips32_insn.r_format.re = insn.mm_fp5_format.fd; 186 mips32_insn.r_format.func = func; 187 } else 188 return SIGILL; 189 break; 190 case mm_32f_40_op: 191 op = -1; /* Invalid */ 192 if (insn.mm_fp2_format.op == mm_fmovt_op) 193 op = 1; 194 else if (insn.mm_fp2_format.op == mm_fmovf_op) 195 op = 0; 196 if (op != -1) { 197 mips32_insn.fp0_format.opcode = cop1_op; 198 mips32_insn.fp0_format.fmt = 199 sdps_format[insn.mm_fp2_format.fmt]; 200 mips32_insn.fp0_format.ft = 201 (insn.mm_fp2_format.cc<<2) + op; 202 mips32_insn.fp0_format.fs = 203 insn.mm_fp2_format.fs; 204 mips32_insn.fp0_format.fd = 205 insn.mm_fp2_format.fd; 206 mips32_insn.fp0_format.func = fmovc_op; 207 } else 208 return SIGILL; 209 break; 210 case mm_32f_60_op: 211 func = -1; /* Invalid */ 212 if (insn.mm_fp0_format.op == mm_fadd_op) 213 func = fadd_op; 214 else if (insn.mm_fp0_format.op == mm_fsub_op) 215 func = fsub_op; 216 else if (insn.mm_fp0_format.op == mm_fmul_op) 217 func = fmul_op; 218 else if (insn.mm_fp0_format.op == mm_fdiv_op) 219 func = fdiv_op; 220 if (func != -1) { 221 mips32_insn.fp0_format.opcode = cop1_op; 222 mips32_insn.fp0_format.fmt = 223 sdps_format[insn.mm_fp0_format.fmt]; 224 mips32_insn.fp0_format.ft = 225 insn.mm_fp0_format.ft; 226 mips32_insn.fp0_format.fs = 227 insn.mm_fp0_format.fs; 228 mips32_insn.fp0_format.fd = 229 insn.mm_fp0_format.fd; 230 mips32_insn.fp0_format.func = func; 231 } else 232 return SIGILL; 233 break; 234 case mm_32f_70_op: 235 func = -1; /* Invalid */ 236 if (insn.mm_fp0_format.op == mm_fmovn_op) 237 func = fmovn_op; 238 else if (insn.mm_fp0_format.op == mm_fmovz_op) 239 func = fmovz_op; 240 if (func != -1) { 241 mips32_insn.fp0_format.opcode = cop1_op; 242 mips32_insn.fp0_format.fmt = 243 sdps_format[insn.mm_fp0_format.fmt]; 244 mips32_insn.fp0_format.ft = 245 insn.mm_fp0_format.ft; 246 mips32_insn.fp0_format.fs = 247 insn.mm_fp0_format.fs; 248 mips32_insn.fp0_format.fd = 249 insn.mm_fp0_format.fd; 250 mips32_insn.fp0_format.func = func; 251 } else 252 return SIGILL; 253 break; 254 case mm_32f_73_op: /* POOL32FXF */ 255 switch (insn.mm_fp1_format.op) { 256 case mm_movf0_op: 257 case mm_movf1_op: 258 case mm_movt0_op: 259 case mm_movt1_op: 260 if ((insn.mm_fp1_format.op & 0x7f) == 261 mm_movf0_op) 262 op = 0; 263 else 264 op = 1; 265 mips32_insn.r_format.opcode = spec_op; 266 mips32_insn.r_format.rs = insn.mm_fp4_format.fs; 267 mips32_insn.r_format.rt = 268 (insn.mm_fp4_format.cc << 2) + op; 269 mips32_insn.r_format.rd = insn.mm_fp4_format.rt; 270 mips32_insn.r_format.re = 0; 271 mips32_insn.r_format.func = movc_op; 272 break; 273 case mm_fcvtd0_op: 274 case mm_fcvtd1_op: 275 case mm_fcvts0_op: 276 case mm_fcvts1_op: 277 if ((insn.mm_fp1_format.op & 0x7f) == 278 mm_fcvtd0_op) { 279 func = fcvtd_op; 280 fmt = swl_format[insn.mm_fp3_format.fmt]; 281 } else { 282 func = fcvts_op; 283 fmt = dwl_format[insn.mm_fp3_format.fmt]; 284 } 285 mips32_insn.fp0_format.opcode = cop1_op; 286 mips32_insn.fp0_format.fmt = fmt; 287 mips32_insn.fp0_format.ft = 0; 288 mips32_insn.fp0_format.fs = 289 insn.mm_fp3_format.fs; 290 mips32_insn.fp0_format.fd = 291 insn.mm_fp3_format.rt; 292 mips32_insn.fp0_format.func = func; 293 break; 294 case mm_fmov0_op: 295 case mm_fmov1_op: 296 case mm_fabs0_op: 297 case mm_fabs1_op: 298 case mm_fneg0_op: 299 case mm_fneg1_op: 300 if ((insn.mm_fp1_format.op & 0x7f) == 301 mm_fmov0_op) 302 func = fmov_op; 303 else if ((insn.mm_fp1_format.op & 0x7f) == 304 mm_fabs0_op) 305 func = fabs_op; 306 else 307 func = fneg_op; 308 mips32_insn.fp0_format.opcode = cop1_op; 309 mips32_insn.fp0_format.fmt = 310 sdps_format[insn.mm_fp3_format.fmt]; 311 mips32_insn.fp0_format.ft = 0; 312 mips32_insn.fp0_format.fs = 313 insn.mm_fp3_format.fs; 314 mips32_insn.fp0_format.fd = 315 insn.mm_fp3_format.rt; 316 mips32_insn.fp0_format.func = func; 317 break; 318 case mm_ffloorl_op: 319 case mm_ffloorw_op: 320 case mm_fceill_op: 321 case mm_fceilw_op: 322 case mm_ftruncl_op: 323 case mm_ftruncw_op: 324 case mm_froundl_op: 325 case mm_froundw_op: 326 case mm_fcvtl_op: 327 case mm_fcvtw_op: 328 if (insn.mm_fp1_format.op == mm_ffloorl_op) 329 func = ffloorl_op; 330 else if (insn.mm_fp1_format.op == mm_ffloorw_op) 331 func = ffloor_op; 332 else if (insn.mm_fp1_format.op == mm_fceill_op) 333 func = fceill_op; 334 else if (insn.mm_fp1_format.op == mm_fceilw_op) 335 func = fceil_op; 336 else if (insn.mm_fp1_format.op == mm_ftruncl_op) 337 func = ftruncl_op; 338 else if (insn.mm_fp1_format.op == mm_ftruncw_op) 339 func = ftrunc_op; 340 else if (insn.mm_fp1_format.op == mm_froundl_op) 341 func = froundl_op; 342 else if (insn.mm_fp1_format.op == mm_froundw_op) 343 func = fround_op; 344 else if (insn.mm_fp1_format.op == mm_fcvtl_op) 345 func = fcvtl_op; 346 else 347 func = fcvtw_op; 348 mips32_insn.fp0_format.opcode = cop1_op; 349 mips32_insn.fp0_format.fmt = 350 sd_format[insn.mm_fp1_format.fmt]; 351 mips32_insn.fp0_format.ft = 0; 352 mips32_insn.fp0_format.fs = 353 insn.mm_fp1_format.fs; 354 mips32_insn.fp0_format.fd = 355 insn.mm_fp1_format.rt; 356 mips32_insn.fp0_format.func = func; 357 break; 358 case mm_frsqrt_op: 359 case mm_fsqrt_op: 360 case mm_frecip_op: 361 if (insn.mm_fp1_format.op == mm_frsqrt_op) 362 func = frsqrt_op; 363 else if (insn.mm_fp1_format.op == mm_fsqrt_op) 364 func = fsqrt_op; 365 else 366 func = frecip_op; 367 mips32_insn.fp0_format.opcode = cop1_op; 368 mips32_insn.fp0_format.fmt = 369 sdps_format[insn.mm_fp1_format.fmt]; 370 mips32_insn.fp0_format.ft = 0; 371 mips32_insn.fp0_format.fs = 372 insn.mm_fp1_format.fs; 373 mips32_insn.fp0_format.fd = 374 insn.mm_fp1_format.rt; 375 mips32_insn.fp0_format.func = func; 376 break; 377 case mm_mfc1_op: 378 case mm_mtc1_op: 379 case mm_cfc1_op: 380 case mm_ctc1_op: 381 case mm_mfhc1_op: 382 case mm_mthc1_op: 383 if (insn.mm_fp1_format.op == mm_mfc1_op) 384 op = mfc_op; 385 else if (insn.mm_fp1_format.op == mm_mtc1_op) 386 op = mtc_op; 387 else if (insn.mm_fp1_format.op == mm_cfc1_op) 388 op = cfc_op; 389 else if (insn.mm_fp1_format.op == mm_ctc1_op) 390 op = ctc_op; 391 else if (insn.mm_fp1_format.op == mm_mfhc1_op) 392 op = mfhc_op; 393 else 394 op = mthc_op; 395 mips32_insn.fp1_format.opcode = cop1_op; 396 mips32_insn.fp1_format.op = op; 397 mips32_insn.fp1_format.rt = 398 insn.mm_fp1_format.rt; 399 mips32_insn.fp1_format.fs = 400 insn.mm_fp1_format.fs; 401 mips32_insn.fp1_format.fd = 0; 402 mips32_insn.fp1_format.func = 0; 403 break; 404 default: 405 return SIGILL; 406 } 407 break; 408 case mm_32f_74_op: /* c.cond.fmt */ 409 mips32_insn.fp0_format.opcode = cop1_op; 410 mips32_insn.fp0_format.fmt = 411 sdps_format[insn.mm_fp4_format.fmt]; 412 mips32_insn.fp0_format.ft = insn.mm_fp4_format.rt; 413 mips32_insn.fp0_format.fs = insn.mm_fp4_format.fs; 414 mips32_insn.fp0_format.fd = insn.mm_fp4_format.cc << 2; 415 mips32_insn.fp0_format.func = 416 insn.mm_fp4_format.cond | MM_MIPS32_COND_FC; 417 break; 418 default: 419 return SIGILL; 420 } 421 break; 422 default: 423 return SIGILL; 424 } 425 426 *insn_ptr = mips32_insn; 427 return 0; 428 } 429 430 /* 431 * Redundant with logic already in kernel/branch.c, 432 * embedded in compute_return_epc. At some point, 433 * a single subroutine should be used across both 434 * modules. 435 */ 436 static int isBranchInstr(struct pt_regs *regs, struct mm_decoded_insn dec_insn, 437 unsigned long *contpc) 438 { 439 union mips_instruction insn = (union mips_instruction)dec_insn.insn; 440 unsigned int fcr31; 441 unsigned int bit = 0; 442 443 switch (insn.i_format.opcode) { 444 case spec_op: 445 switch (insn.r_format.func) { 446 case jalr_op: 447 regs->regs[insn.r_format.rd] = 448 regs->cp0_epc + dec_insn.pc_inc + 449 dec_insn.next_pc_inc; 450 /* Fall through */ 451 case jr_op: 452 /* For R6, JR already emulated in jalr_op */ 453 if (NO_R6EMU && insn.r_format.opcode == jr_op) 454 break; 455 *contpc = regs->regs[insn.r_format.rs]; 456 return 1; 457 } 458 break; 459 case bcond_op: 460 switch (insn.i_format.rt) { 461 case bltzal_op: 462 case bltzall_op: 463 if (NO_R6EMU && (insn.i_format.rs || 464 insn.i_format.rt == bltzall_op)) 465 break; 466 467 regs->regs[31] = regs->cp0_epc + 468 dec_insn.pc_inc + 469 dec_insn.next_pc_inc; 470 /* Fall through */ 471 case bltzl_op: 472 if (NO_R6EMU) 473 break; 474 case bltz_op: 475 if ((long)regs->regs[insn.i_format.rs] < 0) 476 *contpc = regs->cp0_epc + 477 dec_insn.pc_inc + 478 (insn.i_format.simmediate << 2); 479 else 480 *contpc = regs->cp0_epc + 481 dec_insn.pc_inc + 482 dec_insn.next_pc_inc; 483 return 1; 484 case bgezal_op: 485 case bgezall_op: 486 if (NO_R6EMU && (insn.i_format.rs || 487 insn.i_format.rt == bgezall_op)) 488 break; 489 490 regs->regs[31] = regs->cp0_epc + 491 dec_insn.pc_inc + 492 dec_insn.next_pc_inc; 493 /* Fall through */ 494 case bgezl_op: 495 if (NO_R6EMU) 496 break; 497 case bgez_op: 498 if ((long)regs->regs[insn.i_format.rs] >= 0) 499 *contpc = regs->cp0_epc + 500 dec_insn.pc_inc + 501 (insn.i_format.simmediate << 2); 502 else 503 *contpc = regs->cp0_epc + 504 dec_insn.pc_inc + 505 dec_insn.next_pc_inc; 506 return 1; 507 } 508 break; 509 case jalx_op: 510 set_isa16_mode(bit); 511 case jal_op: 512 regs->regs[31] = regs->cp0_epc + 513 dec_insn.pc_inc + 514 dec_insn.next_pc_inc; 515 /* Fall through */ 516 case j_op: 517 *contpc = regs->cp0_epc + dec_insn.pc_inc; 518 *contpc >>= 28; 519 *contpc <<= 28; 520 *contpc |= (insn.j_format.target << 2); 521 /* Set microMIPS mode bit: XOR for jalx. */ 522 *contpc ^= bit; 523 return 1; 524 case beql_op: 525 if (NO_R6EMU) 526 break; 527 case beq_op: 528 if (regs->regs[insn.i_format.rs] == 529 regs->regs[insn.i_format.rt]) 530 *contpc = regs->cp0_epc + 531 dec_insn.pc_inc + 532 (insn.i_format.simmediate << 2); 533 else 534 *contpc = regs->cp0_epc + 535 dec_insn.pc_inc + 536 dec_insn.next_pc_inc; 537 return 1; 538 case bnel_op: 539 if (NO_R6EMU) 540 break; 541 case bne_op: 542 if (regs->regs[insn.i_format.rs] != 543 regs->regs[insn.i_format.rt]) 544 *contpc = regs->cp0_epc + 545 dec_insn.pc_inc + 546 (insn.i_format.simmediate << 2); 547 else 548 *contpc = regs->cp0_epc + 549 dec_insn.pc_inc + 550 dec_insn.next_pc_inc; 551 return 1; 552 case blezl_op: 553 if (NO_R6EMU) 554 break; 555 case blez_op: 556 557 /* 558 * Compact branches for R6 for the 559 * blez and blezl opcodes. 560 * BLEZ | rs = 0 | rt != 0 == BLEZALC 561 * BLEZ | rs = rt != 0 == BGEZALC 562 * BLEZ | rs != 0 | rt != 0 == BGEUC 563 * BLEZL | rs = 0 | rt != 0 == BLEZC 564 * BLEZL | rs = rt != 0 == BGEZC 565 * BLEZL | rs != 0 | rt != 0 == BGEC 566 * 567 * For real BLEZ{,L}, rt is always 0. 568 */ 569 if (cpu_has_mips_r6 && insn.i_format.rt) { 570 if ((insn.i_format.opcode == blez_op) && 571 ((!insn.i_format.rs && insn.i_format.rt) || 572 (insn.i_format.rs == insn.i_format.rt))) 573 regs->regs[31] = regs->cp0_epc + 574 dec_insn.pc_inc; 575 *contpc = regs->cp0_epc + dec_insn.pc_inc + 576 dec_insn.next_pc_inc; 577 578 return 1; 579 } 580 if ((long)regs->regs[insn.i_format.rs] <= 0) 581 *contpc = regs->cp0_epc + 582 dec_insn.pc_inc + 583 (insn.i_format.simmediate << 2); 584 else 585 *contpc = regs->cp0_epc + 586 dec_insn.pc_inc + 587 dec_insn.next_pc_inc; 588 return 1; 589 case bgtzl_op: 590 if (NO_R6EMU) 591 break; 592 case bgtz_op: 593 /* 594 * Compact branches for R6 for the 595 * bgtz and bgtzl opcodes. 596 * BGTZ | rs = 0 | rt != 0 == BGTZALC 597 * BGTZ | rs = rt != 0 == BLTZALC 598 * BGTZ | rs != 0 | rt != 0 == BLTUC 599 * BGTZL | rs = 0 | rt != 0 == BGTZC 600 * BGTZL | rs = rt != 0 == BLTZC 601 * BGTZL | rs != 0 | rt != 0 == BLTC 602 * 603 * *ZALC varint for BGTZ &&& rt != 0 604 * For real GTZ{,L}, rt is always 0. 605 */ 606 if (cpu_has_mips_r6 && insn.i_format.rt) { 607 if ((insn.i_format.opcode == blez_op) && 608 ((!insn.i_format.rs && insn.i_format.rt) || 609 (insn.i_format.rs == insn.i_format.rt))) 610 regs->regs[31] = regs->cp0_epc + 611 dec_insn.pc_inc; 612 *contpc = regs->cp0_epc + dec_insn.pc_inc + 613 dec_insn.next_pc_inc; 614 615 return 1; 616 } 617 618 if ((long)regs->regs[insn.i_format.rs] > 0) 619 *contpc = regs->cp0_epc + 620 dec_insn.pc_inc + 621 (insn.i_format.simmediate << 2); 622 else 623 *contpc = regs->cp0_epc + 624 dec_insn.pc_inc + 625 dec_insn.next_pc_inc; 626 return 1; 627 case cbcond0_op: 628 case cbcond1_op: 629 if (!cpu_has_mips_r6) 630 break; 631 if (insn.i_format.rt && !insn.i_format.rs) 632 regs->regs[31] = regs->cp0_epc + 4; 633 *contpc = regs->cp0_epc + dec_insn.pc_inc + 634 dec_insn.next_pc_inc; 635 636 return 1; 637 #ifdef CONFIG_CPU_CAVIUM_OCTEON 638 case lwc2_op: /* This is bbit0 on Octeon */ 639 if ((regs->regs[insn.i_format.rs] & (1ull<<insn.i_format.rt)) == 0) 640 *contpc = regs->cp0_epc + 4 + (insn.i_format.simmediate << 2); 641 else 642 *contpc = regs->cp0_epc + 8; 643 return 1; 644 case ldc2_op: /* This is bbit032 on Octeon */ 645 if ((regs->regs[insn.i_format.rs] & (1ull<<(insn.i_format.rt + 32))) == 0) 646 *contpc = regs->cp0_epc + 4 + (insn.i_format.simmediate << 2); 647 else 648 *contpc = regs->cp0_epc + 8; 649 return 1; 650 case swc2_op: /* This is bbit1 on Octeon */ 651 if (regs->regs[insn.i_format.rs] & (1ull<<insn.i_format.rt)) 652 *contpc = regs->cp0_epc + 4 + (insn.i_format.simmediate << 2); 653 else 654 *contpc = regs->cp0_epc + 8; 655 return 1; 656 case sdc2_op: /* This is bbit132 on Octeon */ 657 if (regs->regs[insn.i_format.rs] & (1ull<<(insn.i_format.rt + 32))) 658 *contpc = regs->cp0_epc + 4 + (insn.i_format.simmediate << 2); 659 else 660 *contpc = regs->cp0_epc + 8; 661 return 1; 662 #else 663 case bc6_op: 664 /* 665 * Only valid for MIPS R6 but we can still end up 666 * here from a broken userland so just tell emulator 667 * this is not a branch and let it break later on. 668 */ 669 if (!cpu_has_mips_r6) 670 break; 671 *contpc = regs->cp0_epc + dec_insn.pc_inc + 672 dec_insn.next_pc_inc; 673 674 return 1; 675 case balc6_op: 676 if (!cpu_has_mips_r6) 677 break; 678 regs->regs[31] = regs->cp0_epc + 4; 679 *contpc = regs->cp0_epc + dec_insn.pc_inc + 680 dec_insn.next_pc_inc; 681 682 return 1; 683 case beqzcjic_op: 684 if (!cpu_has_mips_r6) 685 break; 686 *contpc = regs->cp0_epc + dec_insn.pc_inc + 687 dec_insn.next_pc_inc; 688 689 return 1; 690 case bnezcjialc_op: 691 if (!cpu_has_mips_r6) 692 break; 693 if (!insn.i_format.rs) 694 regs->regs[31] = regs->cp0_epc + 4; 695 *contpc = regs->cp0_epc + dec_insn.pc_inc + 696 dec_insn.next_pc_inc; 697 698 return 1; 699 #endif 700 case cop0_op: 701 case cop1_op: 702 /* Need to check for R6 bc1nez and bc1eqz branches */ 703 if (cpu_has_mips_r6 && 704 ((insn.i_format.rs == bc1eqz_op) || 705 (insn.i_format.rs == bc1nez_op))) { 706 bit = 0; 707 switch (insn.i_format.rs) { 708 case bc1eqz_op: 709 if (get_fpr32(¤t->thread.fpu.fpr[insn.i_format.rt], 0) & 0x1) 710 bit = 1; 711 break; 712 case bc1nez_op: 713 if (!(get_fpr32(¤t->thread.fpu.fpr[insn.i_format.rt], 0) & 0x1)) 714 bit = 1; 715 break; 716 } 717 if (bit) 718 *contpc = regs->cp0_epc + 719 dec_insn.pc_inc + 720 (insn.i_format.simmediate << 2); 721 else 722 *contpc = regs->cp0_epc + 723 dec_insn.pc_inc + 724 dec_insn.next_pc_inc; 725 726 return 1; 727 } 728 /* R2/R6 compatible cop1 instruction. Fall through */ 729 case cop2_op: 730 case cop1x_op: 731 if (insn.i_format.rs == bc_op) { 732 preempt_disable(); 733 if (is_fpu_owner()) 734 fcr31 = read_32bit_cp1_register(CP1_STATUS); 735 else 736 fcr31 = current->thread.fpu.fcr31; 737 preempt_enable(); 738 739 bit = (insn.i_format.rt >> 2); 740 bit += (bit != 0); 741 bit += 23; 742 switch (insn.i_format.rt & 3) { 743 case 0: /* bc1f */ 744 case 2: /* bc1fl */ 745 if (~fcr31 & (1 << bit)) 746 *contpc = regs->cp0_epc + 747 dec_insn.pc_inc + 748 (insn.i_format.simmediate << 2); 749 else 750 *contpc = regs->cp0_epc + 751 dec_insn.pc_inc + 752 dec_insn.next_pc_inc; 753 return 1; 754 case 1: /* bc1t */ 755 case 3: /* bc1tl */ 756 if (fcr31 & (1 << bit)) 757 *contpc = regs->cp0_epc + 758 dec_insn.pc_inc + 759 (insn.i_format.simmediate << 2); 760 else 761 *contpc = regs->cp0_epc + 762 dec_insn.pc_inc + 763 dec_insn.next_pc_inc; 764 return 1; 765 } 766 } 767 break; 768 } 769 return 0; 770 } 771 772 /* 773 * In the Linux kernel, we support selection of FPR format on the 774 * basis of the Status.FR bit. If an FPU is not present, the FR bit 775 * is hardwired to zero, which would imply a 32-bit FPU even for 776 * 64-bit CPUs so we rather look at TIF_32BIT_FPREGS. 777 * FPU emu is slow and bulky and optimizing this function offers fairly 778 * sizeable benefits so we try to be clever and make this function return 779 * a constant whenever possible, that is on 64-bit kernels without O32 780 * compatibility enabled and on 32-bit without 64-bit FPU support. 781 */ 782 static inline int cop1_64bit(struct pt_regs *xcp) 783 { 784 if (config_enabled(CONFIG_64BIT) && !config_enabled(CONFIG_MIPS32_O32)) 785 return 1; 786 else if (config_enabled(CONFIG_32BIT) && 787 !config_enabled(CONFIG_MIPS_O32_FP64_SUPPORT)) 788 return 0; 789 790 return !test_thread_flag(TIF_32BIT_FPREGS); 791 } 792 793 static inline bool hybrid_fprs(void) 794 { 795 return test_thread_flag(TIF_HYBRID_FPREGS); 796 } 797 798 #define SIFROMREG(si, x) \ 799 do { \ 800 if (cop1_64bit(xcp) && !hybrid_fprs()) \ 801 (si) = (int)get_fpr32(&ctx->fpr[x], 0); \ 802 else \ 803 (si) = (int)get_fpr32(&ctx->fpr[(x) & ~1], (x) & 1); \ 804 } while (0) 805 806 #define SITOREG(si, x) \ 807 do { \ 808 if (cop1_64bit(xcp) && !hybrid_fprs()) { \ 809 unsigned i; \ 810 set_fpr32(&ctx->fpr[x], 0, si); \ 811 for (i = 1; i < ARRAY_SIZE(ctx->fpr[x].val32); i++) \ 812 set_fpr32(&ctx->fpr[x], i, 0); \ 813 } else { \ 814 set_fpr32(&ctx->fpr[(x) & ~1], (x) & 1, si); \ 815 } \ 816 } while (0) 817 818 #define SIFROMHREG(si, x) ((si) = (int)get_fpr32(&ctx->fpr[x], 1)) 819 820 #define SITOHREG(si, x) \ 821 do { \ 822 unsigned i; \ 823 set_fpr32(&ctx->fpr[x], 1, si); \ 824 for (i = 2; i < ARRAY_SIZE(ctx->fpr[x].val32); i++) \ 825 set_fpr32(&ctx->fpr[x], i, 0); \ 826 } while (0) 827 828 #define DIFROMREG(di, x) \ 829 ((di) = get_fpr64(&ctx->fpr[(x) & ~(cop1_64bit(xcp) == 0)], 0)) 830 831 #define DITOREG(di, x) \ 832 do { \ 833 unsigned fpr, i; \ 834 fpr = (x) & ~(cop1_64bit(xcp) == 0); \ 835 set_fpr64(&ctx->fpr[fpr], 0, di); \ 836 for (i = 1; i < ARRAY_SIZE(ctx->fpr[x].val64); i++) \ 837 set_fpr64(&ctx->fpr[fpr], i, 0); \ 838 } while (0) 839 840 #define SPFROMREG(sp, x) SIFROMREG((sp).bits, x) 841 #define SPTOREG(sp, x) SITOREG((sp).bits, x) 842 #define DPFROMREG(dp, x) DIFROMREG((dp).bits, x) 843 #define DPTOREG(dp, x) DITOREG((dp).bits, x) 844 845 /* 846 * Emulate the single floating point instruction pointed at by EPC. 847 * Two instructions if the instruction is in a branch delay slot. 848 */ 849 850 static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_struct *ctx, 851 struct mm_decoded_insn dec_insn, void *__user *fault_addr) 852 { 853 unsigned long contpc = xcp->cp0_epc + dec_insn.pc_inc; 854 unsigned int cond, cbit; 855 mips_instruction ir; 856 int likely, pc_inc; 857 u32 __user *wva; 858 u64 __user *dva; 859 u32 value; 860 u32 wval; 861 u64 dval; 862 int sig; 863 864 /* 865 * These are giving gcc a gentle hint about what to expect in 866 * dec_inst in order to do better optimization. 867 */ 868 if (!cpu_has_mmips && dec_insn.micro_mips_mode) 869 unreachable(); 870 871 /* XXX NEC Vr54xx bug workaround */ 872 if (delay_slot(xcp)) { 873 if (dec_insn.micro_mips_mode) { 874 if (!mm_isBranchInstr(xcp, dec_insn, &contpc)) 875 clear_delay_slot(xcp); 876 } else { 877 if (!isBranchInstr(xcp, dec_insn, &contpc)) 878 clear_delay_slot(xcp); 879 } 880 } 881 882 if (delay_slot(xcp)) { 883 /* 884 * The instruction to be emulated is in a branch delay slot 885 * which means that we have to emulate the branch instruction 886 * BEFORE we do the cop1 instruction. 887 * 888 * This branch could be a COP1 branch, but in that case we 889 * would have had a trap for that instruction, and would not 890 * come through this route. 891 * 892 * Linux MIPS branch emulator operates on context, updating the 893 * cp0_epc. 894 */ 895 ir = dec_insn.next_insn; /* process delay slot instr */ 896 pc_inc = dec_insn.next_pc_inc; 897 } else { 898 ir = dec_insn.insn; /* process current instr */ 899 pc_inc = dec_insn.pc_inc; 900 } 901 902 /* 903 * Since microMIPS FPU instructios are a subset of MIPS32 FPU 904 * instructions, we want to convert microMIPS FPU instructions 905 * into MIPS32 instructions so that we could reuse all of the 906 * FPU emulation code. 907 * 908 * NOTE: We cannot do this for branch instructions since they 909 * are not a subset. Example: Cannot emulate a 16-bit 910 * aligned target address with a MIPS32 instruction. 911 */ 912 if (dec_insn.micro_mips_mode) { 913 /* 914 * If next instruction is a 16-bit instruction, then it 915 * it cannot be a FPU instruction. This could happen 916 * since we can be called for non-FPU instructions. 917 */ 918 if ((pc_inc == 2) || 919 (microMIPS32_to_MIPS32((union mips_instruction *)&ir) 920 == SIGILL)) 921 return SIGILL; 922 } 923 924 emul: 925 perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 1, xcp, 0); 926 MIPS_FPU_EMU_INC_STATS(emulated); 927 switch (MIPSInst_OPCODE(ir)) { 928 case ldc1_op: 929 dva = (u64 __user *) (xcp->regs[MIPSInst_RS(ir)] + 930 MIPSInst_SIMM(ir)); 931 MIPS_FPU_EMU_INC_STATS(loads); 932 933 if (!access_ok(VERIFY_READ, dva, sizeof(u64))) { 934 MIPS_FPU_EMU_INC_STATS(errors); 935 *fault_addr = dva; 936 return SIGBUS; 937 } 938 if (__get_user(dval, dva)) { 939 MIPS_FPU_EMU_INC_STATS(errors); 940 *fault_addr = dva; 941 return SIGSEGV; 942 } 943 DITOREG(dval, MIPSInst_RT(ir)); 944 break; 945 946 case sdc1_op: 947 dva = (u64 __user *) (xcp->regs[MIPSInst_RS(ir)] + 948 MIPSInst_SIMM(ir)); 949 MIPS_FPU_EMU_INC_STATS(stores); 950 DIFROMREG(dval, MIPSInst_RT(ir)); 951 if (!access_ok(VERIFY_WRITE, dva, sizeof(u64))) { 952 MIPS_FPU_EMU_INC_STATS(errors); 953 *fault_addr = dva; 954 return SIGBUS; 955 } 956 if (__put_user(dval, dva)) { 957 MIPS_FPU_EMU_INC_STATS(errors); 958 *fault_addr = dva; 959 return SIGSEGV; 960 } 961 break; 962 963 case lwc1_op: 964 wva = (u32 __user *) (xcp->regs[MIPSInst_RS(ir)] + 965 MIPSInst_SIMM(ir)); 966 MIPS_FPU_EMU_INC_STATS(loads); 967 if (!access_ok(VERIFY_READ, wva, sizeof(u32))) { 968 MIPS_FPU_EMU_INC_STATS(errors); 969 *fault_addr = wva; 970 return SIGBUS; 971 } 972 if (__get_user(wval, wva)) { 973 MIPS_FPU_EMU_INC_STATS(errors); 974 *fault_addr = wva; 975 return SIGSEGV; 976 } 977 SITOREG(wval, MIPSInst_RT(ir)); 978 break; 979 980 case swc1_op: 981 wva = (u32 __user *) (xcp->regs[MIPSInst_RS(ir)] + 982 MIPSInst_SIMM(ir)); 983 MIPS_FPU_EMU_INC_STATS(stores); 984 SIFROMREG(wval, MIPSInst_RT(ir)); 985 if (!access_ok(VERIFY_WRITE, wva, sizeof(u32))) { 986 MIPS_FPU_EMU_INC_STATS(errors); 987 *fault_addr = wva; 988 return SIGBUS; 989 } 990 if (__put_user(wval, wva)) { 991 MIPS_FPU_EMU_INC_STATS(errors); 992 *fault_addr = wva; 993 return SIGSEGV; 994 } 995 break; 996 997 case cop1_op: 998 switch (MIPSInst_RS(ir)) { 999 case dmfc_op: 1000 if (!cpu_has_mips_3_4_5 && !cpu_has_mips64) 1001 return SIGILL; 1002 1003 /* copregister fs -> gpr[rt] */ 1004 if (MIPSInst_RT(ir) != 0) { 1005 DIFROMREG(xcp->regs[MIPSInst_RT(ir)], 1006 MIPSInst_RD(ir)); 1007 } 1008 break; 1009 1010 case dmtc_op: 1011 if (!cpu_has_mips_3_4_5 && !cpu_has_mips64) 1012 return SIGILL; 1013 1014 /* copregister fs <- rt */ 1015 DITOREG(xcp->regs[MIPSInst_RT(ir)], MIPSInst_RD(ir)); 1016 break; 1017 1018 case mfhc_op: 1019 if (!cpu_has_mips_r2) 1020 goto sigill; 1021 1022 /* copregister rd -> gpr[rt] */ 1023 if (MIPSInst_RT(ir) != 0) { 1024 SIFROMHREG(xcp->regs[MIPSInst_RT(ir)], 1025 MIPSInst_RD(ir)); 1026 } 1027 break; 1028 1029 case mthc_op: 1030 if (!cpu_has_mips_r2) 1031 goto sigill; 1032 1033 /* copregister rd <- gpr[rt] */ 1034 SITOHREG(xcp->regs[MIPSInst_RT(ir)], MIPSInst_RD(ir)); 1035 break; 1036 1037 case mfc_op: 1038 /* copregister rd -> gpr[rt] */ 1039 if (MIPSInst_RT(ir) != 0) { 1040 SIFROMREG(xcp->regs[MIPSInst_RT(ir)], 1041 MIPSInst_RD(ir)); 1042 } 1043 break; 1044 1045 case mtc_op: 1046 /* copregister rd <- rt */ 1047 SITOREG(xcp->regs[MIPSInst_RT(ir)], MIPSInst_RD(ir)); 1048 break; 1049 1050 case cfc_op: 1051 /* cop control register rd -> gpr[rt] */ 1052 if (MIPSInst_RD(ir) == FPCREG_CSR) { 1053 value = ctx->fcr31; 1054 value = (value & ~FPU_CSR_RM) | modeindex(value); 1055 pr_debug("%p gpr[%d]<-csr=%08x\n", 1056 (void *) (xcp->cp0_epc), 1057 MIPSInst_RT(ir), value); 1058 } 1059 else if (MIPSInst_RD(ir) == FPCREG_RID) 1060 value = 0; 1061 else 1062 value = 0; 1063 if (MIPSInst_RT(ir)) 1064 xcp->regs[MIPSInst_RT(ir)] = value; 1065 break; 1066 1067 case ctc_op: 1068 /* copregister rd <- rt */ 1069 if (MIPSInst_RT(ir) == 0) 1070 value = 0; 1071 else 1072 value = xcp->regs[MIPSInst_RT(ir)]; 1073 1074 /* we only have one writable control reg 1075 */ 1076 if (MIPSInst_RD(ir) == FPCREG_CSR) { 1077 pr_debug("%p gpr[%d]->csr=%08x\n", 1078 (void *) (xcp->cp0_epc), 1079 MIPSInst_RT(ir), value); 1080 1081 /* 1082 * Don't write reserved bits, 1083 * and convert to ieee library modes 1084 */ 1085 ctx->fcr31 = (value & ~(FPU_CSR_RSVD | FPU_CSR_RM)) | 1086 modeindex(value); 1087 } 1088 if ((ctx->fcr31 >> 5) & ctx->fcr31 & FPU_CSR_ALL_E) { 1089 return SIGFPE; 1090 } 1091 break; 1092 1093 case bc_op: 1094 if (delay_slot(xcp)) 1095 return SIGILL; 1096 1097 if (cpu_has_mips_4_5_r) 1098 cbit = fpucondbit[MIPSInst_RT(ir) >> 2]; 1099 else 1100 cbit = FPU_CSR_COND; 1101 cond = ctx->fcr31 & cbit; 1102 1103 likely = 0; 1104 switch (MIPSInst_RT(ir) & 3) { 1105 case bcfl_op: 1106 likely = 1; 1107 case bcf_op: 1108 cond = !cond; 1109 break; 1110 case bctl_op: 1111 likely = 1; 1112 case bct_op: 1113 break; 1114 default: 1115 /* thats an illegal instruction */ 1116 return SIGILL; 1117 } 1118 1119 set_delay_slot(xcp); 1120 if (cond) { 1121 /* 1122 * Branch taken: emulate dslot instruction 1123 */ 1124 xcp->cp0_epc += dec_insn.pc_inc; 1125 1126 contpc = MIPSInst_SIMM(ir); 1127 ir = dec_insn.next_insn; 1128 if (dec_insn.micro_mips_mode) { 1129 contpc = (xcp->cp0_epc + (contpc << 1)); 1130 1131 /* If 16-bit instruction, not FPU. */ 1132 if ((dec_insn.next_pc_inc == 2) || 1133 (microMIPS32_to_MIPS32((union mips_instruction *)&ir) == SIGILL)) { 1134 1135 /* 1136 * Since this instruction will 1137 * be put on the stack with 1138 * 32-bit words, get around 1139 * this problem by putting a 1140 * NOP16 as the second one. 1141 */ 1142 if (dec_insn.next_pc_inc == 2) 1143 ir = (ir & (~0xffff)) | MM_NOP16; 1144 1145 /* 1146 * Single step the non-CP1 1147 * instruction in the dslot. 1148 */ 1149 return mips_dsemul(xcp, ir, contpc); 1150 } 1151 } else 1152 contpc = (xcp->cp0_epc + (contpc << 2)); 1153 1154 switch (MIPSInst_OPCODE(ir)) { 1155 case lwc1_op: 1156 goto emul; 1157 1158 case swc1_op: 1159 goto emul; 1160 1161 case ldc1_op: 1162 case sdc1_op: 1163 if (cpu_has_mips_2_3_4_5 || 1164 cpu_has_mips64) 1165 goto emul; 1166 1167 return SIGILL; 1168 goto emul; 1169 1170 case cop1_op: 1171 goto emul; 1172 1173 case cop1x_op: 1174 if (cpu_has_mips_4_5 || cpu_has_mips64 || cpu_has_mips32r2) 1175 /* its one of ours */ 1176 goto emul; 1177 1178 return SIGILL; 1179 1180 case spec_op: 1181 if (!cpu_has_mips_4_5_r) 1182 return SIGILL; 1183 1184 if (MIPSInst_FUNC(ir) == movc_op) 1185 goto emul; 1186 break; 1187 } 1188 1189 /* 1190 * Single step the non-cp1 1191 * instruction in the dslot 1192 */ 1193 return mips_dsemul(xcp, ir, contpc); 1194 } else if (likely) { /* branch not taken */ 1195 /* 1196 * branch likely nullifies 1197 * dslot if not taken 1198 */ 1199 xcp->cp0_epc += dec_insn.pc_inc; 1200 contpc += dec_insn.pc_inc; 1201 /* 1202 * else continue & execute 1203 * dslot as normal insn 1204 */ 1205 } 1206 break; 1207 1208 default: 1209 if (!(MIPSInst_RS(ir) & 0x10)) 1210 return SIGILL; 1211 1212 /* a real fpu computation instruction */ 1213 if ((sig = fpu_emu(xcp, ctx, ir))) 1214 return sig; 1215 } 1216 break; 1217 1218 case cop1x_op: 1219 if (!cpu_has_mips_4_5 && !cpu_has_mips64 && !cpu_has_mips32r2) 1220 return SIGILL; 1221 1222 sig = fpux_emu(xcp, ctx, ir, fault_addr); 1223 if (sig) 1224 return sig; 1225 break; 1226 1227 case spec_op: 1228 if (!cpu_has_mips_4_5_r) 1229 return SIGILL; 1230 1231 if (MIPSInst_FUNC(ir) != movc_op) 1232 return SIGILL; 1233 cond = fpucondbit[MIPSInst_RT(ir) >> 2]; 1234 if (((ctx->fcr31 & cond) != 0) == ((MIPSInst_RT(ir) & 1) != 0)) 1235 xcp->regs[MIPSInst_RD(ir)] = 1236 xcp->regs[MIPSInst_RS(ir)]; 1237 break; 1238 default: 1239 sigill: 1240 return SIGILL; 1241 } 1242 1243 /* we did it !! */ 1244 xcp->cp0_epc = contpc; 1245 clear_delay_slot(xcp); 1246 1247 return 0; 1248 } 1249 1250 /* 1251 * Conversion table from MIPS compare ops 48-63 1252 * cond = ieee754dp_cmp(x,y,IEEE754_UN,sig); 1253 */ 1254 static const unsigned char cmptab[8] = { 1255 0, /* cmp_0 (sig) cmp_sf */ 1256 IEEE754_CUN, /* cmp_un (sig) cmp_ngle */ 1257 IEEE754_CEQ, /* cmp_eq (sig) cmp_seq */ 1258 IEEE754_CEQ | IEEE754_CUN, /* cmp_ueq (sig) cmp_ngl */ 1259 IEEE754_CLT, /* cmp_olt (sig) cmp_lt */ 1260 IEEE754_CLT | IEEE754_CUN, /* cmp_ult (sig) cmp_nge */ 1261 IEEE754_CLT | IEEE754_CEQ, /* cmp_ole (sig) cmp_le */ 1262 IEEE754_CLT | IEEE754_CEQ | IEEE754_CUN, /* cmp_ule (sig) cmp_ngt */ 1263 }; 1264 1265 1266 /* 1267 * Additional MIPS4 instructions 1268 */ 1269 1270 #define DEF3OP(name, p, f1, f2, f3) \ 1271 static union ieee754##p fpemu_##p##_##name(union ieee754##p r, \ 1272 union ieee754##p s, union ieee754##p t) \ 1273 { \ 1274 struct _ieee754_csr ieee754_csr_save; \ 1275 s = f1(s, t); \ 1276 ieee754_csr_save = ieee754_csr; \ 1277 s = f2(s, r); \ 1278 ieee754_csr_save.cx |= ieee754_csr.cx; \ 1279 ieee754_csr_save.sx |= ieee754_csr.sx; \ 1280 s = f3(s); \ 1281 ieee754_csr.cx |= ieee754_csr_save.cx; \ 1282 ieee754_csr.sx |= ieee754_csr_save.sx; \ 1283 return s; \ 1284 } 1285 1286 static union ieee754dp fpemu_dp_recip(union ieee754dp d) 1287 { 1288 return ieee754dp_div(ieee754dp_one(0), d); 1289 } 1290 1291 static union ieee754dp fpemu_dp_rsqrt(union ieee754dp d) 1292 { 1293 return ieee754dp_div(ieee754dp_one(0), ieee754dp_sqrt(d)); 1294 } 1295 1296 static union ieee754sp fpemu_sp_recip(union ieee754sp s) 1297 { 1298 return ieee754sp_div(ieee754sp_one(0), s); 1299 } 1300 1301 static union ieee754sp fpemu_sp_rsqrt(union ieee754sp s) 1302 { 1303 return ieee754sp_div(ieee754sp_one(0), ieee754sp_sqrt(s)); 1304 } 1305 1306 DEF3OP(madd, sp, ieee754sp_mul, ieee754sp_add, ); 1307 DEF3OP(msub, sp, ieee754sp_mul, ieee754sp_sub, ); 1308 DEF3OP(nmadd, sp, ieee754sp_mul, ieee754sp_add, ieee754sp_neg); 1309 DEF3OP(nmsub, sp, ieee754sp_mul, ieee754sp_sub, ieee754sp_neg); 1310 DEF3OP(madd, dp, ieee754dp_mul, ieee754dp_add, ); 1311 DEF3OP(msub, dp, ieee754dp_mul, ieee754dp_sub, ); 1312 DEF3OP(nmadd, dp, ieee754dp_mul, ieee754dp_add, ieee754dp_neg); 1313 DEF3OP(nmsub, dp, ieee754dp_mul, ieee754dp_sub, ieee754dp_neg); 1314 1315 static int fpux_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx, 1316 mips_instruction ir, void *__user *fault_addr) 1317 { 1318 unsigned rcsr = 0; /* resulting csr */ 1319 1320 MIPS_FPU_EMU_INC_STATS(cp1xops); 1321 1322 switch (MIPSInst_FMA_FFMT(ir)) { 1323 case s_fmt:{ /* 0 */ 1324 1325 union ieee754sp(*handler) (union ieee754sp, union ieee754sp, union ieee754sp); 1326 union ieee754sp fd, fr, fs, ft; 1327 u32 __user *va; 1328 u32 val; 1329 1330 switch (MIPSInst_FUNC(ir)) { 1331 case lwxc1_op: 1332 va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] + 1333 xcp->regs[MIPSInst_FT(ir)]); 1334 1335 MIPS_FPU_EMU_INC_STATS(loads); 1336 if (!access_ok(VERIFY_READ, va, sizeof(u32))) { 1337 MIPS_FPU_EMU_INC_STATS(errors); 1338 *fault_addr = va; 1339 return SIGBUS; 1340 } 1341 if (__get_user(val, va)) { 1342 MIPS_FPU_EMU_INC_STATS(errors); 1343 *fault_addr = va; 1344 return SIGSEGV; 1345 } 1346 SITOREG(val, MIPSInst_FD(ir)); 1347 break; 1348 1349 case swxc1_op: 1350 va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] + 1351 xcp->regs[MIPSInst_FT(ir)]); 1352 1353 MIPS_FPU_EMU_INC_STATS(stores); 1354 1355 SIFROMREG(val, MIPSInst_FS(ir)); 1356 if (!access_ok(VERIFY_WRITE, va, sizeof(u32))) { 1357 MIPS_FPU_EMU_INC_STATS(errors); 1358 *fault_addr = va; 1359 return SIGBUS; 1360 } 1361 if (put_user(val, va)) { 1362 MIPS_FPU_EMU_INC_STATS(errors); 1363 *fault_addr = va; 1364 return SIGSEGV; 1365 } 1366 break; 1367 1368 case madd_s_op: 1369 handler = fpemu_sp_madd; 1370 goto scoptop; 1371 case msub_s_op: 1372 handler = fpemu_sp_msub; 1373 goto scoptop; 1374 case nmadd_s_op: 1375 handler = fpemu_sp_nmadd; 1376 goto scoptop; 1377 case nmsub_s_op: 1378 handler = fpemu_sp_nmsub; 1379 goto scoptop; 1380 1381 scoptop: 1382 SPFROMREG(fr, MIPSInst_FR(ir)); 1383 SPFROMREG(fs, MIPSInst_FS(ir)); 1384 SPFROMREG(ft, MIPSInst_FT(ir)); 1385 fd = (*handler) (fr, fs, ft); 1386 SPTOREG(fd, MIPSInst_FD(ir)); 1387 1388 copcsr: 1389 if (ieee754_cxtest(IEEE754_INEXACT)) { 1390 MIPS_FPU_EMU_INC_STATS(ieee754_inexact); 1391 rcsr |= FPU_CSR_INE_X | FPU_CSR_INE_S; 1392 } 1393 if (ieee754_cxtest(IEEE754_UNDERFLOW)) { 1394 MIPS_FPU_EMU_INC_STATS(ieee754_underflow); 1395 rcsr |= FPU_CSR_UDF_X | FPU_CSR_UDF_S; 1396 } 1397 if (ieee754_cxtest(IEEE754_OVERFLOW)) { 1398 MIPS_FPU_EMU_INC_STATS(ieee754_overflow); 1399 rcsr |= FPU_CSR_OVF_X | FPU_CSR_OVF_S; 1400 } 1401 if (ieee754_cxtest(IEEE754_INVALID_OPERATION)) { 1402 MIPS_FPU_EMU_INC_STATS(ieee754_invalidop); 1403 rcsr |= FPU_CSR_INV_X | FPU_CSR_INV_S; 1404 } 1405 1406 ctx->fcr31 = (ctx->fcr31 & ~FPU_CSR_ALL_X) | rcsr; 1407 if ((ctx->fcr31 >> 5) & ctx->fcr31 & FPU_CSR_ALL_E) { 1408 /*printk ("SIGFPE: FPU csr = %08x\n", 1409 ctx->fcr31); */ 1410 return SIGFPE; 1411 } 1412 1413 break; 1414 1415 default: 1416 return SIGILL; 1417 } 1418 break; 1419 } 1420 1421 case d_fmt:{ /* 1 */ 1422 union ieee754dp(*handler) (union ieee754dp, union ieee754dp, union ieee754dp); 1423 union ieee754dp fd, fr, fs, ft; 1424 u64 __user *va; 1425 u64 val; 1426 1427 switch (MIPSInst_FUNC(ir)) { 1428 case ldxc1_op: 1429 va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] + 1430 xcp->regs[MIPSInst_FT(ir)]); 1431 1432 MIPS_FPU_EMU_INC_STATS(loads); 1433 if (!access_ok(VERIFY_READ, va, sizeof(u64))) { 1434 MIPS_FPU_EMU_INC_STATS(errors); 1435 *fault_addr = va; 1436 return SIGBUS; 1437 } 1438 if (__get_user(val, va)) { 1439 MIPS_FPU_EMU_INC_STATS(errors); 1440 *fault_addr = va; 1441 return SIGSEGV; 1442 } 1443 DITOREG(val, MIPSInst_FD(ir)); 1444 break; 1445 1446 case sdxc1_op: 1447 va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] + 1448 xcp->regs[MIPSInst_FT(ir)]); 1449 1450 MIPS_FPU_EMU_INC_STATS(stores); 1451 DIFROMREG(val, MIPSInst_FS(ir)); 1452 if (!access_ok(VERIFY_WRITE, va, sizeof(u64))) { 1453 MIPS_FPU_EMU_INC_STATS(errors); 1454 *fault_addr = va; 1455 return SIGBUS; 1456 } 1457 if (__put_user(val, va)) { 1458 MIPS_FPU_EMU_INC_STATS(errors); 1459 *fault_addr = va; 1460 return SIGSEGV; 1461 } 1462 break; 1463 1464 case madd_d_op: 1465 handler = fpemu_dp_madd; 1466 goto dcoptop; 1467 case msub_d_op: 1468 handler = fpemu_dp_msub; 1469 goto dcoptop; 1470 case nmadd_d_op: 1471 handler = fpemu_dp_nmadd; 1472 goto dcoptop; 1473 case nmsub_d_op: 1474 handler = fpemu_dp_nmsub; 1475 goto dcoptop; 1476 1477 dcoptop: 1478 DPFROMREG(fr, MIPSInst_FR(ir)); 1479 DPFROMREG(fs, MIPSInst_FS(ir)); 1480 DPFROMREG(ft, MIPSInst_FT(ir)); 1481 fd = (*handler) (fr, fs, ft); 1482 DPTOREG(fd, MIPSInst_FD(ir)); 1483 goto copcsr; 1484 1485 default: 1486 return SIGILL; 1487 } 1488 break; 1489 } 1490 1491 case 0x3: 1492 if (MIPSInst_FUNC(ir) != pfetch_op) 1493 return SIGILL; 1494 1495 /* ignore prefx operation */ 1496 break; 1497 1498 default: 1499 return SIGILL; 1500 } 1501 1502 return 0; 1503 } 1504 1505 1506 1507 /* 1508 * Emulate a single COP1 arithmetic instruction. 1509 */ 1510 static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx, 1511 mips_instruction ir) 1512 { 1513 int rfmt; /* resulting format */ 1514 unsigned rcsr = 0; /* resulting csr */ 1515 unsigned int oldrm; 1516 unsigned int cbit; 1517 unsigned cond; 1518 union { 1519 union ieee754dp d; 1520 union ieee754sp s; 1521 int w; 1522 s64 l; 1523 } rv; /* resulting value */ 1524 u64 bits; 1525 1526 MIPS_FPU_EMU_INC_STATS(cp1ops); 1527 switch (rfmt = (MIPSInst_FFMT(ir) & 0xf)) { 1528 case s_fmt: { /* 0 */ 1529 union { 1530 union ieee754sp(*b) (union ieee754sp, union ieee754sp); 1531 union ieee754sp(*u) (union ieee754sp); 1532 } handler; 1533 union ieee754sp fs, ft; 1534 1535 switch (MIPSInst_FUNC(ir)) { 1536 /* binary ops */ 1537 case fadd_op: 1538 handler.b = ieee754sp_add; 1539 goto scopbop; 1540 case fsub_op: 1541 handler.b = ieee754sp_sub; 1542 goto scopbop; 1543 case fmul_op: 1544 handler.b = ieee754sp_mul; 1545 goto scopbop; 1546 case fdiv_op: 1547 handler.b = ieee754sp_div; 1548 goto scopbop; 1549 1550 /* unary ops */ 1551 case fsqrt_op: 1552 if (!cpu_has_mips_4_5_r) 1553 return SIGILL; 1554 1555 handler.u = ieee754sp_sqrt; 1556 goto scopuop; 1557 1558 /* 1559 * Note that on some MIPS IV implementations such as the 1560 * R5000 and R8000 the FSQRT and FRECIP instructions do not 1561 * achieve full IEEE-754 accuracy - however this emulator does. 1562 */ 1563 case frsqrt_op: 1564 if (!cpu_has_mips_4_5_r2_r6) 1565 return SIGILL; 1566 1567 handler.u = fpemu_sp_rsqrt; 1568 goto scopuop; 1569 1570 case frecip_op: 1571 if (!cpu_has_mips_4_5_r2_r6) 1572 return SIGILL; 1573 1574 handler.u = fpemu_sp_recip; 1575 goto scopuop; 1576 1577 case fmovc_op: 1578 if (!cpu_has_mips_4_5_r) 1579 return SIGILL; 1580 1581 cond = fpucondbit[MIPSInst_FT(ir) >> 2]; 1582 if (((ctx->fcr31 & cond) != 0) != 1583 ((MIPSInst_FT(ir) & 1) != 0)) 1584 return 0; 1585 SPFROMREG(rv.s, MIPSInst_FS(ir)); 1586 break; 1587 1588 case fmovz_op: 1589 if (!cpu_has_mips_4_5_r) 1590 return SIGILL; 1591 1592 if (xcp->regs[MIPSInst_FT(ir)] != 0) 1593 return 0; 1594 SPFROMREG(rv.s, MIPSInst_FS(ir)); 1595 break; 1596 1597 case fmovn_op: 1598 if (!cpu_has_mips_4_5_r) 1599 return SIGILL; 1600 1601 if (xcp->regs[MIPSInst_FT(ir)] == 0) 1602 return 0; 1603 SPFROMREG(rv.s, MIPSInst_FS(ir)); 1604 break; 1605 1606 case fabs_op: 1607 handler.u = ieee754sp_abs; 1608 goto scopuop; 1609 1610 case fneg_op: 1611 handler.u = ieee754sp_neg; 1612 goto scopuop; 1613 1614 case fmov_op: 1615 /* an easy one */ 1616 SPFROMREG(rv.s, MIPSInst_FS(ir)); 1617 goto copcsr; 1618 1619 /* binary op on handler */ 1620 scopbop: 1621 SPFROMREG(fs, MIPSInst_FS(ir)); 1622 SPFROMREG(ft, MIPSInst_FT(ir)); 1623 1624 rv.s = (*handler.b) (fs, ft); 1625 goto copcsr; 1626 scopuop: 1627 SPFROMREG(fs, MIPSInst_FS(ir)); 1628 rv.s = (*handler.u) (fs); 1629 goto copcsr; 1630 copcsr: 1631 if (ieee754_cxtest(IEEE754_INEXACT)) { 1632 MIPS_FPU_EMU_INC_STATS(ieee754_inexact); 1633 rcsr |= FPU_CSR_INE_X | FPU_CSR_INE_S; 1634 } 1635 if (ieee754_cxtest(IEEE754_UNDERFLOW)) { 1636 MIPS_FPU_EMU_INC_STATS(ieee754_underflow); 1637 rcsr |= FPU_CSR_UDF_X | FPU_CSR_UDF_S; 1638 } 1639 if (ieee754_cxtest(IEEE754_OVERFLOW)) { 1640 MIPS_FPU_EMU_INC_STATS(ieee754_overflow); 1641 rcsr |= FPU_CSR_OVF_X | FPU_CSR_OVF_S; 1642 } 1643 if (ieee754_cxtest(IEEE754_ZERO_DIVIDE)) { 1644 MIPS_FPU_EMU_INC_STATS(ieee754_zerodiv); 1645 rcsr |= FPU_CSR_DIV_X | FPU_CSR_DIV_S; 1646 } 1647 if (ieee754_cxtest(IEEE754_INVALID_OPERATION)) { 1648 MIPS_FPU_EMU_INC_STATS(ieee754_invalidop); 1649 rcsr |= FPU_CSR_INV_X | FPU_CSR_INV_S; 1650 } 1651 break; 1652 1653 /* unary conv ops */ 1654 case fcvts_op: 1655 return SIGILL; /* not defined */ 1656 1657 case fcvtd_op: 1658 SPFROMREG(fs, MIPSInst_FS(ir)); 1659 rv.d = ieee754dp_fsp(fs); 1660 rfmt = d_fmt; 1661 goto copcsr; 1662 1663 case fcvtw_op: 1664 SPFROMREG(fs, MIPSInst_FS(ir)); 1665 rv.w = ieee754sp_tint(fs); 1666 rfmt = w_fmt; 1667 goto copcsr; 1668 1669 case fround_op: 1670 case ftrunc_op: 1671 case fceil_op: 1672 case ffloor_op: 1673 if (!cpu_has_mips_2_3_4_5 && !cpu_has_mips64) 1674 return SIGILL; 1675 1676 oldrm = ieee754_csr.rm; 1677 SPFROMREG(fs, MIPSInst_FS(ir)); 1678 ieee754_csr.rm = modeindex(MIPSInst_FUNC(ir)); 1679 rv.w = ieee754sp_tint(fs); 1680 ieee754_csr.rm = oldrm; 1681 rfmt = w_fmt; 1682 goto copcsr; 1683 1684 case fcvtl_op: 1685 if (!cpu_has_mips_3_4_5 && !cpu_has_mips64) 1686 return SIGILL; 1687 1688 SPFROMREG(fs, MIPSInst_FS(ir)); 1689 rv.l = ieee754sp_tlong(fs); 1690 rfmt = l_fmt; 1691 goto copcsr; 1692 1693 case froundl_op: 1694 case ftruncl_op: 1695 case fceill_op: 1696 case ffloorl_op: 1697 if (!cpu_has_mips_3_4_5 && !cpu_has_mips64) 1698 return SIGILL; 1699 1700 oldrm = ieee754_csr.rm; 1701 SPFROMREG(fs, MIPSInst_FS(ir)); 1702 ieee754_csr.rm = modeindex(MIPSInst_FUNC(ir)); 1703 rv.l = ieee754sp_tlong(fs); 1704 ieee754_csr.rm = oldrm; 1705 rfmt = l_fmt; 1706 goto copcsr; 1707 1708 default: 1709 if (MIPSInst_FUNC(ir) >= fcmp_op) { 1710 unsigned cmpop = MIPSInst_FUNC(ir) - fcmp_op; 1711 union ieee754sp fs, ft; 1712 1713 SPFROMREG(fs, MIPSInst_FS(ir)); 1714 SPFROMREG(ft, MIPSInst_FT(ir)); 1715 rv.w = ieee754sp_cmp(fs, ft, 1716 cmptab[cmpop & 0x7], cmpop & 0x8); 1717 rfmt = -1; 1718 if ((cmpop & 0x8) && ieee754_cxtest 1719 (IEEE754_INVALID_OPERATION)) 1720 rcsr = FPU_CSR_INV_X | FPU_CSR_INV_S; 1721 else 1722 goto copcsr; 1723 1724 } else 1725 return SIGILL; 1726 break; 1727 } 1728 break; 1729 } 1730 1731 case d_fmt: { 1732 union ieee754dp fs, ft; 1733 union { 1734 union ieee754dp(*b) (union ieee754dp, union ieee754dp); 1735 union ieee754dp(*u) (union ieee754dp); 1736 } handler; 1737 1738 switch (MIPSInst_FUNC(ir)) { 1739 /* binary ops */ 1740 case fadd_op: 1741 handler.b = ieee754dp_add; 1742 goto dcopbop; 1743 case fsub_op: 1744 handler.b = ieee754dp_sub; 1745 goto dcopbop; 1746 case fmul_op: 1747 handler.b = ieee754dp_mul; 1748 goto dcopbop; 1749 case fdiv_op: 1750 handler.b = ieee754dp_div; 1751 goto dcopbop; 1752 1753 /* unary ops */ 1754 case fsqrt_op: 1755 if (!cpu_has_mips_2_3_4_5_r) 1756 return SIGILL; 1757 1758 handler.u = ieee754dp_sqrt; 1759 goto dcopuop; 1760 /* 1761 * Note that on some MIPS IV implementations such as the 1762 * R5000 and R8000 the FSQRT and FRECIP instructions do not 1763 * achieve full IEEE-754 accuracy - however this emulator does. 1764 */ 1765 case frsqrt_op: 1766 if (!cpu_has_mips_4_5_r2_r6) 1767 return SIGILL; 1768 1769 handler.u = fpemu_dp_rsqrt; 1770 goto dcopuop; 1771 case frecip_op: 1772 if (!cpu_has_mips_4_5_r2_r6) 1773 return SIGILL; 1774 1775 handler.u = fpemu_dp_recip; 1776 goto dcopuop; 1777 case fmovc_op: 1778 if (!cpu_has_mips_4_5_r) 1779 return SIGILL; 1780 1781 cond = fpucondbit[MIPSInst_FT(ir) >> 2]; 1782 if (((ctx->fcr31 & cond) != 0) != 1783 ((MIPSInst_FT(ir) & 1) != 0)) 1784 return 0; 1785 DPFROMREG(rv.d, MIPSInst_FS(ir)); 1786 break; 1787 case fmovz_op: 1788 if (!cpu_has_mips_4_5_r) 1789 return SIGILL; 1790 1791 if (xcp->regs[MIPSInst_FT(ir)] != 0) 1792 return 0; 1793 DPFROMREG(rv.d, MIPSInst_FS(ir)); 1794 break; 1795 case fmovn_op: 1796 if (!cpu_has_mips_4_5_r) 1797 return SIGILL; 1798 1799 if (xcp->regs[MIPSInst_FT(ir)] == 0) 1800 return 0; 1801 DPFROMREG(rv.d, MIPSInst_FS(ir)); 1802 break; 1803 case fabs_op: 1804 handler.u = ieee754dp_abs; 1805 goto dcopuop; 1806 1807 case fneg_op: 1808 handler.u = ieee754dp_neg; 1809 goto dcopuop; 1810 1811 case fmov_op: 1812 /* an easy one */ 1813 DPFROMREG(rv.d, MIPSInst_FS(ir)); 1814 goto copcsr; 1815 1816 /* binary op on handler */ 1817 dcopbop: 1818 DPFROMREG(fs, MIPSInst_FS(ir)); 1819 DPFROMREG(ft, MIPSInst_FT(ir)); 1820 1821 rv.d = (*handler.b) (fs, ft); 1822 goto copcsr; 1823 dcopuop: 1824 DPFROMREG(fs, MIPSInst_FS(ir)); 1825 rv.d = (*handler.u) (fs); 1826 goto copcsr; 1827 1828 /* 1829 * unary conv ops 1830 */ 1831 case fcvts_op: 1832 DPFROMREG(fs, MIPSInst_FS(ir)); 1833 rv.s = ieee754sp_fdp(fs); 1834 rfmt = s_fmt; 1835 goto copcsr; 1836 1837 case fcvtd_op: 1838 return SIGILL; /* not defined */ 1839 1840 case fcvtw_op: 1841 DPFROMREG(fs, MIPSInst_FS(ir)); 1842 rv.w = ieee754dp_tint(fs); /* wrong */ 1843 rfmt = w_fmt; 1844 goto copcsr; 1845 1846 case fround_op: 1847 case ftrunc_op: 1848 case fceil_op: 1849 case ffloor_op: 1850 if (!cpu_has_mips_2_3_4_5_r) 1851 return SIGILL; 1852 1853 oldrm = ieee754_csr.rm; 1854 DPFROMREG(fs, MIPSInst_FS(ir)); 1855 ieee754_csr.rm = modeindex(MIPSInst_FUNC(ir)); 1856 rv.w = ieee754dp_tint(fs); 1857 ieee754_csr.rm = oldrm; 1858 rfmt = w_fmt; 1859 goto copcsr; 1860 1861 case fcvtl_op: 1862 if (!cpu_has_mips_3_4_5 && !cpu_has_mips64) 1863 return SIGILL; 1864 1865 DPFROMREG(fs, MIPSInst_FS(ir)); 1866 rv.l = ieee754dp_tlong(fs); 1867 rfmt = l_fmt; 1868 goto copcsr; 1869 1870 case froundl_op: 1871 case ftruncl_op: 1872 case fceill_op: 1873 case ffloorl_op: 1874 if (!cpu_has_mips_3_4_5 && !cpu_has_mips64) 1875 return SIGILL; 1876 1877 oldrm = ieee754_csr.rm; 1878 DPFROMREG(fs, MIPSInst_FS(ir)); 1879 ieee754_csr.rm = modeindex(MIPSInst_FUNC(ir)); 1880 rv.l = ieee754dp_tlong(fs); 1881 ieee754_csr.rm = oldrm; 1882 rfmt = l_fmt; 1883 goto copcsr; 1884 1885 default: 1886 if (MIPSInst_FUNC(ir) >= fcmp_op) { 1887 unsigned cmpop = MIPSInst_FUNC(ir) - fcmp_op; 1888 union ieee754dp fs, ft; 1889 1890 DPFROMREG(fs, MIPSInst_FS(ir)); 1891 DPFROMREG(ft, MIPSInst_FT(ir)); 1892 rv.w = ieee754dp_cmp(fs, ft, 1893 cmptab[cmpop & 0x7], cmpop & 0x8); 1894 rfmt = -1; 1895 if ((cmpop & 0x8) 1896 && 1897 ieee754_cxtest 1898 (IEEE754_INVALID_OPERATION)) 1899 rcsr = FPU_CSR_INV_X | FPU_CSR_INV_S; 1900 else 1901 goto copcsr; 1902 1903 } 1904 else { 1905 return SIGILL; 1906 } 1907 break; 1908 } 1909 break; 1910 1911 case w_fmt: 1912 switch (MIPSInst_FUNC(ir)) { 1913 case fcvts_op: 1914 /* convert word to single precision real */ 1915 SPFROMREG(fs, MIPSInst_FS(ir)); 1916 rv.s = ieee754sp_fint(fs.bits); 1917 rfmt = s_fmt; 1918 goto copcsr; 1919 case fcvtd_op: 1920 /* convert word to double precision real */ 1921 SPFROMREG(fs, MIPSInst_FS(ir)); 1922 rv.d = ieee754dp_fint(fs.bits); 1923 rfmt = d_fmt; 1924 goto copcsr; 1925 default: 1926 return SIGILL; 1927 } 1928 break; 1929 } 1930 1931 case l_fmt: 1932 1933 if (!cpu_has_mips_3_4_5 && !cpu_has_mips64) 1934 return SIGILL; 1935 1936 DIFROMREG(bits, MIPSInst_FS(ir)); 1937 1938 switch (MIPSInst_FUNC(ir)) { 1939 case fcvts_op: 1940 /* convert long to single precision real */ 1941 rv.s = ieee754sp_flong(bits); 1942 rfmt = s_fmt; 1943 goto copcsr; 1944 case fcvtd_op: 1945 /* convert long to double precision real */ 1946 rv.d = ieee754dp_flong(bits); 1947 rfmt = d_fmt; 1948 goto copcsr; 1949 default: 1950 return SIGILL; 1951 } 1952 break; 1953 1954 default: 1955 return SIGILL; 1956 } 1957 1958 /* 1959 * Update the fpu CSR register for this operation. 1960 * If an exception is required, generate a tidy SIGFPE exception, 1961 * without updating the result register. 1962 * Note: cause exception bits do not accumulate, they are rewritten 1963 * for each op; only the flag/sticky bits accumulate. 1964 */ 1965 ctx->fcr31 = (ctx->fcr31 & ~FPU_CSR_ALL_X) | rcsr; 1966 if ((ctx->fcr31 >> 5) & ctx->fcr31 & FPU_CSR_ALL_E) { 1967 /*printk ("SIGFPE: FPU csr = %08x\n",ctx->fcr31); */ 1968 return SIGFPE; 1969 } 1970 1971 /* 1972 * Now we can safely write the result back to the register file. 1973 */ 1974 switch (rfmt) { 1975 case -1: 1976 1977 if (cpu_has_mips_4_5_r) 1978 cbit = fpucondbit[MIPSInst_FD(ir) >> 2]; 1979 else 1980 cbit = FPU_CSR_COND; 1981 if (rv.w) 1982 ctx->fcr31 |= cbit; 1983 else 1984 ctx->fcr31 &= ~cbit; 1985 break; 1986 1987 case d_fmt: 1988 DPTOREG(rv.d, MIPSInst_FD(ir)); 1989 break; 1990 case s_fmt: 1991 SPTOREG(rv.s, MIPSInst_FD(ir)); 1992 break; 1993 case w_fmt: 1994 SITOREG(rv.w, MIPSInst_FD(ir)); 1995 break; 1996 case l_fmt: 1997 if (!cpu_has_mips_3_4_5 && !cpu_has_mips64) 1998 return SIGILL; 1999 2000 DITOREG(rv.l, MIPSInst_FD(ir)); 2001 break; 2002 default: 2003 return SIGILL; 2004 } 2005 2006 return 0; 2007 } 2008 2009 int fpu_emulator_cop1Handler(struct pt_regs *xcp, struct mips_fpu_struct *ctx, 2010 int has_fpu, void *__user *fault_addr) 2011 { 2012 unsigned long oldepc, prevepc; 2013 struct mm_decoded_insn dec_insn; 2014 u16 instr[4]; 2015 u16 *instr_ptr; 2016 int sig = 0; 2017 2018 oldepc = xcp->cp0_epc; 2019 do { 2020 prevepc = xcp->cp0_epc; 2021 2022 if (get_isa16_mode(prevepc) && cpu_has_mmips) { 2023 /* 2024 * Get next 2 microMIPS instructions and convert them 2025 * into 32-bit instructions. 2026 */ 2027 if ((get_user(instr[0], (u16 __user *)msk_isa16_mode(xcp->cp0_epc))) || 2028 (get_user(instr[1], (u16 __user *)msk_isa16_mode(xcp->cp0_epc + 2))) || 2029 (get_user(instr[2], (u16 __user *)msk_isa16_mode(xcp->cp0_epc + 4))) || 2030 (get_user(instr[3], (u16 __user *)msk_isa16_mode(xcp->cp0_epc + 6)))) { 2031 MIPS_FPU_EMU_INC_STATS(errors); 2032 return SIGBUS; 2033 } 2034 instr_ptr = instr; 2035 2036 /* Get first instruction. */ 2037 if (mm_insn_16bit(*instr_ptr)) { 2038 /* Duplicate the half-word. */ 2039 dec_insn.insn = (*instr_ptr << 16) | 2040 (*instr_ptr); 2041 /* 16-bit instruction. */ 2042 dec_insn.pc_inc = 2; 2043 instr_ptr += 1; 2044 } else { 2045 dec_insn.insn = (*instr_ptr << 16) | 2046 *(instr_ptr+1); 2047 /* 32-bit instruction. */ 2048 dec_insn.pc_inc = 4; 2049 instr_ptr += 2; 2050 } 2051 /* Get second instruction. */ 2052 if (mm_insn_16bit(*instr_ptr)) { 2053 /* Duplicate the half-word. */ 2054 dec_insn.next_insn = (*instr_ptr << 16) | 2055 (*instr_ptr); 2056 /* 16-bit instruction. */ 2057 dec_insn.next_pc_inc = 2; 2058 } else { 2059 dec_insn.next_insn = (*instr_ptr << 16) | 2060 *(instr_ptr+1); 2061 /* 32-bit instruction. */ 2062 dec_insn.next_pc_inc = 4; 2063 } 2064 dec_insn.micro_mips_mode = 1; 2065 } else { 2066 if ((get_user(dec_insn.insn, 2067 (mips_instruction __user *) xcp->cp0_epc)) || 2068 (get_user(dec_insn.next_insn, 2069 (mips_instruction __user *)(xcp->cp0_epc+4)))) { 2070 MIPS_FPU_EMU_INC_STATS(errors); 2071 return SIGBUS; 2072 } 2073 dec_insn.pc_inc = 4; 2074 dec_insn.next_pc_inc = 4; 2075 dec_insn.micro_mips_mode = 0; 2076 } 2077 2078 if ((dec_insn.insn == 0) || 2079 ((dec_insn.pc_inc == 2) && 2080 ((dec_insn.insn & 0xffff) == MM_NOP16))) 2081 xcp->cp0_epc += dec_insn.pc_inc; /* Skip NOPs */ 2082 else { 2083 /* 2084 * The 'ieee754_csr' is an alias of 2085 * ctx->fcr31. No need to copy ctx->fcr31 to 2086 * ieee754_csr. But ieee754_csr.rm is ieee 2087 * library modes. (not mips rounding mode) 2088 */ 2089 sig = cop1Emulate(xcp, ctx, dec_insn, fault_addr); 2090 } 2091 2092 if (has_fpu) 2093 break; 2094 if (sig) 2095 break; 2096 2097 cond_resched(); 2098 } while (xcp->cp0_epc > prevepc); 2099 2100 /* SIGILL indicates a non-fpu instruction */ 2101 if (sig == SIGILL && xcp->cp0_epc != oldepc) 2102 /* but if EPC has advanced, then ignore it */ 2103 sig = 0; 2104 2105 return sig; 2106 } 2107