1 /* 2 * cp1emu.c: a MIPS coprocessor 1 (FPU) instruction emulator 3 * 4 * MIPS floating point support 5 * Copyright (C) 1994-2000 Algorithmics Ltd. 6 * 7 * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com 8 * Copyright (C) 2000 MIPS Technologies, Inc. 9 * 10 * This program is free software; you can distribute it and/or modify it 11 * under the terms of the GNU General Public License (Version 2) as 12 * published by the Free Software Foundation. 13 * 14 * This program is distributed in the hope it will be useful, but WITHOUT 15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 17 * for more details. 18 * 19 * You should have received a copy of the GNU General Public License along 20 * with this program; if not, write to the Free Software Foundation, Inc., 21 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. 22 * 23 * A complete emulator for MIPS coprocessor 1 instructions. This is 24 * required for #float(switch) or #float(trap), where it catches all 25 * COP1 instructions via the "CoProcessor Unusable" exception. 26 * 27 * More surprisingly it is also required for #float(ieee), to help out 28 * the hardware FPU at the boundaries of the IEEE-754 representation 29 * (denormalised values, infinities, underflow, etc). It is made 30 * quite nasty because emulation of some non-COP1 instructions is 31 * required, e.g. in branch delay slots. 32 * 33 * Note if you know that you won't have an FPU, then you'll get much 34 * better performance by compiling with -msoft-float! 35 */ 36 #include <linux/sched.h> 37 #include <linux/debugfs.h> 38 #include <linux/percpu-defs.h> 39 #include <linux/perf_event.h> 40 41 #include <asm/branch.h> 42 #include <asm/inst.h> 43 #include <asm/ptrace.h> 44 #include <asm/signal.h> 45 #include <linux/uaccess.h> 46 47 #include <asm/cpu-info.h> 48 #include <asm/processor.h> 49 #include <asm/fpu_emulator.h> 50 #include <asm/fpu.h> 51 #include <asm/mips-r2-to-r6-emul.h> 52 53 #include "ieee754.h" 54 55 /* Function which emulates a floating point instruction. */ 56 57 static int fpu_emu(struct pt_regs *, struct mips_fpu_struct *, 58 mips_instruction); 59 60 static int fpux_emu(struct pt_regs *, 61 struct mips_fpu_struct *, mips_instruction, void __user **); 62 63 /* Control registers */ 64 65 #define FPCREG_RID 0 /* $0 = revision id */ 66 #define FPCREG_FCCR 25 /* $25 = fccr */ 67 #define FPCREG_FEXR 26 /* $26 = fexr */ 68 #define FPCREG_FENR 28 /* $28 = fenr */ 69 #define FPCREG_CSR 31 /* $31 = csr */ 70 71 /* convert condition code register number to csr bit */ 72 const unsigned int fpucondbit[8] = { 73 FPU_CSR_COND, 74 FPU_CSR_COND1, 75 FPU_CSR_COND2, 76 FPU_CSR_COND3, 77 FPU_CSR_COND4, 78 FPU_CSR_COND5, 79 FPU_CSR_COND6, 80 FPU_CSR_COND7 81 }; 82 83 /* (microMIPS) Convert certain microMIPS instructions to MIPS32 format. */ 84 static const int sd_format[] = {16, 17, 0, 0, 0, 0, 0, 0}; 85 static const int sdps_format[] = {16, 17, 22, 0, 0, 0, 0, 0}; 86 static const int dwl_format[] = {17, 20, 21, 0, 0, 0, 0, 0}; 87 static const int swl_format[] = {16, 20, 21, 0, 0, 0, 0, 0}; 88 89 /* 90 * This functions translates a 32-bit microMIPS instruction 91 * into a 32-bit MIPS32 instruction. Returns 0 on success 92 * and SIGILL otherwise. 93 */ 94 static int microMIPS32_to_MIPS32(union mips_instruction *insn_ptr) 95 { 96 union mips_instruction insn = *insn_ptr; 97 union mips_instruction mips32_insn = insn; 98 int func, fmt, op; 99 100 switch (insn.mm_i_format.opcode) { 101 case mm_ldc132_op: 102 mips32_insn.mm_i_format.opcode = ldc1_op; 103 mips32_insn.mm_i_format.rt = insn.mm_i_format.rs; 104 mips32_insn.mm_i_format.rs = insn.mm_i_format.rt; 105 break; 106 case mm_lwc132_op: 107 mips32_insn.mm_i_format.opcode = lwc1_op; 108 mips32_insn.mm_i_format.rt = insn.mm_i_format.rs; 109 mips32_insn.mm_i_format.rs = insn.mm_i_format.rt; 110 break; 111 case mm_sdc132_op: 112 mips32_insn.mm_i_format.opcode = sdc1_op; 113 mips32_insn.mm_i_format.rt = insn.mm_i_format.rs; 114 mips32_insn.mm_i_format.rs = insn.mm_i_format.rt; 115 break; 116 case mm_swc132_op: 117 mips32_insn.mm_i_format.opcode = swc1_op; 118 mips32_insn.mm_i_format.rt = insn.mm_i_format.rs; 119 mips32_insn.mm_i_format.rs = insn.mm_i_format.rt; 120 break; 121 case mm_pool32i_op: 122 /* NOTE: offset is << by 1 if in microMIPS mode. */ 123 if ((insn.mm_i_format.rt == mm_bc1f_op) || 124 (insn.mm_i_format.rt == mm_bc1t_op)) { 125 mips32_insn.fb_format.opcode = cop1_op; 126 mips32_insn.fb_format.bc = bc_op; 127 mips32_insn.fb_format.flag = 128 (insn.mm_i_format.rt == mm_bc1t_op) ? 1 : 0; 129 } else 130 return SIGILL; 131 break; 132 case mm_pool32f_op: 133 switch (insn.mm_fp0_format.func) { 134 case mm_32f_01_op: 135 case mm_32f_11_op: 136 case mm_32f_02_op: 137 case mm_32f_12_op: 138 case mm_32f_41_op: 139 case mm_32f_51_op: 140 case mm_32f_42_op: 141 case mm_32f_52_op: 142 op = insn.mm_fp0_format.func; 143 if (op == mm_32f_01_op) 144 func = madd_s_op; 145 else if (op == mm_32f_11_op) 146 func = madd_d_op; 147 else if (op == mm_32f_02_op) 148 func = nmadd_s_op; 149 else if (op == mm_32f_12_op) 150 func = nmadd_d_op; 151 else if (op == mm_32f_41_op) 152 func = msub_s_op; 153 else if (op == mm_32f_51_op) 154 func = msub_d_op; 155 else if (op == mm_32f_42_op) 156 func = nmsub_s_op; 157 else 158 func = nmsub_d_op; 159 mips32_insn.fp6_format.opcode = cop1x_op; 160 mips32_insn.fp6_format.fr = insn.mm_fp6_format.fr; 161 mips32_insn.fp6_format.ft = insn.mm_fp6_format.ft; 162 mips32_insn.fp6_format.fs = insn.mm_fp6_format.fs; 163 mips32_insn.fp6_format.fd = insn.mm_fp6_format.fd; 164 mips32_insn.fp6_format.func = func; 165 break; 166 case mm_32f_10_op: 167 func = -1; /* Invalid */ 168 op = insn.mm_fp5_format.op & 0x7; 169 if (op == mm_ldxc1_op) 170 func = ldxc1_op; 171 else if (op == mm_sdxc1_op) 172 func = sdxc1_op; 173 else if (op == mm_lwxc1_op) 174 func = lwxc1_op; 175 else if (op == mm_swxc1_op) 176 func = swxc1_op; 177 178 if (func != -1) { 179 mips32_insn.r_format.opcode = cop1x_op; 180 mips32_insn.r_format.rs = 181 insn.mm_fp5_format.base; 182 mips32_insn.r_format.rt = 183 insn.mm_fp5_format.index; 184 mips32_insn.r_format.rd = 0; 185 mips32_insn.r_format.re = insn.mm_fp5_format.fd; 186 mips32_insn.r_format.func = func; 187 } else 188 return SIGILL; 189 break; 190 case mm_32f_40_op: 191 op = -1; /* Invalid */ 192 if (insn.mm_fp2_format.op == mm_fmovt_op) 193 op = 1; 194 else if (insn.mm_fp2_format.op == mm_fmovf_op) 195 op = 0; 196 if (op != -1) { 197 mips32_insn.fp0_format.opcode = cop1_op; 198 mips32_insn.fp0_format.fmt = 199 sdps_format[insn.mm_fp2_format.fmt]; 200 mips32_insn.fp0_format.ft = 201 (insn.mm_fp2_format.cc<<2) + op; 202 mips32_insn.fp0_format.fs = 203 insn.mm_fp2_format.fs; 204 mips32_insn.fp0_format.fd = 205 insn.mm_fp2_format.fd; 206 mips32_insn.fp0_format.func = fmovc_op; 207 } else 208 return SIGILL; 209 break; 210 case mm_32f_60_op: 211 func = -1; /* Invalid */ 212 if (insn.mm_fp0_format.op == mm_fadd_op) 213 func = fadd_op; 214 else if (insn.mm_fp0_format.op == mm_fsub_op) 215 func = fsub_op; 216 else if (insn.mm_fp0_format.op == mm_fmul_op) 217 func = fmul_op; 218 else if (insn.mm_fp0_format.op == mm_fdiv_op) 219 func = fdiv_op; 220 if (func != -1) { 221 mips32_insn.fp0_format.opcode = cop1_op; 222 mips32_insn.fp0_format.fmt = 223 sdps_format[insn.mm_fp0_format.fmt]; 224 mips32_insn.fp0_format.ft = 225 insn.mm_fp0_format.ft; 226 mips32_insn.fp0_format.fs = 227 insn.mm_fp0_format.fs; 228 mips32_insn.fp0_format.fd = 229 insn.mm_fp0_format.fd; 230 mips32_insn.fp0_format.func = func; 231 } else 232 return SIGILL; 233 break; 234 case mm_32f_70_op: 235 func = -1; /* Invalid */ 236 if (insn.mm_fp0_format.op == mm_fmovn_op) 237 func = fmovn_op; 238 else if (insn.mm_fp0_format.op == mm_fmovz_op) 239 func = fmovz_op; 240 if (func != -1) { 241 mips32_insn.fp0_format.opcode = cop1_op; 242 mips32_insn.fp0_format.fmt = 243 sdps_format[insn.mm_fp0_format.fmt]; 244 mips32_insn.fp0_format.ft = 245 insn.mm_fp0_format.ft; 246 mips32_insn.fp0_format.fs = 247 insn.mm_fp0_format.fs; 248 mips32_insn.fp0_format.fd = 249 insn.mm_fp0_format.fd; 250 mips32_insn.fp0_format.func = func; 251 } else 252 return SIGILL; 253 break; 254 case mm_32f_73_op: /* POOL32FXF */ 255 switch (insn.mm_fp1_format.op) { 256 case mm_movf0_op: 257 case mm_movf1_op: 258 case mm_movt0_op: 259 case mm_movt1_op: 260 if ((insn.mm_fp1_format.op & 0x7f) == 261 mm_movf0_op) 262 op = 0; 263 else 264 op = 1; 265 mips32_insn.r_format.opcode = spec_op; 266 mips32_insn.r_format.rs = insn.mm_fp4_format.fs; 267 mips32_insn.r_format.rt = 268 (insn.mm_fp4_format.cc << 2) + op; 269 mips32_insn.r_format.rd = insn.mm_fp4_format.rt; 270 mips32_insn.r_format.re = 0; 271 mips32_insn.r_format.func = movc_op; 272 break; 273 case mm_fcvtd0_op: 274 case mm_fcvtd1_op: 275 case mm_fcvts0_op: 276 case mm_fcvts1_op: 277 if ((insn.mm_fp1_format.op & 0x7f) == 278 mm_fcvtd0_op) { 279 func = fcvtd_op; 280 fmt = swl_format[insn.mm_fp3_format.fmt]; 281 } else { 282 func = fcvts_op; 283 fmt = dwl_format[insn.mm_fp3_format.fmt]; 284 } 285 mips32_insn.fp0_format.opcode = cop1_op; 286 mips32_insn.fp0_format.fmt = fmt; 287 mips32_insn.fp0_format.ft = 0; 288 mips32_insn.fp0_format.fs = 289 insn.mm_fp3_format.fs; 290 mips32_insn.fp0_format.fd = 291 insn.mm_fp3_format.rt; 292 mips32_insn.fp0_format.func = func; 293 break; 294 case mm_fmov0_op: 295 case mm_fmov1_op: 296 case mm_fabs0_op: 297 case mm_fabs1_op: 298 case mm_fneg0_op: 299 case mm_fneg1_op: 300 if ((insn.mm_fp1_format.op & 0x7f) == 301 mm_fmov0_op) 302 func = fmov_op; 303 else if ((insn.mm_fp1_format.op & 0x7f) == 304 mm_fabs0_op) 305 func = fabs_op; 306 else 307 func = fneg_op; 308 mips32_insn.fp0_format.opcode = cop1_op; 309 mips32_insn.fp0_format.fmt = 310 sdps_format[insn.mm_fp3_format.fmt]; 311 mips32_insn.fp0_format.ft = 0; 312 mips32_insn.fp0_format.fs = 313 insn.mm_fp3_format.fs; 314 mips32_insn.fp0_format.fd = 315 insn.mm_fp3_format.rt; 316 mips32_insn.fp0_format.func = func; 317 break; 318 case mm_ffloorl_op: 319 case mm_ffloorw_op: 320 case mm_fceill_op: 321 case mm_fceilw_op: 322 case mm_ftruncl_op: 323 case mm_ftruncw_op: 324 case mm_froundl_op: 325 case mm_froundw_op: 326 case mm_fcvtl_op: 327 case mm_fcvtw_op: 328 if (insn.mm_fp1_format.op == mm_ffloorl_op) 329 func = ffloorl_op; 330 else if (insn.mm_fp1_format.op == mm_ffloorw_op) 331 func = ffloor_op; 332 else if (insn.mm_fp1_format.op == mm_fceill_op) 333 func = fceill_op; 334 else if (insn.mm_fp1_format.op == mm_fceilw_op) 335 func = fceil_op; 336 else if (insn.mm_fp1_format.op == mm_ftruncl_op) 337 func = ftruncl_op; 338 else if (insn.mm_fp1_format.op == mm_ftruncw_op) 339 func = ftrunc_op; 340 else if (insn.mm_fp1_format.op == mm_froundl_op) 341 func = froundl_op; 342 else if (insn.mm_fp1_format.op == mm_froundw_op) 343 func = fround_op; 344 else if (insn.mm_fp1_format.op == mm_fcvtl_op) 345 func = fcvtl_op; 346 else 347 func = fcvtw_op; 348 mips32_insn.fp0_format.opcode = cop1_op; 349 mips32_insn.fp0_format.fmt = 350 sd_format[insn.mm_fp1_format.fmt]; 351 mips32_insn.fp0_format.ft = 0; 352 mips32_insn.fp0_format.fs = 353 insn.mm_fp1_format.fs; 354 mips32_insn.fp0_format.fd = 355 insn.mm_fp1_format.rt; 356 mips32_insn.fp0_format.func = func; 357 break; 358 case mm_frsqrt_op: 359 case mm_fsqrt_op: 360 case mm_frecip_op: 361 if (insn.mm_fp1_format.op == mm_frsqrt_op) 362 func = frsqrt_op; 363 else if (insn.mm_fp1_format.op == mm_fsqrt_op) 364 func = fsqrt_op; 365 else 366 func = frecip_op; 367 mips32_insn.fp0_format.opcode = cop1_op; 368 mips32_insn.fp0_format.fmt = 369 sdps_format[insn.mm_fp1_format.fmt]; 370 mips32_insn.fp0_format.ft = 0; 371 mips32_insn.fp0_format.fs = 372 insn.mm_fp1_format.fs; 373 mips32_insn.fp0_format.fd = 374 insn.mm_fp1_format.rt; 375 mips32_insn.fp0_format.func = func; 376 break; 377 case mm_mfc1_op: 378 case mm_mtc1_op: 379 case mm_cfc1_op: 380 case mm_ctc1_op: 381 case mm_mfhc1_op: 382 case mm_mthc1_op: 383 if (insn.mm_fp1_format.op == mm_mfc1_op) 384 op = mfc_op; 385 else if (insn.mm_fp1_format.op == mm_mtc1_op) 386 op = mtc_op; 387 else if (insn.mm_fp1_format.op == mm_cfc1_op) 388 op = cfc_op; 389 else if (insn.mm_fp1_format.op == mm_ctc1_op) 390 op = ctc_op; 391 else if (insn.mm_fp1_format.op == mm_mfhc1_op) 392 op = mfhc_op; 393 else 394 op = mthc_op; 395 mips32_insn.fp1_format.opcode = cop1_op; 396 mips32_insn.fp1_format.op = op; 397 mips32_insn.fp1_format.rt = 398 insn.mm_fp1_format.rt; 399 mips32_insn.fp1_format.fs = 400 insn.mm_fp1_format.fs; 401 mips32_insn.fp1_format.fd = 0; 402 mips32_insn.fp1_format.func = 0; 403 break; 404 default: 405 return SIGILL; 406 } 407 break; 408 case mm_32f_74_op: /* c.cond.fmt */ 409 mips32_insn.fp0_format.opcode = cop1_op; 410 mips32_insn.fp0_format.fmt = 411 sdps_format[insn.mm_fp4_format.fmt]; 412 mips32_insn.fp0_format.ft = insn.mm_fp4_format.rt; 413 mips32_insn.fp0_format.fs = insn.mm_fp4_format.fs; 414 mips32_insn.fp0_format.fd = insn.mm_fp4_format.cc << 2; 415 mips32_insn.fp0_format.func = 416 insn.mm_fp4_format.cond | MM_MIPS32_COND_FC; 417 break; 418 default: 419 return SIGILL; 420 } 421 break; 422 default: 423 return SIGILL; 424 } 425 426 *insn_ptr = mips32_insn; 427 return 0; 428 } 429 430 /* 431 * Redundant with logic already in kernel/branch.c, 432 * embedded in compute_return_epc. At some point, 433 * a single subroutine should be used across both 434 * modules. 435 */ 436 int isBranchInstr(struct pt_regs *regs, struct mm_decoded_insn dec_insn, 437 unsigned long *contpc) 438 { 439 union mips_instruction insn = (union mips_instruction)dec_insn.insn; 440 unsigned int fcr31; 441 unsigned int bit = 0; 442 unsigned int bit0; 443 union fpureg *fpr; 444 445 switch (insn.i_format.opcode) { 446 case spec_op: 447 switch (insn.r_format.func) { 448 case jalr_op: 449 if (insn.r_format.rd != 0) { 450 regs->regs[insn.r_format.rd] = 451 regs->cp0_epc + dec_insn.pc_inc + 452 dec_insn.next_pc_inc; 453 } 454 /* Fall through */ 455 case jr_op: 456 /* For R6, JR already emulated in jalr_op */ 457 if (NO_R6EMU && insn.r_format.func == jr_op) 458 break; 459 *contpc = regs->regs[insn.r_format.rs]; 460 return 1; 461 } 462 break; 463 case bcond_op: 464 switch (insn.i_format.rt) { 465 case bltzal_op: 466 case bltzall_op: 467 if (NO_R6EMU && (insn.i_format.rs || 468 insn.i_format.rt == bltzall_op)) 469 break; 470 471 regs->regs[31] = regs->cp0_epc + 472 dec_insn.pc_inc + 473 dec_insn.next_pc_inc; 474 /* Fall through */ 475 case bltzl_op: 476 if (NO_R6EMU) 477 break; 478 case bltz_op: 479 if ((long)regs->regs[insn.i_format.rs] < 0) 480 *contpc = regs->cp0_epc + 481 dec_insn.pc_inc + 482 (insn.i_format.simmediate << 2); 483 else 484 *contpc = regs->cp0_epc + 485 dec_insn.pc_inc + 486 dec_insn.next_pc_inc; 487 return 1; 488 case bgezal_op: 489 case bgezall_op: 490 if (NO_R6EMU && (insn.i_format.rs || 491 insn.i_format.rt == bgezall_op)) 492 break; 493 494 regs->regs[31] = regs->cp0_epc + 495 dec_insn.pc_inc + 496 dec_insn.next_pc_inc; 497 /* Fall through */ 498 case bgezl_op: 499 if (NO_R6EMU) 500 break; 501 case bgez_op: 502 if ((long)regs->regs[insn.i_format.rs] >= 0) 503 *contpc = regs->cp0_epc + 504 dec_insn.pc_inc + 505 (insn.i_format.simmediate << 2); 506 else 507 *contpc = regs->cp0_epc + 508 dec_insn.pc_inc + 509 dec_insn.next_pc_inc; 510 return 1; 511 } 512 break; 513 case jalx_op: 514 set_isa16_mode(bit); 515 case jal_op: 516 regs->regs[31] = regs->cp0_epc + 517 dec_insn.pc_inc + 518 dec_insn.next_pc_inc; 519 /* Fall through */ 520 case j_op: 521 *contpc = regs->cp0_epc + dec_insn.pc_inc; 522 *contpc >>= 28; 523 *contpc <<= 28; 524 *contpc |= (insn.j_format.target << 2); 525 /* Set microMIPS mode bit: XOR for jalx. */ 526 *contpc ^= bit; 527 return 1; 528 case beql_op: 529 if (NO_R6EMU) 530 break; 531 case beq_op: 532 if (regs->regs[insn.i_format.rs] == 533 regs->regs[insn.i_format.rt]) 534 *contpc = regs->cp0_epc + 535 dec_insn.pc_inc + 536 (insn.i_format.simmediate << 2); 537 else 538 *contpc = regs->cp0_epc + 539 dec_insn.pc_inc + 540 dec_insn.next_pc_inc; 541 return 1; 542 case bnel_op: 543 if (NO_R6EMU) 544 break; 545 case bne_op: 546 if (regs->regs[insn.i_format.rs] != 547 regs->regs[insn.i_format.rt]) 548 *contpc = regs->cp0_epc + 549 dec_insn.pc_inc + 550 (insn.i_format.simmediate << 2); 551 else 552 *contpc = regs->cp0_epc + 553 dec_insn.pc_inc + 554 dec_insn.next_pc_inc; 555 return 1; 556 case blezl_op: 557 if (!insn.i_format.rt && NO_R6EMU) 558 break; 559 case blez_op: 560 561 /* 562 * Compact branches for R6 for the 563 * blez and blezl opcodes. 564 * BLEZ | rs = 0 | rt != 0 == BLEZALC 565 * BLEZ | rs = rt != 0 == BGEZALC 566 * BLEZ | rs != 0 | rt != 0 == BGEUC 567 * BLEZL | rs = 0 | rt != 0 == BLEZC 568 * BLEZL | rs = rt != 0 == BGEZC 569 * BLEZL | rs != 0 | rt != 0 == BGEC 570 * 571 * For real BLEZ{,L}, rt is always 0. 572 */ 573 if (cpu_has_mips_r6 && insn.i_format.rt) { 574 if ((insn.i_format.opcode == blez_op) && 575 ((!insn.i_format.rs && insn.i_format.rt) || 576 (insn.i_format.rs == insn.i_format.rt))) 577 regs->regs[31] = regs->cp0_epc + 578 dec_insn.pc_inc; 579 *contpc = regs->cp0_epc + dec_insn.pc_inc + 580 dec_insn.next_pc_inc; 581 582 return 1; 583 } 584 if ((long)regs->regs[insn.i_format.rs] <= 0) 585 *contpc = regs->cp0_epc + 586 dec_insn.pc_inc + 587 (insn.i_format.simmediate << 2); 588 else 589 *contpc = regs->cp0_epc + 590 dec_insn.pc_inc + 591 dec_insn.next_pc_inc; 592 return 1; 593 case bgtzl_op: 594 if (!insn.i_format.rt && NO_R6EMU) 595 break; 596 case bgtz_op: 597 /* 598 * Compact branches for R6 for the 599 * bgtz and bgtzl opcodes. 600 * BGTZ | rs = 0 | rt != 0 == BGTZALC 601 * BGTZ | rs = rt != 0 == BLTZALC 602 * BGTZ | rs != 0 | rt != 0 == BLTUC 603 * BGTZL | rs = 0 | rt != 0 == BGTZC 604 * BGTZL | rs = rt != 0 == BLTZC 605 * BGTZL | rs != 0 | rt != 0 == BLTC 606 * 607 * *ZALC varint for BGTZ &&& rt != 0 608 * For real GTZ{,L}, rt is always 0. 609 */ 610 if (cpu_has_mips_r6 && insn.i_format.rt) { 611 if ((insn.i_format.opcode == blez_op) && 612 ((!insn.i_format.rs && insn.i_format.rt) || 613 (insn.i_format.rs == insn.i_format.rt))) 614 regs->regs[31] = regs->cp0_epc + 615 dec_insn.pc_inc; 616 *contpc = regs->cp0_epc + dec_insn.pc_inc + 617 dec_insn.next_pc_inc; 618 619 return 1; 620 } 621 622 if ((long)regs->regs[insn.i_format.rs] > 0) 623 *contpc = regs->cp0_epc + 624 dec_insn.pc_inc + 625 (insn.i_format.simmediate << 2); 626 else 627 *contpc = regs->cp0_epc + 628 dec_insn.pc_inc + 629 dec_insn.next_pc_inc; 630 return 1; 631 case pop10_op: 632 case pop30_op: 633 if (!cpu_has_mips_r6) 634 break; 635 if (insn.i_format.rt && !insn.i_format.rs) 636 regs->regs[31] = regs->cp0_epc + 4; 637 *contpc = regs->cp0_epc + dec_insn.pc_inc + 638 dec_insn.next_pc_inc; 639 640 return 1; 641 #ifdef CONFIG_CPU_CAVIUM_OCTEON 642 case lwc2_op: /* This is bbit0 on Octeon */ 643 if ((regs->regs[insn.i_format.rs] & (1ull<<insn.i_format.rt)) == 0) 644 *contpc = regs->cp0_epc + 4 + (insn.i_format.simmediate << 2); 645 else 646 *contpc = regs->cp0_epc + 8; 647 return 1; 648 case ldc2_op: /* This is bbit032 on Octeon */ 649 if ((regs->regs[insn.i_format.rs] & (1ull<<(insn.i_format.rt + 32))) == 0) 650 *contpc = regs->cp0_epc + 4 + (insn.i_format.simmediate << 2); 651 else 652 *contpc = regs->cp0_epc + 8; 653 return 1; 654 case swc2_op: /* This is bbit1 on Octeon */ 655 if (regs->regs[insn.i_format.rs] & (1ull<<insn.i_format.rt)) 656 *contpc = regs->cp0_epc + 4 + (insn.i_format.simmediate << 2); 657 else 658 *contpc = regs->cp0_epc + 8; 659 return 1; 660 case sdc2_op: /* This is bbit132 on Octeon */ 661 if (regs->regs[insn.i_format.rs] & (1ull<<(insn.i_format.rt + 32))) 662 *contpc = regs->cp0_epc + 4 + (insn.i_format.simmediate << 2); 663 else 664 *contpc = regs->cp0_epc + 8; 665 return 1; 666 #else 667 case bc6_op: 668 /* 669 * Only valid for MIPS R6 but we can still end up 670 * here from a broken userland so just tell emulator 671 * this is not a branch and let it break later on. 672 */ 673 if (!cpu_has_mips_r6) 674 break; 675 *contpc = regs->cp0_epc + dec_insn.pc_inc + 676 dec_insn.next_pc_inc; 677 678 return 1; 679 case balc6_op: 680 if (!cpu_has_mips_r6) 681 break; 682 regs->regs[31] = regs->cp0_epc + 4; 683 *contpc = regs->cp0_epc + dec_insn.pc_inc + 684 dec_insn.next_pc_inc; 685 686 return 1; 687 case pop66_op: 688 if (!cpu_has_mips_r6) 689 break; 690 *contpc = regs->cp0_epc + dec_insn.pc_inc + 691 dec_insn.next_pc_inc; 692 693 return 1; 694 case pop76_op: 695 if (!cpu_has_mips_r6) 696 break; 697 if (!insn.i_format.rs) 698 regs->regs[31] = regs->cp0_epc + 4; 699 *contpc = regs->cp0_epc + dec_insn.pc_inc + 700 dec_insn.next_pc_inc; 701 702 return 1; 703 #endif 704 case cop0_op: 705 case cop1_op: 706 /* Need to check for R6 bc1nez and bc1eqz branches */ 707 if (cpu_has_mips_r6 && 708 ((insn.i_format.rs == bc1eqz_op) || 709 (insn.i_format.rs == bc1nez_op))) { 710 bit = 0; 711 fpr = ¤t->thread.fpu.fpr[insn.i_format.rt]; 712 bit0 = get_fpr32(fpr, 0) & 0x1; 713 switch (insn.i_format.rs) { 714 case bc1eqz_op: 715 bit = bit0 == 0; 716 break; 717 case bc1nez_op: 718 bit = bit0 != 0; 719 break; 720 } 721 if (bit) 722 *contpc = regs->cp0_epc + 723 dec_insn.pc_inc + 724 (insn.i_format.simmediate << 2); 725 else 726 *contpc = regs->cp0_epc + 727 dec_insn.pc_inc + 728 dec_insn.next_pc_inc; 729 730 return 1; 731 } 732 /* R2/R6 compatible cop1 instruction. Fall through */ 733 case cop2_op: 734 case cop1x_op: 735 if (insn.i_format.rs == bc_op) { 736 preempt_disable(); 737 if (is_fpu_owner()) 738 fcr31 = read_32bit_cp1_register(CP1_STATUS); 739 else 740 fcr31 = current->thread.fpu.fcr31; 741 preempt_enable(); 742 743 bit = (insn.i_format.rt >> 2); 744 bit += (bit != 0); 745 bit += 23; 746 switch (insn.i_format.rt & 3) { 747 case 0: /* bc1f */ 748 case 2: /* bc1fl */ 749 if (~fcr31 & (1 << bit)) 750 *contpc = regs->cp0_epc + 751 dec_insn.pc_inc + 752 (insn.i_format.simmediate << 2); 753 else 754 *contpc = regs->cp0_epc + 755 dec_insn.pc_inc + 756 dec_insn.next_pc_inc; 757 return 1; 758 case 1: /* bc1t */ 759 case 3: /* bc1tl */ 760 if (fcr31 & (1 << bit)) 761 *contpc = regs->cp0_epc + 762 dec_insn.pc_inc + 763 (insn.i_format.simmediate << 2); 764 else 765 *contpc = regs->cp0_epc + 766 dec_insn.pc_inc + 767 dec_insn.next_pc_inc; 768 return 1; 769 } 770 } 771 break; 772 } 773 return 0; 774 } 775 776 /* 777 * In the Linux kernel, we support selection of FPR format on the 778 * basis of the Status.FR bit. If an FPU is not present, the FR bit 779 * is hardwired to zero, which would imply a 32-bit FPU even for 780 * 64-bit CPUs so we rather look at TIF_32BIT_FPREGS. 781 * FPU emu is slow and bulky and optimizing this function offers fairly 782 * sizeable benefits so we try to be clever and make this function return 783 * a constant whenever possible, that is on 64-bit kernels without O32 784 * compatibility enabled and on 32-bit without 64-bit FPU support. 785 */ 786 static inline int cop1_64bit(struct pt_regs *xcp) 787 { 788 if (IS_ENABLED(CONFIG_64BIT) && !IS_ENABLED(CONFIG_MIPS32_O32)) 789 return 1; 790 else if (IS_ENABLED(CONFIG_32BIT) && 791 !IS_ENABLED(CONFIG_MIPS_O32_FP64_SUPPORT)) 792 return 0; 793 794 return !test_thread_flag(TIF_32BIT_FPREGS); 795 } 796 797 static inline bool hybrid_fprs(void) 798 { 799 return test_thread_flag(TIF_HYBRID_FPREGS); 800 } 801 802 #define SIFROMREG(si, x) \ 803 do { \ 804 if (cop1_64bit(xcp) && !hybrid_fprs()) \ 805 (si) = (int)get_fpr32(&ctx->fpr[x], 0); \ 806 else \ 807 (si) = (int)get_fpr32(&ctx->fpr[(x) & ~1], (x) & 1); \ 808 } while (0) 809 810 #define SITOREG(si, x) \ 811 do { \ 812 if (cop1_64bit(xcp) && !hybrid_fprs()) { \ 813 unsigned int i; \ 814 set_fpr32(&ctx->fpr[x], 0, si); \ 815 for (i = 1; i < ARRAY_SIZE(ctx->fpr[x].val32); i++) \ 816 set_fpr32(&ctx->fpr[x], i, 0); \ 817 } else { \ 818 set_fpr32(&ctx->fpr[(x) & ~1], (x) & 1, si); \ 819 } \ 820 } while (0) 821 822 #define SIFROMHREG(si, x) ((si) = (int)get_fpr32(&ctx->fpr[x], 1)) 823 824 #define SITOHREG(si, x) \ 825 do { \ 826 unsigned int i; \ 827 set_fpr32(&ctx->fpr[x], 1, si); \ 828 for (i = 2; i < ARRAY_SIZE(ctx->fpr[x].val32); i++) \ 829 set_fpr32(&ctx->fpr[x], i, 0); \ 830 } while (0) 831 832 #define DIFROMREG(di, x) \ 833 ((di) = get_fpr64(&ctx->fpr[(x) & ~(cop1_64bit(xcp) ^ 1)], 0)) 834 835 #define DITOREG(di, x) \ 836 do { \ 837 unsigned int fpr, i; \ 838 fpr = (x) & ~(cop1_64bit(xcp) ^ 1); \ 839 set_fpr64(&ctx->fpr[fpr], 0, di); \ 840 for (i = 1; i < ARRAY_SIZE(ctx->fpr[x].val64); i++) \ 841 set_fpr64(&ctx->fpr[fpr], i, 0); \ 842 } while (0) 843 844 #define SPFROMREG(sp, x) SIFROMREG((sp).bits, x) 845 #define SPTOREG(sp, x) SITOREG((sp).bits, x) 846 #define DPFROMREG(dp, x) DIFROMREG((dp).bits, x) 847 #define DPTOREG(dp, x) DITOREG((dp).bits, x) 848 849 /* 850 * Emulate a CFC1 instruction. 851 */ 852 static inline void cop1_cfc(struct pt_regs *xcp, struct mips_fpu_struct *ctx, 853 mips_instruction ir) 854 { 855 u32 fcr31 = ctx->fcr31; 856 u32 value = 0; 857 858 switch (MIPSInst_RD(ir)) { 859 case FPCREG_CSR: 860 value = fcr31; 861 pr_debug("%p gpr[%d]<-csr=%08x\n", 862 (void *)xcp->cp0_epc, MIPSInst_RT(ir), value); 863 break; 864 865 case FPCREG_FENR: 866 if (!cpu_has_mips_r) 867 break; 868 value = (fcr31 >> (FPU_CSR_FS_S - MIPS_FENR_FS_S)) & 869 MIPS_FENR_FS; 870 value |= fcr31 & (FPU_CSR_ALL_E | FPU_CSR_RM); 871 pr_debug("%p gpr[%d]<-enr=%08x\n", 872 (void *)xcp->cp0_epc, MIPSInst_RT(ir), value); 873 break; 874 875 case FPCREG_FEXR: 876 if (!cpu_has_mips_r) 877 break; 878 value = fcr31 & (FPU_CSR_ALL_X | FPU_CSR_ALL_S); 879 pr_debug("%p gpr[%d]<-exr=%08x\n", 880 (void *)xcp->cp0_epc, MIPSInst_RT(ir), value); 881 break; 882 883 case FPCREG_FCCR: 884 if (!cpu_has_mips_r) 885 break; 886 value = (fcr31 >> (FPU_CSR_COND_S - MIPS_FCCR_COND0_S)) & 887 MIPS_FCCR_COND0; 888 value |= (fcr31 >> (FPU_CSR_COND1_S - MIPS_FCCR_COND1_S)) & 889 (MIPS_FCCR_CONDX & ~MIPS_FCCR_COND0); 890 pr_debug("%p gpr[%d]<-ccr=%08x\n", 891 (void *)xcp->cp0_epc, MIPSInst_RT(ir), value); 892 break; 893 894 case FPCREG_RID: 895 value = boot_cpu_data.fpu_id; 896 break; 897 898 default: 899 break; 900 } 901 902 if (MIPSInst_RT(ir)) 903 xcp->regs[MIPSInst_RT(ir)] = value; 904 } 905 906 /* 907 * Emulate a CTC1 instruction. 908 */ 909 static inline void cop1_ctc(struct pt_regs *xcp, struct mips_fpu_struct *ctx, 910 mips_instruction ir) 911 { 912 u32 fcr31 = ctx->fcr31; 913 u32 value; 914 u32 mask; 915 916 if (MIPSInst_RT(ir) == 0) 917 value = 0; 918 else 919 value = xcp->regs[MIPSInst_RT(ir)]; 920 921 switch (MIPSInst_RD(ir)) { 922 case FPCREG_CSR: 923 pr_debug("%p gpr[%d]->csr=%08x\n", 924 (void *)xcp->cp0_epc, MIPSInst_RT(ir), value); 925 926 /* Preserve read-only bits. */ 927 mask = boot_cpu_data.fpu_msk31; 928 fcr31 = (value & ~mask) | (fcr31 & mask); 929 break; 930 931 case FPCREG_FENR: 932 if (!cpu_has_mips_r) 933 break; 934 pr_debug("%p gpr[%d]->enr=%08x\n", 935 (void *)xcp->cp0_epc, MIPSInst_RT(ir), value); 936 fcr31 &= ~(FPU_CSR_FS | FPU_CSR_ALL_E | FPU_CSR_RM); 937 fcr31 |= (value << (FPU_CSR_FS_S - MIPS_FENR_FS_S)) & 938 FPU_CSR_FS; 939 fcr31 |= value & (FPU_CSR_ALL_E | FPU_CSR_RM); 940 break; 941 942 case FPCREG_FEXR: 943 if (!cpu_has_mips_r) 944 break; 945 pr_debug("%p gpr[%d]->exr=%08x\n", 946 (void *)xcp->cp0_epc, MIPSInst_RT(ir), value); 947 fcr31 &= ~(FPU_CSR_ALL_X | FPU_CSR_ALL_S); 948 fcr31 |= value & (FPU_CSR_ALL_X | FPU_CSR_ALL_S); 949 break; 950 951 case FPCREG_FCCR: 952 if (!cpu_has_mips_r) 953 break; 954 pr_debug("%p gpr[%d]->ccr=%08x\n", 955 (void *)xcp->cp0_epc, MIPSInst_RT(ir), value); 956 fcr31 &= ~(FPU_CSR_CONDX | FPU_CSR_COND); 957 fcr31 |= (value << (FPU_CSR_COND_S - MIPS_FCCR_COND0_S)) & 958 FPU_CSR_COND; 959 fcr31 |= (value << (FPU_CSR_COND1_S - MIPS_FCCR_COND1_S)) & 960 FPU_CSR_CONDX; 961 break; 962 963 default: 964 break; 965 } 966 967 ctx->fcr31 = fcr31; 968 } 969 970 /* 971 * Emulate the single floating point instruction pointed at by EPC. 972 * Two instructions if the instruction is in a branch delay slot. 973 */ 974 975 static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_struct *ctx, 976 struct mm_decoded_insn dec_insn, void __user **fault_addr) 977 { 978 unsigned long contpc = xcp->cp0_epc + dec_insn.pc_inc; 979 unsigned int cond, cbit, bit0; 980 mips_instruction ir; 981 int likely, pc_inc; 982 union fpureg *fpr; 983 u32 __user *wva; 984 u64 __user *dva; 985 u32 wval; 986 u64 dval; 987 int sig; 988 989 /* 990 * These are giving gcc a gentle hint about what to expect in 991 * dec_inst in order to do better optimization. 992 */ 993 if (!cpu_has_mmips && dec_insn.micro_mips_mode) 994 unreachable(); 995 996 /* XXX NEC Vr54xx bug workaround */ 997 if (delay_slot(xcp)) { 998 if (dec_insn.micro_mips_mode) { 999 if (!mm_isBranchInstr(xcp, dec_insn, &contpc)) 1000 clear_delay_slot(xcp); 1001 } else { 1002 if (!isBranchInstr(xcp, dec_insn, &contpc)) 1003 clear_delay_slot(xcp); 1004 } 1005 } 1006 1007 if (delay_slot(xcp)) { 1008 /* 1009 * The instruction to be emulated is in a branch delay slot 1010 * which means that we have to emulate the branch instruction 1011 * BEFORE we do the cop1 instruction. 1012 * 1013 * This branch could be a COP1 branch, but in that case we 1014 * would have had a trap for that instruction, and would not 1015 * come through this route. 1016 * 1017 * Linux MIPS branch emulator operates on context, updating the 1018 * cp0_epc. 1019 */ 1020 ir = dec_insn.next_insn; /* process delay slot instr */ 1021 pc_inc = dec_insn.next_pc_inc; 1022 } else { 1023 ir = dec_insn.insn; /* process current instr */ 1024 pc_inc = dec_insn.pc_inc; 1025 } 1026 1027 /* 1028 * Since microMIPS FPU instructios are a subset of MIPS32 FPU 1029 * instructions, we want to convert microMIPS FPU instructions 1030 * into MIPS32 instructions so that we could reuse all of the 1031 * FPU emulation code. 1032 * 1033 * NOTE: We cannot do this for branch instructions since they 1034 * are not a subset. Example: Cannot emulate a 16-bit 1035 * aligned target address with a MIPS32 instruction. 1036 */ 1037 if (dec_insn.micro_mips_mode) { 1038 /* 1039 * If next instruction is a 16-bit instruction, then it 1040 * it cannot be a FPU instruction. This could happen 1041 * since we can be called for non-FPU instructions. 1042 */ 1043 if ((pc_inc == 2) || 1044 (microMIPS32_to_MIPS32((union mips_instruction *)&ir) 1045 == SIGILL)) 1046 return SIGILL; 1047 } 1048 1049 emul: 1050 perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 1, xcp, 0); 1051 MIPS_FPU_EMU_INC_STATS(emulated); 1052 switch (MIPSInst_OPCODE(ir)) { 1053 case ldc1_op: 1054 dva = (u64 __user *) (xcp->regs[MIPSInst_RS(ir)] + 1055 MIPSInst_SIMM(ir)); 1056 MIPS_FPU_EMU_INC_STATS(loads); 1057 1058 if (!access_ok(VERIFY_READ, dva, sizeof(u64))) { 1059 MIPS_FPU_EMU_INC_STATS(errors); 1060 *fault_addr = dva; 1061 return SIGBUS; 1062 } 1063 if (__get_user(dval, dva)) { 1064 MIPS_FPU_EMU_INC_STATS(errors); 1065 *fault_addr = dva; 1066 return SIGSEGV; 1067 } 1068 DITOREG(dval, MIPSInst_RT(ir)); 1069 break; 1070 1071 case sdc1_op: 1072 dva = (u64 __user *) (xcp->regs[MIPSInst_RS(ir)] + 1073 MIPSInst_SIMM(ir)); 1074 MIPS_FPU_EMU_INC_STATS(stores); 1075 DIFROMREG(dval, MIPSInst_RT(ir)); 1076 if (!access_ok(VERIFY_WRITE, dva, sizeof(u64))) { 1077 MIPS_FPU_EMU_INC_STATS(errors); 1078 *fault_addr = dva; 1079 return SIGBUS; 1080 } 1081 if (__put_user(dval, dva)) { 1082 MIPS_FPU_EMU_INC_STATS(errors); 1083 *fault_addr = dva; 1084 return SIGSEGV; 1085 } 1086 break; 1087 1088 case lwc1_op: 1089 wva = (u32 __user *) (xcp->regs[MIPSInst_RS(ir)] + 1090 MIPSInst_SIMM(ir)); 1091 MIPS_FPU_EMU_INC_STATS(loads); 1092 if (!access_ok(VERIFY_READ, wva, sizeof(u32))) { 1093 MIPS_FPU_EMU_INC_STATS(errors); 1094 *fault_addr = wva; 1095 return SIGBUS; 1096 } 1097 if (__get_user(wval, wva)) { 1098 MIPS_FPU_EMU_INC_STATS(errors); 1099 *fault_addr = wva; 1100 return SIGSEGV; 1101 } 1102 SITOREG(wval, MIPSInst_RT(ir)); 1103 break; 1104 1105 case swc1_op: 1106 wva = (u32 __user *) (xcp->regs[MIPSInst_RS(ir)] + 1107 MIPSInst_SIMM(ir)); 1108 MIPS_FPU_EMU_INC_STATS(stores); 1109 SIFROMREG(wval, MIPSInst_RT(ir)); 1110 if (!access_ok(VERIFY_WRITE, wva, sizeof(u32))) { 1111 MIPS_FPU_EMU_INC_STATS(errors); 1112 *fault_addr = wva; 1113 return SIGBUS; 1114 } 1115 if (__put_user(wval, wva)) { 1116 MIPS_FPU_EMU_INC_STATS(errors); 1117 *fault_addr = wva; 1118 return SIGSEGV; 1119 } 1120 break; 1121 1122 case cop1_op: 1123 switch (MIPSInst_RS(ir)) { 1124 case dmfc_op: 1125 if (!cpu_has_mips_3_4_5 && !cpu_has_mips64) 1126 return SIGILL; 1127 1128 /* copregister fs -> gpr[rt] */ 1129 if (MIPSInst_RT(ir) != 0) { 1130 DIFROMREG(xcp->regs[MIPSInst_RT(ir)], 1131 MIPSInst_RD(ir)); 1132 } 1133 break; 1134 1135 case dmtc_op: 1136 if (!cpu_has_mips_3_4_5 && !cpu_has_mips64) 1137 return SIGILL; 1138 1139 /* copregister fs <- rt */ 1140 DITOREG(xcp->regs[MIPSInst_RT(ir)], MIPSInst_RD(ir)); 1141 break; 1142 1143 case mfhc_op: 1144 if (!cpu_has_mips_r2_r6) 1145 return SIGILL; 1146 1147 /* copregister rd -> gpr[rt] */ 1148 if (MIPSInst_RT(ir) != 0) { 1149 SIFROMHREG(xcp->regs[MIPSInst_RT(ir)], 1150 MIPSInst_RD(ir)); 1151 } 1152 break; 1153 1154 case mthc_op: 1155 if (!cpu_has_mips_r2_r6) 1156 return SIGILL; 1157 1158 /* copregister rd <- gpr[rt] */ 1159 SITOHREG(xcp->regs[MIPSInst_RT(ir)], MIPSInst_RD(ir)); 1160 break; 1161 1162 case mfc_op: 1163 /* copregister rd -> gpr[rt] */ 1164 if (MIPSInst_RT(ir) != 0) { 1165 SIFROMREG(xcp->regs[MIPSInst_RT(ir)], 1166 MIPSInst_RD(ir)); 1167 } 1168 break; 1169 1170 case mtc_op: 1171 /* copregister rd <- rt */ 1172 SITOREG(xcp->regs[MIPSInst_RT(ir)], MIPSInst_RD(ir)); 1173 break; 1174 1175 case cfc_op: 1176 /* cop control register rd -> gpr[rt] */ 1177 cop1_cfc(xcp, ctx, ir); 1178 break; 1179 1180 case ctc_op: 1181 /* copregister rd <- rt */ 1182 cop1_ctc(xcp, ctx, ir); 1183 if ((ctx->fcr31 >> 5) & ctx->fcr31 & FPU_CSR_ALL_E) { 1184 return SIGFPE; 1185 } 1186 break; 1187 1188 case bc1eqz_op: 1189 case bc1nez_op: 1190 if (!cpu_has_mips_r6 || delay_slot(xcp)) 1191 return SIGILL; 1192 1193 cond = likely = 0; 1194 fpr = ¤t->thread.fpu.fpr[MIPSInst_RT(ir)]; 1195 bit0 = get_fpr32(fpr, 0) & 0x1; 1196 switch (MIPSInst_RS(ir)) { 1197 case bc1eqz_op: 1198 MIPS_FPU_EMU_INC_STATS(bc1eqz); 1199 cond = bit0 == 0; 1200 break; 1201 case bc1nez_op: 1202 MIPS_FPU_EMU_INC_STATS(bc1nez); 1203 cond = bit0 != 0; 1204 break; 1205 } 1206 goto branch_common; 1207 1208 case bc_op: 1209 if (delay_slot(xcp)) 1210 return SIGILL; 1211 1212 if (cpu_has_mips_4_5_r) 1213 cbit = fpucondbit[MIPSInst_RT(ir) >> 2]; 1214 else 1215 cbit = FPU_CSR_COND; 1216 cond = ctx->fcr31 & cbit; 1217 1218 likely = 0; 1219 switch (MIPSInst_RT(ir) & 3) { 1220 case bcfl_op: 1221 if (cpu_has_mips_2_3_4_5_r) 1222 likely = 1; 1223 /* Fall through */ 1224 case bcf_op: 1225 cond = !cond; 1226 break; 1227 case bctl_op: 1228 if (cpu_has_mips_2_3_4_5_r) 1229 likely = 1; 1230 /* Fall through */ 1231 case bct_op: 1232 break; 1233 } 1234 branch_common: 1235 MIPS_FPU_EMU_INC_STATS(branches); 1236 set_delay_slot(xcp); 1237 if (cond) { 1238 /* 1239 * Branch taken: emulate dslot instruction 1240 */ 1241 unsigned long bcpc; 1242 1243 /* 1244 * Remember EPC at the branch to point back 1245 * at so that any delay-slot instruction 1246 * signal is not silently ignored. 1247 */ 1248 bcpc = xcp->cp0_epc; 1249 xcp->cp0_epc += dec_insn.pc_inc; 1250 1251 contpc = MIPSInst_SIMM(ir); 1252 ir = dec_insn.next_insn; 1253 if (dec_insn.micro_mips_mode) { 1254 contpc = (xcp->cp0_epc + (contpc << 1)); 1255 1256 /* If 16-bit instruction, not FPU. */ 1257 if ((dec_insn.next_pc_inc == 2) || 1258 (microMIPS32_to_MIPS32((union mips_instruction *)&ir) == SIGILL)) { 1259 1260 /* 1261 * Since this instruction will 1262 * be put on the stack with 1263 * 32-bit words, get around 1264 * this problem by putting a 1265 * NOP16 as the second one. 1266 */ 1267 if (dec_insn.next_pc_inc == 2) 1268 ir = (ir & (~0xffff)) | MM_NOP16; 1269 1270 /* 1271 * Single step the non-CP1 1272 * instruction in the dslot. 1273 */ 1274 sig = mips_dsemul(xcp, ir, 1275 bcpc, contpc); 1276 if (sig < 0) 1277 break; 1278 if (sig) 1279 xcp->cp0_epc = bcpc; 1280 /* 1281 * SIGILL forces out of 1282 * the emulation loop. 1283 */ 1284 return sig ? sig : SIGILL; 1285 } 1286 } else 1287 contpc = (xcp->cp0_epc + (contpc << 2)); 1288 1289 switch (MIPSInst_OPCODE(ir)) { 1290 case lwc1_op: 1291 case swc1_op: 1292 goto emul; 1293 1294 case ldc1_op: 1295 case sdc1_op: 1296 if (cpu_has_mips_2_3_4_5_r) 1297 goto emul; 1298 1299 goto bc_sigill; 1300 1301 case cop1_op: 1302 goto emul; 1303 1304 case cop1x_op: 1305 if (cpu_has_mips_4_5_64_r2_r6) 1306 /* its one of ours */ 1307 goto emul; 1308 1309 goto bc_sigill; 1310 1311 case spec_op: 1312 switch (MIPSInst_FUNC(ir)) { 1313 case movc_op: 1314 if (cpu_has_mips_4_5_r) 1315 goto emul; 1316 1317 goto bc_sigill; 1318 } 1319 break; 1320 1321 bc_sigill: 1322 xcp->cp0_epc = bcpc; 1323 return SIGILL; 1324 } 1325 1326 /* 1327 * Single step the non-cp1 1328 * instruction in the dslot 1329 */ 1330 sig = mips_dsemul(xcp, ir, bcpc, contpc); 1331 if (sig < 0) 1332 break; 1333 if (sig) 1334 xcp->cp0_epc = bcpc; 1335 /* SIGILL forces out of the emulation loop. */ 1336 return sig ? sig : SIGILL; 1337 } else if (likely) { /* branch not taken */ 1338 /* 1339 * branch likely nullifies 1340 * dslot if not taken 1341 */ 1342 xcp->cp0_epc += dec_insn.pc_inc; 1343 contpc += dec_insn.pc_inc; 1344 /* 1345 * else continue & execute 1346 * dslot as normal insn 1347 */ 1348 } 1349 break; 1350 1351 default: 1352 if (!(MIPSInst_RS(ir) & 0x10)) 1353 return SIGILL; 1354 1355 /* a real fpu computation instruction */ 1356 sig = fpu_emu(xcp, ctx, ir); 1357 if (sig) 1358 return sig; 1359 } 1360 break; 1361 1362 case cop1x_op: 1363 if (!cpu_has_mips_4_5_64_r2_r6) 1364 return SIGILL; 1365 1366 sig = fpux_emu(xcp, ctx, ir, fault_addr); 1367 if (sig) 1368 return sig; 1369 break; 1370 1371 case spec_op: 1372 if (!cpu_has_mips_4_5_r) 1373 return SIGILL; 1374 1375 if (MIPSInst_FUNC(ir) != movc_op) 1376 return SIGILL; 1377 cond = fpucondbit[MIPSInst_RT(ir) >> 2]; 1378 if (((ctx->fcr31 & cond) != 0) == ((MIPSInst_RT(ir) & 1) != 0)) 1379 xcp->regs[MIPSInst_RD(ir)] = 1380 xcp->regs[MIPSInst_RS(ir)]; 1381 break; 1382 default: 1383 return SIGILL; 1384 } 1385 1386 /* we did it !! */ 1387 xcp->cp0_epc = contpc; 1388 clear_delay_slot(xcp); 1389 1390 return 0; 1391 } 1392 1393 /* 1394 * Conversion table from MIPS compare ops 48-63 1395 * cond = ieee754dp_cmp(x,y,IEEE754_UN,sig); 1396 */ 1397 static const unsigned char cmptab[8] = { 1398 0, /* cmp_0 (sig) cmp_sf */ 1399 IEEE754_CUN, /* cmp_un (sig) cmp_ngle */ 1400 IEEE754_CEQ, /* cmp_eq (sig) cmp_seq */ 1401 IEEE754_CEQ | IEEE754_CUN, /* cmp_ueq (sig) cmp_ngl */ 1402 IEEE754_CLT, /* cmp_olt (sig) cmp_lt */ 1403 IEEE754_CLT | IEEE754_CUN, /* cmp_ult (sig) cmp_nge */ 1404 IEEE754_CLT | IEEE754_CEQ, /* cmp_ole (sig) cmp_le */ 1405 IEEE754_CLT | IEEE754_CEQ | IEEE754_CUN, /* cmp_ule (sig) cmp_ngt */ 1406 }; 1407 1408 static const unsigned char negative_cmptab[8] = { 1409 0, /* Reserved */ 1410 IEEE754_CLT | IEEE754_CGT | IEEE754_CEQ, 1411 IEEE754_CLT | IEEE754_CGT | IEEE754_CUN, 1412 IEEE754_CLT | IEEE754_CGT, 1413 /* Reserved */ 1414 }; 1415 1416 1417 /* 1418 * Additional MIPS4 instructions 1419 */ 1420 1421 #define DEF3OP(name, p, f1, f2, f3) \ 1422 static union ieee754##p fpemu_##p##_##name(union ieee754##p r, \ 1423 union ieee754##p s, union ieee754##p t) \ 1424 { \ 1425 struct _ieee754_csr ieee754_csr_save; \ 1426 s = f1(s, t); \ 1427 ieee754_csr_save = ieee754_csr; \ 1428 s = f2(s, r); \ 1429 ieee754_csr_save.cx |= ieee754_csr.cx; \ 1430 ieee754_csr_save.sx |= ieee754_csr.sx; \ 1431 s = f3(s); \ 1432 ieee754_csr.cx |= ieee754_csr_save.cx; \ 1433 ieee754_csr.sx |= ieee754_csr_save.sx; \ 1434 return s; \ 1435 } 1436 1437 static union ieee754dp fpemu_dp_recip(union ieee754dp d) 1438 { 1439 return ieee754dp_div(ieee754dp_one(0), d); 1440 } 1441 1442 static union ieee754dp fpemu_dp_rsqrt(union ieee754dp d) 1443 { 1444 return ieee754dp_div(ieee754dp_one(0), ieee754dp_sqrt(d)); 1445 } 1446 1447 static union ieee754sp fpemu_sp_recip(union ieee754sp s) 1448 { 1449 return ieee754sp_div(ieee754sp_one(0), s); 1450 } 1451 1452 static union ieee754sp fpemu_sp_rsqrt(union ieee754sp s) 1453 { 1454 return ieee754sp_div(ieee754sp_one(0), ieee754sp_sqrt(s)); 1455 } 1456 1457 DEF3OP(madd, sp, ieee754sp_mul, ieee754sp_add, ); 1458 DEF3OP(msub, sp, ieee754sp_mul, ieee754sp_sub, ); 1459 DEF3OP(nmadd, sp, ieee754sp_mul, ieee754sp_add, ieee754sp_neg); 1460 DEF3OP(nmsub, sp, ieee754sp_mul, ieee754sp_sub, ieee754sp_neg); 1461 DEF3OP(madd, dp, ieee754dp_mul, ieee754dp_add, ); 1462 DEF3OP(msub, dp, ieee754dp_mul, ieee754dp_sub, ); 1463 DEF3OP(nmadd, dp, ieee754dp_mul, ieee754dp_add, ieee754dp_neg); 1464 DEF3OP(nmsub, dp, ieee754dp_mul, ieee754dp_sub, ieee754dp_neg); 1465 1466 static int fpux_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx, 1467 mips_instruction ir, void __user **fault_addr) 1468 { 1469 unsigned int rcsr = 0; /* resulting csr */ 1470 1471 MIPS_FPU_EMU_INC_STATS(cp1xops); 1472 1473 switch (MIPSInst_FMA_FFMT(ir)) { 1474 case s_fmt:{ /* 0 */ 1475 1476 union ieee754sp(*handler) (union ieee754sp, union ieee754sp, union ieee754sp); 1477 union ieee754sp fd, fr, fs, ft; 1478 u32 __user *va; 1479 u32 val; 1480 1481 switch (MIPSInst_FUNC(ir)) { 1482 case lwxc1_op: 1483 va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] + 1484 xcp->regs[MIPSInst_FT(ir)]); 1485 1486 MIPS_FPU_EMU_INC_STATS(loads); 1487 if (!access_ok(VERIFY_READ, va, sizeof(u32))) { 1488 MIPS_FPU_EMU_INC_STATS(errors); 1489 *fault_addr = va; 1490 return SIGBUS; 1491 } 1492 if (__get_user(val, va)) { 1493 MIPS_FPU_EMU_INC_STATS(errors); 1494 *fault_addr = va; 1495 return SIGSEGV; 1496 } 1497 SITOREG(val, MIPSInst_FD(ir)); 1498 break; 1499 1500 case swxc1_op: 1501 va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] + 1502 xcp->regs[MIPSInst_FT(ir)]); 1503 1504 MIPS_FPU_EMU_INC_STATS(stores); 1505 1506 SIFROMREG(val, MIPSInst_FS(ir)); 1507 if (!access_ok(VERIFY_WRITE, va, sizeof(u32))) { 1508 MIPS_FPU_EMU_INC_STATS(errors); 1509 *fault_addr = va; 1510 return SIGBUS; 1511 } 1512 if (put_user(val, va)) { 1513 MIPS_FPU_EMU_INC_STATS(errors); 1514 *fault_addr = va; 1515 return SIGSEGV; 1516 } 1517 break; 1518 1519 case madd_s_op: 1520 handler = fpemu_sp_madd; 1521 goto scoptop; 1522 case msub_s_op: 1523 handler = fpemu_sp_msub; 1524 goto scoptop; 1525 case nmadd_s_op: 1526 handler = fpemu_sp_nmadd; 1527 goto scoptop; 1528 case nmsub_s_op: 1529 handler = fpemu_sp_nmsub; 1530 goto scoptop; 1531 1532 scoptop: 1533 SPFROMREG(fr, MIPSInst_FR(ir)); 1534 SPFROMREG(fs, MIPSInst_FS(ir)); 1535 SPFROMREG(ft, MIPSInst_FT(ir)); 1536 fd = (*handler) (fr, fs, ft); 1537 SPTOREG(fd, MIPSInst_FD(ir)); 1538 1539 copcsr: 1540 if (ieee754_cxtest(IEEE754_INEXACT)) { 1541 MIPS_FPU_EMU_INC_STATS(ieee754_inexact); 1542 rcsr |= FPU_CSR_INE_X | FPU_CSR_INE_S; 1543 } 1544 if (ieee754_cxtest(IEEE754_UNDERFLOW)) { 1545 MIPS_FPU_EMU_INC_STATS(ieee754_underflow); 1546 rcsr |= FPU_CSR_UDF_X | FPU_CSR_UDF_S; 1547 } 1548 if (ieee754_cxtest(IEEE754_OVERFLOW)) { 1549 MIPS_FPU_EMU_INC_STATS(ieee754_overflow); 1550 rcsr |= FPU_CSR_OVF_X | FPU_CSR_OVF_S; 1551 } 1552 if (ieee754_cxtest(IEEE754_INVALID_OPERATION)) { 1553 MIPS_FPU_EMU_INC_STATS(ieee754_invalidop); 1554 rcsr |= FPU_CSR_INV_X | FPU_CSR_INV_S; 1555 } 1556 1557 ctx->fcr31 = (ctx->fcr31 & ~FPU_CSR_ALL_X) | rcsr; 1558 if ((ctx->fcr31 >> 5) & ctx->fcr31 & FPU_CSR_ALL_E) { 1559 /*printk ("SIGFPE: FPU csr = %08x\n", 1560 ctx->fcr31); */ 1561 return SIGFPE; 1562 } 1563 1564 break; 1565 1566 default: 1567 return SIGILL; 1568 } 1569 break; 1570 } 1571 1572 case d_fmt:{ /* 1 */ 1573 union ieee754dp(*handler) (union ieee754dp, union ieee754dp, union ieee754dp); 1574 union ieee754dp fd, fr, fs, ft; 1575 u64 __user *va; 1576 u64 val; 1577 1578 switch (MIPSInst_FUNC(ir)) { 1579 case ldxc1_op: 1580 va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] + 1581 xcp->regs[MIPSInst_FT(ir)]); 1582 1583 MIPS_FPU_EMU_INC_STATS(loads); 1584 if (!access_ok(VERIFY_READ, va, sizeof(u64))) { 1585 MIPS_FPU_EMU_INC_STATS(errors); 1586 *fault_addr = va; 1587 return SIGBUS; 1588 } 1589 if (__get_user(val, va)) { 1590 MIPS_FPU_EMU_INC_STATS(errors); 1591 *fault_addr = va; 1592 return SIGSEGV; 1593 } 1594 DITOREG(val, MIPSInst_FD(ir)); 1595 break; 1596 1597 case sdxc1_op: 1598 va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] + 1599 xcp->regs[MIPSInst_FT(ir)]); 1600 1601 MIPS_FPU_EMU_INC_STATS(stores); 1602 DIFROMREG(val, MIPSInst_FS(ir)); 1603 if (!access_ok(VERIFY_WRITE, va, sizeof(u64))) { 1604 MIPS_FPU_EMU_INC_STATS(errors); 1605 *fault_addr = va; 1606 return SIGBUS; 1607 } 1608 if (__put_user(val, va)) { 1609 MIPS_FPU_EMU_INC_STATS(errors); 1610 *fault_addr = va; 1611 return SIGSEGV; 1612 } 1613 break; 1614 1615 case madd_d_op: 1616 handler = fpemu_dp_madd; 1617 goto dcoptop; 1618 case msub_d_op: 1619 handler = fpemu_dp_msub; 1620 goto dcoptop; 1621 case nmadd_d_op: 1622 handler = fpemu_dp_nmadd; 1623 goto dcoptop; 1624 case nmsub_d_op: 1625 handler = fpemu_dp_nmsub; 1626 goto dcoptop; 1627 1628 dcoptop: 1629 DPFROMREG(fr, MIPSInst_FR(ir)); 1630 DPFROMREG(fs, MIPSInst_FS(ir)); 1631 DPFROMREG(ft, MIPSInst_FT(ir)); 1632 fd = (*handler) (fr, fs, ft); 1633 DPTOREG(fd, MIPSInst_FD(ir)); 1634 goto copcsr; 1635 1636 default: 1637 return SIGILL; 1638 } 1639 break; 1640 } 1641 1642 case 0x3: 1643 if (MIPSInst_FUNC(ir) != pfetch_op) 1644 return SIGILL; 1645 1646 /* ignore prefx operation */ 1647 break; 1648 1649 default: 1650 return SIGILL; 1651 } 1652 1653 return 0; 1654 } 1655 1656 1657 1658 /* 1659 * Emulate a single COP1 arithmetic instruction. 1660 */ 1661 static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx, 1662 mips_instruction ir) 1663 { 1664 int rfmt; /* resulting format */ 1665 unsigned int rcsr = 0; /* resulting csr */ 1666 unsigned int oldrm; 1667 unsigned int cbit; 1668 unsigned int cond; 1669 union { 1670 union ieee754dp d; 1671 union ieee754sp s; 1672 int w; 1673 s64 l; 1674 } rv; /* resulting value */ 1675 u64 bits; 1676 1677 MIPS_FPU_EMU_INC_STATS(cp1ops); 1678 switch (rfmt = (MIPSInst_FFMT(ir) & 0xf)) { 1679 case s_fmt: { /* 0 */ 1680 union { 1681 union ieee754sp(*b) (union ieee754sp, union ieee754sp); 1682 union ieee754sp(*u) (union ieee754sp); 1683 } handler; 1684 union ieee754sp fd, fs, ft; 1685 1686 switch (MIPSInst_FUNC(ir)) { 1687 /* binary ops */ 1688 case fadd_op: 1689 MIPS_FPU_EMU_INC_STATS(add_s); 1690 handler.b = ieee754sp_add; 1691 goto scopbop; 1692 case fsub_op: 1693 MIPS_FPU_EMU_INC_STATS(sub_s); 1694 handler.b = ieee754sp_sub; 1695 goto scopbop; 1696 case fmul_op: 1697 MIPS_FPU_EMU_INC_STATS(mul_s); 1698 handler.b = ieee754sp_mul; 1699 goto scopbop; 1700 case fdiv_op: 1701 MIPS_FPU_EMU_INC_STATS(div_s); 1702 handler.b = ieee754sp_div; 1703 goto scopbop; 1704 1705 /* unary ops */ 1706 case fsqrt_op: 1707 if (!cpu_has_mips_2_3_4_5_r) 1708 return SIGILL; 1709 1710 MIPS_FPU_EMU_INC_STATS(sqrt_s); 1711 handler.u = ieee754sp_sqrt; 1712 goto scopuop; 1713 1714 /* 1715 * Note that on some MIPS IV implementations such as the 1716 * R5000 and R8000 the FSQRT and FRECIP instructions do not 1717 * achieve full IEEE-754 accuracy - however this emulator does. 1718 */ 1719 case frsqrt_op: 1720 if (!cpu_has_mips_4_5_64_r2_r6) 1721 return SIGILL; 1722 1723 MIPS_FPU_EMU_INC_STATS(rsqrt_s); 1724 handler.u = fpemu_sp_rsqrt; 1725 goto scopuop; 1726 1727 case frecip_op: 1728 if (!cpu_has_mips_4_5_64_r2_r6) 1729 return SIGILL; 1730 1731 MIPS_FPU_EMU_INC_STATS(recip_s); 1732 handler.u = fpemu_sp_recip; 1733 goto scopuop; 1734 1735 case fmovc_op: 1736 if (!cpu_has_mips_4_5_r) 1737 return SIGILL; 1738 1739 cond = fpucondbit[MIPSInst_FT(ir) >> 2]; 1740 if (((ctx->fcr31 & cond) != 0) != 1741 ((MIPSInst_FT(ir) & 1) != 0)) 1742 return 0; 1743 SPFROMREG(rv.s, MIPSInst_FS(ir)); 1744 break; 1745 1746 case fmovz_op: 1747 if (!cpu_has_mips_4_5_r) 1748 return SIGILL; 1749 1750 if (xcp->regs[MIPSInst_FT(ir)] != 0) 1751 return 0; 1752 SPFROMREG(rv.s, MIPSInst_FS(ir)); 1753 break; 1754 1755 case fmovn_op: 1756 if (!cpu_has_mips_4_5_r) 1757 return SIGILL; 1758 1759 if (xcp->regs[MIPSInst_FT(ir)] == 0) 1760 return 0; 1761 SPFROMREG(rv.s, MIPSInst_FS(ir)); 1762 break; 1763 1764 case fseleqz_op: 1765 if (!cpu_has_mips_r6) 1766 return SIGILL; 1767 1768 MIPS_FPU_EMU_INC_STATS(seleqz_s); 1769 SPFROMREG(rv.s, MIPSInst_FT(ir)); 1770 if (rv.w & 0x1) 1771 rv.w = 0; 1772 else 1773 SPFROMREG(rv.s, MIPSInst_FS(ir)); 1774 break; 1775 1776 case fselnez_op: 1777 if (!cpu_has_mips_r6) 1778 return SIGILL; 1779 1780 MIPS_FPU_EMU_INC_STATS(selnez_s); 1781 SPFROMREG(rv.s, MIPSInst_FT(ir)); 1782 if (rv.w & 0x1) 1783 SPFROMREG(rv.s, MIPSInst_FS(ir)); 1784 else 1785 rv.w = 0; 1786 break; 1787 1788 case fmaddf_op: { 1789 union ieee754sp ft, fs, fd; 1790 1791 if (!cpu_has_mips_r6) 1792 return SIGILL; 1793 1794 MIPS_FPU_EMU_INC_STATS(maddf_s); 1795 SPFROMREG(ft, MIPSInst_FT(ir)); 1796 SPFROMREG(fs, MIPSInst_FS(ir)); 1797 SPFROMREG(fd, MIPSInst_FD(ir)); 1798 rv.s = ieee754sp_maddf(fd, fs, ft); 1799 goto copcsr; 1800 } 1801 1802 case fmsubf_op: { 1803 union ieee754sp ft, fs, fd; 1804 1805 if (!cpu_has_mips_r6) 1806 return SIGILL; 1807 1808 MIPS_FPU_EMU_INC_STATS(msubf_s); 1809 SPFROMREG(ft, MIPSInst_FT(ir)); 1810 SPFROMREG(fs, MIPSInst_FS(ir)); 1811 SPFROMREG(fd, MIPSInst_FD(ir)); 1812 rv.s = ieee754sp_msubf(fd, fs, ft); 1813 goto copcsr; 1814 } 1815 1816 case frint_op: { 1817 union ieee754sp fs; 1818 1819 if (!cpu_has_mips_r6) 1820 return SIGILL; 1821 1822 MIPS_FPU_EMU_INC_STATS(rint_s); 1823 SPFROMREG(fs, MIPSInst_FS(ir)); 1824 rv.s = ieee754sp_rint(fs); 1825 goto copcsr; 1826 } 1827 1828 case fclass_op: { 1829 union ieee754sp fs; 1830 1831 if (!cpu_has_mips_r6) 1832 return SIGILL; 1833 1834 MIPS_FPU_EMU_INC_STATS(class_s); 1835 SPFROMREG(fs, MIPSInst_FS(ir)); 1836 rv.w = ieee754sp_2008class(fs); 1837 rfmt = w_fmt; 1838 goto copcsr; 1839 } 1840 1841 case fmin_op: { 1842 union ieee754sp fs, ft; 1843 1844 if (!cpu_has_mips_r6) 1845 return SIGILL; 1846 1847 MIPS_FPU_EMU_INC_STATS(min_s); 1848 SPFROMREG(ft, MIPSInst_FT(ir)); 1849 SPFROMREG(fs, MIPSInst_FS(ir)); 1850 rv.s = ieee754sp_fmin(fs, ft); 1851 goto copcsr; 1852 } 1853 1854 case fmina_op: { 1855 union ieee754sp fs, ft; 1856 1857 if (!cpu_has_mips_r6) 1858 return SIGILL; 1859 1860 MIPS_FPU_EMU_INC_STATS(mina_s); 1861 SPFROMREG(ft, MIPSInst_FT(ir)); 1862 SPFROMREG(fs, MIPSInst_FS(ir)); 1863 rv.s = ieee754sp_fmina(fs, ft); 1864 goto copcsr; 1865 } 1866 1867 case fmax_op: { 1868 union ieee754sp fs, ft; 1869 1870 if (!cpu_has_mips_r6) 1871 return SIGILL; 1872 1873 MIPS_FPU_EMU_INC_STATS(max_s); 1874 SPFROMREG(ft, MIPSInst_FT(ir)); 1875 SPFROMREG(fs, MIPSInst_FS(ir)); 1876 rv.s = ieee754sp_fmax(fs, ft); 1877 goto copcsr; 1878 } 1879 1880 case fmaxa_op: { 1881 union ieee754sp fs, ft; 1882 1883 if (!cpu_has_mips_r6) 1884 return SIGILL; 1885 1886 MIPS_FPU_EMU_INC_STATS(maxa_s); 1887 SPFROMREG(ft, MIPSInst_FT(ir)); 1888 SPFROMREG(fs, MIPSInst_FS(ir)); 1889 rv.s = ieee754sp_fmaxa(fs, ft); 1890 goto copcsr; 1891 } 1892 1893 case fabs_op: 1894 MIPS_FPU_EMU_INC_STATS(abs_s); 1895 handler.u = ieee754sp_abs; 1896 goto scopuop; 1897 1898 case fneg_op: 1899 MIPS_FPU_EMU_INC_STATS(neg_s); 1900 handler.u = ieee754sp_neg; 1901 goto scopuop; 1902 1903 case fmov_op: 1904 /* an easy one */ 1905 MIPS_FPU_EMU_INC_STATS(mov_s); 1906 SPFROMREG(rv.s, MIPSInst_FS(ir)); 1907 goto copcsr; 1908 1909 /* binary op on handler */ 1910 scopbop: 1911 SPFROMREG(fs, MIPSInst_FS(ir)); 1912 SPFROMREG(ft, MIPSInst_FT(ir)); 1913 1914 rv.s = (*handler.b) (fs, ft); 1915 goto copcsr; 1916 scopuop: 1917 SPFROMREG(fs, MIPSInst_FS(ir)); 1918 rv.s = (*handler.u) (fs); 1919 goto copcsr; 1920 copcsr: 1921 if (ieee754_cxtest(IEEE754_INEXACT)) { 1922 MIPS_FPU_EMU_INC_STATS(ieee754_inexact); 1923 rcsr |= FPU_CSR_INE_X | FPU_CSR_INE_S; 1924 } 1925 if (ieee754_cxtest(IEEE754_UNDERFLOW)) { 1926 MIPS_FPU_EMU_INC_STATS(ieee754_underflow); 1927 rcsr |= FPU_CSR_UDF_X | FPU_CSR_UDF_S; 1928 } 1929 if (ieee754_cxtest(IEEE754_OVERFLOW)) { 1930 MIPS_FPU_EMU_INC_STATS(ieee754_overflow); 1931 rcsr |= FPU_CSR_OVF_X | FPU_CSR_OVF_S; 1932 } 1933 if (ieee754_cxtest(IEEE754_ZERO_DIVIDE)) { 1934 MIPS_FPU_EMU_INC_STATS(ieee754_zerodiv); 1935 rcsr |= FPU_CSR_DIV_X | FPU_CSR_DIV_S; 1936 } 1937 if (ieee754_cxtest(IEEE754_INVALID_OPERATION)) { 1938 MIPS_FPU_EMU_INC_STATS(ieee754_invalidop); 1939 rcsr |= FPU_CSR_INV_X | FPU_CSR_INV_S; 1940 } 1941 break; 1942 1943 /* unary conv ops */ 1944 case fcvts_op: 1945 return SIGILL; /* not defined */ 1946 1947 case fcvtd_op: 1948 MIPS_FPU_EMU_INC_STATS(cvt_d_s); 1949 SPFROMREG(fs, MIPSInst_FS(ir)); 1950 rv.d = ieee754dp_fsp(fs); 1951 rfmt = d_fmt; 1952 goto copcsr; 1953 1954 case fcvtw_op: 1955 MIPS_FPU_EMU_INC_STATS(cvt_w_s); 1956 SPFROMREG(fs, MIPSInst_FS(ir)); 1957 rv.w = ieee754sp_tint(fs); 1958 rfmt = w_fmt; 1959 goto copcsr; 1960 1961 case fround_op: 1962 case ftrunc_op: 1963 case fceil_op: 1964 case ffloor_op: 1965 if (!cpu_has_mips_2_3_4_5_r) 1966 return SIGILL; 1967 1968 if (MIPSInst_FUNC(ir) == fceil_op) 1969 MIPS_FPU_EMU_INC_STATS(ceil_w_s); 1970 if (MIPSInst_FUNC(ir) == ffloor_op) 1971 MIPS_FPU_EMU_INC_STATS(floor_w_s); 1972 if (MIPSInst_FUNC(ir) == fround_op) 1973 MIPS_FPU_EMU_INC_STATS(round_w_s); 1974 if (MIPSInst_FUNC(ir) == ftrunc_op) 1975 MIPS_FPU_EMU_INC_STATS(trunc_w_s); 1976 1977 oldrm = ieee754_csr.rm; 1978 SPFROMREG(fs, MIPSInst_FS(ir)); 1979 ieee754_csr.rm = MIPSInst_FUNC(ir); 1980 rv.w = ieee754sp_tint(fs); 1981 ieee754_csr.rm = oldrm; 1982 rfmt = w_fmt; 1983 goto copcsr; 1984 1985 case fsel_op: 1986 if (!cpu_has_mips_r6) 1987 return SIGILL; 1988 1989 MIPS_FPU_EMU_INC_STATS(sel_s); 1990 SPFROMREG(fd, MIPSInst_FD(ir)); 1991 if (fd.bits & 0x1) 1992 SPFROMREG(rv.s, MIPSInst_FT(ir)); 1993 else 1994 SPFROMREG(rv.s, MIPSInst_FS(ir)); 1995 break; 1996 1997 case fcvtl_op: 1998 if (!cpu_has_mips_3_4_5_64_r2_r6) 1999 return SIGILL; 2000 2001 MIPS_FPU_EMU_INC_STATS(cvt_l_s); 2002 SPFROMREG(fs, MIPSInst_FS(ir)); 2003 rv.l = ieee754sp_tlong(fs); 2004 rfmt = l_fmt; 2005 goto copcsr; 2006 2007 case froundl_op: 2008 case ftruncl_op: 2009 case fceill_op: 2010 case ffloorl_op: 2011 if (!cpu_has_mips_3_4_5_64_r2_r6) 2012 return SIGILL; 2013 2014 if (MIPSInst_FUNC(ir) == fceill_op) 2015 MIPS_FPU_EMU_INC_STATS(ceil_l_s); 2016 if (MIPSInst_FUNC(ir) == ffloorl_op) 2017 MIPS_FPU_EMU_INC_STATS(floor_l_s); 2018 if (MIPSInst_FUNC(ir) == froundl_op) 2019 MIPS_FPU_EMU_INC_STATS(round_l_s); 2020 if (MIPSInst_FUNC(ir) == ftruncl_op) 2021 MIPS_FPU_EMU_INC_STATS(trunc_l_s); 2022 2023 oldrm = ieee754_csr.rm; 2024 SPFROMREG(fs, MIPSInst_FS(ir)); 2025 ieee754_csr.rm = MIPSInst_FUNC(ir); 2026 rv.l = ieee754sp_tlong(fs); 2027 ieee754_csr.rm = oldrm; 2028 rfmt = l_fmt; 2029 goto copcsr; 2030 2031 default: 2032 if (!NO_R6EMU && MIPSInst_FUNC(ir) >= fcmp_op) { 2033 unsigned int cmpop; 2034 union ieee754sp fs, ft; 2035 2036 cmpop = MIPSInst_FUNC(ir) - fcmp_op; 2037 SPFROMREG(fs, MIPSInst_FS(ir)); 2038 SPFROMREG(ft, MIPSInst_FT(ir)); 2039 rv.w = ieee754sp_cmp(fs, ft, 2040 cmptab[cmpop & 0x7], cmpop & 0x8); 2041 rfmt = -1; 2042 if ((cmpop & 0x8) && ieee754_cxtest 2043 (IEEE754_INVALID_OPERATION)) 2044 rcsr = FPU_CSR_INV_X | FPU_CSR_INV_S; 2045 else 2046 goto copcsr; 2047 2048 } else 2049 return SIGILL; 2050 break; 2051 } 2052 break; 2053 } 2054 2055 case d_fmt: { 2056 union ieee754dp fd, fs, ft; 2057 union { 2058 union ieee754dp(*b) (union ieee754dp, union ieee754dp); 2059 union ieee754dp(*u) (union ieee754dp); 2060 } handler; 2061 2062 switch (MIPSInst_FUNC(ir)) { 2063 /* binary ops */ 2064 case fadd_op: 2065 MIPS_FPU_EMU_INC_STATS(add_d); 2066 handler.b = ieee754dp_add; 2067 goto dcopbop; 2068 case fsub_op: 2069 MIPS_FPU_EMU_INC_STATS(sub_d); 2070 handler.b = ieee754dp_sub; 2071 goto dcopbop; 2072 case fmul_op: 2073 MIPS_FPU_EMU_INC_STATS(mul_d); 2074 handler.b = ieee754dp_mul; 2075 goto dcopbop; 2076 case fdiv_op: 2077 MIPS_FPU_EMU_INC_STATS(div_d); 2078 handler.b = ieee754dp_div; 2079 goto dcopbop; 2080 2081 /* unary ops */ 2082 case fsqrt_op: 2083 if (!cpu_has_mips_2_3_4_5_r) 2084 return SIGILL; 2085 2086 MIPS_FPU_EMU_INC_STATS(sqrt_d); 2087 handler.u = ieee754dp_sqrt; 2088 goto dcopuop; 2089 /* 2090 * Note that on some MIPS IV implementations such as the 2091 * R5000 and R8000 the FSQRT and FRECIP instructions do not 2092 * achieve full IEEE-754 accuracy - however this emulator does. 2093 */ 2094 case frsqrt_op: 2095 if (!cpu_has_mips_4_5_64_r2_r6) 2096 return SIGILL; 2097 2098 MIPS_FPU_EMU_INC_STATS(rsqrt_d); 2099 handler.u = fpemu_dp_rsqrt; 2100 goto dcopuop; 2101 case frecip_op: 2102 if (!cpu_has_mips_4_5_64_r2_r6) 2103 return SIGILL; 2104 2105 MIPS_FPU_EMU_INC_STATS(recip_d); 2106 handler.u = fpemu_dp_recip; 2107 goto dcopuop; 2108 case fmovc_op: 2109 if (!cpu_has_mips_4_5_r) 2110 return SIGILL; 2111 2112 cond = fpucondbit[MIPSInst_FT(ir) >> 2]; 2113 if (((ctx->fcr31 & cond) != 0) != 2114 ((MIPSInst_FT(ir) & 1) != 0)) 2115 return 0; 2116 DPFROMREG(rv.d, MIPSInst_FS(ir)); 2117 break; 2118 case fmovz_op: 2119 if (!cpu_has_mips_4_5_r) 2120 return SIGILL; 2121 2122 if (xcp->regs[MIPSInst_FT(ir)] != 0) 2123 return 0; 2124 DPFROMREG(rv.d, MIPSInst_FS(ir)); 2125 break; 2126 case fmovn_op: 2127 if (!cpu_has_mips_4_5_r) 2128 return SIGILL; 2129 2130 if (xcp->regs[MIPSInst_FT(ir)] == 0) 2131 return 0; 2132 DPFROMREG(rv.d, MIPSInst_FS(ir)); 2133 break; 2134 2135 case fseleqz_op: 2136 if (!cpu_has_mips_r6) 2137 return SIGILL; 2138 2139 MIPS_FPU_EMU_INC_STATS(seleqz_d); 2140 DPFROMREG(rv.d, MIPSInst_FT(ir)); 2141 if (rv.l & 0x1) 2142 rv.l = 0; 2143 else 2144 DPFROMREG(rv.d, MIPSInst_FS(ir)); 2145 break; 2146 2147 case fselnez_op: 2148 if (!cpu_has_mips_r6) 2149 return SIGILL; 2150 2151 MIPS_FPU_EMU_INC_STATS(selnez_d); 2152 DPFROMREG(rv.d, MIPSInst_FT(ir)); 2153 if (rv.l & 0x1) 2154 DPFROMREG(rv.d, MIPSInst_FS(ir)); 2155 else 2156 rv.l = 0; 2157 break; 2158 2159 case fmaddf_op: { 2160 union ieee754dp ft, fs, fd; 2161 2162 if (!cpu_has_mips_r6) 2163 return SIGILL; 2164 2165 MIPS_FPU_EMU_INC_STATS(maddf_d); 2166 DPFROMREG(ft, MIPSInst_FT(ir)); 2167 DPFROMREG(fs, MIPSInst_FS(ir)); 2168 DPFROMREG(fd, MIPSInst_FD(ir)); 2169 rv.d = ieee754dp_maddf(fd, fs, ft); 2170 goto copcsr; 2171 } 2172 2173 case fmsubf_op: { 2174 union ieee754dp ft, fs, fd; 2175 2176 if (!cpu_has_mips_r6) 2177 return SIGILL; 2178 2179 MIPS_FPU_EMU_INC_STATS(msubf_d); 2180 DPFROMREG(ft, MIPSInst_FT(ir)); 2181 DPFROMREG(fs, MIPSInst_FS(ir)); 2182 DPFROMREG(fd, MIPSInst_FD(ir)); 2183 rv.d = ieee754dp_msubf(fd, fs, ft); 2184 goto copcsr; 2185 } 2186 2187 case frint_op: { 2188 union ieee754dp fs; 2189 2190 if (!cpu_has_mips_r6) 2191 return SIGILL; 2192 2193 MIPS_FPU_EMU_INC_STATS(rint_d); 2194 DPFROMREG(fs, MIPSInst_FS(ir)); 2195 rv.d = ieee754dp_rint(fs); 2196 goto copcsr; 2197 } 2198 2199 case fclass_op: { 2200 union ieee754dp fs; 2201 2202 if (!cpu_has_mips_r6) 2203 return SIGILL; 2204 2205 MIPS_FPU_EMU_INC_STATS(class_d); 2206 DPFROMREG(fs, MIPSInst_FS(ir)); 2207 rv.l = ieee754dp_2008class(fs); 2208 rfmt = l_fmt; 2209 goto copcsr; 2210 } 2211 2212 case fmin_op: { 2213 union ieee754dp fs, ft; 2214 2215 if (!cpu_has_mips_r6) 2216 return SIGILL; 2217 2218 MIPS_FPU_EMU_INC_STATS(min_d); 2219 DPFROMREG(ft, MIPSInst_FT(ir)); 2220 DPFROMREG(fs, MIPSInst_FS(ir)); 2221 rv.d = ieee754dp_fmin(fs, ft); 2222 goto copcsr; 2223 } 2224 2225 case fmina_op: { 2226 union ieee754dp fs, ft; 2227 2228 if (!cpu_has_mips_r6) 2229 return SIGILL; 2230 2231 MIPS_FPU_EMU_INC_STATS(mina_d); 2232 DPFROMREG(ft, MIPSInst_FT(ir)); 2233 DPFROMREG(fs, MIPSInst_FS(ir)); 2234 rv.d = ieee754dp_fmina(fs, ft); 2235 goto copcsr; 2236 } 2237 2238 case fmax_op: { 2239 union ieee754dp fs, ft; 2240 2241 if (!cpu_has_mips_r6) 2242 return SIGILL; 2243 2244 MIPS_FPU_EMU_INC_STATS(max_d); 2245 DPFROMREG(ft, MIPSInst_FT(ir)); 2246 DPFROMREG(fs, MIPSInst_FS(ir)); 2247 rv.d = ieee754dp_fmax(fs, ft); 2248 goto copcsr; 2249 } 2250 2251 case fmaxa_op: { 2252 union ieee754dp fs, ft; 2253 2254 if (!cpu_has_mips_r6) 2255 return SIGILL; 2256 2257 MIPS_FPU_EMU_INC_STATS(maxa_d); 2258 DPFROMREG(ft, MIPSInst_FT(ir)); 2259 DPFROMREG(fs, MIPSInst_FS(ir)); 2260 rv.d = ieee754dp_fmaxa(fs, ft); 2261 goto copcsr; 2262 } 2263 2264 case fabs_op: 2265 MIPS_FPU_EMU_INC_STATS(abs_d); 2266 handler.u = ieee754dp_abs; 2267 goto dcopuop; 2268 2269 case fneg_op: 2270 MIPS_FPU_EMU_INC_STATS(neg_d); 2271 handler.u = ieee754dp_neg; 2272 goto dcopuop; 2273 2274 case fmov_op: 2275 /* an easy one */ 2276 MIPS_FPU_EMU_INC_STATS(mov_d); 2277 DPFROMREG(rv.d, MIPSInst_FS(ir)); 2278 goto copcsr; 2279 2280 /* binary op on handler */ 2281 dcopbop: 2282 DPFROMREG(fs, MIPSInst_FS(ir)); 2283 DPFROMREG(ft, MIPSInst_FT(ir)); 2284 2285 rv.d = (*handler.b) (fs, ft); 2286 goto copcsr; 2287 dcopuop: 2288 DPFROMREG(fs, MIPSInst_FS(ir)); 2289 rv.d = (*handler.u) (fs); 2290 goto copcsr; 2291 2292 /* 2293 * unary conv ops 2294 */ 2295 case fcvts_op: 2296 MIPS_FPU_EMU_INC_STATS(cvt_s_d); 2297 DPFROMREG(fs, MIPSInst_FS(ir)); 2298 rv.s = ieee754sp_fdp(fs); 2299 rfmt = s_fmt; 2300 goto copcsr; 2301 2302 case fcvtd_op: 2303 return SIGILL; /* not defined */ 2304 2305 case fcvtw_op: 2306 MIPS_FPU_EMU_INC_STATS(cvt_w_d); 2307 DPFROMREG(fs, MIPSInst_FS(ir)); 2308 rv.w = ieee754dp_tint(fs); /* wrong */ 2309 rfmt = w_fmt; 2310 goto copcsr; 2311 2312 case fround_op: 2313 case ftrunc_op: 2314 case fceil_op: 2315 case ffloor_op: 2316 if (!cpu_has_mips_2_3_4_5_r) 2317 return SIGILL; 2318 2319 if (MIPSInst_FUNC(ir) == fceil_op) 2320 MIPS_FPU_EMU_INC_STATS(ceil_w_d); 2321 if (MIPSInst_FUNC(ir) == ffloor_op) 2322 MIPS_FPU_EMU_INC_STATS(floor_w_d); 2323 if (MIPSInst_FUNC(ir) == fround_op) 2324 MIPS_FPU_EMU_INC_STATS(round_w_d); 2325 if (MIPSInst_FUNC(ir) == ftrunc_op) 2326 MIPS_FPU_EMU_INC_STATS(trunc_w_d); 2327 2328 oldrm = ieee754_csr.rm; 2329 DPFROMREG(fs, MIPSInst_FS(ir)); 2330 ieee754_csr.rm = MIPSInst_FUNC(ir); 2331 rv.w = ieee754dp_tint(fs); 2332 ieee754_csr.rm = oldrm; 2333 rfmt = w_fmt; 2334 goto copcsr; 2335 2336 case fsel_op: 2337 if (!cpu_has_mips_r6) 2338 return SIGILL; 2339 2340 MIPS_FPU_EMU_INC_STATS(sel_d); 2341 DPFROMREG(fd, MIPSInst_FD(ir)); 2342 if (fd.bits & 0x1) 2343 DPFROMREG(rv.d, MIPSInst_FT(ir)); 2344 else 2345 DPFROMREG(rv.d, MIPSInst_FS(ir)); 2346 break; 2347 2348 case fcvtl_op: 2349 if (!cpu_has_mips_3_4_5_64_r2_r6) 2350 return SIGILL; 2351 2352 MIPS_FPU_EMU_INC_STATS(cvt_l_d); 2353 DPFROMREG(fs, MIPSInst_FS(ir)); 2354 rv.l = ieee754dp_tlong(fs); 2355 rfmt = l_fmt; 2356 goto copcsr; 2357 2358 case froundl_op: 2359 case ftruncl_op: 2360 case fceill_op: 2361 case ffloorl_op: 2362 if (!cpu_has_mips_3_4_5_64_r2_r6) 2363 return SIGILL; 2364 2365 if (MIPSInst_FUNC(ir) == fceill_op) 2366 MIPS_FPU_EMU_INC_STATS(ceil_l_d); 2367 if (MIPSInst_FUNC(ir) == ffloorl_op) 2368 MIPS_FPU_EMU_INC_STATS(floor_l_d); 2369 if (MIPSInst_FUNC(ir) == froundl_op) 2370 MIPS_FPU_EMU_INC_STATS(round_l_d); 2371 if (MIPSInst_FUNC(ir) == ftruncl_op) 2372 MIPS_FPU_EMU_INC_STATS(trunc_l_d); 2373 2374 oldrm = ieee754_csr.rm; 2375 DPFROMREG(fs, MIPSInst_FS(ir)); 2376 ieee754_csr.rm = MIPSInst_FUNC(ir); 2377 rv.l = ieee754dp_tlong(fs); 2378 ieee754_csr.rm = oldrm; 2379 rfmt = l_fmt; 2380 goto copcsr; 2381 2382 default: 2383 if (!NO_R6EMU && MIPSInst_FUNC(ir) >= fcmp_op) { 2384 unsigned int cmpop; 2385 union ieee754dp fs, ft; 2386 2387 cmpop = MIPSInst_FUNC(ir) - fcmp_op; 2388 DPFROMREG(fs, MIPSInst_FS(ir)); 2389 DPFROMREG(ft, MIPSInst_FT(ir)); 2390 rv.w = ieee754dp_cmp(fs, ft, 2391 cmptab[cmpop & 0x7], cmpop & 0x8); 2392 rfmt = -1; 2393 if ((cmpop & 0x8) 2394 && 2395 ieee754_cxtest 2396 (IEEE754_INVALID_OPERATION)) 2397 rcsr = FPU_CSR_INV_X | FPU_CSR_INV_S; 2398 else 2399 goto copcsr; 2400 2401 } 2402 else { 2403 return SIGILL; 2404 } 2405 break; 2406 } 2407 break; 2408 } 2409 2410 case w_fmt: { 2411 union ieee754dp fs; 2412 2413 switch (MIPSInst_FUNC(ir)) { 2414 case fcvts_op: 2415 /* convert word to single precision real */ 2416 MIPS_FPU_EMU_INC_STATS(cvt_s_w); 2417 SPFROMREG(fs, MIPSInst_FS(ir)); 2418 rv.s = ieee754sp_fint(fs.bits); 2419 rfmt = s_fmt; 2420 goto copcsr; 2421 case fcvtd_op: 2422 /* convert word to double precision real */ 2423 MIPS_FPU_EMU_INC_STATS(cvt_d_w); 2424 SPFROMREG(fs, MIPSInst_FS(ir)); 2425 rv.d = ieee754dp_fint(fs.bits); 2426 rfmt = d_fmt; 2427 goto copcsr; 2428 default: { 2429 /* Emulating the new CMP.condn.fmt R6 instruction */ 2430 #define CMPOP_MASK 0x7 2431 #define SIGN_BIT (0x1 << 3) 2432 #define PREDICATE_BIT (0x1 << 4) 2433 2434 int cmpop = MIPSInst_FUNC(ir) & CMPOP_MASK; 2435 int sig = MIPSInst_FUNC(ir) & SIGN_BIT; 2436 union ieee754sp fs, ft; 2437 2438 /* This is an R6 only instruction */ 2439 if (!cpu_has_mips_r6 || 2440 (MIPSInst_FUNC(ir) & 0x20)) 2441 return SIGILL; 2442 2443 if (!sig) { 2444 if (!(MIPSInst_FUNC(ir) & PREDICATE_BIT)) { 2445 switch (cmpop) { 2446 case 0: 2447 MIPS_FPU_EMU_INC_STATS(cmp_af_s); 2448 break; 2449 case 1: 2450 MIPS_FPU_EMU_INC_STATS(cmp_un_s); 2451 break; 2452 case 2: 2453 MIPS_FPU_EMU_INC_STATS(cmp_eq_s); 2454 break; 2455 case 3: 2456 MIPS_FPU_EMU_INC_STATS(cmp_ueq_s); 2457 break; 2458 case 4: 2459 MIPS_FPU_EMU_INC_STATS(cmp_lt_s); 2460 break; 2461 case 5: 2462 MIPS_FPU_EMU_INC_STATS(cmp_ult_s); 2463 break; 2464 case 6: 2465 MIPS_FPU_EMU_INC_STATS(cmp_le_s); 2466 break; 2467 case 7: 2468 MIPS_FPU_EMU_INC_STATS(cmp_ule_s); 2469 break; 2470 } 2471 } else { 2472 switch (cmpop) { 2473 case 1: 2474 MIPS_FPU_EMU_INC_STATS(cmp_or_s); 2475 break; 2476 case 2: 2477 MIPS_FPU_EMU_INC_STATS(cmp_une_s); 2478 break; 2479 case 3: 2480 MIPS_FPU_EMU_INC_STATS(cmp_ne_s); 2481 break; 2482 } 2483 } 2484 } else { 2485 if (!(MIPSInst_FUNC(ir) & PREDICATE_BIT)) { 2486 switch (cmpop) { 2487 case 0: 2488 MIPS_FPU_EMU_INC_STATS(cmp_saf_s); 2489 break; 2490 case 1: 2491 MIPS_FPU_EMU_INC_STATS(cmp_sun_s); 2492 break; 2493 case 2: 2494 MIPS_FPU_EMU_INC_STATS(cmp_seq_s); 2495 break; 2496 case 3: 2497 MIPS_FPU_EMU_INC_STATS(cmp_sueq_s); 2498 break; 2499 case 4: 2500 MIPS_FPU_EMU_INC_STATS(cmp_slt_s); 2501 break; 2502 case 5: 2503 MIPS_FPU_EMU_INC_STATS(cmp_sult_s); 2504 break; 2505 case 6: 2506 MIPS_FPU_EMU_INC_STATS(cmp_sle_s); 2507 break; 2508 case 7: 2509 MIPS_FPU_EMU_INC_STATS(cmp_sule_s); 2510 break; 2511 } 2512 } else { 2513 switch (cmpop) { 2514 case 1: 2515 MIPS_FPU_EMU_INC_STATS(cmp_sor_s); 2516 break; 2517 case 2: 2518 MIPS_FPU_EMU_INC_STATS(cmp_sune_s); 2519 break; 2520 case 3: 2521 MIPS_FPU_EMU_INC_STATS(cmp_sne_s); 2522 break; 2523 } 2524 } 2525 } 2526 2527 /* fmt is w_fmt for single precision so fix it */ 2528 rfmt = s_fmt; 2529 /* default to false */ 2530 rv.w = 0; 2531 2532 /* CMP.condn.S */ 2533 SPFROMREG(fs, MIPSInst_FS(ir)); 2534 SPFROMREG(ft, MIPSInst_FT(ir)); 2535 2536 /* positive predicates */ 2537 if (!(MIPSInst_FUNC(ir) & PREDICATE_BIT)) { 2538 if (ieee754sp_cmp(fs, ft, cmptab[cmpop], 2539 sig)) 2540 rv.w = -1; /* true, all 1s */ 2541 if ((sig) && 2542 ieee754_cxtest(IEEE754_INVALID_OPERATION)) 2543 rcsr = FPU_CSR_INV_X | FPU_CSR_INV_S; 2544 else 2545 goto copcsr; 2546 } else { 2547 /* negative predicates */ 2548 switch (cmpop) { 2549 case 1: 2550 case 2: 2551 case 3: 2552 if (ieee754sp_cmp(fs, ft, 2553 negative_cmptab[cmpop], 2554 sig)) 2555 rv.w = -1; /* true, all 1s */ 2556 if (sig && 2557 ieee754_cxtest(IEEE754_INVALID_OPERATION)) 2558 rcsr = FPU_CSR_INV_X | FPU_CSR_INV_S; 2559 else 2560 goto copcsr; 2561 break; 2562 default: 2563 /* Reserved R6 ops */ 2564 return SIGILL; 2565 } 2566 } 2567 break; 2568 } 2569 } 2570 break; 2571 } 2572 2573 case l_fmt: 2574 2575 if (!cpu_has_mips_3_4_5_64_r2_r6) 2576 return SIGILL; 2577 2578 DIFROMREG(bits, MIPSInst_FS(ir)); 2579 2580 switch (MIPSInst_FUNC(ir)) { 2581 case fcvts_op: 2582 /* convert long to single precision real */ 2583 MIPS_FPU_EMU_INC_STATS(cvt_s_l); 2584 rv.s = ieee754sp_flong(bits); 2585 rfmt = s_fmt; 2586 goto copcsr; 2587 case fcvtd_op: 2588 /* convert long to double precision real */ 2589 MIPS_FPU_EMU_INC_STATS(cvt_d_l); 2590 rv.d = ieee754dp_flong(bits); 2591 rfmt = d_fmt; 2592 goto copcsr; 2593 default: { 2594 /* Emulating the new CMP.condn.fmt R6 instruction */ 2595 int cmpop = MIPSInst_FUNC(ir) & CMPOP_MASK; 2596 int sig = MIPSInst_FUNC(ir) & SIGN_BIT; 2597 union ieee754dp fs, ft; 2598 2599 if (!cpu_has_mips_r6 || 2600 (MIPSInst_FUNC(ir) & 0x20)) 2601 return SIGILL; 2602 2603 if (!sig) { 2604 if (!(MIPSInst_FUNC(ir) & PREDICATE_BIT)) { 2605 switch (cmpop) { 2606 case 0: 2607 MIPS_FPU_EMU_INC_STATS(cmp_af_d); 2608 break; 2609 case 1: 2610 MIPS_FPU_EMU_INC_STATS(cmp_un_d); 2611 break; 2612 case 2: 2613 MIPS_FPU_EMU_INC_STATS(cmp_eq_d); 2614 break; 2615 case 3: 2616 MIPS_FPU_EMU_INC_STATS(cmp_ueq_d); 2617 break; 2618 case 4: 2619 MIPS_FPU_EMU_INC_STATS(cmp_lt_d); 2620 break; 2621 case 5: 2622 MIPS_FPU_EMU_INC_STATS(cmp_ult_d); 2623 break; 2624 case 6: 2625 MIPS_FPU_EMU_INC_STATS(cmp_le_d); 2626 break; 2627 case 7: 2628 MIPS_FPU_EMU_INC_STATS(cmp_ule_d); 2629 break; 2630 } 2631 } else { 2632 switch (cmpop) { 2633 case 1: 2634 MIPS_FPU_EMU_INC_STATS(cmp_or_d); 2635 break; 2636 case 2: 2637 MIPS_FPU_EMU_INC_STATS(cmp_une_d); 2638 break; 2639 case 3: 2640 MIPS_FPU_EMU_INC_STATS(cmp_ne_d); 2641 break; 2642 } 2643 } 2644 } else { 2645 if (!(MIPSInst_FUNC(ir) & PREDICATE_BIT)) { 2646 switch (cmpop) { 2647 case 0: 2648 MIPS_FPU_EMU_INC_STATS(cmp_saf_d); 2649 break; 2650 case 1: 2651 MIPS_FPU_EMU_INC_STATS(cmp_sun_d); 2652 break; 2653 case 2: 2654 MIPS_FPU_EMU_INC_STATS(cmp_seq_d); 2655 break; 2656 case 3: 2657 MIPS_FPU_EMU_INC_STATS(cmp_sueq_d); 2658 break; 2659 case 4: 2660 MIPS_FPU_EMU_INC_STATS(cmp_slt_d); 2661 break; 2662 case 5: 2663 MIPS_FPU_EMU_INC_STATS(cmp_sult_d); 2664 break; 2665 case 6: 2666 MIPS_FPU_EMU_INC_STATS(cmp_sle_d); 2667 break; 2668 case 7: 2669 MIPS_FPU_EMU_INC_STATS(cmp_sule_d); 2670 break; 2671 } 2672 } else { 2673 switch (cmpop) { 2674 case 1: 2675 MIPS_FPU_EMU_INC_STATS(cmp_sor_d); 2676 break; 2677 case 2: 2678 MIPS_FPU_EMU_INC_STATS(cmp_sune_d); 2679 break; 2680 case 3: 2681 MIPS_FPU_EMU_INC_STATS(cmp_sne_d); 2682 break; 2683 } 2684 } 2685 } 2686 2687 /* fmt is l_fmt for double precision so fix it */ 2688 rfmt = d_fmt; 2689 /* default to false */ 2690 rv.l = 0; 2691 2692 /* CMP.condn.D */ 2693 DPFROMREG(fs, MIPSInst_FS(ir)); 2694 DPFROMREG(ft, MIPSInst_FT(ir)); 2695 2696 /* positive predicates */ 2697 if (!(MIPSInst_FUNC(ir) & PREDICATE_BIT)) { 2698 if (ieee754dp_cmp(fs, ft, 2699 cmptab[cmpop], sig)) 2700 rv.l = -1LL; /* true, all 1s */ 2701 if (sig && 2702 ieee754_cxtest(IEEE754_INVALID_OPERATION)) 2703 rcsr = FPU_CSR_INV_X | FPU_CSR_INV_S; 2704 else 2705 goto copcsr; 2706 } else { 2707 /* negative predicates */ 2708 switch (cmpop) { 2709 case 1: 2710 case 2: 2711 case 3: 2712 if (ieee754dp_cmp(fs, ft, 2713 negative_cmptab[cmpop], 2714 sig)) 2715 rv.l = -1LL; /* true, all 1s */ 2716 if (sig && 2717 ieee754_cxtest(IEEE754_INVALID_OPERATION)) 2718 rcsr = FPU_CSR_INV_X | FPU_CSR_INV_S; 2719 else 2720 goto copcsr; 2721 break; 2722 default: 2723 /* Reserved R6 ops */ 2724 return SIGILL; 2725 } 2726 } 2727 break; 2728 } 2729 } 2730 break; 2731 2732 default: 2733 return SIGILL; 2734 } 2735 2736 /* 2737 * Update the fpu CSR register for this operation. 2738 * If an exception is required, generate a tidy SIGFPE exception, 2739 * without updating the result register. 2740 * Note: cause exception bits do not accumulate, they are rewritten 2741 * for each op; only the flag/sticky bits accumulate. 2742 */ 2743 ctx->fcr31 = (ctx->fcr31 & ~FPU_CSR_ALL_X) | rcsr; 2744 if ((ctx->fcr31 >> 5) & ctx->fcr31 & FPU_CSR_ALL_E) { 2745 /*printk ("SIGFPE: FPU csr = %08x\n",ctx->fcr31); */ 2746 return SIGFPE; 2747 } 2748 2749 /* 2750 * Now we can safely write the result back to the register file. 2751 */ 2752 switch (rfmt) { 2753 case -1: 2754 2755 if (cpu_has_mips_4_5_r) 2756 cbit = fpucondbit[MIPSInst_FD(ir) >> 2]; 2757 else 2758 cbit = FPU_CSR_COND; 2759 if (rv.w) 2760 ctx->fcr31 |= cbit; 2761 else 2762 ctx->fcr31 &= ~cbit; 2763 break; 2764 2765 case d_fmt: 2766 DPTOREG(rv.d, MIPSInst_FD(ir)); 2767 break; 2768 case s_fmt: 2769 SPTOREG(rv.s, MIPSInst_FD(ir)); 2770 break; 2771 case w_fmt: 2772 SITOREG(rv.w, MIPSInst_FD(ir)); 2773 break; 2774 case l_fmt: 2775 if (!cpu_has_mips_3_4_5_64_r2_r6) 2776 return SIGILL; 2777 2778 DITOREG(rv.l, MIPSInst_FD(ir)); 2779 break; 2780 default: 2781 return SIGILL; 2782 } 2783 2784 return 0; 2785 } 2786 2787 /* 2788 * Emulate FPU instructions. 2789 * 2790 * If we use FPU hardware, then we have been typically called to handle 2791 * an unimplemented operation, such as where an operand is a NaN or 2792 * denormalized. In that case exit the emulation loop after a single 2793 * iteration so as to let hardware execute any subsequent instructions. 2794 * 2795 * If we have no FPU hardware or it has been disabled, then continue 2796 * emulating floating-point instructions until one of these conditions 2797 * has occurred: 2798 * 2799 * - a non-FPU instruction has been encountered, 2800 * 2801 * - an attempt to emulate has ended with a signal, 2802 * 2803 * - the ISA mode has been switched. 2804 * 2805 * We need to terminate the emulation loop if we got switched to the 2806 * MIPS16 mode, whether supported or not, so that we do not attempt 2807 * to emulate a MIPS16 instruction as a regular MIPS FPU instruction. 2808 * Similarly if we got switched to the microMIPS mode and only the 2809 * regular MIPS mode is supported, so that we do not attempt to emulate 2810 * a microMIPS instruction as a regular MIPS FPU instruction. Or if 2811 * we got switched to the regular MIPS mode and only the microMIPS mode 2812 * is supported, so that we do not attempt to emulate a regular MIPS 2813 * instruction that should cause an Address Error exception instead. 2814 * For simplicity we always terminate upon an ISA mode switch. 2815 */ 2816 int fpu_emulator_cop1Handler(struct pt_regs *xcp, struct mips_fpu_struct *ctx, 2817 int has_fpu, void __user **fault_addr) 2818 { 2819 unsigned long oldepc, prevepc; 2820 struct mm_decoded_insn dec_insn; 2821 u16 instr[4]; 2822 u16 *instr_ptr; 2823 int sig = 0; 2824 2825 oldepc = xcp->cp0_epc; 2826 do { 2827 prevepc = xcp->cp0_epc; 2828 2829 if (get_isa16_mode(prevepc) && cpu_has_mmips) { 2830 /* 2831 * Get next 2 microMIPS instructions and convert them 2832 * into 32-bit instructions. 2833 */ 2834 if ((get_user(instr[0], (u16 __user *)msk_isa16_mode(xcp->cp0_epc))) || 2835 (get_user(instr[1], (u16 __user *)msk_isa16_mode(xcp->cp0_epc + 2))) || 2836 (get_user(instr[2], (u16 __user *)msk_isa16_mode(xcp->cp0_epc + 4))) || 2837 (get_user(instr[3], (u16 __user *)msk_isa16_mode(xcp->cp0_epc + 6)))) { 2838 MIPS_FPU_EMU_INC_STATS(errors); 2839 return SIGBUS; 2840 } 2841 instr_ptr = instr; 2842 2843 /* Get first instruction. */ 2844 if (mm_insn_16bit(*instr_ptr)) { 2845 /* Duplicate the half-word. */ 2846 dec_insn.insn = (*instr_ptr << 16) | 2847 (*instr_ptr); 2848 /* 16-bit instruction. */ 2849 dec_insn.pc_inc = 2; 2850 instr_ptr += 1; 2851 } else { 2852 dec_insn.insn = (*instr_ptr << 16) | 2853 *(instr_ptr+1); 2854 /* 32-bit instruction. */ 2855 dec_insn.pc_inc = 4; 2856 instr_ptr += 2; 2857 } 2858 /* Get second instruction. */ 2859 if (mm_insn_16bit(*instr_ptr)) { 2860 /* Duplicate the half-word. */ 2861 dec_insn.next_insn = (*instr_ptr << 16) | 2862 (*instr_ptr); 2863 /* 16-bit instruction. */ 2864 dec_insn.next_pc_inc = 2; 2865 } else { 2866 dec_insn.next_insn = (*instr_ptr << 16) | 2867 *(instr_ptr+1); 2868 /* 32-bit instruction. */ 2869 dec_insn.next_pc_inc = 4; 2870 } 2871 dec_insn.micro_mips_mode = 1; 2872 } else { 2873 if ((get_user(dec_insn.insn, 2874 (mips_instruction __user *) xcp->cp0_epc)) || 2875 (get_user(dec_insn.next_insn, 2876 (mips_instruction __user *)(xcp->cp0_epc+4)))) { 2877 MIPS_FPU_EMU_INC_STATS(errors); 2878 return SIGBUS; 2879 } 2880 dec_insn.pc_inc = 4; 2881 dec_insn.next_pc_inc = 4; 2882 dec_insn.micro_mips_mode = 0; 2883 } 2884 2885 if ((dec_insn.insn == 0) || 2886 ((dec_insn.pc_inc == 2) && 2887 ((dec_insn.insn & 0xffff) == MM_NOP16))) 2888 xcp->cp0_epc += dec_insn.pc_inc; /* Skip NOPs */ 2889 else { 2890 /* 2891 * The 'ieee754_csr' is an alias of ctx->fcr31. 2892 * No need to copy ctx->fcr31 to ieee754_csr. 2893 */ 2894 sig = cop1Emulate(xcp, ctx, dec_insn, fault_addr); 2895 } 2896 2897 if (has_fpu) 2898 break; 2899 if (sig) 2900 break; 2901 /* 2902 * We have to check for the ISA bit explicitly here, 2903 * because `get_isa16_mode' may return 0 if support 2904 * for code compression has been globally disabled, 2905 * or otherwise we may produce the wrong signal or 2906 * even proceed successfully where we must not. 2907 */ 2908 if ((xcp->cp0_epc ^ prevepc) & 0x1) 2909 break; 2910 2911 cond_resched(); 2912 } while (xcp->cp0_epc > prevepc); 2913 2914 /* SIGILL indicates a non-fpu instruction */ 2915 if (sig == SIGILL && xcp->cp0_epc != oldepc) 2916 /* but if EPC has advanced, then ignore it */ 2917 sig = 0; 2918 2919 return sig; 2920 } 2921