1 /* 2 * cp1emu.c: a MIPS coprocessor 1 (FPU) instruction emulator 3 * 4 * MIPS floating point support 5 * Copyright (C) 1994-2000 Algorithmics Ltd. 6 * 7 * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com 8 * Copyright (C) 2000 MIPS Technologies, Inc. 9 * 10 * This program is free software; you can distribute it and/or modify it 11 * under the terms of the GNU General Public License (Version 2) as 12 * published by the Free Software Foundation. 13 * 14 * This program is distributed in the hope it will be useful, but WITHOUT 15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 17 * for more details. 18 * 19 * You should have received a copy of the GNU General Public License along 20 * with this program; if not, write to the Free Software Foundation, Inc., 21 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. 22 * 23 * A complete emulator for MIPS coprocessor 1 instructions. This is 24 * required for #float(switch) or #float(trap), where it catches all 25 * COP1 instructions via the "CoProcessor Unusable" exception. 26 * 27 * More surprisingly it is also required for #float(ieee), to help out 28 * the hardware FPU at the boundaries of the IEEE-754 representation 29 * (denormalised values, infinities, underflow, etc). It is made 30 * quite nasty because emulation of some non-COP1 instructions is 31 * required, e.g. in branch delay slots. 32 * 33 * Note if you know that you won't have an FPU, then you'll get much 34 * better performance by compiling with -msoft-float! 35 */ 36 #include <linux/sched.h> 37 #include <linux/debugfs.h> 38 #include <linux/percpu-defs.h> 39 #include <linux/perf_event.h> 40 41 #include <asm/branch.h> 42 #include <asm/inst.h> 43 #include <asm/ptrace.h> 44 #include <asm/signal.h> 45 #include <asm/uaccess.h> 46 47 #include <asm/cpu-info.h> 48 #include <asm/processor.h> 49 #include <asm/fpu_emulator.h> 50 #include <asm/fpu.h> 51 #include <asm/mips-r2-to-r6-emul.h> 52 53 #include "ieee754.h" 54 55 /* Function which emulates a floating point instruction. */ 56 57 static int fpu_emu(struct pt_regs *, struct mips_fpu_struct *, 58 mips_instruction); 59 60 static int fpux_emu(struct pt_regs *, 61 struct mips_fpu_struct *, mips_instruction, void *__user *); 62 63 /* Control registers */ 64 65 #define FPCREG_RID 0 /* $0 = revision id */ 66 #define FPCREG_FCCR 25 /* $25 = fccr */ 67 #define FPCREG_FEXR 26 /* $26 = fexr */ 68 #define FPCREG_FENR 28 /* $28 = fenr */ 69 #define FPCREG_CSR 31 /* $31 = csr */ 70 71 /* convert condition code register number to csr bit */ 72 const unsigned int fpucondbit[8] = { 73 FPU_CSR_COND, 74 FPU_CSR_COND1, 75 FPU_CSR_COND2, 76 FPU_CSR_COND3, 77 FPU_CSR_COND4, 78 FPU_CSR_COND5, 79 FPU_CSR_COND6, 80 FPU_CSR_COND7 81 }; 82 83 /* (microMIPS) Convert certain microMIPS instructions to MIPS32 format. */ 84 static const int sd_format[] = {16, 17, 0, 0, 0, 0, 0, 0}; 85 static const int sdps_format[] = {16, 17, 22, 0, 0, 0, 0, 0}; 86 static const int dwl_format[] = {17, 20, 21, 0, 0, 0, 0, 0}; 87 static const int swl_format[] = {16, 20, 21, 0, 0, 0, 0, 0}; 88 89 /* 90 * This functions translates a 32-bit microMIPS instruction 91 * into a 32-bit MIPS32 instruction. Returns 0 on success 92 * and SIGILL otherwise. 93 */ 94 static int microMIPS32_to_MIPS32(union mips_instruction *insn_ptr) 95 { 96 union mips_instruction insn = *insn_ptr; 97 union mips_instruction mips32_insn = insn; 98 int func, fmt, op; 99 100 switch (insn.mm_i_format.opcode) { 101 case mm_ldc132_op: 102 mips32_insn.mm_i_format.opcode = ldc1_op; 103 mips32_insn.mm_i_format.rt = insn.mm_i_format.rs; 104 mips32_insn.mm_i_format.rs = insn.mm_i_format.rt; 105 break; 106 case mm_lwc132_op: 107 mips32_insn.mm_i_format.opcode = lwc1_op; 108 mips32_insn.mm_i_format.rt = insn.mm_i_format.rs; 109 mips32_insn.mm_i_format.rs = insn.mm_i_format.rt; 110 break; 111 case mm_sdc132_op: 112 mips32_insn.mm_i_format.opcode = sdc1_op; 113 mips32_insn.mm_i_format.rt = insn.mm_i_format.rs; 114 mips32_insn.mm_i_format.rs = insn.mm_i_format.rt; 115 break; 116 case mm_swc132_op: 117 mips32_insn.mm_i_format.opcode = swc1_op; 118 mips32_insn.mm_i_format.rt = insn.mm_i_format.rs; 119 mips32_insn.mm_i_format.rs = insn.mm_i_format.rt; 120 break; 121 case mm_pool32i_op: 122 /* NOTE: offset is << by 1 if in microMIPS mode. */ 123 if ((insn.mm_i_format.rt == mm_bc1f_op) || 124 (insn.mm_i_format.rt == mm_bc1t_op)) { 125 mips32_insn.fb_format.opcode = cop1_op; 126 mips32_insn.fb_format.bc = bc_op; 127 mips32_insn.fb_format.flag = 128 (insn.mm_i_format.rt == mm_bc1t_op) ? 1 : 0; 129 } else 130 return SIGILL; 131 break; 132 case mm_pool32f_op: 133 switch (insn.mm_fp0_format.func) { 134 case mm_32f_01_op: 135 case mm_32f_11_op: 136 case mm_32f_02_op: 137 case mm_32f_12_op: 138 case mm_32f_41_op: 139 case mm_32f_51_op: 140 case mm_32f_42_op: 141 case mm_32f_52_op: 142 op = insn.mm_fp0_format.func; 143 if (op == mm_32f_01_op) 144 func = madd_s_op; 145 else if (op == mm_32f_11_op) 146 func = madd_d_op; 147 else if (op == mm_32f_02_op) 148 func = nmadd_s_op; 149 else if (op == mm_32f_12_op) 150 func = nmadd_d_op; 151 else if (op == mm_32f_41_op) 152 func = msub_s_op; 153 else if (op == mm_32f_51_op) 154 func = msub_d_op; 155 else if (op == mm_32f_42_op) 156 func = nmsub_s_op; 157 else 158 func = nmsub_d_op; 159 mips32_insn.fp6_format.opcode = cop1x_op; 160 mips32_insn.fp6_format.fr = insn.mm_fp6_format.fr; 161 mips32_insn.fp6_format.ft = insn.mm_fp6_format.ft; 162 mips32_insn.fp6_format.fs = insn.mm_fp6_format.fs; 163 mips32_insn.fp6_format.fd = insn.mm_fp6_format.fd; 164 mips32_insn.fp6_format.func = func; 165 break; 166 case mm_32f_10_op: 167 func = -1; /* Invalid */ 168 op = insn.mm_fp5_format.op & 0x7; 169 if (op == mm_ldxc1_op) 170 func = ldxc1_op; 171 else if (op == mm_sdxc1_op) 172 func = sdxc1_op; 173 else if (op == mm_lwxc1_op) 174 func = lwxc1_op; 175 else if (op == mm_swxc1_op) 176 func = swxc1_op; 177 178 if (func != -1) { 179 mips32_insn.r_format.opcode = cop1x_op; 180 mips32_insn.r_format.rs = 181 insn.mm_fp5_format.base; 182 mips32_insn.r_format.rt = 183 insn.mm_fp5_format.index; 184 mips32_insn.r_format.rd = 0; 185 mips32_insn.r_format.re = insn.mm_fp5_format.fd; 186 mips32_insn.r_format.func = func; 187 } else 188 return SIGILL; 189 break; 190 case mm_32f_40_op: 191 op = -1; /* Invalid */ 192 if (insn.mm_fp2_format.op == mm_fmovt_op) 193 op = 1; 194 else if (insn.mm_fp2_format.op == mm_fmovf_op) 195 op = 0; 196 if (op != -1) { 197 mips32_insn.fp0_format.opcode = cop1_op; 198 mips32_insn.fp0_format.fmt = 199 sdps_format[insn.mm_fp2_format.fmt]; 200 mips32_insn.fp0_format.ft = 201 (insn.mm_fp2_format.cc<<2) + op; 202 mips32_insn.fp0_format.fs = 203 insn.mm_fp2_format.fs; 204 mips32_insn.fp0_format.fd = 205 insn.mm_fp2_format.fd; 206 mips32_insn.fp0_format.func = fmovc_op; 207 } else 208 return SIGILL; 209 break; 210 case mm_32f_60_op: 211 func = -1; /* Invalid */ 212 if (insn.mm_fp0_format.op == mm_fadd_op) 213 func = fadd_op; 214 else if (insn.mm_fp0_format.op == mm_fsub_op) 215 func = fsub_op; 216 else if (insn.mm_fp0_format.op == mm_fmul_op) 217 func = fmul_op; 218 else if (insn.mm_fp0_format.op == mm_fdiv_op) 219 func = fdiv_op; 220 if (func != -1) { 221 mips32_insn.fp0_format.opcode = cop1_op; 222 mips32_insn.fp0_format.fmt = 223 sdps_format[insn.mm_fp0_format.fmt]; 224 mips32_insn.fp0_format.ft = 225 insn.mm_fp0_format.ft; 226 mips32_insn.fp0_format.fs = 227 insn.mm_fp0_format.fs; 228 mips32_insn.fp0_format.fd = 229 insn.mm_fp0_format.fd; 230 mips32_insn.fp0_format.func = func; 231 } else 232 return SIGILL; 233 break; 234 case mm_32f_70_op: 235 func = -1; /* Invalid */ 236 if (insn.mm_fp0_format.op == mm_fmovn_op) 237 func = fmovn_op; 238 else if (insn.mm_fp0_format.op == mm_fmovz_op) 239 func = fmovz_op; 240 if (func != -1) { 241 mips32_insn.fp0_format.opcode = cop1_op; 242 mips32_insn.fp0_format.fmt = 243 sdps_format[insn.mm_fp0_format.fmt]; 244 mips32_insn.fp0_format.ft = 245 insn.mm_fp0_format.ft; 246 mips32_insn.fp0_format.fs = 247 insn.mm_fp0_format.fs; 248 mips32_insn.fp0_format.fd = 249 insn.mm_fp0_format.fd; 250 mips32_insn.fp0_format.func = func; 251 } else 252 return SIGILL; 253 break; 254 case mm_32f_73_op: /* POOL32FXF */ 255 switch (insn.mm_fp1_format.op) { 256 case mm_movf0_op: 257 case mm_movf1_op: 258 case mm_movt0_op: 259 case mm_movt1_op: 260 if ((insn.mm_fp1_format.op & 0x7f) == 261 mm_movf0_op) 262 op = 0; 263 else 264 op = 1; 265 mips32_insn.r_format.opcode = spec_op; 266 mips32_insn.r_format.rs = insn.mm_fp4_format.fs; 267 mips32_insn.r_format.rt = 268 (insn.mm_fp4_format.cc << 2) + op; 269 mips32_insn.r_format.rd = insn.mm_fp4_format.rt; 270 mips32_insn.r_format.re = 0; 271 mips32_insn.r_format.func = movc_op; 272 break; 273 case mm_fcvtd0_op: 274 case mm_fcvtd1_op: 275 case mm_fcvts0_op: 276 case mm_fcvts1_op: 277 if ((insn.mm_fp1_format.op & 0x7f) == 278 mm_fcvtd0_op) { 279 func = fcvtd_op; 280 fmt = swl_format[insn.mm_fp3_format.fmt]; 281 } else { 282 func = fcvts_op; 283 fmt = dwl_format[insn.mm_fp3_format.fmt]; 284 } 285 mips32_insn.fp0_format.opcode = cop1_op; 286 mips32_insn.fp0_format.fmt = fmt; 287 mips32_insn.fp0_format.ft = 0; 288 mips32_insn.fp0_format.fs = 289 insn.mm_fp3_format.fs; 290 mips32_insn.fp0_format.fd = 291 insn.mm_fp3_format.rt; 292 mips32_insn.fp0_format.func = func; 293 break; 294 case mm_fmov0_op: 295 case mm_fmov1_op: 296 case mm_fabs0_op: 297 case mm_fabs1_op: 298 case mm_fneg0_op: 299 case mm_fneg1_op: 300 if ((insn.mm_fp1_format.op & 0x7f) == 301 mm_fmov0_op) 302 func = fmov_op; 303 else if ((insn.mm_fp1_format.op & 0x7f) == 304 mm_fabs0_op) 305 func = fabs_op; 306 else 307 func = fneg_op; 308 mips32_insn.fp0_format.opcode = cop1_op; 309 mips32_insn.fp0_format.fmt = 310 sdps_format[insn.mm_fp3_format.fmt]; 311 mips32_insn.fp0_format.ft = 0; 312 mips32_insn.fp0_format.fs = 313 insn.mm_fp3_format.fs; 314 mips32_insn.fp0_format.fd = 315 insn.mm_fp3_format.rt; 316 mips32_insn.fp0_format.func = func; 317 break; 318 case mm_ffloorl_op: 319 case mm_ffloorw_op: 320 case mm_fceill_op: 321 case mm_fceilw_op: 322 case mm_ftruncl_op: 323 case mm_ftruncw_op: 324 case mm_froundl_op: 325 case mm_froundw_op: 326 case mm_fcvtl_op: 327 case mm_fcvtw_op: 328 if (insn.mm_fp1_format.op == mm_ffloorl_op) 329 func = ffloorl_op; 330 else if (insn.mm_fp1_format.op == mm_ffloorw_op) 331 func = ffloor_op; 332 else if (insn.mm_fp1_format.op == mm_fceill_op) 333 func = fceill_op; 334 else if (insn.mm_fp1_format.op == mm_fceilw_op) 335 func = fceil_op; 336 else if (insn.mm_fp1_format.op == mm_ftruncl_op) 337 func = ftruncl_op; 338 else if (insn.mm_fp1_format.op == mm_ftruncw_op) 339 func = ftrunc_op; 340 else if (insn.mm_fp1_format.op == mm_froundl_op) 341 func = froundl_op; 342 else if (insn.mm_fp1_format.op == mm_froundw_op) 343 func = fround_op; 344 else if (insn.mm_fp1_format.op == mm_fcvtl_op) 345 func = fcvtl_op; 346 else 347 func = fcvtw_op; 348 mips32_insn.fp0_format.opcode = cop1_op; 349 mips32_insn.fp0_format.fmt = 350 sd_format[insn.mm_fp1_format.fmt]; 351 mips32_insn.fp0_format.ft = 0; 352 mips32_insn.fp0_format.fs = 353 insn.mm_fp1_format.fs; 354 mips32_insn.fp0_format.fd = 355 insn.mm_fp1_format.rt; 356 mips32_insn.fp0_format.func = func; 357 break; 358 case mm_frsqrt_op: 359 case mm_fsqrt_op: 360 case mm_frecip_op: 361 if (insn.mm_fp1_format.op == mm_frsqrt_op) 362 func = frsqrt_op; 363 else if (insn.mm_fp1_format.op == mm_fsqrt_op) 364 func = fsqrt_op; 365 else 366 func = frecip_op; 367 mips32_insn.fp0_format.opcode = cop1_op; 368 mips32_insn.fp0_format.fmt = 369 sdps_format[insn.mm_fp1_format.fmt]; 370 mips32_insn.fp0_format.ft = 0; 371 mips32_insn.fp0_format.fs = 372 insn.mm_fp1_format.fs; 373 mips32_insn.fp0_format.fd = 374 insn.mm_fp1_format.rt; 375 mips32_insn.fp0_format.func = func; 376 break; 377 case mm_mfc1_op: 378 case mm_mtc1_op: 379 case mm_cfc1_op: 380 case mm_ctc1_op: 381 case mm_mfhc1_op: 382 case mm_mthc1_op: 383 if (insn.mm_fp1_format.op == mm_mfc1_op) 384 op = mfc_op; 385 else if (insn.mm_fp1_format.op == mm_mtc1_op) 386 op = mtc_op; 387 else if (insn.mm_fp1_format.op == mm_cfc1_op) 388 op = cfc_op; 389 else if (insn.mm_fp1_format.op == mm_ctc1_op) 390 op = ctc_op; 391 else if (insn.mm_fp1_format.op == mm_mfhc1_op) 392 op = mfhc_op; 393 else 394 op = mthc_op; 395 mips32_insn.fp1_format.opcode = cop1_op; 396 mips32_insn.fp1_format.op = op; 397 mips32_insn.fp1_format.rt = 398 insn.mm_fp1_format.rt; 399 mips32_insn.fp1_format.fs = 400 insn.mm_fp1_format.fs; 401 mips32_insn.fp1_format.fd = 0; 402 mips32_insn.fp1_format.func = 0; 403 break; 404 default: 405 return SIGILL; 406 } 407 break; 408 case mm_32f_74_op: /* c.cond.fmt */ 409 mips32_insn.fp0_format.opcode = cop1_op; 410 mips32_insn.fp0_format.fmt = 411 sdps_format[insn.mm_fp4_format.fmt]; 412 mips32_insn.fp0_format.ft = insn.mm_fp4_format.rt; 413 mips32_insn.fp0_format.fs = insn.mm_fp4_format.fs; 414 mips32_insn.fp0_format.fd = insn.mm_fp4_format.cc << 2; 415 mips32_insn.fp0_format.func = 416 insn.mm_fp4_format.cond | MM_MIPS32_COND_FC; 417 break; 418 default: 419 return SIGILL; 420 } 421 break; 422 default: 423 return SIGILL; 424 } 425 426 *insn_ptr = mips32_insn; 427 return 0; 428 } 429 430 /* 431 * Redundant with logic already in kernel/branch.c, 432 * embedded in compute_return_epc. At some point, 433 * a single subroutine should be used across both 434 * modules. 435 */ 436 int isBranchInstr(struct pt_regs *regs, struct mm_decoded_insn dec_insn, 437 unsigned long *contpc) 438 { 439 union mips_instruction insn = (union mips_instruction)dec_insn.insn; 440 unsigned int fcr31; 441 unsigned int bit = 0; 442 443 switch (insn.i_format.opcode) { 444 case spec_op: 445 switch (insn.r_format.func) { 446 case jalr_op: 447 if (insn.r_format.rd != 0) { 448 regs->regs[insn.r_format.rd] = 449 regs->cp0_epc + dec_insn.pc_inc + 450 dec_insn.next_pc_inc; 451 } 452 /* Fall through */ 453 case jr_op: 454 /* For R6, JR already emulated in jalr_op */ 455 if (NO_R6EMU && insn.r_format.func == jr_op) 456 break; 457 *contpc = regs->regs[insn.r_format.rs]; 458 return 1; 459 } 460 break; 461 case bcond_op: 462 switch (insn.i_format.rt) { 463 case bltzal_op: 464 case bltzall_op: 465 if (NO_R6EMU && (insn.i_format.rs || 466 insn.i_format.rt == bltzall_op)) 467 break; 468 469 regs->regs[31] = regs->cp0_epc + 470 dec_insn.pc_inc + 471 dec_insn.next_pc_inc; 472 /* Fall through */ 473 case bltzl_op: 474 if (NO_R6EMU) 475 break; 476 case bltz_op: 477 if ((long)regs->regs[insn.i_format.rs] < 0) 478 *contpc = regs->cp0_epc + 479 dec_insn.pc_inc + 480 (insn.i_format.simmediate << 2); 481 else 482 *contpc = regs->cp0_epc + 483 dec_insn.pc_inc + 484 dec_insn.next_pc_inc; 485 return 1; 486 case bgezal_op: 487 case bgezall_op: 488 if (NO_R6EMU && (insn.i_format.rs || 489 insn.i_format.rt == bgezall_op)) 490 break; 491 492 regs->regs[31] = regs->cp0_epc + 493 dec_insn.pc_inc + 494 dec_insn.next_pc_inc; 495 /* Fall through */ 496 case bgezl_op: 497 if (NO_R6EMU) 498 break; 499 case bgez_op: 500 if ((long)regs->regs[insn.i_format.rs] >= 0) 501 *contpc = regs->cp0_epc + 502 dec_insn.pc_inc + 503 (insn.i_format.simmediate << 2); 504 else 505 *contpc = regs->cp0_epc + 506 dec_insn.pc_inc + 507 dec_insn.next_pc_inc; 508 return 1; 509 } 510 break; 511 case jalx_op: 512 set_isa16_mode(bit); 513 case jal_op: 514 regs->regs[31] = regs->cp0_epc + 515 dec_insn.pc_inc + 516 dec_insn.next_pc_inc; 517 /* Fall through */ 518 case j_op: 519 *contpc = regs->cp0_epc + dec_insn.pc_inc; 520 *contpc >>= 28; 521 *contpc <<= 28; 522 *contpc |= (insn.j_format.target << 2); 523 /* Set microMIPS mode bit: XOR for jalx. */ 524 *contpc ^= bit; 525 return 1; 526 case beql_op: 527 if (NO_R6EMU) 528 break; 529 case beq_op: 530 if (regs->regs[insn.i_format.rs] == 531 regs->regs[insn.i_format.rt]) 532 *contpc = regs->cp0_epc + 533 dec_insn.pc_inc + 534 (insn.i_format.simmediate << 2); 535 else 536 *contpc = regs->cp0_epc + 537 dec_insn.pc_inc + 538 dec_insn.next_pc_inc; 539 return 1; 540 case bnel_op: 541 if (NO_R6EMU) 542 break; 543 case bne_op: 544 if (regs->regs[insn.i_format.rs] != 545 regs->regs[insn.i_format.rt]) 546 *contpc = regs->cp0_epc + 547 dec_insn.pc_inc + 548 (insn.i_format.simmediate << 2); 549 else 550 *contpc = regs->cp0_epc + 551 dec_insn.pc_inc + 552 dec_insn.next_pc_inc; 553 return 1; 554 case blezl_op: 555 if (!insn.i_format.rt && NO_R6EMU) 556 break; 557 case blez_op: 558 559 /* 560 * Compact branches for R6 for the 561 * blez and blezl opcodes. 562 * BLEZ | rs = 0 | rt != 0 == BLEZALC 563 * BLEZ | rs = rt != 0 == BGEZALC 564 * BLEZ | rs != 0 | rt != 0 == BGEUC 565 * BLEZL | rs = 0 | rt != 0 == BLEZC 566 * BLEZL | rs = rt != 0 == BGEZC 567 * BLEZL | rs != 0 | rt != 0 == BGEC 568 * 569 * For real BLEZ{,L}, rt is always 0. 570 */ 571 if (cpu_has_mips_r6 && insn.i_format.rt) { 572 if ((insn.i_format.opcode == blez_op) && 573 ((!insn.i_format.rs && insn.i_format.rt) || 574 (insn.i_format.rs == insn.i_format.rt))) 575 regs->regs[31] = regs->cp0_epc + 576 dec_insn.pc_inc; 577 *contpc = regs->cp0_epc + dec_insn.pc_inc + 578 dec_insn.next_pc_inc; 579 580 return 1; 581 } 582 if ((long)regs->regs[insn.i_format.rs] <= 0) 583 *contpc = regs->cp0_epc + 584 dec_insn.pc_inc + 585 (insn.i_format.simmediate << 2); 586 else 587 *contpc = regs->cp0_epc + 588 dec_insn.pc_inc + 589 dec_insn.next_pc_inc; 590 return 1; 591 case bgtzl_op: 592 if (!insn.i_format.rt && NO_R6EMU) 593 break; 594 case bgtz_op: 595 /* 596 * Compact branches for R6 for the 597 * bgtz and bgtzl opcodes. 598 * BGTZ | rs = 0 | rt != 0 == BGTZALC 599 * BGTZ | rs = rt != 0 == BLTZALC 600 * BGTZ | rs != 0 | rt != 0 == BLTUC 601 * BGTZL | rs = 0 | rt != 0 == BGTZC 602 * BGTZL | rs = rt != 0 == BLTZC 603 * BGTZL | rs != 0 | rt != 0 == BLTC 604 * 605 * *ZALC varint for BGTZ &&& rt != 0 606 * For real GTZ{,L}, rt is always 0. 607 */ 608 if (cpu_has_mips_r6 && insn.i_format.rt) { 609 if ((insn.i_format.opcode == blez_op) && 610 ((!insn.i_format.rs && insn.i_format.rt) || 611 (insn.i_format.rs == insn.i_format.rt))) 612 regs->regs[31] = regs->cp0_epc + 613 dec_insn.pc_inc; 614 *contpc = regs->cp0_epc + dec_insn.pc_inc + 615 dec_insn.next_pc_inc; 616 617 return 1; 618 } 619 620 if ((long)regs->regs[insn.i_format.rs] > 0) 621 *contpc = regs->cp0_epc + 622 dec_insn.pc_inc + 623 (insn.i_format.simmediate << 2); 624 else 625 *contpc = regs->cp0_epc + 626 dec_insn.pc_inc + 627 dec_insn.next_pc_inc; 628 return 1; 629 case pop10_op: 630 case pop30_op: 631 if (!cpu_has_mips_r6) 632 break; 633 if (insn.i_format.rt && !insn.i_format.rs) 634 regs->regs[31] = regs->cp0_epc + 4; 635 *contpc = regs->cp0_epc + dec_insn.pc_inc + 636 dec_insn.next_pc_inc; 637 638 return 1; 639 #ifdef CONFIG_CPU_CAVIUM_OCTEON 640 case lwc2_op: /* This is bbit0 on Octeon */ 641 if ((regs->regs[insn.i_format.rs] & (1ull<<insn.i_format.rt)) == 0) 642 *contpc = regs->cp0_epc + 4 + (insn.i_format.simmediate << 2); 643 else 644 *contpc = regs->cp0_epc + 8; 645 return 1; 646 case ldc2_op: /* This is bbit032 on Octeon */ 647 if ((regs->regs[insn.i_format.rs] & (1ull<<(insn.i_format.rt + 32))) == 0) 648 *contpc = regs->cp0_epc + 4 + (insn.i_format.simmediate << 2); 649 else 650 *contpc = regs->cp0_epc + 8; 651 return 1; 652 case swc2_op: /* This is bbit1 on Octeon */ 653 if (regs->regs[insn.i_format.rs] & (1ull<<insn.i_format.rt)) 654 *contpc = regs->cp0_epc + 4 + (insn.i_format.simmediate << 2); 655 else 656 *contpc = regs->cp0_epc + 8; 657 return 1; 658 case sdc2_op: /* This is bbit132 on Octeon */ 659 if (regs->regs[insn.i_format.rs] & (1ull<<(insn.i_format.rt + 32))) 660 *contpc = regs->cp0_epc + 4 + (insn.i_format.simmediate << 2); 661 else 662 *contpc = regs->cp0_epc + 8; 663 return 1; 664 #else 665 case bc6_op: 666 /* 667 * Only valid for MIPS R6 but we can still end up 668 * here from a broken userland so just tell emulator 669 * this is not a branch and let it break later on. 670 */ 671 if (!cpu_has_mips_r6) 672 break; 673 *contpc = regs->cp0_epc + dec_insn.pc_inc + 674 dec_insn.next_pc_inc; 675 676 return 1; 677 case balc6_op: 678 if (!cpu_has_mips_r6) 679 break; 680 regs->regs[31] = regs->cp0_epc + 4; 681 *contpc = regs->cp0_epc + dec_insn.pc_inc + 682 dec_insn.next_pc_inc; 683 684 return 1; 685 case pop66_op: 686 if (!cpu_has_mips_r6) 687 break; 688 *contpc = regs->cp0_epc + dec_insn.pc_inc + 689 dec_insn.next_pc_inc; 690 691 return 1; 692 case pop76_op: 693 if (!cpu_has_mips_r6) 694 break; 695 if (!insn.i_format.rs) 696 regs->regs[31] = regs->cp0_epc + 4; 697 *contpc = regs->cp0_epc + dec_insn.pc_inc + 698 dec_insn.next_pc_inc; 699 700 return 1; 701 #endif 702 case cop0_op: 703 case cop1_op: 704 /* Need to check for R6 bc1nez and bc1eqz branches */ 705 if (cpu_has_mips_r6 && 706 ((insn.i_format.rs == bc1eqz_op) || 707 (insn.i_format.rs == bc1nez_op))) { 708 bit = 0; 709 switch (insn.i_format.rs) { 710 case bc1eqz_op: 711 if (get_fpr32(¤t->thread.fpu.fpr[insn.i_format.rt], 0) & 0x1) 712 bit = 1; 713 break; 714 case bc1nez_op: 715 if (!(get_fpr32(¤t->thread.fpu.fpr[insn.i_format.rt], 0) & 0x1)) 716 bit = 1; 717 break; 718 } 719 if (bit) 720 *contpc = regs->cp0_epc + 721 dec_insn.pc_inc + 722 (insn.i_format.simmediate << 2); 723 else 724 *contpc = regs->cp0_epc + 725 dec_insn.pc_inc + 726 dec_insn.next_pc_inc; 727 728 return 1; 729 } 730 /* R2/R6 compatible cop1 instruction. Fall through */ 731 case cop2_op: 732 case cop1x_op: 733 if (insn.i_format.rs == bc_op) { 734 preempt_disable(); 735 if (is_fpu_owner()) 736 fcr31 = read_32bit_cp1_register(CP1_STATUS); 737 else 738 fcr31 = current->thread.fpu.fcr31; 739 preempt_enable(); 740 741 bit = (insn.i_format.rt >> 2); 742 bit += (bit != 0); 743 bit += 23; 744 switch (insn.i_format.rt & 3) { 745 case 0: /* bc1f */ 746 case 2: /* bc1fl */ 747 if (~fcr31 & (1 << bit)) 748 *contpc = regs->cp0_epc + 749 dec_insn.pc_inc + 750 (insn.i_format.simmediate << 2); 751 else 752 *contpc = regs->cp0_epc + 753 dec_insn.pc_inc + 754 dec_insn.next_pc_inc; 755 return 1; 756 case 1: /* bc1t */ 757 case 3: /* bc1tl */ 758 if (fcr31 & (1 << bit)) 759 *contpc = regs->cp0_epc + 760 dec_insn.pc_inc + 761 (insn.i_format.simmediate << 2); 762 else 763 *contpc = regs->cp0_epc + 764 dec_insn.pc_inc + 765 dec_insn.next_pc_inc; 766 return 1; 767 } 768 } 769 break; 770 } 771 return 0; 772 } 773 774 /* 775 * In the Linux kernel, we support selection of FPR format on the 776 * basis of the Status.FR bit. If an FPU is not present, the FR bit 777 * is hardwired to zero, which would imply a 32-bit FPU even for 778 * 64-bit CPUs so we rather look at TIF_32BIT_FPREGS. 779 * FPU emu is slow and bulky and optimizing this function offers fairly 780 * sizeable benefits so we try to be clever and make this function return 781 * a constant whenever possible, that is on 64-bit kernels without O32 782 * compatibility enabled and on 32-bit without 64-bit FPU support. 783 */ 784 static inline int cop1_64bit(struct pt_regs *xcp) 785 { 786 if (IS_ENABLED(CONFIG_64BIT) && !IS_ENABLED(CONFIG_MIPS32_O32)) 787 return 1; 788 else if (IS_ENABLED(CONFIG_32BIT) && 789 !IS_ENABLED(CONFIG_MIPS_O32_FP64_SUPPORT)) 790 return 0; 791 792 return !test_thread_flag(TIF_32BIT_FPREGS); 793 } 794 795 static inline bool hybrid_fprs(void) 796 { 797 return test_thread_flag(TIF_HYBRID_FPREGS); 798 } 799 800 #define SIFROMREG(si, x) \ 801 do { \ 802 if (cop1_64bit(xcp) && !hybrid_fprs()) \ 803 (si) = (int)get_fpr32(&ctx->fpr[x], 0); \ 804 else \ 805 (si) = (int)get_fpr32(&ctx->fpr[(x) & ~1], (x) & 1); \ 806 } while (0) 807 808 #define SITOREG(si, x) \ 809 do { \ 810 if (cop1_64bit(xcp) && !hybrid_fprs()) { \ 811 unsigned i; \ 812 set_fpr32(&ctx->fpr[x], 0, si); \ 813 for (i = 1; i < ARRAY_SIZE(ctx->fpr[x].val32); i++) \ 814 set_fpr32(&ctx->fpr[x], i, 0); \ 815 } else { \ 816 set_fpr32(&ctx->fpr[(x) & ~1], (x) & 1, si); \ 817 } \ 818 } while (0) 819 820 #define SIFROMHREG(si, x) ((si) = (int)get_fpr32(&ctx->fpr[x], 1)) 821 822 #define SITOHREG(si, x) \ 823 do { \ 824 unsigned i; \ 825 set_fpr32(&ctx->fpr[x], 1, si); \ 826 for (i = 2; i < ARRAY_SIZE(ctx->fpr[x].val32); i++) \ 827 set_fpr32(&ctx->fpr[x], i, 0); \ 828 } while (0) 829 830 #define DIFROMREG(di, x) \ 831 ((di) = get_fpr64(&ctx->fpr[(x) & ~(cop1_64bit(xcp) == 0)], 0)) 832 833 #define DITOREG(di, x) \ 834 do { \ 835 unsigned fpr, i; \ 836 fpr = (x) & ~(cop1_64bit(xcp) == 0); \ 837 set_fpr64(&ctx->fpr[fpr], 0, di); \ 838 for (i = 1; i < ARRAY_SIZE(ctx->fpr[x].val64); i++) \ 839 set_fpr64(&ctx->fpr[fpr], i, 0); \ 840 } while (0) 841 842 #define SPFROMREG(sp, x) SIFROMREG((sp).bits, x) 843 #define SPTOREG(sp, x) SITOREG((sp).bits, x) 844 #define DPFROMREG(dp, x) DIFROMREG((dp).bits, x) 845 #define DPTOREG(dp, x) DITOREG((dp).bits, x) 846 847 /* 848 * Emulate a CFC1 instruction. 849 */ 850 static inline void cop1_cfc(struct pt_regs *xcp, struct mips_fpu_struct *ctx, 851 mips_instruction ir) 852 { 853 u32 fcr31 = ctx->fcr31; 854 u32 value = 0; 855 856 switch (MIPSInst_RD(ir)) { 857 case FPCREG_CSR: 858 value = fcr31; 859 pr_debug("%p gpr[%d]<-csr=%08x\n", 860 (void *)xcp->cp0_epc, MIPSInst_RT(ir), value); 861 break; 862 863 case FPCREG_FENR: 864 if (!cpu_has_mips_r) 865 break; 866 value = (fcr31 >> (FPU_CSR_FS_S - MIPS_FENR_FS_S)) & 867 MIPS_FENR_FS; 868 value |= fcr31 & (FPU_CSR_ALL_E | FPU_CSR_RM); 869 pr_debug("%p gpr[%d]<-enr=%08x\n", 870 (void *)xcp->cp0_epc, MIPSInst_RT(ir), value); 871 break; 872 873 case FPCREG_FEXR: 874 if (!cpu_has_mips_r) 875 break; 876 value = fcr31 & (FPU_CSR_ALL_X | FPU_CSR_ALL_S); 877 pr_debug("%p gpr[%d]<-exr=%08x\n", 878 (void *)xcp->cp0_epc, MIPSInst_RT(ir), value); 879 break; 880 881 case FPCREG_FCCR: 882 if (!cpu_has_mips_r) 883 break; 884 value = (fcr31 >> (FPU_CSR_COND_S - MIPS_FCCR_COND0_S)) & 885 MIPS_FCCR_COND0; 886 value |= (fcr31 >> (FPU_CSR_COND1_S - MIPS_FCCR_COND1_S)) & 887 (MIPS_FCCR_CONDX & ~MIPS_FCCR_COND0); 888 pr_debug("%p gpr[%d]<-ccr=%08x\n", 889 (void *)xcp->cp0_epc, MIPSInst_RT(ir), value); 890 break; 891 892 case FPCREG_RID: 893 value = boot_cpu_data.fpu_id; 894 break; 895 896 default: 897 break; 898 } 899 900 if (MIPSInst_RT(ir)) 901 xcp->regs[MIPSInst_RT(ir)] = value; 902 } 903 904 /* 905 * Emulate a CTC1 instruction. 906 */ 907 static inline void cop1_ctc(struct pt_regs *xcp, struct mips_fpu_struct *ctx, 908 mips_instruction ir) 909 { 910 u32 fcr31 = ctx->fcr31; 911 u32 value; 912 u32 mask; 913 914 if (MIPSInst_RT(ir) == 0) 915 value = 0; 916 else 917 value = xcp->regs[MIPSInst_RT(ir)]; 918 919 switch (MIPSInst_RD(ir)) { 920 case FPCREG_CSR: 921 pr_debug("%p gpr[%d]->csr=%08x\n", 922 (void *)xcp->cp0_epc, MIPSInst_RT(ir), value); 923 924 /* Preserve read-only bits. */ 925 mask = boot_cpu_data.fpu_msk31; 926 fcr31 = (value & ~mask) | (fcr31 & mask); 927 break; 928 929 case FPCREG_FENR: 930 if (!cpu_has_mips_r) 931 break; 932 pr_debug("%p gpr[%d]->enr=%08x\n", 933 (void *)xcp->cp0_epc, MIPSInst_RT(ir), value); 934 fcr31 &= ~(FPU_CSR_FS | FPU_CSR_ALL_E | FPU_CSR_RM); 935 fcr31 |= (value << (FPU_CSR_FS_S - MIPS_FENR_FS_S)) & 936 FPU_CSR_FS; 937 fcr31 |= value & (FPU_CSR_ALL_E | FPU_CSR_RM); 938 break; 939 940 case FPCREG_FEXR: 941 if (!cpu_has_mips_r) 942 break; 943 pr_debug("%p gpr[%d]->exr=%08x\n", 944 (void *)xcp->cp0_epc, MIPSInst_RT(ir), value); 945 fcr31 &= ~(FPU_CSR_ALL_X | FPU_CSR_ALL_S); 946 fcr31 |= value & (FPU_CSR_ALL_X | FPU_CSR_ALL_S); 947 break; 948 949 case FPCREG_FCCR: 950 if (!cpu_has_mips_r) 951 break; 952 pr_debug("%p gpr[%d]->ccr=%08x\n", 953 (void *)xcp->cp0_epc, MIPSInst_RT(ir), value); 954 fcr31 &= ~(FPU_CSR_CONDX | FPU_CSR_COND); 955 fcr31 |= (value << (FPU_CSR_COND_S - MIPS_FCCR_COND0_S)) & 956 FPU_CSR_COND; 957 fcr31 |= (value << (FPU_CSR_COND1_S - MIPS_FCCR_COND1_S)) & 958 FPU_CSR_CONDX; 959 break; 960 961 default: 962 break; 963 } 964 965 ctx->fcr31 = fcr31; 966 } 967 968 /* 969 * Emulate the single floating point instruction pointed at by EPC. 970 * Two instructions if the instruction is in a branch delay slot. 971 */ 972 973 static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_struct *ctx, 974 struct mm_decoded_insn dec_insn, void *__user *fault_addr) 975 { 976 unsigned long contpc = xcp->cp0_epc + dec_insn.pc_inc; 977 unsigned int cond, cbit, bit0; 978 mips_instruction ir; 979 int likely, pc_inc; 980 union fpureg *fpr; 981 u32 __user *wva; 982 u64 __user *dva; 983 u32 wval; 984 u64 dval; 985 int sig; 986 987 /* 988 * These are giving gcc a gentle hint about what to expect in 989 * dec_inst in order to do better optimization. 990 */ 991 if (!cpu_has_mmips && dec_insn.micro_mips_mode) 992 unreachable(); 993 994 /* XXX NEC Vr54xx bug workaround */ 995 if (delay_slot(xcp)) { 996 if (dec_insn.micro_mips_mode) { 997 if (!mm_isBranchInstr(xcp, dec_insn, &contpc)) 998 clear_delay_slot(xcp); 999 } else { 1000 if (!isBranchInstr(xcp, dec_insn, &contpc)) 1001 clear_delay_slot(xcp); 1002 } 1003 } 1004 1005 if (delay_slot(xcp)) { 1006 /* 1007 * The instruction to be emulated is in a branch delay slot 1008 * which means that we have to emulate the branch instruction 1009 * BEFORE we do the cop1 instruction. 1010 * 1011 * This branch could be a COP1 branch, but in that case we 1012 * would have had a trap for that instruction, and would not 1013 * come through this route. 1014 * 1015 * Linux MIPS branch emulator operates on context, updating the 1016 * cp0_epc. 1017 */ 1018 ir = dec_insn.next_insn; /* process delay slot instr */ 1019 pc_inc = dec_insn.next_pc_inc; 1020 } else { 1021 ir = dec_insn.insn; /* process current instr */ 1022 pc_inc = dec_insn.pc_inc; 1023 } 1024 1025 /* 1026 * Since microMIPS FPU instructios are a subset of MIPS32 FPU 1027 * instructions, we want to convert microMIPS FPU instructions 1028 * into MIPS32 instructions so that we could reuse all of the 1029 * FPU emulation code. 1030 * 1031 * NOTE: We cannot do this for branch instructions since they 1032 * are not a subset. Example: Cannot emulate a 16-bit 1033 * aligned target address with a MIPS32 instruction. 1034 */ 1035 if (dec_insn.micro_mips_mode) { 1036 /* 1037 * If next instruction is a 16-bit instruction, then it 1038 * it cannot be a FPU instruction. This could happen 1039 * since we can be called for non-FPU instructions. 1040 */ 1041 if ((pc_inc == 2) || 1042 (microMIPS32_to_MIPS32((union mips_instruction *)&ir) 1043 == SIGILL)) 1044 return SIGILL; 1045 } 1046 1047 emul: 1048 perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 1, xcp, 0); 1049 MIPS_FPU_EMU_INC_STATS(emulated); 1050 switch (MIPSInst_OPCODE(ir)) { 1051 case ldc1_op: 1052 dva = (u64 __user *) (xcp->regs[MIPSInst_RS(ir)] + 1053 MIPSInst_SIMM(ir)); 1054 MIPS_FPU_EMU_INC_STATS(loads); 1055 1056 if (!access_ok(VERIFY_READ, dva, sizeof(u64))) { 1057 MIPS_FPU_EMU_INC_STATS(errors); 1058 *fault_addr = dva; 1059 return SIGBUS; 1060 } 1061 if (__get_user(dval, dva)) { 1062 MIPS_FPU_EMU_INC_STATS(errors); 1063 *fault_addr = dva; 1064 return SIGSEGV; 1065 } 1066 DITOREG(dval, MIPSInst_RT(ir)); 1067 break; 1068 1069 case sdc1_op: 1070 dva = (u64 __user *) (xcp->regs[MIPSInst_RS(ir)] + 1071 MIPSInst_SIMM(ir)); 1072 MIPS_FPU_EMU_INC_STATS(stores); 1073 DIFROMREG(dval, MIPSInst_RT(ir)); 1074 if (!access_ok(VERIFY_WRITE, dva, sizeof(u64))) { 1075 MIPS_FPU_EMU_INC_STATS(errors); 1076 *fault_addr = dva; 1077 return SIGBUS; 1078 } 1079 if (__put_user(dval, dva)) { 1080 MIPS_FPU_EMU_INC_STATS(errors); 1081 *fault_addr = dva; 1082 return SIGSEGV; 1083 } 1084 break; 1085 1086 case lwc1_op: 1087 wva = (u32 __user *) (xcp->regs[MIPSInst_RS(ir)] + 1088 MIPSInst_SIMM(ir)); 1089 MIPS_FPU_EMU_INC_STATS(loads); 1090 if (!access_ok(VERIFY_READ, wva, sizeof(u32))) { 1091 MIPS_FPU_EMU_INC_STATS(errors); 1092 *fault_addr = wva; 1093 return SIGBUS; 1094 } 1095 if (__get_user(wval, wva)) { 1096 MIPS_FPU_EMU_INC_STATS(errors); 1097 *fault_addr = wva; 1098 return SIGSEGV; 1099 } 1100 SITOREG(wval, MIPSInst_RT(ir)); 1101 break; 1102 1103 case swc1_op: 1104 wva = (u32 __user *) (xcp->regs[MIPSInst_RS(ir)] + 1105 MIPSInst_SIMM(ir)); 1106 MIPS_FPU_EMU_INC_STATS(stores); 1107 SIFROMREG(wval, MIPSInst_RT(ir)); 1108 if (!access_ok(VERIFY_WRITE, wva, sizeof(u32))) { 1109 MIPS_FPU_EMU_INC_STATS(errors); 1110 *fault_addr = wva; 1111 return SIGBUS; 1112 } 1113 if (__put_user(wval, wva)) { 1114 MIPS_FPU_EMU_INC_STATS(errors); 1115 *fault_addr = wva; 1116 return SIGSEGV; 1117 } 1118 break; 1119 1120 case cop1_op: 1121 switch (MIPSInst_RS(ir)) { 1122 case dmfc_op: 1123 if (!cpu_has_mips_3_4_5 && !cpu_has_mips64) 1124 return SIGILL; 1125 1126 /* copregister fs -> gpr[rt] */ 1127 if (MIPSInst_RT(ir) != 0) { 1128 DIFROMREG(xcp->regs[MIPSInst_RT(ir)], 1129 MIPSInst_RD(ir)); 1130 } 1131 break; 1132 1133 case dmtc_op: 1134 if (!cpu_has_mips_3_4_5 && !cpu_has_mips64) 1135 return SIGILL; 1136 1137 /* copregister fs <- rt */ 1138 DITOREG(xcp->regs[MIPSInst_RT(ir)], MIPSInst_RD(ir)); 1139 break; 1140 1141 case mfhc_op: 1142 if (!cpu_has_mips_r2_r6) 1143 goto sigill; 1144 1145 /* copregister rd -> gpr[rt] */ 1146 if (MIPSInst_RT(ir) != 0) { 1147 SIFROMHREG(xcp->regs[MIPSInst_RT(ir)], 1148 MIPSInst_RD(ir)); 1149 } 1150 break; 1151 1152 case mthc_op: 1153 if (!cpu_has_mips_r2_r6) 1154 goto sigill; 1155 1156 /* copregister rd <- gpr[rt] */ 1157 SITOHREG(xcp->regs[MIPSInst_RT(ir)], MIPSInst_RD(ir)); 1158 break; 1159 1160 case mfc_op: 1161 /* copregister rd -> gpr[rt] */ 1162 if (MIPSInst_RT(ir) != 0) { 1163 SIFROMREG(xcp->regs[MIPSInst_RT(ir)], 1164 MIPSInst_RD(ir)); 1165 } 1166 break; 1167 1168 case mtc_op: 1169 /* copregister rd <- rt */ 1170 SITOREG(xcp->regs[MIPSInst_RT(ir)], MIPSInst_RD(ir)); 1171 break; 1172 1173 case cfc_op: 1174 /* cop control register rd -> gpr[rt] */ 1175 cop1_cfc(xcp, ctx, ir); 1176 break; 1177 1178 case ctc_op: 1179 /* copregister rd <- rt */ 1180 cop1_ctc(xcp, ctx, ir); 1181 if ((ctx->fcr31 >> 5) & ctx->fcr31 & FPU_CSR_ALL_E) { 1182 return SIGFPE; 1183 } 1184 break; 1185 1186 case bc1eqz_op: 1187 case bc1nez_op: 1188 if (!cpu_has_mips_r6 || delay_slot(xcp)) 1189 return SIGILL; 1190 1191 cond = likely = 0; 1192 fpr = ¤t->thread.fpu.fpr[MIPSInst_RT(ir)]; 1193 bit0 = get_fpr32(fpr, 0) & 0x1; 1194 switch (MIPSInst_RS(ir)) { 1195 case bc1eqz_op: 1196 cond = bit0 == 0; 1197 break; 1198 case bc1nez_op: 1199 cond = bit0 != 0; 1200 break; 1201 } 1202 goto branch_common; 1203 1204 case bc_op: 1205 if (delay_slot(xcp)) 1206 return SIGILL; 1207 1208 if (cpu_has_mips_4_5_r) 1209 cbit = fpucondbit[MIPSInst_RT(ir) >> 2]; 1210 else 1211 cbit = FPU_CSR_COND; 1212 cond = ctx->fcr31 & cbit; 1213 1214 likely = 0; 1215 switch (MIPSInst_RT(ir) & 3) { 1216 case bcfl_op: 1217 if (cpu_has_mips_2_3_4_5_r) 1218 likely = 1; 1219 /* Fall through */ 1220 case bcf_op: 1221 cond = !cond; 1222 break; 1223 case bctl_op: 1224 if (cpu_has_mips_2_3_4_5_r) 1225 likely = 1; 1226 /* Fall through */ 1227 case bct_op: 1228 break; 1229 } 1230 branch_common: 1231 set_delay_slot(xcp); 1232 if (cond) { 1233 /* 1234 * Branch taken: emulate dslot instruction 1235 */ 1236 unsigned long bcpc; 1237 1238 /* 1239 * Remember EPC at the branch to point back 1240 * at so that any delay-slot instruction 1241 * signal is not silently ignored. 1242 */ 1243 bcpc = xcp->cp0_epc; 1244 xcp->cp0_epc += dec_insn.pc_inc; 1245 1246 contpc = MIPSInst_SIMM(ir); 1247 ir = dec_insn.next_insn; 1248 if (dec_insn.micro_mips_mode) { 1249 contpc = (xcp->cp0_epc + (contpc << 1)); 1250 1251 /* If 16-bit instruction, not FPU. */ 1252 if ((dec_insn.next_pc_inc == 2) || 1253 (microMIPS32_to_MIPS32((union mips_instruction *)&ir) == SIGILL)) { 1254 1255 /* 1256 * Since this instruction will 1257 * be put on the stack with 1258 * 32-bit words, get around 1259 * this problem by putting a 1260 * NOP16 as the second one. 1261 */ 1262 if (dec_insn.next_pc_inc == 2) 1263 ir = (ir & (~0xffff)) | MM_NOP16; 1264 1265 /* 1266 * Single step the non-CP1 1267 * instruction in the dslot. 1268 */ 1269 sig = mips_dsemul(xcp, ir, 1270 bcpc, contpc); 1271 if (sig < 0) 1272 break; 1273 if (sig) 1274 xcp->cp0_epc = bcpc; 1275 /* 1276 * SIGILL forces out of 1277 * the emulation loop. 1278 */ 1279 return sig ? sig : SIGILL; 1280 } 1281 } else 1282 contpc = (xcp->cp0_epc + (contpc << 2)); 1283 1284 switch (MIPSInst_OPCODE(ir)) { 1285 case lwc1_op: 1286 case swc1_op: 1287 goto emul; 1288 1289 case ldc1_op: 1290 case sdc1_op: 1291 if (cpu_has_mips_2_3_4_5_r) 1292 goto emul; 1293 1294 goto bc_sigill; 1295 1296 case cop1_op: 1297 goto emul; 1298 1299 case cop1x_op: 1300 if (cpu_has_mips_4_5_64_r2_r6) 1301 /* its one of ours */ 1302 goto emul; 1303 1304 goto bc_sigill; 1305 1306 case spec_op: 1307 switch (MIPSInst_FUNC(ir)) { 1308 case movc_op: 1309 if (cpu_has_mips_4_5_r) 1310 goto emul; 1311 1312 goto bc_sigill; 1313 } 1314 break; 1315 1316 bc_sigill: 1317 xcp->cp0_epc = bcpc; 1318 return SIGILL; 1319 } 1320 1321 /* 1322 * Single step the non-cp1 1323 * instruction in the dslot 1324 */ 1325 sig = mips_dsemul(xcp, ir, bcpc, contpc); 1326 if (sig < 0) 1327 break; 1328 if (sig) 1329 xcp->cp0_epc = bcpc; 1330 /* SIGILL forces out of the emulation loop. */ 1331 return sig ? sig : SIGILL; 1332 } else if (likely) { /* branch not taken */ 1333 /* 1334 * branch likely nullifies 1335 * dslot if not taken 1336 */ 1337 xcp->cp0_epc += dec_insn.pc_inc; 1338 contpc += dec_insn.pc_inc; 1339 /* 1340 * else continue & execute 1341 * dslot as normal insn 1342 */ 1343 } 1344 break; 1345 1346 default: 1347 if (!(MIPSInst_RS(ir) & 0x10)) 1348 return SIGILL; 1349 1350 /* a real fpu computation instruction */ 1351 if ((sig = fpu_emu(xcp, ctx, ir))) 1352 return sig; 1353 } 1354 break; 1355 1356 case cop1x_op: 1357 if (!cpu_has_mips_4_5_64_r2_r6) 1358 return SIGILL; 1359 1360 sig = fpux_emu(xcp, ctx, ir, fault_addr); 1361 if (sig) 1362 return sig; 1363 break; 1364 1365 case spec_op: 1366 if (!cpu_has_mips_4_5_r) 1367 return SIGILL; 1368 1369 if (MIPSInst_FUNC(ir) != movc_op) 1370 return SIGILL; 1371 cond = fpucondbit[MIPSInst_RT(ir) >> 2]; 1372 if (((ctx->fcr31 & cond) != 0) == ((MIPSInst_RT(ir) & 1) != 0)) 1373 xcp->regs[MIPSInst_RD(ir)] = 1374 xcp->regs[MIPSInst_RS(ir)]; 1375 break; 1376 default: 1377 sigill: 1378 return SIGILL; 1379 } 1380 1381 /* we did it !! */ 1382 xcp->cp0_epc = contpc; 1383 clear_delay_slot(xcp); 1384 1385 return 0; 1386 } 1387 1388 /* 1389 * Conversion table from MIPS compare ops 48-63 1390 * cond = ieee754dp_cmp(x,y,IEEE754_UN,sig); 1391 */ 1392 static const unsigned char cmptab[8] = { 1393 0, /* cmp_0 (sig) cmp_sf */ 1394 IEEE754_CUN, /* cmp_un (sig) cmp_ngle */ 1395 IEEE754_CEQ, /* cmp_eq (sig) cmp_seq */ 1396 IEEE754_CEQ | IEEE754_CUN, /* cmp_ueq (sig) cmp_ngl */ 1397 IEEE754_CLT, /* cmp_olt (sig) cmp_lt */ 1398 IEEE754_CLT | IEEE754_CUN, /* cmp_ult (sig) cmp_nge */ 1399 IEEE754_CLT | IEEE754_CEQ, /* cmp_ole (sig) cmp_le */ 1400 IEEE754_CLT | IEEE754_CEQ | IEEE754_CUN, /* cmp_ule (sig) cmp_ngt */ 1401 }; 1402 1403 static const unsigned char negative_cmptab[8] = { 1404 0, /* Reserved */ 1405 IEEE754_CLT | IEEE754_CGT | IEEE754_CEQ, 1406 IEEE754_CLT | IEEE754_CGT | IEEE754_CUN, 1407 IEEE754_CLT | IEEE754_CGT, 1408 /* Reserved */ 1409 }; 1410 1411 1412 /* 1413 * Additional MIPS4 instructions 1414 */ 1415 1416 #define DEF3OP(name, p, f1, f2, f3) \ 1417 static union ieee754##p fpemu_##p##_##name(union ieee754##p r, \ 1418 union ieee754##p s, union ieee754##p t) \ 1419 { \ 1420 struct _ieee754_csr ieee754_csr_save; \ 1421 s = f1(s, t); \ 1422 ieee754_csr_save = ieee754_csr; \ 1423 s = f2(s, r); \ 1424 ieee754_csr_save.cx |= ieee754_csr.cx; \ 1425 ieee754_csr_save.sx |= ieee754_csr.sx; \ 1426 s = f3(s); \ 1427 ieee754_csr.cx |= ieee754_csr_save.cx; \ 1428 ieee754_csr.sx |= ieee754_csr_save.sx; \ 1429 return s; \ 1430 } 1431 1432 static union ieee754dp fpemu_dp_recip(union ieee754dp d) 1433 { 1434 return ieee754dp_div(ieee754dp_one(0), d); 1435 } 1436 1437 static union ieee754dp fpemu_dp_rsqrt(union ieee754dp d) 1438 { 1439 return ieee754dp_div(ieee754dp_one(0), ieee754dp_sqrt(d)); 1440 } 1441 1442 static union ieee754sp fpemu_sp_recip(union ieee754sp s) 1443 { 1444 return ieee754sp_div(ieee754sp_one(0), s); 1445 } 1446 1447 static union ieee754sp fpemu_sp_rsqrt(union ieee754sp s) 1448 { 1449 return ieee754sp_div(ieee754sp_one(0), ieee754sp_sqrt(s)); 1450 } 1451 1452 DEF3OP(madd, sp, ieee754sp_mul, ieee754sp_add, ); 1453 DEF3OP(msub, sp, ieee754sp_mul, ieee754sp_sub, ); 1454 DEF3OP(nmadd, sp, ieee754sp_mul, ieee754sp_add, ieee754sp_neg); 1455 DEF3OP(nmsub, sp, ieee754sp_mul, ieee754sp_sub, ieee754sp_neg); 1456 DEF3OP(madd, dp, ieee754dp_mul, ieee754dp_add, ); 1457 DEF3OP(msub, dp, ieee754dp_mul, ieee754dp_sub, ); 1458 DEF3OP(nmadd, dp, ieee754dp_mul, ieee754dp_add, ieee754dp_neg); 1459 DEF3OP(nmsub, dp, ieee754dp_mul, ieee754dp_sub, ieee754dp_neg); 1460 1461 static int fpux_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx, 1462 mips_instruction ir, void *__user *fault_addr) 1463 { 1464 unsigned rcsr = 0; /* resulting csr */ 1465 1466 MIPS_FPU_EMU_INC_STATS(cp1xops); 1467 1468 switch (MIPSInst_FMA_FFMT(ir)) { 1469 case s_fmt:{ /* 0 */ 1470 1471 union ieee754sp(*handler) (union ieee754sp, union ieee754sp, union ieee754sp); 1472 union ieee754sp fd, fr, fs, ft; 1473 u32 __user *va; 1474 u32 val; 1475 1476 switch (MIPSInst_FUNC(ir)) { 1477 case lwxc1_op: 1478 va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] + 1479 xcp->regs[MIPSInst_FT(ir)]); 1480 1481 MIPS_FPU_EMU_INC_STATS(loads); 1482 if (!access_ok(VERIFY_READ, va, sizeof(u32))) { 1483 MIPS_FPU_EMU_INC_STATS(errors); 1484 *fault_addr = va; 1485 return SIGBUS; 1486 } 1487 if (__get_user(val, va)) { 1488 MIPS_FPU_EMU_INC_STATS(errors); 1489 *fault_addr = va; 1490 return SIGSEGV; 1491 } 1492 SITOREG(val, MIPSInst_FD(ir)); 1493 break; 1494 1495 case swxc1_op: 1496 va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] + 1497 xcp->regs[MIPSInst_FT(ir)]); 1498 1499 MIPS_FPU_EMU_INC_STATS(stores); 1500 1501 SIFROMREG(val, MIPSInst_FS(ir)); 1502 if (!access_ok(VERIFY_WRITE, va, sizeof(u32))) { 1503 MIPS_FPU_EMU_INC_STATS(errors); 1504 *fault_addr = va; 1505 return SIGBUS; 1506 } 1507 if (put_user(val, va)) { 1508 MIPS_FPU_EMU_INC_STATS(errors); 1509 *fault_addr = va; 1510 return SIGSEGV; 1511 } 1512 break; 1513 1514 case madd_s_op: 1515 handler = fpemu_sp_madd; 1516 goto scoptop; 1517 case msub_s_op: 1518 handler = fpemu_sp_msub; 1519 goto scoptop; 1520 case nmadd_s_op: 1521 handler = fpemu_sp_nmadd; 1522 goto scoptop; 1523 case nmsub_s_op: 1524 handler = fpemu_sp_nmsub; 1525 goto scoptop; 1526 1527 scoptop: 1528 SPFROMREG(fr, MIPSInst_FR(ir)); 1529 SPFROMREG(fs, MIPSInst_FS(ir)); 1530 SPFROMREG(ft, MIPSInst_FT(ir)); 1531 fd = (*handler) (fr, fs, ft); 1532 SPTOREG(fd, MIPSInst_FD(ir)); 1533 1534 copcsr: 1535 if (ieee754_cxtest(IEEE754_INEXACT)) { 1536 MIPS_FPU_EMU_INC_STATS(ieee754_inexact); 1537 rcsr |= FPU_CSR_INE_X | FPU_CSR_INE_S; 1538 } 1539 if (ieee754_cxtest(IEEE754_UNDERFLOW)) { 1540 MIPS_FPU_EMU_INC_STATS(ieee754_underflow); 1541 rcsr |= FPU_CSR_UDF_X | FPU_CSR_UDF_S; 1542 } 1543 if (ieee754_cxtest(IEEE754_OVERFLOW)) { 1544 MIPS_FPU_EMU_INC_STATS(ieee754_overflow); 1545 rcsr |= FPU_CSR_OVF_X | FPU_CSR_OVF_S; 1546 } 1547 if (ieee754_cxtest(IEEE754_INVALID_OPERATION)) { 1548 MIPS_FPU_EMU_INC_STATS(ieee754_invalidop); 1549 rcsr |= FPU_CSR_INV_X | FPU_CSR_INV_S; 1550 } 1551 1552 ctx->fcr31 = (ctx->fcr31 & ~FPU_CSR_ALL_X) | rcsr; 1553 if ((ctx->fcr31 >> 5) & ctx->fcr31 & FPU_CSR_ALL_E) { 1554 /*printk ("SIGFPE: FPU csr = %08x\n", 1555 ctx->fcr31); */ 1556 return SIGFPE; 1557 } 1558 1559 break; 1560 1561 default: 1562 return SIGILL; 1563 } 1564 break; 1565 } 1566 1567 case d_fmt:{ /* 1 */ 1568 union ieee754dp(*handler) (union ieee754dp, union ieee754dp, union ieee754dp); 1569 union ieee754dp fd, fr, fs, ft; 1570 u64 __user *va; 1571 u64 val; 1572 1573 switch (MIPSInst_FUNC(ir)) { 1574 case ldxc1_op: 1575 va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] + 1576 xcp->regs[MIPSInst_FT(ir)]); 1577 1578 MIPS_FPU_EMU_INC_STATS(loads); 1579 if (!access_ok(VERIFY_READ, va, sizeof(u64))) { 1580 MIPS_FPU_EMU_INC_STATS(errors); 1581 *fault_addr = va; 1582 return SIGBUS; 1583 } 1584 if (__get_user(val, va)) { 1585 MIPS_FPU_EMU_INC_STATS(errors); 1586 *fault_addr = va; 1587 return SIGSEGV; 1588 } 1589 DITOREG(val, MIPSInst_FD(ir)); 1590 break; 1591 1592 case sdxc1_op: 1593 va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] + 1594 xcp->regs[MIPSInst_FT(ir)]); 1595 1596 MIPS_FPU_EMU_INC_STATS(stores); 1597 DIFROMREG(val, MIPSInst_FS(ir)); 1598 if (!access_ok(VERIFY_WRITE, va, sizeof(u64))) { 1599 MIPS_FPU_EMU_INC_STATS(errors); 1600 *fault_addr = va; 1601 return SIGBUS; 1602 } 1603 if (__put_user(val, va)) { 1604 MIPS_FPU_EMU_INC_STATS(errors); 1605 *fault_addr = va; 1606 return SIGSEGV; 1607 } 1608 break; 1609 1610 case madd_d_op: 1611 handler = fpemu_dp_madd; 1612 goto dcoptop; 1613 case msub_d_op: 1614 handler = fpemu_dp_msub; 1615 goto dcoptop; 1616 case nmadd_d_op: 1617 handler = fpemu_dp_nmadd; 1618 goto dcoptop; 1619 case nmsub_d_op: 1620 handler = fpemu_dp_nmsub; 1621 goto dcoptop; 1622 1623 dcoptop: 1624 DPFROMREG(fr, MIPSInst_FR(ir)); 1625 DPFROMREG(fs, MIPSInst_FS(ir)); 1626 DPFROMREG(ft, MIPSInst_FT(ir)); 1627 fd = (*handler) (fr, fs, ft); 1628 DPTOREG(fd, MIPSInst_FD(ir)); 1629 goto copcsr; 1630 1631 default: 1632 return SIGILL; 1633 } 1634 break; 1635 } 1636 1637 case 0x3: 1638 if (MIPSInst_FUNC(ir) != pfetch_op) 1639 return SIGILL; 1640 1641 /* ignore prefx operation */ 1642 break; 1643 1644 default: 1645 return SIGILL; 1646 } 1647 1648 return 0; 1649 } 1650 1651 1652 1653 /* 1654 * Emulate a single COP1 arithmetic instruction. 1655 */ 1656 static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx, 1657 mips_instruction ir) 1658 { 1659 int rfmt; /* resulting format */ 1660 unsigned rcsr = 0; /* resulting csr */ 1661 unsigned int oldrm; 1662 unsigned int cbit; 1663 unsigned cond; 1664 union { 1665 union ieee754dp d; 1666 union ieee754sp s; 1667 int w; 1668 s64 l; 1669 } rv; /* resulting value */ 1670 u64 bits; 1671 1672 MIPS_FPU_EMU_INC_STATS(cp1ops); 1673 switch (rfmt = (MIPSInst_FFMT(ir) & 0xf)) { 1674 case s_fmt: { /* 0 */ 1675 union { 1676 union ieee754sp(*b) (union ieee754sp, union ieee754sp); 1677 union ieee754sp(*u) (union ieee754sp); 1678 } handler; 1679 union ieee754sp fd, fs, ft; 1680 1681 switch (MIPSInst_FUNC(ir)) { 1682 /* binary ops */ 1683 case fadd_op: 1684 handler.b = ieee754sp_add; 1685 goto scopbop; 1686 case fsub_op: 1687 handler.b = ieee754sp_sub; 1688 goto scopbop; 1689 case fmul_op: 1690 handler.b = ieee754sp_mul; 1691 goto scopbop; 1692 case fdiv_op: 1693 handler.b = ieee754sp_div; 1694 goto scopbop; 1695 1696 /* unary ops */ 1697 case fsqrt_op: 1698 if (!cpu_has_mips_2_3_4_5_r) 1699 return SIGILL; 1700 1701 handler.u = ieee754sp_sqrt; 1702 goto scopuop; 1703 1704 /* 1705 * Note that on some MIPS IV implementations such as the 1706 * R5000 and R8000 the FSQRT and FRECIP instructions do not 1707 * achieve full IEEE-754 accuracy - however this emulator does. 1708 */ 1709 case frsqrt_op: 1710 if (!cpu_has_mips_4_5_64_r2_r6) 1711 return SIGILL; 1712 1713 handler.u = fpemu_sp_rsqrt; 1714 goto scopuop; 1715 1716 case frecip_op: 1717 if (!cpu_has_mips_4_5_64_r2_r6) 1718 return SIGILL; 1719 1720 handler.u = fpemu_sp_recip; 1721 goto scopuop; 1722 1723 case fmovc_op: 1724 if (!cpu_has_mips_4_5_r) 1725 return SIGILL; 1726 1727 cond = fpucondbit[MIPSInst_FT(ir) >> 2]; 1728 if (((ctx->fcr31 & cond) != 0) != 1729 ((MIPSInst_FT(ir) & 1) != 0)) 1730 return 0; 1731 SPFROMREG(rv.s, MIPSInst_FS(ir)); 1732 break; 1733 1734 case fmovz_op: 1735 if (!cpu_has_mips_4_5_r) 1736 return SIGILL; 1737 1738 if (xcp->regs[MIPSInst_FT(ir)] != 0) 1739 return 0; 1740 SPFROMREG(rv.s, MIPSInst_FS(ir)); 1741 break; 1742 1743 case fmovn_op: 1744 if (!cpu_has_mips_4_5_r) 1745 return SIGILL; 1746 1747 if (xcp->regs[MIPSInst_FT(ir)] == 0) 1748 return 0; 1749 SPFROMREG(rv.s, MIPSInst_FS(ir)); 1750 break; 1751 1752 case fseleqz_op: 1753 if (!cpu_has_mips_r6) 1754 return SIGILL; 1755 1756 SPFROMREG(rv.s, MIPSInst_FT(ir)); 1757 if (rv.w & 0x1) 1758 rv.w = 0; 1759 else 1760 SPFROMREG(rv.s, MIPSInst_FS(ir)); 1761 break; 1762 1763 case fselnez_op: 1764 if (!cpu_has_mips_r6) 1765 return SIGILL; 1766 1767 SPFROMREG(rv.s, MIPSInst_FT(ir)); 1768 if (rv.w & 0x1) 1769 SPFROMREG(rv.s, MIPSInst_FS(ir)); 1770 else 1771 rv.w = 0; 1772 break; 1773 1774 case fmaddf_op: { 1775 union ieee754sp ft, fs, fd; 1776 1777 if (!cpu_has_mips_r6) 1778 return SIGILL; 1779 1780 SPFROMREG(ft, MIPSInst_FT(ir)); 1781 SPFROMREG(fs, MIPSInst_FS(ir)); 1782 SPFROMREG(fd, MIPSInst_FD(ir)); 1783 rv.s = ieee754sp_maddf(fd, fs, ft); 1784 break; 1785 } 1786 1787 case fmsubf_op: { 1788 union ieee754sp ft, fs, fd; 1789 1790 if (!cpu_has_mips_r6) 1791 return SIGILL; 1792 1793 SPFROMREG(ft, MIPSInst_FT(ir)); 1794 SPFROMREG(fs, MIPSInst_FS(ir)); 1795 SPFROMREG(fd, MIPSInst_FD(ir)); 1796 rv.s = ieee754sp_msubf(fd, fs, ft); 1797 break; 1798 } 1799 1800 case frint_op: { 1801 union ieee754sp fs; 1802 1803 if (!cpu_has_mips_r6) 1804 return SIGILL; 1805 1806 SPFROMREG(fs, MIPSInst_FS(ir)); 1807 rv.l = ieee754sp_tlong(fs); 1808 rv.s = ieee754sp_flong(rv.l); 1809 goto copcsr; 1810 } 1811 1812 case fclass_op: { 1813 union ieee754sp fs; 1814 1815 if (!cpu_has_mips_r6) 1816 return SIGILL; 1817 1818 SPFROMREG(fs, MIPSInst_FS(ir)); 1819 rv.w = ieee754sp_2008class(fs); 1820 rfmt = w_fmt; 1821 break; 1822 } 1823 1824 case fmin_op: { 1825 union ieee754sp fs, ft; 1826 1827 if (!cpu_has_mips_r6) 1828 return SIGILL; 1829 1830 SPFROMREG(ft, MIPSInst_FT(ir)); 1831 SPFROMREG(fs, MIPSInst_FS(ir)); 1832 rv.s = ieee754sp_fmin(fs, ft); 1833 break; 1834 } 1835 1836 case fmina_op: { 1837 union ieee754sp fs, ft; 1838 1839 if (!cpu_has_mips_r6) 1840 return SIGILL; 1841 1842 SPFROMREG(ft, MIPSInst_FT(ir)); 1843 SPFROMREG(fs, MIPSInst_FS(ir)); 1844 rv.s = ieee754sp_fmina(fs, ft); 1845 break; 1846 } 1847 1848 case fmax_op: { 1849 union ieee754sp fs, ft; 1850 1851 if (!cpu_has_mips_r6) 1852 return SIGILL; 1853 1854 SPFROMREG(ft, MIPSInst_FT(ir)); 1855 SPFROMREG(fs, MIPSInst_FS(ir)); 1856 rv.s = ieee754sp_fmax(fs, ft); 1857 break; 1858 } 1859 1860 case fmaxa_op: { 1861 union ieee754sp fs, ft; 1862 1863 if (!cpu_has_mips_r6) 1864 return SIGILL; 1865 1866 SPFROMREG(ft, MIPSInst_FT(ir)); 1867 SPFROMREG(fs, MIPSInst_FS(ir)); 1868 rv.s = ieee754sp_fmaxa(fs, ft); 1869 break; 1870 } 1871 1872 case fabs_op: 1873 handler.u = ieee754sp_abs; 1874 goto scopuop; 1875 1876 case fneg_op: 1877 handler.u = ieee754sp_neg; 1878 goto scopuop; 1879 1880 case fmov_op: 1881 /* an easy one */ 1882 SPFROMREG(rv.s, MIPSInst_FS(ir)); 1883 goto copcsr; 1884 1885 /* binary op on handler */ 1886 scopbop: 1887 SPFROMREG(fs, MIPSInst_FS(ir)); 1888 SPFROMREG(ft, MIPSInst_FT(ir)); 1889 1890 rv.s = (*handler.b) (fs, ft); 1891 goto copcsr; 1892 scopuop: 1893 SPFROMREG(fs, MIPSInst_FS(ir)); 1894 rv.s = (*handler.u) (fs); 1895 goto copcsr; 1896 copcsr: 1897 if (ieee754_cxtest(IEEE754_INEXACT)) { 1898 MIPS_FPU_EMU_INC_STATS(ieee754_inexact); 1899 rcsr |= FPU_CSR_INE_X | FPU_CSR_INE_S; 1900 } 1901 if (ieee754_cxtest(IEEE754_UNDERFLOW)) { 1902 MIPS_FPU_EMU_INC_STATS(ieee754_underflow); 1903 rcsr |= FPU_CSR_UDF_X | FPU_CSR_UDF_S; 1904 } 1905 if (ieee754_cxtest(IEEE754_OVERFLOW)) { 1906 MIPS_FPU_EMU_INC_STATS(ieee754_overflow); 1907 rcsr |= FPU_CSR_OVF_X | FPU_CSR_OVF_S; 1908 } 1909 if (ieee754_cxtest(IEEE754_ZERO_DIVIDE)) { 1910 MIPS_FPU_EMU_INC_STATS(ieee754_zerodiv); 1911 rcsr |= FPU_CSR_DIV_X | FPU_CSR_DIV_S; 1912 } 1913 if (ieee754_cxtest(IEEE754_INVALID_OPERATION)) { 1914 MIPS_FPU_EMU_INC_STATS(ieee754_invalidop); 1915 rcsr |= FPU_CSR_INV_X | FPU_CSR_INV_S; 1916 } 1917 break; 1918 1919 /* unary conv ops */ 1920 case fcvts_op: 1921 return SIGILL; /* not defined */ 1922 1923 case fcvtd_op: 1924 SPFROMREG(fs, MIPSInst_FS(ir)); 1925 rv.d = ieee754dp_fsp(fs); 1926 rfmt = d_fmt; 1927 goto copcsr; 1928 1929 case fcvtw_op: 1930 SPFROMREG(fs, MIPSInst_FS(ir)); 1931 rv.w = ieee754sp_tint(fs); 1932 rfmt = w_fmt; 1933 goto copcsr; 1934 1935 case fround_op: 1936 case ftrunc_op: 1937 case fceil_op: 1938 case ffloor_op: 1939 if (!cpu_has_mips_2_3_4_5_r) 1940 return SIGILL; 1941 1942 oldrm = ieee754_csr.rm; 1943 SPFROMREG(fs, MIPSInst_FS(ir)); 1944 ieee754_csr.rm = MIPSInst_FUNC(ir); 1945 rv.w = ieee754sp_tint(fs); 1946 ieee754_csr.rm = oldrm; 1947 rfmt = w_fmt; 1948 goto copcsr; 1949 1950 case fsel_op: 1951 if (!cpu_has_mips_r6) 1952 return SIGILL; 1953 1954 SPFROMREG(fd, MIPSInst_FD(ir)); 1955 if (fd.bits & 0x1) 1956 SPFROMREG(rv.s, MIPSInst_FT(ir)); 1957 else 1958 SPFROMREG(rv.s, MIPSInst_FS(ir)); 1959 break; 1960 1961 case fcvtl_op: 1962 if (!cpu_has_mips_3_4_5_64_r2_r6) 1963 return SIGILL; 1964 1965 SPFROMREG(fs, MIPSInst_FS(ir)); 1966 rv.l = ieee754sp_tlong(fs); 1967 rfmt = l_fmt; 1968 goto copcsr; 1969 1970 case froundl_op: 1971 case ftruncl_op: 1972 case fceill_op: 1973 case ffloorl_op: 1974 if (!cpu_has_mips_3_4_5_64_r2_r6) 1975 return SIGILL; 1976 1977 oldrm = ieee754_csr.rm; 1978 SPFROMREG(fs, MIPSInst_FS(ir)); 1979 ieee754_csr.rm = MIPSInst_FUNC(ir); 1980 rv.l = ieee754sp_tlong(fs); 1981 ieee754_csr.rm = oldrm; 1982 rfmt = l_fmt; 1983 goto copcsr; 1984 1985 default: 1986 if (!NO_R6EMU && MIPSInst_FUNC(ir) >= fcmp_op) { 1987 unsigned cmpop = MIPSInst_FUNC(ir) - fcmp_op; 1988 union ieee754sp fs, ft; 1989 1990 SPFROMREG(fs, MIPSInst_FS(ir)); 1991 SPFROMREG(ft, MIPSInst_FT(ir)); 1992 rv.w = ieee754sp_cmp(fs, ft, 1993 cmptab[cmpop & 0x7], cmpop & 0x8); 1994 rfmt = -1; 1995 if ((cmpop & 0x8) && ieee754_cxtest 1996 (IEEE754_INVALID_OPERATION)) 1997 rcsr = FPU_CSR_INV_X | FPU_CSR_INV_S; 1998 else 1999 goto copcsr; 2000 2001 } else 2002 return SIGILL; 2003 break; 2004 } 2005 break; 2006 } 2007 2008 case d_fmt: { 2009 union ieee754dp fd, fs, ft; 2010 union { 2011 union ieee754dp(*b) (union ieee754dp, union ieee754dp); 2012 union ieee754dp(*u) (union ieee754dp); 2013 } handler; 2014 2015 switch (MIPSInst_FUNC(ir)) { 2016 /* binary ops */ 2017 case fadd_op: 2018 handler.b = ieee754dp_add; 2019 goto dcopbop; 2020 case fsub_op: 2021 handler.b = ieee754dp_sub; 2022 goto dcopbop; 2023 case fmul_op: 2024 handler.b = ieee754dp_mul; 2025 goto dcopbop; 2026 case fdiv_op: 2027 handler.b = ieee754dp_div; 2028 goto dcopbop; 2029 2030 /* unary ops */ 2031 case fsqrt_op: 2032 if (!cpu_has_mips_2_3_4_5_r) 2033 return SIGILL; 2034 2035 handler.u = ieee754dp_sqrt; 2036 goto dcopuop; 2037 /* 2038 * Note that on some MIPS IV implementations such as the 2039 * R5000 and R8000 the FSQRT and FRECIP instructions do not 2040 * achieve full IEEE-754 accuracy - however this emulator does. 2041 */ 2042 case frsqrt_op: 2043 if (!cpu_has_mips_4_5_64_r2_r6) 2044 return SIGILL; 2045 2046 handler.u = fpemu_dp_rsqrt; 2047 goto dcopuop; 2048 case frecip_op: 2049 if (!cpu_has_mips_4_5_64_r2_r6) 2050 return SIGILL; 2051 2052 handler.u = fpemu_dp_recip; 2053 goto dcopuop; 2054 case fmovc_op: 2055 if (!cpu_has_mips_4_5_r) 2056 return SIGILL; 2057 2058 cond = fpucondbit[MIPSInst_FT(ir) >> 2]; 2059 if (((ctx->fcr31 & cond) != 0) != 2060 ((MIPSInst_FT(ir) & 1) != 0)) 2061 return 0; 2062 DPFROMREG(rv.d, MIPSInst_FS(ir)); 2063 break; 2064 case fmovz_op: 2065 if (!cpu_has_mips_4_5_r) 2066 return SIGILL; 2067 2068 if (xcp->regs[MIPSInst_FT(ir)] != 0) 2069 return 0; 2070 DPFROMREG(rv.d, MIPSInst_FS(ir)); 2071 break; 2072 case fmovn_op: 2073 if (!cpu_has_mips_4_5_r) 2074 return SIGILL; 2075 2076 if (xcp->regs[MIPSInst_FT(ir)] == 0) 2077 return 0; 2078 DPFROMREG(rv.d, MIPSInst_FS(ir)); 2079 break; 2080 2081 case fseleqz_op: 2082 if (!cpu_has_mips_r6) 2083 return SIGILL; 2084 2085 DPFROMREG(rv.d, MIPSInst_FT(ir)); 2086 if (rv.l & 0x1) 2087 rv.l = 0; 2088 else 2089 DPFROMREG(rv.d, MIPSInst_FS(ir)); 2090 break; 2091 2092 case fselnez_op: 2093 if (!cpu_has_mips_r6) 2094 return SIGILL; 2095 2096 DPFROMREG(rv.d, MIPSInst_FT(ir)); 2097 if (rv.l & 0x1) 2098 DPFROMREG(rv.d, MIPSInst_FS(ir)); 2099 else 2100 rv.l = 0; 2101 break; 2102 2103 case fmaddf_op: { 2104 union ieee754dp ft, fs, fd; 2105 2106 if (!cpu_has_mips_r6) 2107 return SIGILL; 2108 2109 DPFROMREG(ft, MIPSInst_FT(ir)); 2110 DPFROMREG(fs, MIPSInst_FS(ir)); 2111 DPFROMREG(fd, MIPSInst_FD(ir)); 2112 rv.d = ieee754dp_maddf(fd, fs, ft); 2113 break; 2114 } 2115 2116 case fmsubf_op: { 2117 union ieee754dp ft, fs, fd; 2118 2119 if (!cpu_has_mips_r6) 2120 return SIGILL; 2121 2122 DPFROMREG(ft, MIPSInst_FT(ir)); 2123 DPFROMREG(fs, MIPSInst_FS(ir)); 2124 DPFROMREG(fd, MIPSInst_FD(ir)); 2125 rv.d = ieee754dp_msubf(fd, fs, ft); 2126 break; 2127 } 2128 2129 case frint_op: { 2130 union ieee754dp fs; 2131 2132 if (!cpu_has_mips_r6) 2133 return SIGILL; 2134 2135 DPFROMREG(fs, MIPSInst_FS(ir)); 2136 rv.l = ieee754dp_tlong(fs); 2137 rv.d = ieee754dp_flong(rv.l); 2138 goto copcsr; 2139 } 2140 2141 case fclass_op: { 2142 union ieee754dp fs; 2143 2144 if (!cpu_has_mips_r6) 2145 return SIGILL; 2146 2147 DPFROMREG(fs, MIPSInst_FS(ir)); 2148 rv.w = ieee754dp_2008class(fs); 2149 rfmt = w_fmt; 2150 break; 2151 } 2152 2153 case fmin_op: { 2154 union ieee754dp fs, ft; 2155 2156 if (!cpu_has_mips_r6) 2157 return SIGILL; 2158 2159 DPFROMREG(ft, MIPSInst_FT(ir)); 2160 DPFROMREG(fs, MIPSInst_FS(ir)); 2161 rv.d = ieee754dp_fmin(fs, ft); 2162 break; 2163 } 2164 2165 case fmina_op: { 2166 union ieee754dp fs, ft; 2167 2168 if (!cpu_has_mips_r6) 2169 return SIGILL; 2170 2171 DPFROMREG(ft, MIPSInst_FT(ir)); 2172 DPFROMREG(fs, MIPSInst_FS(ir)); 2173 rv.d = ieee754dp_fmina(fs, ft); 2174 break; 2175 } 2176 2177 case fmax_op: { 2178 union ieee754dp fs, ft; 2179 2180 if (!cpu_has_mips_r6) 2181 return SIGILL; 2182 2183 DPFROMREG(ft, MIPSInst_FT(ir)); 2184 DPFROMREG(fs, MIPSInst_FS(ir)); 2185 rv.d = ieee754dp_fmax(fs, ft); 2186 break; 2187 } 2188 2189 case fmaxa_op: { 2190 union ieee754dp fs, ft; 2191 2192 if (!cpu_has_mips_r6) 2193 return SIGILL; 2194 2195 DPFROMREG(ft, MIPSInst_FT(ir)); 2196 DPFROMREG(fs, MIPSInst_FS(ir)); 2197 rv.d = ieee754dp_fmaxa(fs, ft); 2198 break; 2199 } 2200 2201 case fabs_op: 2202 handler.u = ieee754dp_abs; 2203 goto dcopuop; 2204 2205 case fneg_op: 2206 handler.u = ieee754dp_neg; 2207 goto dcopuop; 2208 2209 case fmov_op: 2210 /* an easy one */ 2211 DPFROMREG(rv.d, MIPSInst_FS(ir)); 2212 goto copcsr; 2213 2214 /* binary op on handler */ 2215 dcopbop: 2216 DPFROMREG(fs, MIPSInst_FS(ir)); 2217 DPFROMREG(ft, MIPSInst_FT(ir)); 2218 2219 rv.d = (*handler.b) (fs, ft); 2220 goto copcsr; 2221 dcopuop: 2222 DPFROMREG(fs, MIPSInst_FS(ir)); 2223 rv.d = (*handler.u) (fs); 2224 goto copcsr; 2225 2226 /* 2227 * unary conv ops 2228 */ 2229 case fcvts_op: 2230 DPFROMREG(fs, MIPSInst_FS(ir)); 2231 rv.s = ieee754sp_fdp(fs); 2232 rfmt = s_fmt; 2233 goto copcsr; 2234 2235 case fcvtd_op: 2236 return SIGILL; /* not defined */ 2237 2238 case fcvtw_op: 2239 DPFROMREG(fs, MIPSInst_FS(ir)); 2240 rv.w = ieee754dp_tint(fs); /* wrong */ 2241 rfmt = w_fmt; 2242 goto copcsr; 2243 2244 case fround_op: 2245 case ftrunc_op: 2246 case fceil_op: 2247 case ffloor_op: 2248 if (!cpu_has_mips_2_3_4_5_r) 2249 return SIGILL; 2250 2251 oldrm = ieee754_csr.rm; 2252 DPFROMREG(fs, MIPSInst_FS(ir)); 2253 ieee754_csr.rm = MIPSInst_FUNC(ir); 2254 rv.w = ieee754dp_tint(fs); 2255 ieee754_csr.rm = oldrm; 2256 rfmt = w_fmt; 2257 goto copcsr; 2258 2259 case fsel_op: 2260 if (!cpu_has_mips_r6) 2261 return SIGILL; 2262 2263 DPFROMREG(fd, MIPSInst_FD(ir)); 2264 if (fd.bits & 0x1) 2265 DPFROMREG(rv.d, MIPSInst_FT(ir)); 2266 else 2267 DPFROMREG(rv.d, MIPSInst_FS(ir)); 2268 break; 2269 2270 case fcvtl_op: 2271 if (!cpu_has_mips_3_4_5_64_r2_r6) 2272 return SIGILL; 2273 2274 DPFROMREG(fs, MIPSInst_FS(ir)); 2275 rv.l = ieee754dp_tlong(fs); 2276 rfmt = l_fmt; 2277 goto copcsr; 2278 2279 case froundl_op: 2280 case ftruncl_op: 2281 case fceill_op: 2282 case ffloorl_op: 2283 if (!cpu_has_mips_3_4_5_64_r2_r6) 2284 return SIGILL; 2285 2286 oldrm = ieee754_csr.rm; 2287 DPFROMREG(fs, MIPSInst_FS(ir)); 2288 ieee754_csr.rm = MIPSInst_FUNC(ir); 2289 rv.l = ieee754dp_tlong(fs); 2290 ieee754_csr.rm = oldrm; 2291 rfmt = l_fmt; 2292 goto copcsr; 2293 2294 default: 2295 if (!NO_R6EMU && MIPSInst_FUNC(ir) >= fcmp_op) { 2296 unsigned cmpop = MIPSInst_FUNC(ir) - fcmp_op; 2297 union ieee754dp fs, ft; 2298 2299 DPFROMREG(fs, MIPSInst_FS(ir)); 2300 DPFROMREG(ft, MIPSInst_FT(ir)); 2301 rv.w = ieee754dp_cmp(fs, ft, 2302 cmptab[cmpop & 0x7], cmpop & 0x8); 2303 rfmt = -1; 2304 if ((cmpop & 0x8) 2305 && 2306 ieee754_cxtest 2307 (IEEE754_INVALID_OPERATION)) 2308 rcsr = FPU_CSR_INV_X | FPU_CSR_INV_S; 2309 else 2310 goto copcsr; 2311 2312 } 2313 else { 2314 return SIGILL; 2315 } 2316 break; 2317 } 2318 break; 2319 } 2320 2321 case w_fmt: { 2322 union ieee754dp fs; 2323 2324 switch (MIPSInst_FUNC(ir)) { 2325 case fcvts_op: 2326 /* convert word to single precision real */ 2327 SPFROMREG(fs, MIPSInst_FS(ir)); 2328 rv.s = ieee754sp_fint(fs.bits); 2329 rfmt = s_fmt; 2330 goto copcsr; 2331 case fcvtd_op: 2332 /* convert word to double precision real */ 2333 SPFROMREG(fs, MIPSInst_FS(ir)); 2334 rv.d = ieee754dp_fint(fs.bits); 2335 rfmt = d_fmt; 2336 goto copcsr; 2337 default: { 2338 /* Emulating the new CMP.condn.fmt R6 instruction */ 2339 #define CMPOP_MASK 0x7 2340 #define SIGN_BIT (0x1 << 3) 2341 #define PREDICATE_BIT (0x1 << 4) 2342 2343 int cmpop = MIPSInst_FUNC(ir) & CMPOP_MASK; 2344 int sig = MIPSInst_FUNC(ir) & SIGN_BIT; 2345 union ieee754sp fs, ft; 2346 2347 /* This is an R6 only instruction */ 2348 if (!cpu_has_mips_r6 || 2349 (MIPSInst_FUNC(ir) & 0x20)) 2350 return SIGILL; 2351 2352 /* fmt is w_fmt for single precision so fix it */ 2353 rfmt = s_fmt; 2354 /* default to false */ 2355 rv.w = 0; 2356 2357 /* CMP.condn.S */ 2358 SPFROMREG(fs, MIPSInst_FS(ir)); 2359 SPFROMREG(ft, MIPSInst_FT(ir)); 2360 2361 /* positive predicates */ 2362 if (!(MIPSInst_FUNC(ir) & PREDICATE_BIT)) { 2363 if (ieee754sp_cmp(fs, ft, cmptab[cmpop], 2364 sig)) 2365 rv.w = -1; /* true, all 1s */ 2366 if ((sig) && 2367 ieee754_cxtest(IEEE754_INVALID_OPERATION)) 2368 rcsr = FPU_CSR_INV_X | FPU_CSR_INV_S; 2369 else 2370 goto copcsr; 2371 } else { 2372 /* negative predicates */ 2373 switch (cmpop) { 2374 case 1: 2375 case 2: 2376 case 3: 2377 if (ieee754sp_cmp(fs, ft, 2378 negative_cmptab[cmpop], 2379 sig)) 2380 rv.w = -1; /* true, all 1s */ 2381 if (sig && 2382 ieee754_cxtest(IEEE754_INVALID_OPERATION)) 2383 rcsr = FPU_CSR_INV_X | FPU_CSR_INV_S; 2384 else 2385 goto copcsr; 2386 break; 2387 default: 2388 /* Reserved R6 ops */ 2389 pr_err("Reserved MIPS R6 CMP.condn.S operation\n"); 2390 return SIGILL; 2391 } 2392 } 2393 break; 2394 } 2395 } 2396 } 2397 2398 case l_fmt: 2399 2400 if (!cpu_has_mips_3_4_5_64_r2_r6) 2401 return SIGILL; 2402 2403 DIFROMREG(bits, MIPSInst_FS(ir)); 2404 2405 switch (MIPSInst_FUNC(ir)) { 2406 case fcvts_op: 2407 /* convert long to single precision real */ 2408 rv.s = ieee754sp_flong(bits); 2409 rfmt = s_fmt; 2410 goto copcsr; 2411 case fcvtd_op: 2412 /* convert long to double precision real */ 2413 rv.d = ieee754dp_flong(bits); 2414 rfmt = d_fmt; 2415 goto copcsr; 2416 default: { 2417 /* Emulating the new CMP.condn.fmt R6 instruction */ 2418 int cmpop = MIPSInst_FUNC(ir) & CMPOP_MASK; 2419 int sig = MIPSInst_FUNC(ir) & SIGN_BIT; 2420 union ieee754dp fs, ft; 2421 2422 if (!cpu_has_mips_r6 || 2423 (MIPSInst_FUNC(ir) & 0x20)) 2424 return SIGILL; 2425 2426 /* fmt is l_fmt for double precision so fix it */ 2427 rfmt = d_fmt; 2428 /* default to false */ 2429 rv.l = 0; 2430 2431 /* CMP.condn.D */ 2432 DPFROMREG(fs, MIPSInst_FS(ir)); 2433 DPFROMREG(ft, MIPSInst_FT(ir)); 2434 2435 /* positive predicates */ 2436 if (!(MIPSInst_FUNC(ir) & PREDICATE_BIT)) { 2437 if (ieee754dp_cmp(fs, ft, 2438 cmptab[cmpop], sig)) 2439 rv.l = -1LL; /* true, all 1s */ 2440 if (sig && 2441 ieee754_cxtest(IEEE754_INVALID_OPERATION)) 2442 rcsr = FPU_CSR_INV_X | FPU_CSR_INV_S; 2443 else 2444 goto copcsr; 2445 } else { 2446 /* negative predicates */ 2447 switch (cmpop) { 2448 case 1: 2449 case 2: 2450 case 3: 2451 if (ieee754dp_cmp(fs, ft, 2452 negative_cmptab[cmpop], 2453 sig)) 2454 rv.l = -1LL; /* true, all 1s */ 2455 if (sig && 2456 ieee754_cxtest(IEEE754_INVALID_OPERATION)) 2457 rcsr = FPU_CSR_INV_X | FPU_CSR_INV_S; 2458 else 2459 goto copcsr; 2460 break; 2461 default: 2462 /* Reserved R6 ops */ 2463 pr_err("Reserved MIPS R6 CMP.condn.D operation\n"); 2464 return SIGILL; 2465 } 2466 } 2467 break; 2468 } 2469 } 2470 default: 2471 return SIGILL; 2472 } 2473 2474 /* 2475 * Update the fpu CSR register for this operation. 2476 * If an exception is required, generate a tidy SIGFPE exception, 2477 * without updating the result register. 2478 * Note: cause exception bits do not accumulate, they are rewritten 2479 * for each op; only the flag/sticky bits accumulate. 2480 */ 2481 ctx->fcr31 = (ctx->fcr31 & ~FPU_CSR_ALL_X) | rcsr; 2482 if ((ctx->fcr31 >> 5) & ctx->fcr31 & FPU_CSR_ALL_E) { 2483 /*printk ("SIGFPE: FPU csr = %08x\n",ctx->fcr31); */ 2484 return SIGFPE; 2485 } 2486 2487 /* 2488 * Now we can safely write the result back to the register file. 2489 */ 2490 switch (rfmt) { 2491 case -1: 2492 2493 if (cpu_has_mips_4_5_r) 2494 cbit = fpucondbit[MIPSInst_FD(ir) >> 2]; 2495 else 2496 cbit = FPU_CSR_COND; 2497 if (rv.w) 2498 ctx->fcr31 |= cbit; 2499 else 2500 ctx->fcr31 &= ~cbit; 2501 break; 2502 2503 case d_fmt: 2504 DPTOREG(rv.d, MIPSInst_FD(ir)); 2505 break; 2506 case s_fmt: 2507 SPTOREG(rv.s, MIPSInst_FD(ir)); 2508 break; 2509 case w_fmt: 2510 SITOREG(rv.w, MIPSInst_FD(ir)); 2511 break; 2512 case l_fmt: 2513 if (!cpu_has_mips_3_4_5_64_r2_r6) 2514 return SIGILL; 2515 2516 DITOREG(rv.l, MIPSInst_FD(ir)); 2517 break; 2518 default: 2519 return SIGILL; 2520 } 2521 2522 return 0; 2523 } 2524 2525 int fpu_emulator_cop1Handler(struct pt_regs *xcp, struct mips_fpu_struct *ctx, 2526 int has_fpu, void *__user *fault_addr) 2527 { 2528 unsigned long oldepc, prevepc; 2529 struct mm_decoded_insn dec_insn; 2530 u16 instr[4]; 2531 u16 *instr_ptr; 2532 int sig = 0; 2533 2534 oldepc = xcp->cp0_epc; 2535 do { 2536 prevepc = xcp->cp0_epc; 2537 2538 if (get_isa16_mode(prevepc) && cpu_has_mmips) { 2539 /* 2540 * Get next 2 microMIPS instructions and convert them 2541 * into 32-bit instructions. 2542 */ 2543 if ((get_user(instr[0], (u16 __user *)msk_isa16_mode(xcp->cp0_epc))) || 2544 (get_user(instr[1], (u16 __user *)msk_isa16_mode(xcp->cp0_epc + 2))) || 2545 (get_user(instr[2], (u16 __user *)msk_isa16_mode(xcp->cp0_epc + 4))) || 2546 (get_user(instr[3], (u16 __user *)msk_isa16_mode(xcp->cp0_epc + 6)))) { 2547 MIPS_FPU_EMU_INC_STATS(errors); 2548 return SIGBUS; 2549 } 2550 instr_ptr = instr; 2551 2552 /* Get first instruction. */ 2553 if (mm_insn_16bit(*instr_ptr)) { 2554 /* Duplicate the half-word. */ 2555 dec_insn.insn = (*instr_ptr << 16) | 2556 (*instr_ptr); 2557 /* 16-bit instruction. */ 2558 dec_insn.pc_inc = 2; 2559 instr_ptr += 1; 2560 } else { 2561 dec_insn.insn = (*instr_ptr << 16) | 2562 *(instr_ptr+1); 2563 /* 32-bit instruction. */ 2564 dec_insn.pc_inc = 4; 2565 instr_ptr += 2; 2566 } 2567 /* Get second instruction. */ 2568 if (mm_insn_16bit(*instr_ptr)) { 2569 /* Duplicate the half-word. */ 2570 dec_insn.next_insn = (*instr_ptr << 16) | 2571 (*instr_ptr); 2572 /* 16-bit instruction. */ 2573 dec_insn.next_pc_inc = 2; 2574 } else { 2575 dec_insn.next_insn = (*instr_ptr << 16) | 2576 *(instr_ptr+1); 2577 /* 32-bit instruction. */ 2578 dec_insn.next_pc_inc = 4; 2579 } 2580 dec_insn.micro_mips_mode = 1; 2581 } else { 2582 if ((get_user(dec_insn.insn, 2583 (mips_instruction __user *) xcp->cp0_epc)) || 2584 (get_user(dec_insn.next_insn, 2585 (mips_instruction __user *)(xcp->cp0_epc+4)))) { 2586 MIPS_FPU_EMU_INC_STATS(errors); 2587 return SIGBUS; 2588 } 2589 dec_insn.pc_inc = 4; 2590 dec_insn.next_pc_inc = 4; 2591 dec_insn.micro_mips_mode = 0; 2592 } 2593 2594 if ((dec_insn.insn == 0) || 2595 ((dec_insn.pc_inc == 2) && 2596 ((dec_insn.insn & 0xffff) == MM_NOP16))) 2597 xcp->cp0_epc += dec_insn.pc_inc; /* Skip NOPs */ 2598 else { 2599 /* 2600 * The 'ieee754_csr' is an alias of ctx->fcr31. 2601 * No need to copy ctx->fcr31 to ieee754_csr. 2602 */ 2603 sig = cop1Emulate(xcp, ctx, dec_insn, fault_addr); 2604 } 2605 2606 if (has_fpu) 2607 break; 2608 if (sig) 2609 break; 2610 2611 cond_resched(); 2612 } while (xcp->cp0_epc > prevepc); 2613 2614 /* SIGILL indicates a non-fpu instruction */ 2615 if (sig == SIGILL && xcp->cp0_epc != oldepc) 2616 /* but if EPC has advanced, then ignore it */ 2617 sig = 0; 2618 2619 return sig; 2620 } 2621