11da177e4SLinus Torvalds /* 21da177e4SLinus Torvalds * cp1emu.c: a MIPS coprocessor 1 (fpu) instruction emulator 31da177e4SLinus Torvalds * 41da177e4SLinus Torvalds * MIPS floating point support 51da177e4SLinus Torvalds * Copyright (C) 1994-2000 Algorithmics Ltd. 61da177e4SLinus Torvalds * 71da177e4SLinus Torvalds * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com 81da177e4SLinus Torvalds * Copyright (C) 2000 MIPS Technologies, Inc. 91da177e4SLinus Torvalds * 101da177e4SLinus Torvalds * This program is free software; you can distribute it and/or modify it 111da177e4SLinus Torvalds * under the terms of the GNU General Public License (Version 2) as 121da177e4SLinus Torvalds * published by the Free Software Foundation. 131da177e4SLinus Torvalds * 141da177e4SLinus Torvalds * This program is distributed in the hope it will be useful, but WITHOUT 151da177e4SLinus Torvalds * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 161da177e4SLinus Torvalds * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 171da177e4SLinus Torvalds * for more details. 181da177e4SLinus Torvalds * 191da177e4SLinus Torvalds * You should have received a copy of the GNU General Public License along 201da177e4SLinus Torvalds * with this program; if not, write to the Free Software Foundation, Inc., 211da177e4SLinus Torvalds * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. 221da177e4SLinus Torvalds * 231da177e4SLinus Torvalds * A complete emulator for MIPS coprocessor 1 instructions. This is 241da177e4SLinus Torvalds * required for #float(switch) or #float(trap), where it catches all 251da177e4SLinus Torvalds * COP1 instructions via the "CoProcessor Unusable" exception. 261da177e4SLinus Torvalds * 271da177e4SLinus Torvalds * More surprisingly it is also required for #float(ieee), to help out 281da177e4SLinus Torvalds * the hardware fpu at the boundaries of the IEEE-754 representation 291da177e4SLinus Torvalds * (denormalised values, infinities, underflow, etc). It is made 301da177e4SLinus Torvalds * quite nasty because emulation of some non-COP1 instructions is 311da177e4SLinus Torvalds * required, e.g. in branch delay slots. 321da177e4SLinus Torvalds * 331da177e4SLinus Torvalds * Note if you know that you won't have an fpu, then you'll get much 341da177e4SLinus Torvalds * better performance by compiling with -msoft-float! 351da177e4SLinus Torvalds */ 361da177e4SLinus Torvalds #include <linux/sched.h> 3783fd38caSAtsushi Nemoto #include <linux/debugfs.h> 387f788d2dSDeng-Cheng Zhu #include <linux/perf_event.h> 391da177e4SLinus Torvalds 40*cd8ee345SRalf Baechle #include <asm/branch.h> 411da177e4SLinus Torvalds #include <asm/inst.h> 421da177e4SLinus Torvalds #include <asm/ptrace.h> 431da177e4SLinus Torvalds #include <asm/signal.h> 44*cd8ee345SRalf Baechle #include <asm/uaccess.h> 45*cd8ee345SRalf Baechle 46*cd8ee345SRalf Baechle #include <asm/processor.h> 471da177e4SLinus Torvalds #include <asm/fpu_emulator.h> 48102cedc3SLeonid Yegoshin #include <asm/fpu.h> 491da177e4SLinus Torvalds 501da177e4SLinus Torvalds #include "ieee754.h" 511da177e4SLinus Torvalds 521da177e4SLinus Torvalds /* Strap kernel emulator for full MIPS IV emulation */ 531da177e4SLinus Torvalds 541da177e4SLinus Torvalds #ifdef __mips 551da177e4SLinus Torvalds #undef __mips 561da177e4SLinus Torvalds #endif 571da177e4SLinus Torvalds #define __mips 4 581da177e4SLinus Torvalds 591da177e4SLinus Torvalds /* Function which emulates a floating point instruction. */ 601da177e4SLinus Torvalds 61eae89076SAtsushi Nemoto static int fpu_emu(struct pt_regs *, struct mips_fpu_struct *, 621da177e4SLinus Torvalds mips_instruction); 631da177e4SLinus Torvalds 641da177e4SLinus Torvalds #if __mips >= 4 && __mips != 32 651da177e4SLinus Torvalds static int fpux_emu(struct pt_regs *, 66515b029dSDavid Daney struct mips_fpu_struct *, mips_instruction, void *__user *); 671da177e4SLinus Torvalds #endif 681da177e4SLinus Torvalds 69eae89076SAtsushi Nemoto /* Further private data for which no space exists in mips_fpu_struct */ 701da177e4SLinus Torvalds 71b6ee75edSDavid Daney #ifdef CONFIG_DEBUG_FS 72b6ee75edSDavid Daney DEFINE_PER_CPU(struct mips_fpu_emulator_stats, fpuemustats); 73b6ee75edSDavid Daney #endif 741da177e4SLinus Torvalds 751da177e4SLinus Torvalds /* Control registers */ 761da177e4SLinus Torvalds 771da177e4SLinus Torvalds #define FPCREG_RID 0 /* $0 = revision id */ 781da177e4SLinus Torvalds #define FPCREG_CSR 31 /* $31 = csr */ 791da177e4SLinus Torvalds 8095e8f634SShane McDonald /* Determine rounding mode from the RM bits of the FCSR */ 8195e8f634SShane McDonald #define modeindex(v) ((v) & FPU_CSR_RM) 8295e8f634SShane McDonald 83102cedc3SLeonid Yegoshin /* microMIPS bitfields */ 84102cedc3SLeonid Yegoshin #define MM_POOL32A_MINOR_MASK 0x3f 85102cedc3SLeonid Yegoshin #define MM_POOL32A_MINOR_SHIFT 0x6 86102cedc3SLeonid Yegoshin #define MM_MIPS32_COND_FC 0x30 87102cedc3SLeonid Yegoshin 881da177e4SLinus Torvalds /* Convert Mips rounding mode (0..3) to IEEE library modes. */ 891da177e4SLinus Torvalds static const unsigned char ieee_rm[4] = { 90cd21dfcfSRalf Baechle [FPU_CSR_RN] = IEEE754_RN, 91cd21dfcfSRalf Baechle [FPU_CSR_RZ] = IEEE754_RZ, 92cd21dfcfSRalf Baechle [FPU_CSR_RU] = IEEE754_RU, 93cd21dfcfSRalf Baechle [FPU_CSR_RD] = IEEE754_RD, 94cd21dfcfSRalf Baechle }; 95cd21dfcfSRalf Baechle /* Convert IEEE library modes to Mips rounding mode (0..3). */ 96cd21dfcfSRalf Baechle static const unsigned char mips_rm[4] = { 97cd21dfcfSRalf Baechle [IEEE754_RN] = FPU_CSR_RN, 98cd21dfcfSRalf Baechle [IEEE754_RZ] = FPU_CSR_RZ, 99cd21dfcfSRalf Baechle [IEEE754_RD] = FPU_CSR_RD, 100cd21dfcfSRalf Baechle [IEEE754_RU] = FPU_CSR_RU, 1011da177e4SLinus Torvalds }; 1021da177e4SLinus Torvalds 1031da177e4SLinus Torvalds #if __mips >= 4 1041da177e4SLinus Torvalds /* convert condition code register number to csr bit */ 1051da177e4SLinus Torvalds static const unsigned int fpucondbit[8] = { 1061da177e4SLinus Torvalds FPU_CSR_COND0, 1071da177e4SLinus Torvalds FPU_CSR_COND1, 1081da177e4SLinus Torvalds FPU_CSR_COND2, 1091da177e4SLinus Torvalds FPU_CSR_COND3, 1101da177e4SLinus Torvalds FPU_CSR_COND4, 1111da177e4SLinus Torvalds FPU_CSR_COND5, 1121da177e4SLinus Torvalds FPU_CSR_COND6, 1131da177e4SLinus Torvalds FPU_CSR_COND7 1141da177e4SLinus Torvalds }; 1151da177e4SLinus Torvalds #endif 1161da177e4SLinus Torvalds 117102cedc3SLeonid Yegoshin /* (microMIPS) Convert 16-bit register encoding to 32-bit register encoding. */ 118102cedc3SLeonid Yegoshin static const unsigned int reg16to32map[8] = {16, 17, 2, 3, 4, 5, 6, 7}; 119102cedc3SLeonid Yegoshin 120102cedc3SLeonid Yegoshin /* (microMIPS) Convert certain microMIPS instructions to MIPS32 format. */ 121102cedc3SLeonid Yegoshin static const int sd_format[] = {16, 17, 0, 0, 0, 0, 0, 0}; 122102cedc3SLeonid Yegoshin static const int sdps_format[] = {16, 17, 22, 0, 0, 0, 0, 0}; 123102cedc3SLeonid Yegoshin static const int dwl_format[] = {17, 20, 21, 0, 0, 0, 0, 0}; 124102cedc3SLeonid Yegoshin static const int swl_format[] = {16, 20, 21, 0, 0, 0, 0, 0}; 125102cedc3SLeonid Yegoshin 126102cedc3SLeonid Yegoshin /* 127102cedc3SLeonid Yegoshin * This functions translates a 32-bit microMIPS instruction 128102cedc3SLeonid Yegoshin * into a 32-bit MIPS32 instruction. Returns 0 on success 129102cedc3SLeonid Yegoshin * and SIGILL otherwise. 130102cedc3SLeonid Yegoshin */ 131102cedc3SLeonid Yegoshin static int microMIPS32_to_MIPS32(union mips_instruction *insn_ptr) 132102cedc3SLeonid Yegoshin { 133102cedc3SLeonid Yegoshin union mips_instruction insn = *insn_ptr; 134102cedc3SLeonid Yegoshin union mips_instruction mips32_insn = insn; 135102cedc3SLeonid Yegoshin int func, fmt, op; 136102cedc3SLeonid Yegoshin 137102cedc3SLeonid Yegoshin switch (insn.mm_i_format.opcode) { 138102cedc3SLeonid Yegoshin case mm_ldc132_op: 139102cedc3SLeonid Yegoshin mips32_insn.mm_i_format.opcode = ldc1_op; 140102cedc3SLeonid Yegoshin mips32_insn.mm_i_format.rt = insn.mm_i_format.rs; 141102cedc3SLeonid Yegoshin mips32_insn.mm_i_format.rs = insn.mm_i_format.rt; 142102cedc3SLeonid Yegoshin break; 143102cedc3SLeonid Yegoshin case mm_lwc132_op: 144102cedc3SLeonid Yegoshin mips32_insn.mm_i_format.opcode = lwc1_op; 145102cedc3SLeonid Yegoshin mips32_insn.mm_i_format.rt = insn.mm_i_format.rs; 146102cedc3SLeonid Yegoshin mips32_insn.mm_i_format.rs = insn.mm_i_format.rt; 147102cedc3SLeonid Yegoshin break; 148102cedc3SLeonid Yegoshin case mm_sdc132_op: 149102cedc3SLeonid Yegoshin mips32_insn.mm_i_format.opcode = sdc1_op; 150102cedc3SLeonid Yegoshin mips32_insn.mm_i_format.rt = insn.mm_i_format.rs; 151102cedc3SLeonid Yegoshin mips32_insn.mm_i_format.rs = insn.mm_i_format.rt; 152102cedc3SLeonid Yegoshin break; 153102cedc3SLeonid Yegoshin case mm_swc132_op: 154102cedc3SLeonid Yegoshin mips32_insn.mm_i_format.opcode = swc1_op; 155102cedc3SLeonid Yegoshin mips32_insn.mm_i_format.rt = insn.mm_i_format.rs; 156102cedc3SLeonid Yegoshin mips32_insn.mm_i_format.rs = insn.mm_i_format.rt; 157102cedc3SLeonid Yegoshin break; 158102cedc3SLeonid Yegoshin case mm_pool32i_op: 159102cedc3SLeonid Yegoshin /* NOTE: offset is << by 1 if in microMIPS mode. */ 160102cedc3SLeonid Yegoshin if ((insn.mm_i_format.rt == mm_bc1f_op) || 161102cedc3SLeonid Yegoshin (insn.mm_i_format.rt == mm_bc1t_op)) { 162102cedc3SLeonid Yegoshin mips32_insn.fb_format.opcode = cop1_op; 163102cedc3SLeonid Yegoshin mips32_insn.fb_format.bc = bc_op; 164102cedc3SLeonid Yegoshin mips32_insn.fb_format.flag = 165102cedc3SLeonid Yegoshin (insn.mm_i_format.rt == mm_bc1t_op) ? 1 : 0; 166102cedc3SLeonid Yegoshin } else 167102cedc3SLeonid Yegoshin return SIGILL; 168102cedc3SLeonid Yegoshin break; 169102cedc3SLeonid Yegoshin case mm_pool32f_op: 170102cedc3SLeonid Yegoshin switch (insn.mm_fp0_format.func) { 171102cedc3SLeonid Yegoshin case mm_32f_01_op: 172102cedc3SLeonid Yegoshin case mm_32f_11_op: 173102cedc3SLeonid Yegoshin case mm_32f_02_op: 174102cedc3SLeonid Yegoshin case mm_32f_12_op: 175102cedc3SLeonid Yegoshin case mm_32f_41_op: 176102cedc3SLeonid Yegoshin case mm_32f_51_op: 177102cedc3SLeonid Yegoshin case mm_32f_42_op: 178102cedc3SLeonid Yegoshin case mm_32f_52_op: 179102cedc3SLeonid Yegoshin op = insn.mm_fp0_format.func; 180102cedc3SLeonid Yegoshin if (op == mm_32f_01_op) 181102cedc3SLeonid Yegoshin func = madd_s_op; 182102cedc3SLeonid Yegoshin else if (op == mm_32f_11_op) 183102cedc3SLeonid Yegoshin func = madd_d_op; 184102cedc3SLeonid Yegoshin else if (op == mm_32f_02_op) 185102cedc3SLeonid Yegoshin func = nmadd_s_op; 186102cedc3SLeonid Yegoshin else if (op == mm_32f_12_op) 187102cedc3SLeonid Yegoshin func = nmadd_d_op; 188102cedc3SLeonid Yegoshin else if (op == mm_32f_41_op) 189102cedc3SLeonid Yegoshin func = msub_s_op; 190102cedc3SLeonid Yegoshin else if (op == mm_32f_51_op) 191102cedc3SLeonid Yegoshin func = msub_d_op; 192102cedc3SLeonid Yegoshin else if (op == mm_32f_42_op) 193102cedc3SLeonid Yegoshin func = nmsub_s_op; 194102cedc3SLeonid Yegoshin else 195102cedc3SLeonid Yegoshin func = nmsub_d_op; 196102cedc3SLeonid Yegoshin mips32_insn.fp6_format.opcode = cop1x_op; 197102cedc3SLeonid Yegoshin mips32_insn.fp6_format.fr = insn.mm_fp6_format.fr; 198102cedc3SLeonid Yegoshin mips32_insn.fp6_format.ft = insn.mm_fp6_format.ft; 199102cedc3SLeonid Yegoshin mips32_insn.fp6_format.fs = insn.mm_fp6_format.fs; 200102cedc3SLeonid Yegoshin mips32_insn.fp6_format.fd = insn.mm_fp6_format.fd; 201102cedc3SLeonid Yegoshin mips32_insn.fp6_format.func = func; 202102cedc3SLeonid Yegoshin break; 203102cedc3SLeonid Yegoshin case mm_32f_10_op: 204102cedc3SLeonid Yegoshin func = -1; /* Invalid */ 205102cedc3SLeonid Yegoshin op = insn.mm_fp5_format.op & 0x7; 206102cedc3SLeonid Yegoshin if (op == mm_ldxc1_op) 207102cedc3SLeonid Yegoshin func = ldxc1_op; 208102cedc3SLeonid Yegoshin else if (op == mm_sdxc1_op) 209102cedc3SLeonid Yegoshin func = sdxc1_op; 210102cedc3SLeonid Yegoshin else if (op == mm_lwxc1_op) 211102cedc3SLeonid Yegoshin func = lwxc1_op; 212102cedc3SLeonid Yegoshin else if (op == mm_swxc1_op) 213102cedc3SLeonid Yegoshin func = swxc1_op; 214102cedc3SLeonid Yegoshin 215102cedc3SLeonid Yegoshin if (func != -1) { 216102cedc3SLeonid Yegoshin mips32_insn.r_format.opcode = cop1x_op; 217102cedc3SLeonid Yegoshin mips32_insn.r_format.rs = 218102cedc3SLeonid Yegoshin insn.mm_fp5_format.base; 219102cedc3SLeonid Yegoshin mips32_insn.r_format.rt = 220102cedc3SLeonid Yegoshin insn.mm_fp5_format.index; 221102cedc3SLeonid Yegoshin mips32_insn.r_format.rd = 0; 222102cedc3SLeonid Yegoshin mips32_insn.r_format.re = insn.mm_fp5_format.fd; 223102cedc3SLeonid Yegoshin mips32_insn.r_format.func = func; 224102cedc3SLeonid Yegoshin } else 225102cedc3SLeonid Yegoshin return SIGILL; 226102cedc3SLeonid Yegoshin break; 227102cedc3SLeonid Yegoshin case mm_32f_40_op: 228102cedc3SLeonid Yegoshin op = -1; /* Invalid */ 229102cedc3SLeonid Yegoshin if (insn.mm_fp2_format.op == mm_fmovt_op) 230102cedc3SLeonid Yegoshin op = 1; 231102cedc3SLeonid Yegoshin else if (insn.mm_fp2_format.op == mm_fmovf_op) 232102cedc3SLeonid Yegoshin op = 0; 233102cedc3SLeonid Yegoshin if (op != -1) { 234102cedc3SLeonid Yegoshin mips32_insn.fp0_format.opcode = cop1_op; 235102cedc3SLeonid Yegoshin mips32_insn.fp0_format.fmt = 236102cedc3SLeonid Yegoshin sdps_format[insn.mm_fp2_format.fmt]; 237102cedc3SLeonid Yegoshin mips32_insn.fp0_format.ft = 238102cedc3SLeonid Yegoshin (insn.mm_fp2_format.cc<<2) + op; 239102cedc3SLeonid Yegoshin mips32_insn.fp0_format.fs = 240102cedc3SLeonid Yegoshin insn.mm_fp2_format.fs; 241102cedc3SLeonid Yegoshin mips32_insn.fp0_format.fd = 242102cedc3SLeonid Yegoshin insn.mm_fp2_format.fd; 243102cedc3SLeonid Yegoshin mips32_insn.fp0_format.func = fmovc_op; 244102cedc3SLeonid Yegoshin } else 245102cedc3SLeonid Yegoshin return SIGILL; 246102cedc3SLeonid Yegoshin break; 247102cedc3SLeonid Yegoshin case mm_32f_60_op: 248102cedc3SLeonid Yegoshin func = -1; /* Invalid */ 249102cedc3SLeonid Yegoshin if (insn.mm_fp0_format.op == mm_fadd_op) 250102cedc3SLeonid Yegoshin func = fadd_op; 251102cedc3SLeonid Yegoshin else if (insn.mm_fp0_format.op == mm_fsub_op) 252102cedc3SLeonid Yegoshin func = fsub_op; 253102cedc3SLeonid Yegoshin else if (insn.mm_fp0_format.op == mm_fmul_op) 254102cedc3SLeonid Yegoshin func = fmul_op; 255102cedc3SLeonid Yegoshin else if (insn.mm_fp0_format.op == mm_fdiv_op) 256102cedc3SLeonid Yegoshin func = fdiv_op; 257102cedc3SLeonid Yegoshin if (func != -1) { 258102cedc3SLeonid Yegoshin mips32_insn.fp0_format.opcode = cop1_op; 259102cedc3SLeonid Yegoshin mips32_insn.fp0_format.fmt = 260102cedc3SLeonid Yegoshin sdps_format[insn.mm_fp0_format.fmt]; 261102cedc3SLeonid Yegoshin mips32_insn.fp0_format.ft = 262102cedc3SLeonid Yegoshin insn.mm_fp0_format.ft; 263102cedc3SLeonid Yegoshin mips32_insn.fp0_format.fs = 264102cedc3SLeonid Yegoshin insn.mm_fp0_format.fs; 265102cedc3SLeonid Yegoshin mips32_insn.fp0_format.fd = 266102cedc3SLeonid Yegoshin insn.mm_fp0_format.fd; 267102cedc3SLeonid Yegoshin mips32_insn.fp0_format.func = func; 268102cedc3SLeonid Yegoshin } else 269102cedc3SLeonid Yegoshin return SIGILL; 270102cedc3SLeonid Yegoshin break; 271102cedc3SLeonid Yegoshin case mm_32f_70_op: 272102cedc3SLeonid Yegoshin func = -1; /* Invalid */ 273102cedc3SLeonid Yegoshin if (insn.mm_fp0_format.op == mm_fmovn_op) 274102cedc3SLeonid Yegoshin func = fmovn_op; 275102cedc3SLeonid Yegoshin else if (insn.mm_fp0_format.op == mm_fmovz_op) 276102cedc3SLeonid Yegoshin func = fmovz_op; 277102cedc3SLeonid Yegoshin if (func != -1) { 278102cedc3SLeonid Yegoshin mips32_insn.fp0_format.opcode = cop1_op; 279102cedc3SLeonid Yegoshin mips32_insn.fp0_format.fmt = 280102cedc3SLeonid Yegoshin sdps_format[insn.mm_fp0_format.fmt]; 281102cedc3SLeonid Yegoshin mips32_insn.fp0_format.ft = 282102cedc3SLeonid Yegoshin insn.mm_fp0_format.ft; 283102cedc3SLeonid Yegoshin mips32_insn.fp0_format.fs = 284102cedc3SLeonid Yegoshin insn.mm_fp0_format.fs; 285102cedc3SLeonid Yegoshin mips32_insn.fp0_format.fd = 286102cedc3SLeonid Yegoshin insn.mm_fp0_format.fd; 287102cedc3SLeonid Yegoshin mips32_insn.fp0_format.func = func; 288102cedc3SLeonid Yegoshin } else 289102cedc3SLeonid Yegoshin return SIGILL; 290102cedc3SLeonid Yegoshin break; 291102cedc3SLeonid Yegoshin case mm_32f_73_op: /* POOL32FXF */ 292102cedc3SLeonid Yegoshin switch (insn.mm_fp1_format.op) { 293102cedc3SLeonid Yegoshin case mm_movf0_op: 294102cedc3SLeonid Yegoshin case mm_movf1_op: 295102cedc3SLeonid Yegoshin case mm_movt0_op: 296102cedc3SLeonid Yegoshin case mm_movt1_op: 297102cedc3SLeonid Yegoshin if ((insn.mm_fp1_format.op & 0x7f) == 298102cedc3SLeonid Yegoshin mm_movf0_op) 299102cedc3SLeonid Yegoshin op = 0; 300102cedc3SLeonid Yegoshin else 301102cedc3SLeonid Yegoshin op = 1; 302102cedc3SLeonid Yegoshin mips32_insn.r_format.opcode = spec_op; 303102cedc3SLeonid Yegoshin mips32_insn.r_format.rs = insn.mm_fp4_format.fs; 304102cedc3SLeonid Yegoshin mips32_insn.r_format.rt = 305102cedc3SLeonid Yegoshin (insn.mm_fp4_format.cc << 2) + op; 306102cedc3SLeonid Yegoshin mips32_insn.r_format.rd = insn.mm_fp4_format.rt; 307102cedc3SLeonid Yegoshin mips32_insn.r_format.re = 0; 308102cedc3SLeonid Yegoshin mips32_insn.r_format.func = movc_op; 309102cedc3SLeonid Yegoshin break; 310102cedc3SLeonid Yegoshin case mm_fcvtd0_op: 311102cedc3SLeonid Yegoshin case mm_fcvtd1_op: 312102cedc3SLeonid Yegoshin case mm_fcvts0_op: 313102cedc3SLeonid Yegoshin case mm_fcvts1_op: 314102cedc3SLeonid Yegoshin if ((insn.mm_fp1_format.op & 0x7f) == 315102cedc3SLeonid Yegoshin mm_fcvtd0_op) { 316102cedc3SLeonid Yegoshin func = fcvtd_op; 317102cedc3SLeonid Yegoshin fmt = swl_format[insn.mm_fp3_format.fmt]; 318102cedc3SLeonid Yegoshin } else { 319102cedc3SLeonid Yegoshin func = fcvts_op; 320102cedc3SLeonid Yegoshin fmt = dwl_format[insn.mm_fp3_format.fmt]; 321102cedc3SLeonid Yegoshin } 322102cedc3SLeonid Yegoshin mips32_insn.fp0_format.opcode = cop1_op; 323102cedc3SLeonid Yegoshin mips32_insn.fp0_format.fmt = fmt; 324102cedc3SLeonid Yegoshin mips32_insn.fp0_format.ft = 0; 325102cedc3SLeonid Yegoshin mips32_insn.fp0_format.fs = 326102cedc3SLeonid Yegoshin insn.mm_fp3_format.fs; 327102cedc3SLeonid Yegoshin mips32_insn.fp0_format.fd = 328102cedc3SLeonid Yegoshin insn.mm_fp3_format.rt; 329102cedc3SLeonid Yegoshin mips32_insn.fp0_format.func = func; 330102cedc3SLeonid Yegoshin break; 331102cedc3SLeonid Yegoshin case mm_fmov0_op: 332102cedc3SLeonid Yegoshin case mm_fmov1_op: 333102cedc3SLeonid Yegoshin case mm_fabs0_op: 334102cedc3SLeonid Yegoshin case mm_fabs1_op: 335102cedc3SLeonid Yegoshin case mm_fneg0_op: 336102cedc3SLeonid Yegoshin case mm_fneg1_op: 337102cedc3SLeonid Yegoshin if ((insn.mm_fp1_format.op & 0x7f) == 338102cedc3SLeonid Yegoshin mm_fmov0_op) 339102cedc3SLeonid Yegoshin func = fmov_op; 340102cedc3SLeonid Yegoshin else if ((insn.mm_fp1_format.op & 0x7f) == 341102cedc3SLeonid Yegoshin mm_fabs0_op) 342102cedc3SLeonid Yegoshin func = fabs_op; 343102cedc3SLeonid Yegoshin else 344102cedc3SLeonid Yegoshin func = fneg_op; 345102cedc3SLeonid Yegoshin mips32_insn.fp0_format.opcode = cop1_op; 346102cedc3SLeonid Yegoshin mips32_insn.fp0_format.fmt = 347102cedc3SLeonid Yegoshin sdps_format[insn.mm_fp3_format.fmt]; 348102cedc3SLeonid Yegoshin mips32_insn.fp0_format.ft = 0; 349102cedc3SLeonid Yegoshin mips32_insn.fp0_format.fs = 350102cedc3SLeonid Yegoshin insn.mm_fp3_format.fs; 351102cedc3SLeonid Yegoshin mips32_insn.fp0_format.fd = 352102cedc3SLeonid Yegoshin insn.mm_fp3_format.rt; 353102cedc3SLeonid Yegoshin mips32_insn.fp0_format.func = func; 354102cedc3SLeonid Yegoshin break; 355102cedc3SLeonid Yegoshin case mm_ffloorl_op: 356102cedc3SLeonid Yegoshin case mm_ffloorw_op: 357102cedc3SLeonid Yegoshin case mm_fceill_op: 358102cedc3SLeonid Yegoshin case mm_fceilw_op: 359102cedc3SLeonid Yegoshin case mm_ftruncl_op: 360102cedc3SLeonid Yegoshin case mm_ftruncw_op: 361102cedc3SLeonid Yegoshin case mm_froundl_op: 362102cedc3SLeonid Yegoshin case mm_froundw_op: 363102cedc3SLeonid Yegoshin case mm_fcvtl_op: 364102cedc3SLeonid Yegoshin case mm_fcvtw_op: 365102cedc3SLeonid Yegoshin if (insn.mm_fp1_format.op == mm_ffloorl_op) 366102cedc3SLeonid Yegoshin func = ffloorl_op; 367102cedc3SLeonid Yegoshin else if (insn.mm_fp1_format.op == mm_ffloorw_op) 368102cedc3SLeonid Yegoshin func = ffloor_op; 369102cedc3SLeonid Yegoshin else if (insn.mm_fp1_format.op == mm_fceill_op) 370102cedc3SLeonid Yegoshin func = fceill_op; 371102cedc3SLeonid Yegoshin else if (insn.mm_fp1_format.op == mm_fceilw_op) 372102cedc3SLeonid Yegoshin func = fceil_op; 373102cedc3SLeonid Yegoshin else if (insn.mm_fp1_format.op == mm_ftruncl_op) 374102cedc3SLeonid Yegoshin func = ftruncl_op; 375102cedc3SLeonid Yegoshin else if (insn.mm_fp1_format.op == mm_ftruncw_op) 376102cedc3SLeonid Yegoshin func = ftrunc_op; 377102cedc3SLeonid Yegoshin else if (insn.mm_fp1_format.op == mm_froundl_op) 378102cedc3SLeonid Yegoshin func = froundl_op; 379102cedc3SLeonid Yegoshin else if (insn.mm_fp1_format.op == mm_froundw_op) 380102cedc3SLeonid Yegoshin func = fround_op; 381102cedc3SLeonid Yegoshin else if (insn.mm_fp1_format.op == mm_fcvtl_op) 382102cedc3SLeonid Yegoshin func = fcvtl_op; 383102cedc3SLeonid Yegoshin else 384102cedc3SLeonid Yegoshin func = fcvtw_op; 385102cedc3SLeonid Yegoshin mips32_insn.fp0_format.opcode = cop1_op; 386102cedc3SLeonid Yegoshin mips32_insn.fp0_format.fmt = 387102cedc3SLeonid Yegoshin sd_format[insn.mm_fp1_format.fmt]; 388102cedc3SLeonid Yegoshin mips32_insn.fp0_format.ft = 0; 389102cedc3SLeonid Yegoshin mips32_insn.fp0_format.fs = 390102cedc3SLeonid Yegoshin insn.mm_fp1_format.fs; 391102cedc3SLeonid Yegoshin mips32_insn.fp0_format.fd = 392102cedc3SLeonid Yegoshin insn.mm_fp1_format.rt; 393102cedc3SLeonid Yegoshin mips32_insn.fp0_format.func = func; 394102cedc3SLeonid Yegoshin break; 395102cedc3SLeonid Yegoshin case mm_frsqrt_op: 396102cedc3SLeonid Yegoshin case mm_fsqrt_op: 397102cedc3SLeonid Yegoshin case mm_frecip_op: 398102cedc3SLeonid Yegoshin if (insn.mm_fp1_format.op == mm_frsqrt_op) 399102cedc3SLeonid Yegoshin func = frsqrt_op; 400102cedc3SLeonid Yegoshin else if (insn.mm_fp1_format.op == mm_fsqrt_op) 401102cedc3SLeonid Yegoshin func = fsqrt_op; 402102cedc3SLeonid Yegoshin else 403102cedc3SLeonid Yegoshin func = frecip_op; 404102cedc3SLeonid Yegoshin mips32_insn.fp0_format.opcode = cop1_op; 405102cedc3SLeonid Yegoshin mips32_insn.fp0_format.fmt = 406102cedc3SLeonid Yegoshin sdps_format[insn.mm_fp1_format.fmt]; 407102cedc3SLeonid Yegoshin mips32_insn.fp0_format.ft = 0; 408102cedc3SLeonid Yegoshin mips32_insn.fp0_format.fs = 409102cedc3SLeonid Yegoshin insn.mm_fp1_format.fs; 410102cedc3SLeonid Yegoshin mips32_insn.fp0_format.fd = 411102cedc3SLeonid Yegoshin insn.mm_fp1_format.rt; 412102cedc3SLeonid Yegoshin mips32_insn.fp0_format.func = func; 413102cedc3SLeonid Yegoshin break; 414102cedc3SLeonid Yegoshin case mm_mfc1_op: 415102cedc3SLeonid Yegoshin case mm_mtc1_op: 416102cedc3SLeonid Yegoshin case mm_cfc1_op: 417102cedc3SLeonid Yegoshin case mm_ctc1_op: 4189355e59cSSteven J. Hill case mm_mfhc1_op: 4199355e59cSSteven J. Hill case mm_mthc1_op: 420102cedc3SLeonid Yegoshin if (insn.mm_fp1_format.op == mm_mfc1_op) 421102cedc3SLeonid Yegoshin op = mfc_op; 422102cedc3SLeonid Yegoshin else if (insn.mm_fp1_format.op == mm_mtc1_op) 423102cedc3SLeonid Yegoshin op = mtc_op; 424102cedc3SLeonid Yegoshin else if (insn.mm_fp1_format.op == mm_cfc1_op) 425102cedc3SLeonid Yegoshin op = cfc_op; 4269355e59cSSteven J. Hill else if (insn.mm_fp1_format.op == mm_ctc1_op) 427102cedc3SLeonid Yegoshin op = ctc_op; 4289355e59cSSteven J. Hill else if (insn.mm_fp1_format.op == mm_mfhc1_op) 4299355e59cSSteven J. Hill op = mfhc_op; 4309355e59cSSteven J. Hill else 4319355e59cSSteven J. Hill op = mthc_op; 432102cedc3SLeonid Yegoshin mips32_insn.fp1_format.opcode = cop1_op; 433102cedc3SLeonid Yegoshin mips32_insn.fp1_format.op = op; 434102cedc3SLeonid Yegoshin mips32_insn.fp1_format.rt = 435102cedc3SLeonid Yegoshin insn.mm_fp1_format.rt; 436102cedc3SLeonid Yegoshin mips32_insn.fp1_format.fs = 437102cedc3SLeonid Yegoshin insn.mm_fp1_format.fs; 438102cedc3SLeonid Yegoshin mips32_insn.fp1_format.fd = 0; 439102cedc3SLeonid Yegoshin mips32_insn.fp1_format.func = 0; 440102cedc3SLeonid Yegoshin break; 441102cedc3SLeonid Yegoshin default: 442102cedc3SLeonid Yegoshin return SIGILL; 443102cedc3SLeonid Yegoshin } 444102cedc3SLeonid Yegoshin break; 445102cedc3SLeonid Yegoshin case mm_32f_74_op: /* c.cond.fmt */ 446102cedc3SLeonid Yegoshin mips32_insn.fp0_format.opcode = cop1_op; 447102cedc3SLeonid Yegoshin mips32_insn.fp0_format.fmt = 448102cedc3SLeonid Yegoshin sdps_format[insn.mm_fp4_format.fmt]; 449102cedc3SLeonid Yegoshin mips32_insn.fp0_format.ft = insn.mm_fp4_format.rt; 450102cedc3SLeonid Yegoshin mips32_insn.fp0_format.fs = insn.mm_fp4_format.fs; 451102cedc3SLeonid Yegoshin mips32_insn.fp0_format.fd = insn.mm_fp4_format.cc << 2; 452102cedc3SLeonid Yegoshin mips32_insn.fp0_format.func = 453102cedc3SLeonid Yegoshin insn.mm_fp4_format.cond | MM_MIPS32_COND_FC; 454102cedc3SLeonid Yegoshin break; 455102cedc3SLeonid Yegoshin default: 456102cedc3SLeonid Yegoshin return SIGILL; 457102cedc3SLeonid Yegoshin } 458102cedc3SLeonid Yegoshin break; 459102cedc3SLeonid Yegoshin default: 460102cedc3SLeonid Yegoshin return SIGILL; 461102cedc3SLeonid Yegoshin } 462102cedc3SLeonid Yegoshin 463102cedc3SLeonid Yegoshin *insn_ptr = mips32_insn; 464102cedc3SLeonid Yegoshin return 0; 465102cedc3SLeonid Yegoshin } 466102cedc3SLeonid Yegoshin 467102cedc3SLeonid Yegoshin int mm_isBranchInstr(struct pt_regs *regs, struct mm_decoded_insn dec_insn, 468102cedc3SLeonid Yegoshin unsigned long *contpc) 469102cedc3SLeonid Yegoshin { 470102cedc3SLeonid Yegoshin union mips_instruction insn = (union mips_instruction)dec_insn.insn; 471102cedc3SLeonid Yegoshin int bc_false = 0; 472102cedc3SLeonid Yegoshin unsigned int fcr31; 473102cedc3SLeonid Yegoshin unsigned int bit; 474102cedc3SLeonid Yegoshin 475fe6d2909SDavid Daney if (!cpu_has_mmips) 476fe6d2909SDavid Daney return 0; 477fe6d2909SDavid Daney 478102cedc3SLeonid Yegoshin switch (insn.mm_i_format.opcode) { 479102cedc3SLeonid Yegoshin case mm_pool32a_op: 480102cedc3SLeonid Yegoshin if ((insn.mm_i_format.simmediate & MM_POOL32A_MINOR_MASK) == 481102cedc3SLeonid Yegoshin mm_pool32axf_op) { 482102cedc3SLeonid Yegoshin switch (insn.mm_i_format.simmediate >> 483102cedc3SLeonid Yegoshin MM_POOL32A_MINOR_SHIFT) { 484102cedc3SLeonid Yegoshin case mm_jalr_op: 485102cedc3SLeonid Yegoshin case mm_jalrhb_op: 486102cedc3SLeonid Yegoshin case mm_jalrs_op: 487102cedc3SLeonid Yegoshin case mm_jalrshb_op: 488102cedc3SLeonid Yegoshin if (insn.mm_i_format.rt != 0) /* Not mm_jr */ 489102cedc3SLeonid Yegoshin regs->regs[insn.mm_i_format.rt] = 490102cedc3SLeonid Yegoshin regs->cp0_epc + 491102cedc3SLeonid Yegoshin dec_insn.pc_inc + 492102cedc3SLeonid Yegoshin dec_insn.next_pc_inc; 493102cedc3SLeonid Yegoshin *contpc = regs->regs[insn.mm_i_format.rs]; 494102cedc3SLeonid Yegoshin return 1; 495102cedc3SLeonid Yegoshin } 496102cedc3SLeonid Yegoshin } 497102cedc3SLeonid Yegoshin break; 498102cedc3SLeonid Yegoshin case mm_pool32i_op: 499102cedc3SLeonid Yegoshin switch (insn.mm_i_format.rt) { 500102cedc3SLeonid Yegoshin case mm_bltzals_op: 501102cedc3SLeonid Yegoshin case mm_bltzal_op: 502102cedc3SLeonid Yegoshin regs->regs[31] = regs->cp0_epc + 503102cedc3SLeonid Yegoshin dec_insn.pc_inc + 504102cedc3SLeonid Yegoshin dec_insn.next_pc_inc; 505102cedc3SLeonid Yegoshin /* Fall through */ 506102cedc3SLeonid Yegoshin case mm_bltz_op: 507102cedc3SLeonid Yegoshin if ((long)regs->regs[insn.mm_i_format.rs] < 0) 508102cedc3SLeonid Yegoshin *contpc = regs->cp0_epc + 509102cedc3SLeonid Yegoshin dec_insn.pc_inc + 510102cedc3SLeonid Yegoshin (insn.mm_i_format.simmediate << 1); 511102cedc3SLeonid Yegoshin else 512102cedc3SLeonid Yegoshin *contpc = regs->cp0_epc + 513102cedc3SLeonid Yegoshin dec_insn.pc_inc + 514102cedc3SLeonid Yegoshin dec_insn.next_pc_inc; 515102cedc3SLeonid Yegoshin return 1; 516102cedc3SLeonid Yegoshin case mm_bgezals_op: 517102cedc3SLeonid Yegoshin case mm_bgezal_op: 518102cedc3SLeonid Yegoshin regs->regs[31] = regs->cp0_epc + 519102cedc3SLeonid Yegoshin dec_insn.pc_inc + 520102cedc3SLeonid Yegoshin dec_insn.next_pc_inc; 521102cedc3SLeonid Yegoshin /* Fall through */ 522102cedc3SLeonid Yegoshin case mm_bgez_op: 523102cedc3SLeonid Yegoshin if ((long)regs->regs[insn.mm_i_format.rs] >= 0) 524102cedc3SLeonid Yegoshin *contpc = regs->cp0_epc + 525102cedc3SLeonid Yegoshin dec_insn.pc_inc + 526102cedc3SLeonid Yegoshin (insn.mm_i_format.simmediate << 1); 527102cedc3SLeonid Yegoshin else 528102cedc3SLeonid Yegoshin *contpc = regs->cp0_epc + 529102cedc3SLeonid Yegoshin dec_insn.pc_inc + 530102cedc3SLeonid Yegoshin dec_insn.next_pc_inc; 531102cedc3SLeonid Yegoshin return 1; 532102cedc3SLeonid Yegoshin case mm_blez_op: 533102cedc3SLeonid Yegoshin if ((long)regs->regs[insn.mm_i_format.rs] <= 0) 534102cedc3SLeonid Yegoshin *contpc = regs->cp0_epc + 535102cedc3SLeonid Yegoshin dec_insn.pc_inc + 536102cedc3SLeonid Yegoshin (insn.mm_i_format.simmediate << 1); 537102cedc3SLeonid Yegoshin else 538102cedc3SLeonid Yegoshin *contpc = regs->cp0_epc + 539102cedc3SLeonid Yegoshin dec_insn.pc_inc + 540102cedc3SLeonid Yegoshin dec_insn.next_pc_inc; 541102cedc3SLeonid Yegoshin return 1; 542102cedc3SLeonid Yegoshin case mm_bgtz_op: 543102cedc3SLeonid Yegoshin if ((long)regs->regs[insn.mm_i_format.rs] <= 0) 544102cedc3SLeonid Yegoshin *contpc = regs->cp0_epc + 545102cedc3SLeonid Yegoshin dec_insn.pc_inc + 546102cedc3SLeonid Yegoshin (insn.mm_i_format.simmediate << 1); 547102cedc3SLeonid Yegoshin else 548102cedc3SLeonid Yegoshin *contpc = regs->cp0_epc + 549102cedc3SLeonid Yegoshin dec_insn.pc_inc + 550102cedc3SLeonid Yegoshin dec_insn.next_pc_inc; 551102cedc3SLeonid Yegoshin return 1; 552102cedc3SLeonid Yegoshin case mm_bc2f_op: 553102cedc3SLeonid Yegoshin case mm_bc1f_op: 554102cedc3SLeonid Yegoshin bc_false = 1; 555102cedc3SLeonid Yegoshin /* Fall through */ 556102cedc3SLeonid Yegoshin case mm_bc2t_op: 557102cedc3SLeonid Yegoshin case mm_bc1t_op: 558102cedc3SLeonid Yegoshin preempt_disable(); 559102cedc3SLeonid Yegoshin if (is_fpu_owner()) 560102cedc3SLeonid Yegoshin asm volatile("cfc1\t%0,$31" : "=r" (fcr31)); 561102cedc3SLeonid Yegoshin else 562102cedc3SLeonid Yegoshin fcr31 = current->thread.fpu.fcr31; 563102cedc3SLeonid Yegoshin preempt_enable(); 564102cedc3SLeonid Yegoshin 565102cedc3SLeonid Yegoshin if (bc_false) 566102cedc3SLeonid Yegoshin fcr31 = ~fcr31; 567102cedc3SLeonid Yegoshin 568102cedc3SLeonid Yegoshin bit = (insn.mm_i_format.rs >> 2); 569102cedc3SLeonid Yegoshin bit += (bit != 0); 570102cedc3SLeonid Yegoshin bit += 23; 571102cedc3SLeonid Yegoshin if (fcr31 & (1 << bit)) 572102cedc3SLeonid Yegoshin *contpc = regs->cp0_epc + 573102cedc3SLeonid Yegoshin dec_insn.pc_inc + 574102cedc3SLeonid Yegoshin (insn.mm_i_format.simmediate << 1); 575102cedc3SLeonid Yegoshin else 576102cedc3SLeonid Yegoshin *contpc = regs->cp0_epc + 577102cedc3SLeonid Yegoshin dec_insn.pc_inc + dec_insn.next_pc_inc; 578102cedc3SLeonid Yegoshin return 1; 579102cedc3SLeonid Yegoshin } 580102cedc3SLeonid Yegoshin break; 581102cedc3SLeonid Yegoshin case mm_pool16c_op: 582102cedc3SLeonid Yegoshin switch (insn.mm_i_format.rt) { 583102cedc3SLeonid Yegoshin case mm_jalr16_op: 584102cedc3SLeonid Yegoshin case mm_jalrs16_op: 585102cedc3SLeonid Yegoshin regs->regs[31] = regs->cp0_epc + 586102cedc3SLeonid Yegoshin dec_insn.pc_inc + dec_insn.next_pc_inc; 587102cedc3SLeonid Yegoshin /* Fall through */ 588102cedc3SLeonid Yegoshin case mm_jr16_op: 589102cedc3SLeonid Yegoshin *contpc = regs->regs[insn.mm_i_format.rs]; 590102cedc3SLeonid Yegoshin return 1; 591102cedc3SLeonid Yegoshin } 592102cedc3SLeonid Yegoshin break; 593102cedc3SLeonid Yegoshin case mm_beqz16_op: 594102cedc3SLeonid Yegoshin if ((long)regs->regs[reg16to32map[insn.mm_b1_format.rs]] == 0) 595102cedc3SLeonid Yegoshin *contpc = regs->cp0_epc + 596102cedc3SLeonid Yegoshin dec_insn.pc_inc + 597102cedc3SLeonid Yegoshin (insn.mm_b1_format.simmediate << 1); 598102cedc3SLeonid Yegoshin else 599102cedc3SLeonid Yegoshin *contpc = regs->cp0_epc + 600102cedc3SLeonid Yegoshin dec_insn.pc_inc + dec_insn.next_pc_inc; 601102cedc3SLeonid Yegoshin return 1; 602102cedc3SLeonid Yegoshin case mm_bnez16_op: 603102cedc3SLeonid Yegoshin if ((long)regs->regs[reg16to32map[insn.mm_b1_format.rs]] != 0) 604102cedc3SLeonid Yegoshin *contpc = regs->cp0_epc + 605102cedc3SLeonid Yegoshin dec_insn.pc_inc + 606102cedc3SLeonid Yegoshin (insn.mm_b1_format.simmediate << 1); 607102cedc3SLeonid Yegoshin else 608102cedc3SLeonid Yegoshin *contpc = regs->cp0_epc + 609102cedc3SLeonid Yegoshin dec_insn.pc_inc + dec_insn.next_pc_inc; 610102cedc3SLeonid Yegoshin return 1; 611102cedc3SLeonid Yegoshin case mm_b16_op: 612102cedc3SLeonid Yegoshin *contpc = regs->cp0_epc + dec_insn.pc_inc + 613102cedc3SLeonid Yegoshin (insn.mm_b0_format.simmediate << 1); 614102cedc3SLeonid Yegoshin return 1; 615102cedc3SLeonid Yegoshin case mm_beq32_op: 616102cedc3SLeonid Yegoshin if (regs->regs[insn.mm_i_format.rs] == 617102cedc3SLeonid Yegoshin regs->regs[insn.mm_i_format.rt]) 618102cedc3SLeonid Yegoshin *contpc = regs->cp0_epc + 619102cedc3SLeonid Yegoshin dec_insn.pc_inc + 620102cedc3SLeonid Yegoshin (insn.mm_i_format.simmediate << 1); 621102cedc3SLeonid Yegoshin else 622102cedc3SLeonid Yegoshin *contpc = regs->cp0_epc + 623102cedc3SLeonid Yegoshin dec_insn.pc_inc + 624102cedc3SLeonid Yegoshin dec_insn.next_pc_inc; 625102cedc3SLeonid Yegoshin return 1; 626102cedc3SLeonid Yegoshin case mm_bne32_op: 627102cedc3SLeonid Yegoshin if (regs->regs[insn.mm_i_format.rs] != 628102cedc3SLeonid Yegoshin regs->regs[insn.mm_i_format.rt]) 629102cedc3SLeonid Yegoshin *contpc = regs->cp0_epc + 630102cedc3SLeonid Yegoshin dec_insn.pc_inc + 631102cedc3SLeonid Yegoshin (insn.mm_i_format.simmediate << 1); 632102cedc3SLeonid Yegoshin else 633102cedc3SLeonid Yegoshin *contpc = regs->cp0_epc + 634102cedc3SLeonid Yegoshin dec_insn.pc_inc + dec_insn.next_pc_inc; 635102cedc3SLeonid Yegoshin return 1; 636102cedc3SLeonid Yegoshin case mm_jalx32_op: 637102cedc3SLeonid Yegoshin regs->regs[31] = regs->cp0_epc + 638102cedc3SLeonid Yegoshin dec_insn.pc_inc + dec_insn.next_pc_inc; 639102cedc3SLeonid Yegoshin *contpc = regs->cp0_epc + dec_insn.pc_inc; 640102cedc3SLeonid Yegoshin *contpc >>= 28; 641102cedc3SLeonid Yegoshin *contpc <<= 28; 642102cedc3SLeonid Yegoshin *contpc |= (insn.j_format.target << 2); 643102cedc3SLeonid Yegoshin return 1; 644102cedc3SLeonid Yegoshin case mm_jals32_op: 645102cedc3SLeonid Yegoshin case mm_jal32_op: 646102cedc3SLeonid Yegoshin regs->regs[31] = regs->cp0_epc + 647102cedc3SLeonid Yegoshin dec_insn.pc_inc + dec_insn.next_pc_inc; 648102cedc3SLeonid Yegoshin /* Fall through */ 649102cedc3SLeonid Yegoshin case mm_j32_op: 650102cedc3SLeonid Yegoshin *contpc = regs->cp0_epc + dec_insn.pc_inc; 651102cedc3SLeonid Yegoshin *contpc >>= 27; 652102cedc3SLeonid Yegoshin *contpc <<= 27; 653102cedc3SLeonid Yegoshin *contpc |= (insn.j_format.target << 1); 654102cedc3SLeonid Yegoshin set_isa16_mode(*contpc); 655102cedc3SLeonid Yegoshin return 1; 656102cedc3SLeonid Yegoshin } 657102cedc3SLeonid Yegoshin return 0; 658102cedc3SLeonid Yegoshin } 6591da177e4SLinus Torvalds 6601da177e4SLinus Torvalds /* 6611da177e4SLinus Torvalds * Redundant with logic already in kernel/branch.c, 6621da177e4SLinus Torvalds * embedded in compute_return_epc. At some point, 6631da177e4SLinus Torvalds * a single subroutine should be used across both 6641da177e4SLinus Torvalds * modules. 6651da177e4SLinus Torvalds */ 666102cedc3SLeonid Yegoshin static int isBranchInstr(struct pt_regs *regs, struct mm_decoded_insn dec_insn, 667102cedc3SLeonid Yegoshin unsigned long *contpc) 6681da177e4SLinus Torvalds { 669102cedc3SLeonid Yegoshin union mips_instruction insn = (union mips_instruction)dec_insn.insn; 670102cedc3SLeonid Yegoshin unsigned int fcr31; 671102cedc3SLeonid Yegoshin unsigned int bit = 0; 672102cedc3SLeonid Yegoshin 673102cedc3SLeonid Yegoshin switch (insn.i_format.opcode) { 6741da177e4SLinus Torvalds case spec_op: 675102cedc3SLeonid Yegoshin switch (insn.r_format.func) { 6761da177e4SLinus Torvalds case jalr_op: 677102cedc3SLeonid Yegoshin regs->regs[insn.r_format.rd] = 678102cedc3SLeonid Yegoshin regs->cp0_epc + dec_insn.pc_inc + 679102cedc3SLeonid Yegoshin dec_insn.next_pc_inc; 680102cedc3SLeonid Yegoshin /* Fall through */ 6811da177e4SLinus Torvalds case jr_op: 682102cedc3SLeonid Yegoshin *contpc = regs->regs[insn.r_format.rs]; 6831da177e4SLinus Torvalds return 1; 6841da177e4SLinus Torvalds } 6851da177e4SLinus Torvalds break; 6861da177e4SLinus Torvalds case bcond_op: 687102cedc3SLeonid Yegoshin switch (insn.i_format.rt) { 6881da177e4SLinus Torvalds case bltzal_op: 6891da177e4SLinus Torvalds case bltzall_op: 690102cedc3SLeonid Yegoshin regs->regs[31] = regs->cp0_epc + 691102cedc3SLeonid Yegoshin dec_insn.pc_inc + 692102cedc3SLeonid Yegoshin dec_insn.next_pc_inc; 693102cedc3SLeonid Yegoshin /* Fall through */ 694102cedc3SLeonid Yegoshin case bltz_op: 695102cedc3SLeonid Yegoshin case bltzl_op: 696102cedc3SLeonid Yegoshin if ((long)regs->regs[insn.i_format.rs] < 0) 697102cedc3SLeonid Yegoshin *contpc = regs->cp0_epc + 698102cedc3SLeonid Yegoshin dec_insn.pc_inc + 699102cedc3SLeonid Yegoshin (insn.i_format.simmediate << 2); 700102cedc3SLeonid Yegoshin else 701102cedc3SLeonid Yegoshin *contpc = regs->cp0_epc + 702102cedc3SLeonid Yegoshin dec_insn.pc_inc + 703102cedc3SLeonid Yegoshin dec_insn.next_pc_inc; 7041da177e4SLinus Torvalds return 1; 705102cedc3SLeonid Yegoshin case bgezal_op: 706102cedc3SLeonid Yegoshin case bgezall_op: 707102cedc3SLeonid Yegoshin regs->regs[31] = regs->cp0_epc + 708102cedc3SLeonid Yegoshin dec_insn.pc_inc + 709102cedc3SLeonid Yegoshin dec_insn.next_pc_inc; 710102cedc3SLeonid Yegoshin /* Fall through */ 711102cedc3SLeonid Yegoshin case bgez_op: 712102cedc3SLeonid Yegoshin case bgezl_op: 713102cedc3SLeonid Yegoshin if ((long)regs->regs[insn.i_format.rs] >= 0) 714102cedc3SLeonid Yegoshin *contpc = regs->cp0_epc + 715102cedc3SLeonid Yegoshin dec_insn.pc_inc + 716102cedc3SLeonid Yegoshin (insn.i_format.simmediate << 2); 717102cedc3SLeonid Yegoshin else 718102cedc3SLeonid Yegoshin *contpc = regs->cp0_epc + 719102cedc3SLeonid Yegoshin dec_insn.pc_inc + 720102cedc3SLeonid Yegoshin dec_insn.next_pc_inc; 721102cedc3SLeonid Yegoshin return 1; 7221da177e4SLinus Torvalds } 7231da177e4SLinus Torvalds break; 7241da177e4SLinus Torvalds case jalx_op: 725102cedc3SLeonid Yegoshin set_isa16_mode(bit); 726102cedc3SLeonid Yegoshin case jal_op: 727102cedc3SLeonid Yegoshin regs->regs[31] = regs->cp0_epc + 728102cedc3SLeonid Yegoshin dec_insn.pc_inc + 729102cedc3SLeonid Yegoshin dec_insn.next_pc_inc; 730102cedc3SLeonid Yegoshin /* Fall through */ 731102cedc3SLeonid Yegoshin case j_op: 732102cedc3SLeonid Yegoshin *contpc = regs->cp0_epc + dec_insn.pc_inc; 733102cedc3SLeonid Yegoshin *contpc >>= 28; 734102cedc3SLeonid Yegoshin *contpc <<= 28; 735102cedc3SLeonid Yegoshin *contpc |= (insn.j_format.target << 2); 736102cedc3SLeonid Yegoshin /* Set microMIPS mode bit: XOR for jalx. */ 737102cedc3SLeonid Yegoshin *contpc ^= bit; 7381da177e4SLinus Torvalds return 1; 739102cedc3SLeonid Yegoshin case beq_op: 740102cedc3SLeonid Yegoshin case beql_op: 741102cedc3SLeonid Yegoshin if (regs->regs[insn.i_format.rs] == 742102cedc3SLeonid Yegoshin regs->regs[insn.i_format.rt]) 743102cedc3SLeonid Yegoshin *contpc = regs->cp0_epc + 744102cedc3SLeonid Yegoshin dec_insn.pc_inc + 745102cedc3SLeonid Yegoshin (insn.i_format.simmediate << 2); 746102cedc3SLeonid Yegoshin else 747102cedc3SLeonid Yegoshin *contpc = regs->cp0_epc + 748102cedc3SLeonid Yegoshin dec_insn.pc_inc + 749102cedc3SLeonid Yegoshin dec_insn.next_pc_inc; 750102cedc3SLeonid Yegoshin return 1; 751102cedc3SLeonid Yegoshin case bne_op: 752102cedc3SLeonid Yegoshin case bnel_op: 753102cedc3SLeonid Yegoshin if (regs->regs[insn.i_format.rs] != 754102cedc3SLeonid Yegoshin regs->regs[insn.i_format.rt]) 755102cedc3SLeonid Yegoshin *contpc = regs->cp0_epc + 756102cedc3SLeonid Yegoshin dec_insn.pc_inc + 757102cedc3SLeonid Yegoshin (insn.i_format.simmediate << 2); 758102cedc3SLeonid Yegoshin else 759102cedc3SLeonid Yegoshin *contpc = regs->cp0_epc + 760102cedc3SLeonid Yegoshin dec_insn.pc_inc + 761102cedc3SLeonid Yegoshin dec_insn.next_pc_inc; 762102cedc3SLeonid Yegoshin return 1; 763102cedc3SLeonid Yegoshin case blez_op: 764102cedc3SLeonid Yegoshin case blezl_op: 765102cedc3SLeonid Yegoshin if ((long)regs->regs[insn.i_format.rs] <= 0) 766102cedc3SLeonid Yegoshin *contpc = regs->cp0_epc + 767102cedc3SLeonid Yegoshin dec_insn.pc_inc + 768102cedc3SLeonid Yegoshin (insn.i_format.simmediate << 2); 769102cedc3SLeonid Yegoshin else 770102cedc3SLeonid Yegoshin *contpc = regs->cp0_epc + 771102cedc3SLeonid Yegoshin dec_insn.pc_inc + 772102cedc3SLeonid Yegoshin dec_insn.next_pc_inc; 773102cedc3SLeonid Yegoshin return 1; 774102cedc3SLeonid Yegoshin case bgtz_op: 775102cedc3SLeonid Yegoshin case bgtzl_op: 776102cedc3SLeonid Yegoshin if ((long)regs->regs[insn.i_format.rs] > 0) 777102cedc3SLeonid Yegoshin *contpc = regs->cp0_epc + 778102cedc3SLeonid Yegoshin dec_insn.pc_inc + 779102cedc3SLeonid Yegoshin (insn.i_format.simmediate << 2); 780102cedc3SLeonid Yegoshin else 781102cedc3SLeonid Yegoshin *contpc = regs->cp0_epc + 782102cedc3SLeonid Yegoshin dec_insn.pc_inc + 783102cedc3SLeonid Yegoshin dec_insn.next_pc_inc; 784102cedc3SLeonid Yegoshin return 1; 785c26d4219SDavid Daney #ifdef CONFIG_CPU_CAVIUM_OCTEON 786c26d4219SDavid Daney case lwc2_op: /* This is bbit0 on Octeon */ 787c26d4219SDavid Daney if ((regs->regs[insn.i_format.rs] & (1ull<<insn.i_format.rt)) == 0) 788c26d4219SDavid Daney *contpc = regs->cp0_epc + 4 + (insn.i_format.simmediate << 2); 789c26d4219SDavid Daney else 790c26d4219SDavid Daney *contpc = regs->cp0_epc + 8; 791c26d4219SDavid Daney return 1; 792c26d4219SDavid Daney case ldc2_op: /* This is bbit032 on Octeon */ 793c26d4219SDavid Daney if ((regs->regs[insn.i_format.rs] & (1ull<<(insn.i_format.rt + 32))) == 0) 794c26d4219SDavid Daney *contpc = regs->cp0_epc + 4 + (insn.i_format.simmediate << 2); 795c26d4219SDavid Daney else 796c26d4219SDavid Daney *contpc = regs->cp0_epc + 8; 797c26d4219SDavid Daney return 1; 798c26d4219SDavid Daney case swc2_op: /* This is bbit1 on Octeon */ 799c26d4219SDavid Daney if (regs->regs[insn.i_format.rs] & (1ull<<insn.i_format.rt)) 800c26d4219SDavid Daney *contpc = regs->cp0_epc + 4 + (insn.i_format.simmediate << 2); 801c26d4219SDavid Daney else 802c26d4219SDavid Daney *contpc = regs->cp0_epc + 8; 803c26d4219SDavid Daney return 1; 804c26d4219SDavid Daney case sdc2_op: /* This is bbit132 on Octeon */ 805c26d4219SDavid Daney if (regs->regs[insn.i_format.rs] & (1ull<<(insn.i_format.rt + 32))) 806c26d4219SDavid Daney *contpc = regs->cp0_epc + 4 + (insn.i_format.simmediate << 2); 807c26d4219SDavid Daney else 808c26d4219SDavid Daney *contpc = regs->cp0_epc + 8; 809c26d4219SDavid Daney return 1; 810c26d4219SDavid Daney #endif 8111da177e4SLinus Torvalds case cop0_op: 8121da177e4SLinus Torvalds case cop1_op: 8131da177e4SLinus Torvalds case cop2_op: 8141da177e4SLinus Torvalds case cop1x_op: 815102cedc3SLeonid Yegoshin if (insn.i_format.rs == bc_op) { 816102cedc3SLeonid Yegoshin preempt_disable(); 817102cedc3SLeonid Yegoshin if (is_fpu_owner()) 818102cedc3SLeonid Yegoshin asm volatile("cfc1\t%0,$31" : "=r" (fcr31)); 819102cedc3SLeonid Yegoshin else 820102cedc3SLeonid Yegoshin fcr31 = current->thread.fpu.fcr31; 821102cedc3SLeonid Yegoshin preempt_enable(); 822102cedc3SLeonid Yegoshin 823102cedc3SLeonid Yegoshin bit = (insn.i_format.rt >> 2); 824102cedc3SLeonid Yegoshin bit += (bit != 0); 825102cedc3SLeonid Yegoshin bit += 23; 826102cedc3SLeonid Yegoshin switch (insn.i_format.rt & 3) { 827102cedc3SLeonid Yegoshin case 0: /* bc1f */ 828102cedc3SLeonid Yegoshin case 2: /* bc1fl */ 829102cedc3SLeonid Yegoshin if (~fcr31 & (1 << bit)) 830102cedc3SLeonid Yegoshin *contpc = regs->cp0_epc + 831102cedc3SLeonid Yegoshin dec_insn.pc_inc + 832102cedc3SLeonid Yegoshin (insn.i_format.simmediate << 2); 833102cedc3SLeonid Yegoshin else 834102cedc3SLeonid Yegoshin *contpc = regs->cp0_epc + 835102cedc3SLeonid Yegoshin dec_insn.pc_inc + 836102cedc3SLeonid Yegoshin dec_insn.next_pc_inc; 837102cedc3SLeonid Yegoshin return 1; 838102cedc3SLeonid Yegoshin case 1: /* bc1t */ 839102cedc3SLeonid Yegoshin case 3: /* bc1tl */ 840102cedc3SLeonid Yegoshin if (fcr31 & (1 << bit)) 841102cedc3SLeonid Yegoshin *contpc = regs->cp0_epc + 842102cedc3SLeonid Yegoshin dec_insn.pc_inc + 843102cedc3SLeonid Yegoshin (insn.i_format.simmediate << 2); 844102cedc3SLeonid Yegoshin else 845102cedc3SLeonid Yegoshin *contpc = regs->cp0_epc + 846102cedc3SLeonid Yegoshin dec_insn.pc_inc + 847102cedc3SLeonid Yegoshin dec_insn.next_pc_inc; 8481da177e4SLinus Torvalds return 1; 8491da177e4SLinus Torvalds } 850102cedc3SLeonid Yegoshin } 851102cedc3SLeonid Yegoshin break; 852102cedc3SLeonid Yegoshin } 8531da177e4SLinus Torvalds return 0; 8541da177e4SLinus Torvalds } 8551da177e4SLinus Torvalds 8561da177e4SLinus Torvalds /* 8571da177e4SLinus Torvalds * In the Linux kernel, we support selection of FPR format on the 858da0bac33SDavid Daney * basis of the Status.FR bit. If an FPU is not present, the FR bit 859da0bac33SDavid Daney * is hardwired to zero, which would imply a 32-bit FPU even for 860597ce172SPaul Burton * 64-bit CPUs so we rather look at TIF_32BIT_FPREGS. 86151d943f0SRalf Baechle * FPU emu is slow and bulky and optimizing this function offers fairly 86251d943f0SRalf Baechle * sizeable benefits so we try to be clever and make this function return 86351d943f0SRalf Baechle * a constant whenever possible, that is on 64-bit kernels without O32 864597ce172SPaul Burton * compatibility enabled and on 32-bit without 64-bit FPU support. 8651da177e4SLinus Torvalds */ 866da0bac33SDavid Daney static inline int cop1_64bit(struct pt_regs *xcp) 867da0bac33SDavid Daney { 86851d943f0SRalf Baechle #if defined(CONFIG_64BIT) && !defined(CONFIG_MIPS32_O32) 86951d943f0SRalf Baechle return 1; 870597ce172SPaul Burton #elif defined(CONFIG_32BIT) && !defined(CONFIG_MIPS_O32_FP64_SUPPORT) 871da0bac33SDavid Daney return 0; 872597ce172SPaul Burton #else 873597ce172SPaul Burton return !test_thread_flag(TIF_32BIT_FPREGS); 8741da177e4SLinus Torvalds #endif 875da0bac33SDavid Daney } 8761da177e4SLinus Torvalds 877bbd426f5SPaul Burton #define SIFROMREG(si, x) do { \ 878bbd426f5SPaul Burton if (cop1_64bit(xcp)) \ 879bbd426f5SPaul Burton (si) = get_fpr32(&ctx->fpr[x], 0); \ 880bbd426f5SPaul Burton else \ 881bbd426f5SPaul Burton (si) = get_fpr32(&ctx->fpr[(x) & ~1], (x) & 1); \ 882bbd426f5SPaul Burton } while (0) 883da0bac33SDavid Daney 884bbd426f5SPaul Burton #define SITOREG(si, x) do { \ 885ef1c47afSPaul Burton if (cop1_64bit(xcp)) { \ 886ef1c47afSPaul Burton unsigned i; \ 887bbd426f5SPaul Burton set_fpr32(&ctx->fpr[x], 0, si); \ 888ef1c47afSPaul Burton for (i = 1; i < ARRAY_SIZE(ctx->fpr[x].val32); i++) \ 889ef1c47afSPaul Burton set_fpr32(&ctx->fpr[x], i, 0); \ 890ef1c47afSPaul Burton } else { \ 891bbd426f5SPaul Burton set_fpr32(&ctx->fpr[(x) & ~1], (x) & 1, si); \ 892ef1c47afSPaul Burton } \ 893bbd426f5SPaul Burton } while (0) 8941da177e4SLinus Torvalds 895bbd426f5SPaul Burton #define SIFROMHREG(si, x) ((si) = get_fpr32(&ctx->fpr[x], 1)) 896ef1c47afSPaul Burton 897ef1c47afSPaul Burton #define SITOHREG(si, x) do { \ 898ef1c47afSPaul Burton unsigned i; \ 899ef1c47afSPaul Burton set_fpr32(&ctx->fpr[x], 1, si); \ 900ef1c47afSPaul Burton for (i = 2; i < ARRAY_SIZE(ctx->fpr[x].val32); i++) \ 901ef1c47afSPaul Burton set_fpr32(&ctx->fpr[x], i, 0); \ 902ef1c47afSPaul Burton } while (0) 9031ac94400SLeonid Yegoshin 904bbd426f5SPaul Burton #define DIFROMREG(di, x) \ 905bbd426f5SPaul Burton ((di) = get_fpr64(&ctx->fpr[(x) & ~(cop1_64bit(xcp) == 0)], 0)) 906bbd426f5SPaul Burton 907ef1c47afSPaul Burton #define DITOREG(di, x) do { \ 908ef1c47afSPaul Burton unsigned fpr, i; \ 909ef1c47afSPaul Burton fpr = (x) & ~(cop1_64bit(xcp) == 0); \ 910ef1c47afSPaul Burton set_fpr64(&ctx->fpr[fpr], 0, di); \ 911ef1c47afSPaul Burton for (i = 1; i < ARRAY_SIZE(ctx->fpr[x].val64); i++) \ 912ef1c47afSPaul Burton set_fpr64(&ctx->fpr[fpr], i, 0); \ 913ef1c47afSPaul Burton } while (0) 9141da177e4SLinus Torvalds 9151da177e4SLinus Torvalds #define SPFROMREG(sp, x) SIFROMREG((sp).bits, x) 9161da177e4SLinus Torvalds #define SPTOREG(sp, x) SITOREG((sp).bits, x) 9171da177e4SLinus Torvalds #define DPFROMREG(dp, x) DIFROMREG((dp).bits, x) 9181da177e4SLinus Torvalds #define DPTOREG(dp, x) DITOREG((dp).bits, x) 9191da177e4SLinus Torvalds 9201da177e4SLinus Torvalds /* 9211da177e4SLinus Torvalds * Emulate the single floating point instruction pointed at by EPC. 9221da177e4SLinus Torvalds * Two instructions if the instruction is in a branch delay slot. 9231da177e4SLinus Torvalds */ 9241da177e4SLinus Torvalds 925515b029dSDavid Daney static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_struct *ctx, 926102cedc3SLeonid Yegoshin struct mm_decoded_insn dec_insn, void *__user *fault_addr) 9271da177e4SLinus Torvalds { 9281da177e4SLinus Torvalds mips_instruction ir; 929102cedc3SLeonid Yegoshin unsigned long contpc = xcp->cp0_epc + dec_insn.pc_inc; 9301da177e4SLinus Torvalds unsigned int cond; 931102cedc3SLeonid Yegoshin int pc_inc; 9321da177e4SLinus Torvalds 9331da177e4SLinus Torvalds /* XXX NEC Vr54xx bug workaround */ 934e7e9cae5SRalf Baechle if (delay_slot(xcp)) { 935102cedc3SLeonid Yegoshin if (dec_insn.micro_mips_mode) { 936102cedc3SLeonid Yegoshin if (!mm_isBranchInstr(xcp, dec_insn, &contpc)) 937e7e9cae5SRalf Baechle clear_delay_slot(xcp); 938102cedc3SLeonid Yegoshin } else { 939102cedc3SLeonid Yegoshin if (!isBranchInstr(xcp, dec_insn, &contpc)) 940e7e9cae5SRalf Baechle clear_delay_slot(xcp); 941102cedc3SLeonid Yegoshin } 942102cedc3SLeonid Yegoshin } 9431da177e4SLinus Torvalds 944e7e9cae5SRalf Baechle if (delay_slot(xcp)) { 9451da177e4SLinus Torvalds /* 9461da177e4SLinus Torvalds * The instruction to be emulated is in a branch delay slot 9471da177e4SLinus Torvalds * which means that we have to emulate the branch instruction 9481da177e4SLinus Torvalds * BEFORE we do the cop1 instruction. 9491da177e4SLinus Torvalds * 9501da177e4SLinus Torvalds * This branch could be a COP1 branch, but in that case we 9511da177e4SLinus Torvalds * would have had a trap for that instruction, and would not 9521da177e4SLinus Torvalds * come through this route. 9531da177e4SLinus Torvalds * 9541da177e4SLinus Torvalds * Linux MIPS branch emulator operates on context, updating the 9551da177e4SLinus Torvalds * cp0_epc. 9561da177e4SLinus Torvalds */ 957102cedc3SLeonid Yegoshin ir = dec_insn.next_insn; /* process delay slot instr */ 958102cedc3SLeonid Yegoshin pc_inc = dec_insn.next_pc_inc; 959333d1f67SRalf Baechle } else { 960102cedc3SLeonid Yegoshin ir = dec_insn.insn; /* process current instr */ 961102cedc3SLeonid Yegoshin pc_inc = dec_insn.pc_inc; 962102cedc3SLeonid Yegoshin } 963102cedc3SLeonid Yegoshin 964102cedc3SLeonid Yegoshin /* 965102cedc3SLeonid Yegoshin * Since microMIPS FPU instructios are a subset of MIPS32 FPU 966102cedc3SLeonid Yegoshin * instructions, we want to convert microMIPS FPU instructions 967102cedc3SLeonid Yegoshin * into MIPS32 instructions so that we could reuse all of the 968102cedc3SLeonid Yegoshin * FPU emulation code. 969102cedc3SLeonid Yegoshin * 970102cedc3SLeonid Yegoshin * NOTE: We cannot do this for branch instructions since they 971102cedc3SLeonid Yegoshin * are not a subset. Example: Cannot emulate a 16-bit 972102cedc3SLeonid Yegoshin * aligned target address with a MIPS32 instruction. 973102cedc3SLeonid Yegoshin */ 974102cedc3SLeonid Yegoshin if (dec_insn.micro_mips_mode) { 975102cedc3SLeonid Yegoshin /* 976102cedc3SLeonid Yegoshin * If next instruction is a 16-bit instruction, then it 977102cedc3SLeonid Yegoshin * it cannot be a FPU instruction. This could happen 978102cedc3SLeonid Yegoshin * since we can be called for non-FPU instructions. 979102cedc3SLeonid Yegoshin */ 980102cedc3SLeonid Yegoshin if ((pc_inc == 2) || 981102cedc3SLeonid Yegoshin (microMIPS32_to_MIPS32((union mips_instruction *)&ir) 982102cedc3SLeonid Yegoshin == SIGILL)) 983102cedc3SLeonid Yegoshin return SIGILL; 9841da177e4SLinus Torvalds } 9851da177e4SLinus Torvalds 9861da177e4SLinus Torvalds emul: 987a8b0ca17SPeter Zijlstra perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 1, xcp, 0); 988b6ee75edSDavid Daney MIPS_FPU_EMU_INC_STATS(emulated); 9891da177e4SLinus Torvalds switch (MIPSInst_OPCODE(ir)) { 9901da177e4SLinus Torvalds case ldc1_op:{ 9913fccc015SRalf Baechle u64 __user *va = (u64 __user *) (xcp->regs[MIPSInst_RS(ir)] + 9921da177e4SLinus Torvalds MIPSInst_SIMM(ir)); 9931da177e4SLinus Torvalds u64 val; 9941da177e4SLinus Torvalds 995b6ee75edSDavid Daney MIPS_FPU_EMU_INC_STATS(loads); 996515b029dSDavid Daney 997515b029dSDavid Daney if (!access_ok(VERIFY_READ, va, sizeof(u64))) { 998b6ee75edSDavid Daney MIPS_FPU_EMU_INC_STATS(errors); 999515b029dSDavid Daney *fault_addr = va; 10001da177e4SLinus Torvalds return SIGBUS; 10011da177e4SLinus Torvalds } 1002515b029dSDavid Daney if (__get_user(val, va)) { 1003515b029dSDavid Daney MIPS_FPU_EMU_INC_STATS(errors); 1004515b029dSDavid Daney *fault_addr = va; 1005515b029dSDavid Daney return SIGSEGV; 1006515b029dSDavid Daney } 10071da177e4SLinus Torvalds DITOREG(val, MIPSInst_RT(ir)); 10081da177e4SLinus Torvalds break; 10091da177e4SLinus Torvalds } 10101da177e4SLinus Torvalds 10111da177e4SLinus Torvalds case sdc1_op:{ 10123fccc015SRalf Baechle u64 __user *va = (u64 __user *) (xcp->regs[MIPSInst_RS(ir)] + 10131da177e4SLinus Torvalds MIPSInst_SIMM(ir)); 10141da177e4SLinus Torvalds u64 val; 10151da177e4SLinus Torvalds 1016b6ee75edSDavid Daney MIPS_FPU_EMU_INC_STATS(stores); 10171da177e4SLinus Torvalds DIFROMREG(val, MIPSInst_RT(ir)); 1018515b029dSDavid Daney if (!access_ok(VERIFY_WRITE, va, sizeof(u64))) { 1019b6ee75edSDavid Daney MIPS_FPU_EMU_INC_STATS(errors); 1020515b029dSDavid Daney *fault_addr = va; 10211da177e4SLinus Torvalds return SIGBUS; 10221da177e4SLinus Torvalds } 1023515b029dSDavid Daney if (__put_user(val, va)) { 1024515b029dSDavid Daney MIPS_FPU_EMU_INC_STATS(errors); 1025515b029dSDavid Daney *fault_addr = va; 1026515b029dSDavid Daney return SIGSEGV; 1027515b029dSDavid Daney } 10281da177e4SLinus Torvalds break; 10291da177e4SLinus Torvalds } 10301da177e4SLinus Torvalds 10311da177e4SLinus Torvalds case lwc1_op:{ 10323fccc015SRalf Baechle u32 __user *va = (u32 __user *) (xcp->regs[MIPSInst_RS(ir)] + 10331da177e4SLinus Torvalds MIPSInst_SIMM(ir)); 10341da177e4SLinus Torvalds u32 val; 10351da177e4SLinus Torvalds 1036b6ee75edSDavid Daney MIPS_FPU_EMU_INC_STATS(loads); 1037515b029dSDavid Daney if (!access_ok(VERIFY_READ, va, sizeof(u32))) { 1038b6ee75edSDavid Daney MIPS_FPU_EMU_INC_STATS(errors); 1039515b029dSDavid Daney *fault_addr = va; 10401da177e4SLinus Torvalds return SIGBUS; 10411da177e4SLinus Torvalds } 1042515b029dSDavid Daney if (__get_user(val, va)) { 1043515b029dSDavid Daney MIPS_FPU_EMU_INC_STATS(errors); 1044515b029dSDavid Daney *fault_addr = va; 1045515b029dSDavid Daney return SIGSEGV; 1046515b029dSDavid Daney } 10471da177e4SLinus Torvalds SITOREG(val, MIPSInst_RT(ir)); 10481da177e4SLinus Torvalds break; 10491da177e4SLinus Torvalds } 10501da177e4SLinus Torvalds 10511da177e4SLinus Torvalds case swc1_op:{ 10523fccc015SRalf Baechle u32 __user *va = (u32 __user *) (xcp->regs[MIPSInst_RS(ir)] + 10531da177e4SLinus Torvalds MIPSInst_SIMM(ir)); 10541da177e4SLinus Torvalds u32 val; 10551da177e4SLinus Torvalds 1056b6ee75edSDavid Daney MIPS_FPU_EMU_INC_STATS(stores); 10571da177e4SLinus Torvalds SIFROMREG(val, MIPSInst_RT(ir)); 1058515b029dSDavid Daney if (!access_ok(VERIFY_WRITE, va, sizeof(u32))) { 1059b6ee75edSDavid Daney MIPS_FPU_EMU_INC_STATS(errors); 1060515b029dSDavid Daney *fault_addr = va; 10611da177e4SLinus Torvalds return SIGBUS; 10621da177e4SLinus Torvalds } 1063515b029dSDavid Daney if (__put_user(val, va)) { 1064515b029dSDavid Daney MIPS_FPU_EMU_INC_STATS(errors); 1065515b029dSDavid Daney *fault_addr = va; 1066515b029dSDavid Daney return SIGSEGV; 1067515b029dSDavid Daney } 10681da177e4SLinus Torvalds break; 10691da177e4SLinus Torvalds } 10701da177e4SLinus Torvalds 10711da177e4SLinus Torvalds case cop1_op: 10721da177e4SLinus Torvalds switch (MIPSInst_RS(ir)) { 10731da177e4SLinus Torvalds 10744b724efdSRalf Baechle #if defined(__mips64) 10751da177e4SLinus Torvalds case dmfc_op: 10761da177e4SLinus Torvalds /* copregister fs -> gpr[rt] */ 10771da177e4SLinus Torvalds if (MIPSInst_RT(ir) != 0) { 10781da177e4SLinus Torvalds DIFROMREG(xcp->regs[MIPSInst_RT(ir)], 10791da177e4SLinus Torvalds MIPSInst_RD(ir)); 10801da177e4SLinus Torvalds } 10811da177e4SLinus Torvalds break; 10821da177e4SLinus Torvalds 10831da177e4SLinus Torvalds case dmtc_op: 10841da177e4SLinus Torvalds /* copregister fs <- rt */ 10851da177e4SLinus Torvalds DITOREG(xcp->regs[MIPSInst_RT(ir)], MIPSInst_RD(ir)); 10861da177e4SLinus Torvalds break; 10871da177e4SLinus Torvalds #endif 10881da177e4SLinus Torvalds 10891ac94400SLeonid Yegoshin case mfhc_op: 10901ac94400SLeonid Yegoshin if (!cpu_has_mips_r2) 10911ac94400SLeonid Yegoshin goto sigill; 10921ac94400SLeonid Yegoshin 10931ac94400SLeonid Yegoshin /* copregister rd -> gpr[rt] */ 10941ac94400SLeonid Yegoshin if (MIPSInst_RT(ir) != 0) { 10951ac94400SLeonid Yegoshin SIFROMHREG(xcp->regs[MIPSInst_RT(ir)], 10961ac94400SLeonid Yegoshin MIPSInst_RD(ir)); 10971ac94400SLeonid Yegoshin } 10981ac94400SLeonid Yegoshin break; 10991ac94400SLeonid Yegoshin 11001ac94400SLeonid Yegoshin case mthc_op: 11011ac94400SLeonid Yegoshin if (!cpu_has_mips_r2) 11021ac94400SLeonid Yegoshin goto sigill; 11031ac94400SLeonid Yegoshin 11041ac94400SLeonid Yegoshin /* copregister rd <- gpr[rt] */ 11051ac94400SLeonid Yegoshin SITOHREG(xcp->regs[MIPSInst_RT(ir)], MIPSInst_RD(ir)); 11061ac94400SLeonid Yegoshin break; 11071ac94400SLeonid Yegoshin 11081da177e4SLinus Torvalds case mfc_op: 11091da177e4SLinus Torvalds /* copregister rd -> gpr[rt] */ 11101da177e4SLinus Torvalds if (MIPSInst_RT(ir) != 0) { 11111da177e4SLinus Torvalds SIFROMREG(xcp->regs[MIPSInst_RT(ir)], 11121da177e4SLinus Torvalds MIPSInst_RD(ir)); 11131da177e4SLinus Torvalds } 11141da177e4SLinus Torvalds break; 11151da177e4SLinus Torvalds 11161da177e4SLinus Torvalds case mtc_op: 11171da177e4SLinus Torvalds /* copregister rd <- rt */ 11181da177e4SLinus Torvalds SITOREG(xcp->regs[MIPSInst_RT(ir)], MIPSInst_RD(ir)); 11191da177e4SLinus Torvalds break; 11201da177e4SLinus Torvalds 11211da177e4SLinus Torvalds case cfc_op:{ 11221da177e4SLinus Torvalds /* cop control register rd -> gpr[rt] */ 11231da177e4SLinus Torvalds u32 value; 11241da177e4SLinus Torvalds 11251da177e4SLinus Torvalds if (MIPSInst_RD(ir) == FPCREG_CSR) { 11261da177e4SLinus Torvalds value = ctx->fcr31; 11273f135530SShane McDonald value = (value & ~FPU_CSR_RM) | 11283f135530SShane McDonald mips_rm[modeindex(value)]; 11291da177e4SLinus Torvalds #ifdef CSRTRACE 11301da177e4SLinus Torvalds printk("%p gpr[%d]<-csr=%08x\n", 1131333d1f67SRalf Baechle (void *) (xcp->cp0_epc), 11321da177e4SLinus Torvalds MIPSInst_RT(ir), value); 11331da177e4SLinus Torvalds #endif 11341da177e4SLinus Torvalds } 11351da177e4SLinus Torvalds else if (MIPSInst_RD(ir) == FPCREG_RID) 11361da177e4SLinus Torvalds value = 0; 11371da177e4SLinus Torvalds else 11381da177e4SLinus Torvalds value = 0; 11391da177e4SLinus Torvalds if (MIPSInst_RT(ir)) 11401da177e4SLinus Torvalds xcp->regs[MIPSInst_RT(ir)] = value; 11411da177e4SLinus Torvalds break; 11421da177e4SLinus Torvalds } 11431da177e4SLinus Torvalds 11441da177e4SLinus Torvalds case ctc_op:{ 11451da177e4SLinus Torvalds /* copregister rd <- rt */ 11461da177e4SLinus Torvalds u32 value; 11471da177e4SLinus Torvalds 11481da177e4SLinus Torvalds if (MIPSInst_RT(ir) == 0) 11491da177e4SLinus Torvalds value = 0; 11501da177e4SLinus Torvalds else 11511da177e4SLinus Torvalds value = xcp->regs[MIPSInst_RT(ir)]; 11521da177e4SLinus Torvalds 11531da177e4SLinus Torvalds /* we only have one writable control reg 11541da177e4SLinus Torvalds */ 11551da177e4SLinus Torvalds if (MIPSInst_RD(ir) == FPCREG_CSR) { 11561da177e4SLinus Torvalds #ifdef CSRTRACE 11571da177e4SLinus Torvalds printk("%p gpr[%d]->csr=%08x\n", 1158333d1f67SRalf Baechle (void *) (xcp->cp0_epc), 11591da177e4SLinus Torvalds MIPSInst_RT(ir), value); 11601da177e4SLinus Torvalds #endif 116195e8f634SShane McDonald 116295e8f634SShane McDonald /* 116395e8f634SShane McDonald * Don't write reserved bits, 116495e8f634SShane McDonald * and convert to ieee library modes 116595e8f634SShane McDonald */ 116695e8f634SShane McDonald ctx->fcr31 = (value & 116795e8f634SShane McDonald ~(FPU_CSR_RSVD | FPU_CSR_RM)) | 116895e8f634SShane McDonald ieee_rm[modeindex(value)]; 11691da177e4SLinus Torvalds } 11701da177e4SLinus Torvalds if ((ctx->fcr31 >> 5) & ctx->fcr31 & FPU_CSR_ALL_E) { 11711da177e4SLinus Torvalds return SIGFPE; 11721da177e4SLinus Torvalds } 11731da177e4SLinus Torvalds break; 11741da177e4SLinus Torvalds } 11751da177e4SLinus Torvalds 11761da177e4SLinus Torvalds case bc_op:{ 11771da177e4SLinus Torvalds int likely = 0; 11781da177e4SLinus Torvalds 1179e7e9cae5SRalf Baechle if (delay_slot(xcp)) 11801da177e4SLinus Torvalds return SIGILL; 11811da177e4SLinus Torvalds 11821da177e4SLinus Torvalds #if __mips >= 4 11831da177e4SLinus Torvalds cond = ctx->fcr31 & fpucondbit[MIPSInst_RT(ir) >> 2]; 11841da177e4SLinus Torvalds #else 11851da177e4SLinus Torvalds cond = ctx->fcr31 & FPU_CSR_COND; 11861da177e4SLinus Torvalds #endif 11871da177e4SLinus Torvalds switch (MIPSInst_RT(ir) & 3) { 11881da177e4SLinus Torvalds case bcfl_op: 11891da177e4SLinus Torvalds likely = 1; 11901da177e4SLinus Torvalds case bcf_op: 11911da177e4SLinus Torvalds cond = !cond; 11921da177e4SLinus Torvalds break; 11931da177e4SLinus Torvalds case bctl_op: 11941da177e4SLinus Torvalds likely = 1; 11951da177e4SLinus Torvalds case bct_op: 11961da177e4SLinus Torvalds break; 11971da177e4SLinus Torvalds default: 11981da177e4SLinus Torvalds /* thats an illegal instruction */ 11991da177e4SLinus Torvalds return SIGILL; 12001da177e4SLinus Torvalds } 12011da177e4SLinus Torvalds 1202e7e9cae5SRalf Baechle set_delay_slot(xcp); 12031da177e4SLinus Torvalds if (cond) { 12041da177e4SLinus Torvalds /* branch taken: emulate dslot 12051da177e4SLinus Torvalds * instruction 12061da177e4SLinus Torvalds */ 1207102cedc3SLeonid Yegoshin xcp->cp0_epc += dec_insn.pc_inc; 12081da177e4SLinus Torvalds 1209102cedc3SLeonid Yegoshin contpc = MIPSInst_SIMM(ir); 1210102cedc3SLeonid Yegoshin ir = dec_insn.next_insn; 1211102cedc3SLeonid Yegoshin if (dec_insn.micro_mips_mode) { 1212102cedc3SLeonid Yegoshin contpc = (xcp->cp0_epc + (contpc << 1)); 1213102cedc3SLeonid Yegoshin 1214102cedc3SLeonid Yegoshin /* If 16-bit instruction, not FPU. */ 1215102cedc3SLeonid Yegoshin if ((dec_insn.next_pc_inc == 2) || 1216102cedc3SLeonid Yegoshin (microMIPS32_to_MIPS32((union mips_instruction *)&ir) == SIGILL)) { 1217102cedc3SLeonid Yegoshin 1218102cedc3SLeonid Yegoshin /* 1219102cedc3SLeonid Yegoshin * Since this instruction will 1220102cedc3SLeonid Yegoshin * be put on the stack with 1221102cedc3SLeonid Yegoshin * 32-bit words, get around 1222102cedc3SLeonid Yegoshin * this problem by putting a 1223102cedc3SLeonid Yegoshin * NOP16 as the second one. 1224102cedc3SLeonid Yegoshin */ 1225102cedc3SLeonid Yegoshin if (dec_insn.next_pc_inc == 2) 1226102cedc3SLeonid Yegoshin ir = (ir & (~0xffff)) | MM_NOP16; 1227102cedc3SLeonid Yegoshin 1228102cedc3SLeonid Yegoshin /* 1229102cedc3SLeonid Yegoshin * Single step the non-CP1 1230102cedc3SLeonid Yegoshin * instruction in the dslot. 1231102cedc3SLeonid Yegoshin */ 1232102cedc3SLeonid Yegoshin return mips_dsemul(xcp, ir, contpc); 1233515b029dSDavid Daney } 1234102cedc3SLeonid Yegoshin } else 1235102cedc3SLeonid Yegoshin contpc = (xcp->cp0_epc + (contpc << 2)); 12361da177e4SLinus Torvalds 12371da177e4SLinus Torvalds switch (MIPSInst_OPCODE(ir)) { 12381da177e4SLinus Torvalds case lwc1_op: 12391da177e4SLinus Torvalds case swc1_op: 12404b724efdSRalf Baechle #if (__mips >= 2 || defined(__mips64)) 12411da177e4SLinus Torvalds case ldc1_op: 12421da177e4SLinus Torvalds case sdc1_op: 12431da177e4SLinus Torvalds #endif 12441da177e4SLinus Torvalds case cop1_op: 12451da177e4SLinus Torvalds #if __mips >= 4 && __mips != 32 12461da177e4SLinus Torvalds case cop1x_op: 12471da177e4SLinus Torvalds #endif 12481da177e4SLinus Torvalds /* its one of ours */ 12491da177e4SLinus Torvalds goto emul; 12501da177e4SLinus Torvalds #if __mips >= 4 12511da177e4SLinus Torvalds case spec_op: 12521da177e4SLinus Torvalds if (MIPSInst_FUNC(ir) == movc_op) 12531da177e4SLinus Torvalds goto emul; 12541da177e4SLinus Torvalds break; 12551da177e4SLinus Torvalds #endif 12561da177e4SLinus Torvalds } 12571da177e4SLinus Torvalds 12581da177e4SLinus Torvalds /* 12591da177e4SLinus Torvalds * Single step the non-cp1 12601da177e4SLinus Torvalds * instruction in the dslot 12611da177e4SLinus Torvalds */ 1262e70dfc10SAtsushi Nemoto return mips_dsemul(xcp, ir, contpc); 12631da177e4SLinus Torvalds } 12641da177e4SLinus Torvalds else { 12651da177e4SLinus Torvalds /* branch not taken */ 12661da177e4SLinus Torvalds if (likely) { 12671da177e4SLinus Torvalds /* 12681da177e4SLinus Torvalds * branch likely nullifies 12691da177e4SLinus Torvalds * dslot if not taken 12701da177e4SLinus Torvalds */ 1271102cedc3SLeonid Yegoshin xcp->cp0_epc += dec_insn.pc_inc; 1272102cedc3SLeonid Yegoshin contpc += dec_insn.pc_inc; 12731da177e4SLinus Torvalds /* 12741da177e4SLinus Torvalds * else continue & execute 12751da177e4SLinus Torvalds * dslot as normal insn 12761da177e4SLinus Torvalds */ 12771da177e4SLinus Torvalds } 12781da177e4SLinus Torvalds } 12791da177e4SLinus Torvalds break; 12801da177e4SLinus Torvalds } 12811da177e4SLinus Torvalds 12821da177e4SLinus Torvalds default: 12831da177e4SLinus Torvalds if (!(MIPSInst_RS(ir) & 0x10)) 12841da177e4SLinus Torvalds return SIGILL; 12851da177e4SLinus Torvalds { 12861da177e4SLinus Torvalds int sig; 12871da177e4SLinus Torvalds 12881da177e4SLinus Torvalds /* a real fpu computation instruction */ 12891da177e4SLinus Torvalds if ((sig = fpu_emu(xcp, ctx, ir))) 12901da177e4SLinus Torvalds return sig; 12911da177e4SLinus Torvalds } 12921da177e4SLinus Torvalds } 12931da177e4SLinus Torvalds break; 12941da177e4SLinus Torvalds 12951da177e4SLinus Torvalds #if __mips >= 4 && __mips != 32 12961da177e4SLinus Torvalds case cop1x_op:{ 1297515b029dSDavid Daney int sig = fpux_emu(xcp, ctx, ir, fault_addr); 1298515b029dSDavid Daney if (sig) 12991da177e4SLinus Torvalds return sig; 13001da177e4SLinus Torvalds break; 13011da177e4SLinus Torvalds } 13021da177e4SLinus Torvalds #endif 13031da177e4SLinus Torvalds 13041da177e4SLinus Torvalds #if __mips >= 4 13051da177e4SLinus Torvalds case spec_op: 13061da177e4SLinus Torvalds if (MIPSInst_FUNC(ir) != movc_op) 13071da177e4SLinus Torvalds return SIGILL; 13081da177e4SLinus Torvalds cond = fpucondbit[MIPSInst_RT(ir) >> 2]; 13091da177e4SLinus Torvalds if (((ctx->fcr31 & cond) != 0) == ((MIPSInst_RT(ir) & 1) != 0)) 13101da177e4SLinus Torvalds xcp->regs[MIPSInst_RD(ir)] = 13111da177e4SLinus Torvalds xcp->regs[MIPSInst_RS(ir)]; 13121da177e4SLinus Torvalds break; 13131da177e4SLinus Torvalds #endif 13141da177e4SLinus Torvalds 13151da177e4SLinus Torvalds default: 13161ac94400SLeonid Yegoshin sigill: 13171da177e4SLinus Torvalds return SIGILL; 13181da177e4SLinus Torvalds } 13191da177e4SLinus Torvalds 13201da177e4SLinus Torvalds /* we did it !! */ 1321e70dfc10SAtsushi Nemoto xcp->cp0_epc = contpc; 1322e7e9cae5SRalf Baechle clear_delay_slot(xcp); 1323333d1f67SRalf Baechle 13241da177e4SLinus Torvalds return 0; 13251da177e4SLinus Torvalds } 13261da177e4SLinus Torvalds 13271da177e4SLinus Torvalds /* 13281da177e4SLinus Torvalds * Conversion table from MIPS compare ops 48-63 13291da177e4SLinus Torvalds * cond = ieee754dp_cmp(x,y,IEEE754_UN,sig); 13301da177e4SLinus Torvalds */ 13311da177e4SLinus Torvalds static const unsigned char cmptab[8] = { 13321da177e4SLinus Torvalds 0, /* cmp_0 (sig) cmp_sf */ 13331da177e4SLinus Torvalds IEEE754_CUN, /* cmp_un (sig) cmp_ngle */ 13341da177e4SLinus Torvalds IEEE754_CEQ, /* cmp_eq (sig) cmp_seq */ 13351da177e4SLinus Torvalds IEEE754_CEQ | IEEE754_CUN, /* cmp_ueq (sig) cmp_ngl */ 13361da177e4SLinus Torvalds IEEE754_CLT, /* cmp_olt (sig) cmp_lt */ 13371da177e4SLinus Torvalds IEEE754_CLT | IEEE754_CUN, /* cmp_ult (sig) cmp_nge */ 13381da177e4SLinus Torvalds IEEE754_CLT | IEEE754_CEQ, /* cmp_ole (sig) cmp_le */ 13391da177e4SLinus Torvalds IEEE754_CLT | IEEE754_CEQ | IEEE754_CUN, /* cmp_ule (sig) cmp_ngt */ 13401da177e4SLinus Torvalds }; 13411da177e4SLinus Torvalds 13421da177e4SLinus Torvalds 13431da177e4SLinus Torvalds #if __mips >= 4 && __mips != 32 13441da177e4SLinus Torvalds 13451da177e4SLinus Torvalds /* 13461da177e4SLinus Torvalds * Additional MIPS4 instructions 13471da177e4SLinus Torvalds */ 13481da177e4SLinus Torvalds 13491da177e4SLinus Torvalds #define DEF3OP(name, p, f1, f2, f3) \ 13502209bcb1SRalf Baechle static union ieee754##p fpemu_##p##_##name(union ieee754##p r, union ieee754##p s, \ 13512209bcb1SRalf Baechle union ieee754##p t) \ 13521da177e4SLinus Torvalds { \ 1353cd21dfcfSRalf Baechle struct _ieee754_csr ieee754_csr_save; \ 13541da177e4SLinus Torvalds s = f1(s, t); \ 13551da177e4SLinus Torvalds ieee754_csr_save = ieee754_csr; \ 13561da177e4SLinus Torvalds s = f2(s, r); \ 13571da177e4SLinus Torvalds ieee754_csr_save.cx |= ieee754_csr.cx; \ 13581da177e4SLinus Torvalds ieee754_csr_save.sx |= ieee754_csr.sx; \ 13591da177e4SLinus Torvalds s = f3(s); \ 13601da177e4SLinus Torvalds ieee754_csr.cx |= ieee754_csr_save.cx; \ 13611da177e4SLinus Torvalds ieee754_csr.sx |= ieee754_csr_save.sx; \ 13621da177e4SLinus Torvalds return s; \ 13631da177e4SLinus Torvalds } 13641da177e4SLinus Torvalds 13652209bcb1SRalf Baechle static union ieee754dp fpemu_dp_recip(union ieee754dp d) 13661da177e4SLinus Torvalds { 13671da177e4SLinus Torvalds return ieee754dp_div(ieee754dp_one(0), d); 13681da177e4SLinus Torvalds } 13691da177e4SLinus Torvalds 13702209bcb1SRalf Baechle static union ieee754dp fpemu_dp_rsqrt(union ieee754dp d) 13711da177e4SLinus Torvalds { 13721da177e4SLinus Torvalds return ieee754dp_div(ieee754dp_one(0), ieee754dp_sqrt(d)); 13731da177e4SLinus Torvalds } 13741da177e4SLinus Torvalds 13752209bcb1SRalf Baechle static union ieee754sp fpemu_sp_recip(union ieee754sp s) 13761da177e4SLinus Torvalds { 13771da177e4SLinus Torvalds return ieee754sp_div(ieee754sp_one(0), s); 13781da177e4SLinus Torvalds } 13791da177e4SLinus Torvalds 13802209bcb1SRalf Baechle static union ieee754sp fpemu_sp_rsqrt(union ieee754sp s) 13811da177e4SLinus Torvalds { 13821da177e4SLinus Torvalds return ieee754sp_div(ieee754sp_one(0), ieee754sp_sqrt(s)); 13831da177e4SLinus Torvalds } 13841da177e4SLinus Torvalds 13851da177e4SLinus Torvalds DEF3OP(madd, sp, ieee754sp_mul, ieee754sp_add, ); 13861da177e4SLinus Torvalds DEF3OP(msub, sp, ieee754sp_mul, ieee754sp_sub, ); 13871da177e4SLinus Torvalds DEF3OP(nmadd, sp, ieee754sp_mul, ieee754sp_add, ieee754sp_neg); 13881da177e4SLinus Torvalds DEF3OP(nmsub, sp, ieee754sp_mul, ieee754sp_sub, ieee754sp_neg); 13891da177e4SLinus Torvalds DEF3OP(madd, dp, ieee754dp_mul, ieee754dp_add, ); 13901da177e4SLinus Torvalds DEF3OP(msub, dp, ieee754dp_mul, ieee754dp_sub, ); 13911da177e4SLinus Torvalds DEF3OP(nmadd, dp, ieee754dp_mul, ieee754dp_add, ieee754dp_neg); 13921da177e4SLinus Torvalds DEF3OP(nmsub, dp, ieee754dp_mul, ieee754dp_sub, ieee754dp_neg); 13931da177e4SLinus Torvalds 1394eae89076SAtsushi Nemoto static int fpux_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx, 1395515b029dSDavid Daney mips_instruction ir, void *__user *fault_addr) 13961da177e4SLinus Torvalds { 13971da177e4SLinus Torvalds unsigned rcsr = 0; /* resulting csr */ 13981da177e4SLinus Torvalds 1399b6ee75edSDavid Daney MIPS_FPU_EMU_INC_STATS(cp1xops); 14001da177e4SLinus Torvalds 14011da177e4SLinus Torvalds switch (MIPSInst_FMA_FFMT(ir)) { 14021da177e4SLinus Torvalds case s_fmt:{ /* 0 */ 14031da177e4SLinus Torvalds 14042209bcb1SRalf Baechle union ieee754sp(*handler) (union ieee754sp, union ieee754sp, union ieee754sp); 14052209bcb1SRalf Baechle union ieee754sp fd, fr, fs, ft; 14063fccc015SRalf Baechle u32 __user *va; 14071da177e4SLinus Torvalds u32 val; 14081da177e4SLinus Torvalds 14091da177e4SLinus Torvalds switch (MIPSInst_FUNC(ir)) { 14101da177e4SLinus Torvalds case lwxc1_op: 14113fccc015SRalf Baechle va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] + 14121da177e4SLinus Torvalds xcp->regs[MIPSInst_FT(ir)]); 14131da177e4SLinus Torvalds 1414b6ee75edSDavid Daney MIPS_FPU_EMU_INC_STATS(loads); 1415515b029dSDavid Daney if (!access_ok(VERIFY_READ, va, sizeof(u32))) { 1416b6ee75edSDavid Daney MIPS_FPU_EMU_INC_STATS(errors); 1417515b029dSDavid Daney *fault_addr = va; 14181da177e4SLinus Torvalds return SIGBUS; 14191da177e4SLinus Torvalds } 1420515b029dSDavid Daney if (__get_user(val, va)) { 1421515b029dSDavid Daney MIPS_FPU_EMU_INC_STATS(errors); 1422515b029dSDavid Daney *fault_addr = va; 1423515b029dSDavid Daney return SIGSEGV; 1424515b029dSDavid Daney } 14251da177e4SLinus Torvalds SITOREG(val, MIPSInst_FD(ir)); 14261da177e4SLinus Torvalds break; 14271da177e4SLinus Torvalds 14281da177e4SLinus Torvalds case swxc1_op: 14293fccc015SRalf Baechle va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] + 14301da177e4SLinus Torvalds xcp->regs[MIPSInst_FT(ir)]); 14311da177e4SLinus Torvalds 1432b6ee75edSDavid Daney MIPS_FPU_EMU_INC_STATS(stores); 14331da177e4SLinus Torvalds 14341da177e4SLinus Torvalds SIFROMREG(val, MIPSInst_FS(ir)); 1435515b029dSDavid Daney if (!access_ok(VERIFY_WRITE, va, sizeof(u32))) { 1436515b029dSDavid Daney MIPS_FPU_EMU_INC_STATS(errors); 1437515b029dSDavid Daney *fault_addr = va; 1438515b029dSDavid Daney return SIGBUS; 1439515b029dSDavid Daney } 14401da177e4SLinus Torvalds if (put_user(val, va)) { 1441b6ee75edSDavid Daney MIPS_FPU_EMU_INC_STATS(errors); 1442515b029dSDavid Daney *fault_addr = va; 1443515b029dSDavid Daney return SIGSEGV; 14441da177e4SLinus Torvalds } 14451da177e4SLinus Torvalds break; 14461da177e4SLinus Torvalds 14471da177e4SLinus Torvalds case madd_s_op: 14481da177e4SLinus Torvalds handler = fpemu_sp_madd; 14491da177e4SLinus Torvalds goto scoptop; 14501da177e4SLinus Torvalds case msub_s_op: 14511da177e4SLinus Torvalds handler = fpemu_sp_msub; 14521da177e4SLinus Torvalds goto scoptop; 14531da177e4SLinus Torvalds case nmadd_s_op: 14541da177e4SLinus Torvalds handler = fpemu_sp_nmadd; 14551da177e4SLinus Torvalds goto scoptop; 14561da177e4SLinus Torvalds case nmsub_s_op: 14571da177e4SLinus Torvalds handler = fpemu_sp_nmsub; 14581da177e4SLinus Torvalds goto scoptop; 14591da177e4SLinus Torvalds 14601da177e4SLinus Torvalds scoptop: 14611da177e4SLinus Torvalds SPFROMREG(fr, MIPSInst_FR(ir)); 14621da177e4SLinus Torvalds SPFROMREG(fs, MIPSInst_FS(ir)); 14631da177e4SLinus Torvalds SPFROMREG(ft, MIPSInst_FT(ir)); 14641da177e4SLinus Torvalds fd = (*handler) (fr, fs, ft); 14651da177e4SLinus Torvalds SPTOREG(fd, MIPSInst_FD(ir)); 14661da177e4SLinus Torvalds 14671da177e4SLinus Torvalds copcsr: 14681da177e4SLinus Torvalds if (ieee754_cxtest(IEEE754_INEXACT)) 14691da177e4SLinus Torvalds rcsr |= FPU_CSR_INE_X | FPU_CSR_INE_S; 14701da177e4SLinus Torvalds if (ieee754_cxtest(IEEE754_UNDERFLOW)) 14711da177e4SLinus Torvalds rcsr |= FPU_CSR_UDF_X | FPU_CSR_UDF_S; 14721da177e4SLinus Torvalds if (ieee754_cxtest(IEEE754_OVERFLOW)) 14731da177e4SLinus Torvalds rcsr |= FPU_CSR_OVF_X | FPU_CSR_OVF_S; 14741da177e4SLinus Torvalds if (ieee754_cxtest(IEEE754_INVALID_OPERATION)) 14751da177e4SLinus Torvalds rcsr |= FPU_CSR_INV_X | FPU_CSR_INV_S; 14761da177e4SLinus Torvalds 14771da177e4SLinus Torvalds ctx->fcr31 = (ctx->fcr31 & ~FPU_CSR_ALL_X) | rcsr; 14781da177e4SLinus Torvalds if ((ctx->fcr31 >> 5) & ctx->fcr31 & FPU_CSR_ALL_E) { 14791da177e4SLinus Torvalds /*printk ("SIGFPE: fpu csr = %08x\n", 14801da177e4SLinus Torvalds ctx->fcr31); */ 14811da177e4SLinus Torvalds return SIGFPE; 14821da177e4SLinus Torvalds } 14831da177e4SLinus Torvalds 14841da177e4SLinus Torvalds break; 14851da177e4SLinus Torvalds 14861da177e4SLinus Torvalds default: 14871da177e4SLinus Torvalds return SIGILL; 14881da177e4SLinus Torvalds } 14891da177e4SLinus Torvalds break; 14901da177e4SLinus Torvalds } 14911da177e4SLinus Torvalds 14921da177e4SLinus Torvalds case d_fmt:{ /* 1 */ 14932209bcb1SRalf Baechle union ieee754dp(*handler) (union ieee754dp, union ieee754dp, union ieee754dp); 14942209bcb1SRalf Baechle union ieee754dp fd, fr, fs, ft; 14953fccc015SRalf Baechle u64 __user *va; 14961da177e4SLinus Torvalds u64 val; 14971da177e4SLinus Torvalds 14981da177e4SLinus Torvalds switch (MIPSInst_FUNC(ir)) { 14991da177e4SLinus Torvalds case ldxc1_op: 15003fccc015SRalf Baechle va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] + 15011da177e4SLinus Torvalds xcp->regs[MIPSInst_FT(ir)]); 15021da177e4SLinus Torvalds 1503b6ee75edSDavid Daney MIPS_FPU_EMU_INC_STATS(loads); 1504515b029dSDavid Daney if (!access_ok(VERIFY_READ, va, sizeof(u64))) { 1505b6ee75edSDavid Daney MIPS_FPU_EMU_INC_STATS(errors); 1506515b029dSDavid Daney *fault_addr = va; 15071da177e4SLinus Torvalds return SIGBUS; 15081da177e4SLinus Torvalds } 1509515b029dSDavid Daney if (__get_user(val, va)) { 1510515b029dSDavid Daney MIPS_FPU_EMU_INC_STATS(errors); 1511515b029dSDavid Daney *fault_addr = va; 1512515b029dSDavid Daney return SIGSEGV; 1513515b029dSDavid Daney } 15141da177e4SLinus Torvalds DITOREG(val, MIPSInst_FD(ir)); 15151da177e4SLinus Torvalds break; 15161da177e4SLinus Torvalds 15171da177e4SLinus Torvalds case sdxc1_op: 15183fccc015SRalf Baechle va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] + 15191da177e4SLinus Torvalds xcp->regs[MIPSInst_FT(ir)]); 15201da177e4SLinus Torvalds 1521b6ee75edSDavid Daney MIPS_FPU_EMU_INC_STATS(stores); 15221da177e4SLinus Torvalds DIFROMREG(val, MIPSInst_FS(ir)); 1523515b029dSDavid Daney if (!access_ok(VERIFY_WRITE, va, sizeof(u64))) { 1524b6ee75edSDavid Daney MIPS_FPU_EMU_INC_STATS(errors); 1525515b029dSDavid Daney *fault_addr = va; 15261da177e4SLinus Torvalds return SIGBUS; 15271da177e4SLinus Torvalds } 1528515b029dSDavid Daney if (__put_user(val, va)) { 1529515b029dSDavid Daney MIPS_FPU_EMU_INC_STATS(errors); 1530515b029dSDavid Daney *fault_addr = va; 1531515b029dSDavid Daney return SIGSEGV; 1532515b029dSDavid Daney } 15331da177e4SLinus Torvalds break; 15341da177e4SLinus Torvalds 15351da177e4SLinus Torvalds case madd_d_op: 15361da177e4SLinus Torvalds handler = fpemu_dp_madd; 15371da177e4SLinus Torvalds goto dcoptop; 15381da177e4SLinus Torvalds case msub_d_op: 15391da177e4SLinus Torvalds handler = fpemu_dp_msub; 15401da177e4SLinus Torvalds goto dcoptop; 15411da177e4SLinus Torvalds case nmadd_d_op: 15421da177e4SLinus Torvalds handler = fpemu_dp_nmadd; 15431da177e4SLinus Torvalds goto dcoptop; 15441da177e4SLinus Torvalds case nmsub_d_op: 15451da177e4SLinus Torvalds handler = fpemu_dp_nmsub; 15461da177e4SLinus Torvalds goto dcoptop; 15471da177e4SLinus Torvalds 15481da177e4SLinus Torvalds dcoptop: 15491da177e4SLinus Torvalds DPFROMREG(fr, MIPSInst_FR(ir)); 15501da177e4SLinus Torvalds DPFROMREG(fs, MIPSInst_FS(ir)); 15511da177e4SLinus Torvalds DPFROMREG(ft, MIPSInst_FT(ir)); 15521da177e4SLinus Torvalds fd = (*handler) (fr, fs, ft); 15531da177e4SLinus Torvalds DPTOREG(fd, MIPSInst_FD(ir)); 15541da177e4SLinus Torvalds goto copcsr; 15551da177e4SLinus Torvalds 15561da177e4SLinus Torvalds default: 15571da177e4SLinus Torvalds return SIGILL; 15581da177e4SLinus Torvalds } 15591da177e4SLinus Torvalds break; 15601da177e4SLinus Torvalds } 15611da177e4SLinus Torvalds 156251061b88SDeng-Cheng Zhu case 0x3: 156351061b88SDeng-Cheng Zhu if (MIPSInst_FUNC(ir) != pfetch_op) 15641da177e4SLinus Torvalds return SIGILL; 156551061b88SDeng-Cheng Zhu 15661da177e4SLinus Torvalds /* ignore prefx operation */ 15671da177e4SLinus Torvalds break; 15681da177e4SLinus Torvalds 15691da177e4SLinus Torvalds default: 15701da177e4SLinus Torvalds return SIGILL; 15711da177e4SLinus Torvalds } 15721da177e4SLinus Torvalds 15731da177e4SLinus Torvalds return 0; 15741da177e4SLinus Torvalds } 15751da177e4SLinus Torvalds #endif 15761da177e4SLinus Torvalds 15771da177e4SLinus Torvalds 15781da177e4SLinus Torvalds 15791da177e4SLinus Torvalds /* 15801da177e4SLinus Torvalds * Emulate a single COP1 arithmetic instruction. 15811da177e4SLinus Torvalds */ 1582eae89076SAtsushi Nemoto static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx, 15831da177e4SLinus Torvalds mips_instruction ir) 15841da177e4SLinus Torvalds { 15851da177e4SLinus Torvalds int rfmt; /* resulting format */ 15861da177e4SLinus Torvalds unsigned rcsr = 0; /* resulting csr */ 15871da177e4SLinus Torvalds unsigned cond; 15881da177e4SLinus Torvalds union { 15892209bcb1SRalf Baechle union ieee754dp d; 15902209bcb1SRalf Baechle union ieee754sp s; 15911da177e4SLinus Torvalds int w; 1592766160c2SYoichi Yuasa #ifdef __mips64 15931da177e4SLinus Torvalds s64 l; 15941da177e4SLinus Torvalds #endif 15951da177e4SLinus Torvalds } rv; /* resulting value */ 15961da177e4SLinus Torvalds 1597b6ee75edSDavid Daney MIPS_FPU_EMU_INC_STATS(cp1ops); 15981da177e4SLinus Torvalds switch (rfmt = (MIPSInst_FFMT(ir) & 0xf)) { 15991da177e4SLinus Torvalds case s_fmt:{ /* 0 */ 16001da177e4SLinus Torvalds union { 16012209bcb1SRalf Baechle union ieee754sp(*b) (union ieee754sp, union ieee754sp); 16022209bcb1SRalf Baechle union ieee754sp(*u) (union ieee754sp); 16031da177e4SLinus Torvalds } handler; 16041da177e4SLinus Torvalds 16051da177e4SLinus Torvalds switch (MIPSInst_FUNC(ir)) { 16061da177e4SLinus Torvalds /* binary ops */ 16071da177e4SLinus Torvalds case fadd_op: 16081da177e4SLinus Torvalds handler.b = ieee754sp_add; 16091da177e4SLinus Torvalds goto scopbop; 16101da177e4SLinus Torvalds case fsub_op: 16111da177e4SLinus Torvalds handler.b = ieee754sp_sub; 16121da177e4SLinus Torvalds goto scopbop; 16131da177e4SLinus Torvalds case fmul_op: 16141da177e4SLinus Torvalds handler.b = ieee754sp_mul; 16151da177e4SLinus Torvalds goto scopbop; 16161da177e4SLinus Torvalds case fdiv_op: 16171da177e4SLinus Torvalds handler.b = ieee754sp_div; 16181da177e4SLinus Torvalds goto scopbop; 16191da177e4SLinus Torvalds 16201da177e4SLinus Torvalds /* unary ops */ 1621587cb98fSRalf Baechle #if __mips >= 2 || defined(__mips64) 16221da177e4SLinus Torvalds case fsqrt_op: 16231da177e4SLinus Torvalds handler.u = ieee754sp_sqrt; 16241da177e4SLinus Torvalds goto scopuop; 16251da177e4SLinus Torvalds #endif 16261da177e4SLinus Torvalds #if __mips >= 4 && __mips != 32 16271da177e4SLinus Torvalds case frsqrt_op: 16281da177e4SLinus Torvalds handler.u = fpemu_sp_rsqrt; 16291da177e4SLinus Torvalds goto scopuop; 16301da177e4SLinus Torvalds case frecip_op: 16311da177e4SLinus Torvalds handler.u = fpemu_sp_recip; 16321da177e4SLinus Torvalds goto scopuop; 16331da177e4SLinus Torvalds #endif 16341da177e4SLinus Torvalds #if __mips >= 4 16351da177e4SLinus Torvalds case fmovc_op: 16361da177e4SLinus Torvalds cond = fpucondbit[MIPSInst_FT(ir) >> 2]; 16371da177e4SLinus Torvalds if (((ctx->fcr31 & cond) != 0) != 16381da177e4SLinus Torvalds ((MIPSInst_FT(ir) & 1) != 0)) 16391da177e4SLinus Torvalds return 0; 16401da177e4SLinus Torvalds SPFROMREG(rv.s, MIPSInst_FS(ir)); 16411da177e4SLinus Torvalds break; 16421da177e4SLinus Torvalds case fmovz_op: 16431da177e4SLinus Torvalds if (xcp->regs[MIPSInst_FT(ir)] != 0) 16441da177e4SLinus Torvalds return 0; 16451da177e4SLinus Torvalds SPFROMREG(rv.s, MIPSInst_FS(ir)); 16461da177e4SLinus Torvalds break; 16471da177e4SLinus Torvalds case fmovn_op: 16481da177e4SLinus Torvalds if (xcp->regs[MIPSInst_FT(ir)] == 0) 16491da177e4SLinus Torvalds return 0; 16501da177e4SLinus Torvalds SPFROMREG(rv.s, MIPSInst_FS(ir)); 16511da177e4SLinus Torvalds break; 16521da177e4SLinus Torvalds #endif 16531da177e4SLinus Torvalds case fabs_op: 16541da177e4SLinus Torvalds handler.u = ieee754sp_abs; 16551da177e4SLinus Torvalds goto scopuop; 16561da177e4SLinus Torvalds case fneg_op: 16571da177e4SLinus Torvalds handler.u = ieee754sp_neg; 16581da177e4SLinus Torvalds goto scopuop; 16591da177e4SLinus Torvalds case fmov_op: 16601da177e4SLinus Torvalds /* an easy one */ 16611da177e4SLinus Torvalds SPFROMREG(rv.s, MIPSInst_FS(ir)); 16621da177e4SLinus Torvalds goto copcsr; 16631da177e4SLinus Torvalds 16641da177e4SLinus Torvalds /* binary op on handler */ 16651da177e4SLinus Torvalds scopbop: 16661da177e4SLinus Torvalds { 16672209bcb1SRalf Baechle union ieee754sp fs, ft; 16681da177e4SLinus Torvalds 16691da177e4SLinus Torvalds SPFROMREG(fs, MIPSInst_FS(ir)); 16701da177e4SLinus Torvalds SPFROMREG(ft, MIPSInst_FT(ir)); 16711da177e4SLinus Torvalds 16721da177e4SLinus Torvalds rv.s = (*handler.b) (fs, ft); 16731da177e4SLinus Torvalds goto copcsr; 16741da177e4SLinus Torvalds } 16751da177e4SLinus Torvalds scopuop: 16761da177e4SLinus Torvalds { 16772209bcb1SRalf Baechle union ieee754sp fs; 16781da177e4SLinus Torvalds 16791da177e4SLinus Torvalds SPFROMREG(fs, MIPSInst_FS(ir)); 16801da177e4SLinus Torvalds rv.s = (*handler.u) (fs); 16811da177e4SLinus Torvalds goto copcsr; 16821da177e4SLinus Torvalds } 16831da177e4SLinus Torvalds copcsr: 16841da177e4SLinus Torvalds if (ieee754_cxtest(IEEE754_INEXACT)) 16851da177e4SLinus Torvalds rcsr |= FPU_CSR_INE_X | FPU_CSR_INE_S; 16861da177e4SLinus Torvalds if (ieee754_cxtest(IEEE754_UNDERFLOW)) 16871da177e4SLinus Torvalds rcsr |= FPU_CSR_UDF_X | FPU_CSR_UDF_S; 16881da177e4SLinus Torvalds if (ieee754_cxtest(IEEE754_OVERFLOW)) 16891da177e4SLinus Torvalds rcsr |= FPU_CSR_OVF_X | FPU_CSR_OVF_S; 16901da177e4SLinus Torvalds if (ieee754_cxtest(IEEE754_ZERO_DIVIDE)) 16911da177e4SLinus Torvalds rcsr |= FPU_CSR_DIV_X | FPU_CSR_DIV_S; 16921da177e4SLinus Torvalds if (ieee754_cxtest(IEEE754_INVALID_OPERATION)) 16931da177e4SLinus Torvalds rcsr |= FPU_CSR_INV_X | FPU_CSR_INV_S; 16941da177e4SLinus Torvalds break; 16951da177e4SLinus Torvalds 16961da177e4SLinus Torvalds /* unary conv ops */ 16971da177e4SLinus Torvalds case fcvts_op: 16981da177e4SLinus Torvalds return SIGILL; /* not defined */ 16991da177e4SLinus Torvalds case fcvtd_op:{ 17002209bcb1SRalf Baechle union ieee754sp fs; 17011da177e4SLinus Torvalds 17021da177e4SLinus Torvalds SPFROMREG(fs, MIPSInst_FS(ir)); 17031da177e4SLinus Torvalds rv.d = ieee754dp_fsp(fs); 17041da177e4SLinus Torvalds rfmt = d_fmt; 17051da177e4SLinus Torvalds goto copcsr; 17061da177e4SLinus Torvalds } 17071da177e4SLinus Torvalds case fcvtw_op:{ 17082209bcb1SRalf Baechle union ieee754sp fs; 17091da177e4SLinus Torvalds 17101da177e4SLinus Torvalds SPFROMREG(fs, MIPSInst_FS(ir)); 17111da177e4SLinus Torvalds rv.w = ieee754sp_tint(fs); 17121da177e4SLinus Torvalds rfmt = w_fmt; 17131da177e4SLinus Torvalds goto copcsr; 17141da177e4SLinus Torvalds } 17151da177e4SLinus Torvalds 1716587cb98fSRalf Baechle #if __mips >= 2 || defined(__mips64) 17171da177e4SLinus Torvalds case fround_op: 17181da177e4SLinus Torvalds case ftrunc_op: 17191da177e4SLinus Torvalds case fceil_op: 17201da177e4SLinus Torvalds case ffloor_op:{ 17211da177e4SLinus Torvalds unsigned int oldrm = ieee754_csr.rm; 17222209bcb1SRalf Baechle union ieee754sp fs; 17231da177e4SLinus Torvalds 17241da177e4SLinus Torvalds SPFROMREG(fs, MIPSInst_FS(ir)); 17253f135530SShane McDonald ieee754_csr.rm = ieee_rm[modeindex(MIPSInst_FUNC(ir))]; 17261da177e4SLinus Torvalds rv.w = ieee754sp_tint(fs); 17271da177e4SLinus Torvalds ieee754_csr.rm = oldrm; 17281da177e4SLinus Torvalds rfmt = w_fmt; 17291da177e4SLinus Torvalds goto copcsr; 17301da177e4SLinus Torvalds } 17311da177e4SLinus Torvalds #endif /* __mips >= 2 */ 17321da177e4SLinus Torvalds 17334b724efdSRalf Baechle #if defined(__mips64) 17341da177e4SLinus Torvalds case fcvtl_op:{ 17352209bcb1SRalf Baechle union ieee754sp fs; 17361da177e4SLinus Torvalds 17371da177e4SLinus Torvalds SPFROMREG(fs, MIPSInst_FS(ir)); 17381da177e4SLinus Torvalds rv.l = ieee754sp_tlong(fs); 17391da177e4SLinus Torvalds rfmt = l_fmt; 17401da177e4SLinus Torvalds goto copcsr; 17411da177e4SLinus Torvalds } 17421da177e4SLinus Torvalds 17431da177e4SLinus Torvalds case froundl_op: 17441da177e4SLinus Torvalds case ftruncl_op: 17451da177e4SLinus Torvalds case fceill_op: 17461da177e4SLinus Torvalds case ffloorl_op:{ 17471da177e4SLinus Torvalds unsigned int oldrm = ieee754_csr.rm; 17482209bcb1SRalf Baechle union ieee754sp fs; 17491da177e4SLinus Torvalds 17501da177e4SLinus Torvalds SPFROMREG(fs, MIPSInst_FS(ir)); 17513f135530SShane McDonald ieee754_csr.rm = ieee_rm[modeindex(MIPSInst_FUNC(ir))]; 17521da177e4SLinus Torvalds rv.l = ieee754sp_tlong(fs); 17531da177e4SLinus Torvalds ieee754_csr.rm = oldrm; 17541da177e4SLinus Torvalds rfmt = l_fmt; 17551da177e4SLinus Torvalds goto copcsr; 17561da177e4SLinus Torvalds } 17574b724efdSRalf Baechle #endif /* defined(__mips64) */ 17581da177e4SLinus Torvalds 17591da177e4SLinus Torvalds default: 17601da177e4SLinus Torvalds if (MIPSInst_FUNC(ir) >= fcmp_op) { 17611da177e4SLinus Torvalds unsigned cmpop = MIPSInst_FUNC(ir) - fcmp_op; 17622209bcb1SRalf Baechle union ieee754sp fs, ft; 17631da177e4SLinus Torvalds 17641da177e4SLinus Torvalds SPFROMREG(fs, MIPSInst_FS(ir)); 17651da177e4SLinus Torvalds SPFROMREG(ft, MIPSInst_FT(ir)); 17661da177e4SLinus Torvalds rv.w = ieee754sp_cmp(fs, ft, 17671da177e4SLinus Torvalds cmptab[cmpop & 0x7], cmpop & 0x8); 17681da177e4SLinus Torvalds rfmt = -1; 17691da177e4SLinus Torvalds if ((cmpop & 0x8) && ieee754_cxtest 17701da177e4SLinus Torvalds (IEEE754_INVALID_OPERATION)) 17711da177e4SLinus Torvalds rcsr = FPU_CSR_INV_X | FPU_CSR_INV_S; 17721da177e4SLinus Torvalds else 17731da177e4SLinus Torvalds goto copcsr; 17741da177e4SLinus Torvalds 17751da177e4SLinus Torvalds } 17761da177e4SLinus Torvalds else { 17771da177e4SLinus Torvalds return SIGILL; 17781da177e4SLinus Torvalds } 17791da177e4SLinus Torvalds break; 17801da177e4SLinus Torvalds } 17811da177e4SLinus Torvalds break; 17821da177e4SLinus Torvalds } 17831da177e4SLinus Torvalds 17841da177e4SLinus Torvalds case d_fmt:{ 17851da177e4SLinus Torvalds union { 17862209bcb1SRalf Baechle union ieee754dp(*b) (union ieee754dp, union ieee754dp); 17872209bcb1SRalf Baechle union ieee754dp(*u) (union ieee754dp); 17881da177e4SLinus Torvalds } handler; 17891da177e4SLinus Torvalds 17901da177e4SLinus Torvalds switch (MIPSInst_FUNC(ir)) { 17911da177e4SLinus Torvalds /* binary ops */ 17921da177e4SLinus Torvalds case fadd_op: 17931da177e4SLinus Torvalds handler.b = ieee754dp_add; 17941da177e4SLinus Torvalds goto dcopbop; 17951da177e4SLinus Torvalds case fsub_op: 17961da177e4SLinus Torvalds handler.b = ieee754dp_sub; 17971da177e4SLinus Torvalds goto dcopbop; 17981da177e4SLinus Torvalds case fmul_op: 17991da177e4SLinus Torvalds handler.b = ieee754dp_mul; 18001da177e4SLinus Torvalds goto dcopbop; 18011da177e4SLinus Torvalds case fdiv_op: 18021da177e4SLinus Torvalds handler.b = ieee754dp_div; 18031da177e4SLinus Torvalds goto dcopbop; 18041da177e4SLinus Torvalds 18051da177e4SLinus Torvalds /* unary ops */ 1806587cb98fSRalf Baechle #if __mips >= 2 || defined(__mips64) 18071da177e4SLinus Torvalds case fsqrt_op: 18081da177e4SLinus Torvalds handler.u = ieee754dp_sqrt; 18091da177e4SLinus Torvalds goto dcopuop; 18101da177e4SLinus Torvalds #endif 18111da177e4SLinus Torvalds #if __mips >= 4 && __mips != 32 18121da177e4SLinus Torvalds case frsqrt_op: 18131da177e4SLinus Torvalds handler.u = fpemu_dp_rsqrt; 18141da177e4SLinus Torvalds goto dcopuop; 18151da177e4SLinus Torvalds case frecip_op: 18161da177e4SLinus Torvalds handler.u = fpemu_dp_recip; 18171da177e4SLinus Torvalds goto dcopuop; 18181da177e4SLinus Torvalds #endif 18191da177e4SLinus Torvalds #if __mips >= 4 18201da177e4SLinus Torvalds case fmovc_op: 18211da177e4SLinus Torvalds cond = fpucondbit[MIPSInst_FT(ir) >> 2]; 18221da177e4SLinus Torvalds if (((ctx->fcr31 & cond) != 0) != 18231da177e4SLinus Torvalds ((MIPSInst_FT(ir) & 1) != 0)) 18241da177e4SLinus Torvalds return 0; 18251da177e4SLinus Torvalds DPFROMREG(rv.d, MIPSInst_FS(ir)); 18261da177e4SLinus Torvalds break; 18271da177e4SLinus Torvalds case fmovz_op: 18281da177e4SLinus Torvalds if (xcp->regs[MIPSInst_FT(ir)] != 0) 18291da177e4SLinus Torvalds return 0; 18301da177e4SLinus Torvalds DPFROMREG(rv.d, MIPSInst_FS(ir)); 18311da177e4SLinus Torvalds break; 18321da177e4SLinus Torvalds case fmovn_op: 18331da177e4SLinus Torvalds if (xcp->regs[MIPSInst_FT(ir)] == 0) 18341da177e4SLinus Torvalds return 0; 18351da177e4SLinus Torvalds DPFROMREG(rv.d, MIPSInst_FS(ir)); 18361da177e4SLinus Torvalds break; 18371da177e4SLinus Torvalds #endif 18381da177e4SLinus Torvalds case fabs_op: 18391da177e4SLinus Torvalds handler.u = ieee754dp_abs; 18401da177e4SLinus Torvalds goto dcopuop; 18411da177e4SLinus Torvalds 18421da177e4SLinus Torvalds case fneg_op: 18431da177e4SLinus Torvalds handler.u = ieee754dp_neg; 18441da177e4SLinus Torvalds goto dcopuop; 18451da177e4SLinus Torvalds 18461da177e4SLinus Torvalds case fmov_op: 18471da177e4SLinus Torvalds /* an easy one */ 18481da177e4SLinus Torvalds DPFROMREG(rv.d, MIPSInst_FS(ir)); 18491da177e4SLinus Torvalds goto copcsr; 18501da177e4SLinus Torvalds 18511da177e4SLinus Torvalds /* binary op on handler */ 18521da177e4SLinus Torvalds dcopbop:{ 18532209bcb1SRalf Baechle union ieee754dp fs, ft; 18541da177e4SLinus Torvalds 18551da177e4SLinus Torvalds DPFROMREG(fs, MIPSInst_FS(ir)); 18561da177e4SLinus Torvalds DPFROMREG(ft, MIPSInst_FT(ir)); 18571da177e4SLinus Torvalds 18581da177e4SLinus Torvalds rv.d = (*handler.b) (fs, ft); 18591da177e4SLinus Torvalds goto copcsr; 18601da177e4SLinus Torvalds } 18611da177e4SLinus Torvalds dcopuop:{ 18622209bcb1SRalf Baechle union ieee754dp fs; 18631da177e4SLinus Torvalds 18641da177e4SLinus Torvalds DPFROMREG(fs, MIPSInst_FS(ir)); 18651da177e4SLinus Torvalds rv.d = (*handler.u) (fs); 18661da177e4SLinus Torvalds goto copcsr; 18671da177e4SLinus Torvalds } 18681da177e4SLinus Torvalds 18691da177e4SLinus Torvalds /* unary conv ops */ 18701da177e4SLinus Torvalds case fcvts_op:{ 18712209bcb1SRalf Baechle union ieee754dp fs; 18721da177e4SLinus Torvalds 18731da177e4SLinus Torvalds DPFROMREG(fs, MIPSInst_FS(ir)); 18741da177e4SLinus Torvalds rv.s = ieee754sp_fdp(fs); 18751da177e4SLinus Torvalds rfmt = s_fmt; 18761da177e4SLinus Torvalds goto copcsr; 18771da177e4SLinus Torvalds } 18781da177e4SLinus Torvalds case fcvtd_op: 18791da177e4SLinus Torvalds return SIGILL; /* not defined */ 18801da177e4SLinus Torvalds 18811da177e4SLinus Torvalds case fcvtw_op:{ 18822209bcb1SRalf Baechle union ieee754dp fs; 18831da177e4SLinus Torvalds 18841da177e4SLinus Torvalds DPFROMREG(fs, MIPSInst_FS(ir)); 18851da177e4SLinus Torvalds rv.w = ieee754dp_tint(fs); /* wrong */ 18861da177e4SLinus Torvalds rfmt = w_fmt; 18871da177e4SLinus Torvalds goto copcsr; 18881da177e4SLinus Torvalds } 18891da177e4SLinus Torvalds 1890587cb98fSRalf Baechle #if __mips >= 2 || defined(__mips64) 18911da177e4SLinus Torvalds case fround_op: 18921da177e4SLinus Torvalds case ftrunc_op: 18931da177e4SLinus Torvalds case fceil_op: 18941da177e4SLinus Torvalds case ffloor_op:{ 18951da177e4SLinus Torvalds unsigned int oldrm = ieee754_csr.rm; 18962209bcb1SRalf Baechle union ieee754dp fs; 18971da177e4SLinus Torvalds 18981da177e4SLinus Torvalds DPFROMREG(fs, MIPSInst_FS(ir)); 18993f135530SShane McDonald ieee754_csr.rm = ieee_rm[modeindex(MIPSInst_FUNC(ir))]; 19001da177e4SLinus Torvalds rv.w = ieee754dp_tint(fs); 19011da177e4SLinus Torvalds ieee754_csr.rm = oldrm; 19021da177e4SLinus Torvalds rfmt = w_fmt; 19031da177e4SLinus Torvalds goto copcsr; 19041da177e4SLinus Torvalds } 19051da177e4SLinus Torvalds #endif 19061da177e4SLinus Torvalds 19074b724efdSRalf Baechle #if defined(__mips64) 19081da177e4SLinus Torvalds case fcvtl_op:{ 19092209bcb1SRalf Baechle union ieee754dp fs; 19101da177e4SLinus Torvalds 19111da177e4SLinus Torvalds DPFROMREG(fs, MIPSInst_FS(ir)); 19121da177e4SLinus Torvalds rv.l = ieee754dp_tlong(fs); 19131da177e4SLinus Torvalds rfmt = l_fmt; 19141da177e4SLinus Torvalds goto copcsr; 19151da177e4SLinus Torvalds } 19161da177e4SLinus Torvalds 19171da177e4SLinus Torvalds case froundl_op: 19181da177e4SLinus Torvalds case ftruncl_op: 19191da177e4SLinus Torvalds case fceill_op: 19201da177e4SLinus Torvalds case ffloorl_op:{ 19211da177e4SLinus Torvalds unsigned int oldrm = ieee754_csr.rm; 19222209bcb1SRalf Baechle union ieee754dp fs; 19231da177e4SLinus Torvalds 19241da177e4SLinus Torvalds DPFROMREG(fs, MIPSInst_FS(ir)); 19253f135530SShane McDonald ieee754_csr.rm = ieee_rm[modeindex(MIPSInst_FUNC(ir))]; 19261da177e4SLinus Torvalds rv.l = ieee754dp_tlong(fs); 19271da177e4SLinus Torvalds ieee754_csr.rm = oldrm; 19281da177e4SLinus Torvalds rfmt = l_fmt; 19291da177e4SLinus Torvalds goto copcsr; 19301da177e4SLinus Torvalds } 19314b724efdSRalf Baechle #endif /* __mips >= 3 */ 19321da177e4SLinus Torvalds 19331da177e4SLinus Torvalds default: 19341da177e4SLinus Torvalds if (MIPSInst_FUNC(ir) >= fcmp_op) { 19351da177e4SLinus Torvalds unsigned cmpop = MIPSInst_FUNC(ir) - fcmp_op; 19362209bcb1SRalf Baechle union ieee754dp fs, ft; 19371da177e4SLinus Torvalds 19381da177e4SLinus Torvalds DPFROMREG(fs, MIPSInst_FS(ir)); 19391da177e4SLinus Torvalds DPFROMREG(ft, MIPSInst_FT(ir)); 19401da177e4SLinus Torvalds rv.w = ieee754dp_cmp(fs, ft, 19411da177e4SLinus Torvalds cmptab[cmpop & 0x7], cmpop & 0x8); 19421da177e4SLinus Torvalds rfmt = -1; 19431da177e4SLinus Torvalds if ((cmpop & 0x8) 19441da177e4SLinus Torvalds && 19451da177e4SLinus Torvalds ieee754_cxtest 19461da177e4SLinus Torvalds (IEEE754_INVALID_OPERATION)) 19471da177e4SLinus Torvalds rcsr = FPU_CSR_INV_X | FPU_CSR_INV_S; 19481da177e4SLinus Torvalds else 19491da177e4SLinus Torvalds goto copcsr; 19501da177e4SLinus Torvalds 19511da177e4SLinus Torvalds } 19521da177e4SLinus Torvalds else { 19531da177e4SLinus Torvalds return SIGILL; 19541da177e4SLinus Torvalds } 19551da177e4SLinus Torvalds break; 19561da177e4SLinus Torvalds } 19571da177e4SLinus Torvalds break; 19581da177e4SLinus Torvalds } 19591da177e4SLinus Torvalds 19601da177e4SLinus Torvalds case w_fmt:{ 19612209bcb1SRalf Baechle union ieee754sp fs; 19621da177e4SLinus Torvalds 19631da177e4SLinus Torvalds switch (MIPSInst_FUNC(ir)) { 19641da177e4SLinus Torvalds case fcvts_op: 19651da177e4SLinus Torvalds /* convert word to single precision real */ 19661da177e4SLinus Torvalds SPFROMREG(fs, MIPSInst_FS(ir)); 19671da177e4SLinus Torvalds rv.s = ieee754sp_fint(fs.bits); 19681da177e4SLinus Torvalds rfmt = s_fmt; 19691da177e4SLinus Torvalds goto copcsr; 19701da177e4SLinus Torvalds case fcvtd_op: 19711da177e4SLinus Torvalds /* convert word to double precision real */ 19721da177e4SLinus Torvalds SPFROMREG(fs, MIPSInst_FS(ir)); 19731da177e4SLinus Torvalds rv.d = ieee754dp_fint(fs.bits); 19741da177e4SLinus Torvalds rfmt = d_fmt; 19751da177e4SLinus Torvalds goto copcsr; 19761da177e4SLinus Torvalds default: 19771da177e4SLinus Torvalds return SIGILL; 19781da177e4SLinus Torvalds } 19791da177e4SLinus Torvalds break; 19801da177e4SLinus Torvalds } 19811da177e4SLinus Torvalds 19824b724efdSRalf Baechle #if defined(__mips64) 19831da177e4SLinus Torvalds case l_fmt:{ 1984bbd426f5SPaul Burton u64 bits; 1985bbd426f5SPaul Burton DIFROMREG(bits, MIPSInst_FS(ir)); 1986bbd426f5SPaul Burton 19871da177e4SLinus Torvalds switch (MIPSInst_FUNC(ir)) { 19881da177e4SLinus Torvalds case fcvts_op: 19891da177e4SLinus Torvalds /* convert long to single precision real */ 1990bbd426f5SPaul Burton rv.s = ieee754sp_flong(bits); 19911da177e4SLinus Torvalds rfmt = s_fmt; 19921da177e4SLinus Torvalds goto copcsr; 19931da177e4SLinus Torvalds case fcvtd_op: 19941da177e4SLinus Torvalds /* convert long to double precision real */ 1995bbd426f5SPaul Burton rv.d = ieee754dp_flong(bits); 19961da177e4SLinus Torvalds rfmt = d_fmt; 19971da177e4SLinus Torvalds goto copcsr; 19981da177e4SLinus Torvalds default: 19991da177e4SLinus Torvalds return SIGILL; 20001da177e4SLinus Torvalds } 20011da177e4SLinus Torvalds break; 20021da177e4SLinus Torvalds } 20031da177e4SLinus Torvalds #endif 20041da177e4SLinus Torvalds 20051da177e4SLinus Torvalds default: 20061da177e4SLinus Torvalds return SIGILL; 20071da177e4SLinus Torvalds } 20081da177e4SLinus Torvalds 20091da177e4SLinus Torvalds /* 20101da177e4SLinus Torvalds * Update the fpu CSR register for this operation. 20111da177e4SLinus Torvalds * If an exception is required, generate a tidy SIGFPE exception, 20121da177e4SLinus Torvalds * without updating the result register. 20131da177e4SLinus Torvalds * Note: cause exception bits do not accumulate, they are rewritten 20141da177e4SLinus Torvalds * for each op; only the flag/sticky bits accumulate. 20151da177e4SLinus Torvalds */ 20161da177e4SLinus Torvalds ctx->fcr31 = (ctx->fcr31 & ~FPU_CSR_ALL_X) | rcsr; 20171da177e4SLinus Torvalds if ((ctx->fcr31 >> 5) & ctx->fcr31 & FPU_CSR_ALL_E) { 20181da177e4SLinus Torvalds /*printk ("SIGFPE: fpu csr = %08x\n",ctx->fcr31); */ 20191da177e4SLinus Torvalds return SIGFPE; 20201da177e4SLinus Torvalds } 20211da177e4SLinus Torvalds 20221da177e4SLinus Torvalds /* 20231da177e4SLinus Torvalds * Now we can safely write the result back to the register file. 20241da177e4SLinus Torvalds */ 20251da177e4SLinus Torvalds switch (rfmt) { 20261da177e4SLinus Torvalds case -1:{ 20271da177e4SLinus Torvalds #if __mips >= 4 20281da177e4SLinus Torvalds cond = fpucondbit[MIPSInst_FD(ir) >> 2]; 20291da177e4SLinus Torvalds #else 20301da177e4SLinus Torvalds cond = FPU_CSR_COND; 20311da177e4SLinus Torvalds #endif 20321da177e4SLinus Torvalds if (rv.w) 20331da177e4SLinus Torvalds ctx->fcr31 |= cond; 20341da177e4SLinus Torvalds else 20351da177e4SLinus Torvalds ctx->fcr31 &= ~cond; 20361da177e4SLinus Torvalds break; 20371da177e4SLinus Torvalds } 20381da177e4SLinus Torvalds case d_fmt: 20391da177e4SLinus Torvalds DPTOREG(rv.d, MIPSInst_FD(ir)); 20401da177e4SLinus Torvalds break; 20411da177e4SLinus Torvalds case s_fmt: 20421da177e4SLinus Torvalds SPTOREG(rv.s, MIPSInst_FD(ir)); 20431da177e4SLinus Torvalds break; 20441da177e4SLinus Torvalds case w_fmt: 20451da177e4SLinus Torvalds SITOREG(rv.w, MIPSInst_FD(ir)); 20461da177e4SLinus Torvalds break; 20474b724efdSRalf Baechle #if defined(__mips64) 20481da177e4SLinus Torvalds case l_fmt: 20491da177e4SLinus Torvalds DITOREG(rv.l, MIPSInst_FD(ir)); 20501da177e4SLinus Torvalds break; 20511da177e4SLinus Torvalds #endif 20521da177e4SLinus Torvalds default: 20531da177e4SLinus Torvalds return SIGILL; 20541da177e4SLinus Torvalds } 20551da177e4SLinus Torvalds 20561da177e4SLinus Torvalds return 0; 20571da177e4SLinus Torvalds } 20581da177e4SLinus Torvalds 2059e04582b7SAtsushi Nemoto int fpu_emulator_cop1Handler(struct pt_regs *xcp, struct mips_fpu_struct *ctx, 2060515b029dSDavid Daney int has_fpu, void *__user *fault_addr) 20611da177e4SLinus Torvalds { 2062333d1f67SRalf Baechle unsigned long oldepc, prevepc; 2063102cedc3SLeonid Yegoshin struct mm_decoded_insn dec_insn; 2064102cedc3SLeonid Yegoshin u16 instr[4]; 2065102cedc3SLeonid Yegoshin u16 *instr_ptr; 20661da177e4SLinus Torvalds int sig = 0; 20671da177e4SLinus Torvalds 20681da177e4SLinus Torvalds oldepc = xcp->cp0_epc; 20691da177e4SLinus Torvalds do { 20701da177e4SLinus Torvalds prevepc = xcp->cp0_epc; 20711da177e4SLinus Torvalds 2072102cedc3SLeonid Yegoshin if (get_isa16_mode(prevepc) && cpu_has_mmips) { 2073102cedc3SLeonid Yegoshin /* 2074102cedc3SLeonid Yegoshin * Get next 2 microMIPS instructions and convert them 2075102cedc3SLeonid Yegoshin * into 32-bit instructions. 2076102cedc3SLeonid Yegoshin */ 2077102cedc3SLeonid Yegoshin if ((get_user(instr[0], (u16 __user *)msk_isa16_mode(xcp->cp0_epc))) || 2078102cedc3SLeonid Yegoshin (get_user(instr[1], (u16 __user *)msk_isa16_mode(xcp->cp0_epc + 2))) || 2079102cedc3SLeonid Yegoshin (get_user(instr[2], (u16 __user *)msk_isa16_mode(xcp->cp0_epc + 4))) || 2080102cedc3SLeonid Yegoshin (get_user(instr[3], (u16 __user *)msk_isa16_mode(xcp->cp0_epc + 6)))) { 2081b6ee75edSDavid Daney MIPS_FPU_EMU_INC_STATS(errors); 20821da177e4SLinus Torvalds return SIGBUS; 20831da177e4SLinus Torvalds } 2084102cedc3SLeonid Yegoshin instr_ptr = instr; 2085102cedc3SLeonid Yegoshin 2086102cedc3SLeonid Yegoshin /* Get first instruction. */ 2087102cedc3SLeonid Yegoshin if (mm_insn_16bit(*instr_ptr)) { 2088102cedc3SLeonid Yegoshin /* Duplicate the half-word. */ 2089102cedc3SLeonid Yegoshin dec_insn.insn = (*instr_ptr << 16) | 2090102cedc3SLeonid Yegoshin (*instr_ptr); 2091102cedc3SLeonid Yegoshin /* 16-bit instruction. */ 2092102cedc3SLeonid Yegoshin dec_insn.pc_inc = 2; 2093102cedc3SLeonid Yegoshin instr_ptr += 1; 2094102cedc3SLeonid Yegoshin } else { 2095102cedc3SLeonid Yegoshin dec_insn.insn = (*instr_ptr << 16) | 2096102cedc3SLeonid Yegoshin *(instr_ptr+1); 2097102cedc3SLeonid Yegoshin /* 32-bit instruction. */ 2098102cedc3SLeonid Yegoshin dec_insn.pc_inc = 4; 2099102cedc3SLeonid Yegoshin instr_ptr += 2; 2100515b029dSDavid Daney } 2101102cedc3SLeonid Yegoshin /* Get second instruction. */ 2102102cedc3SLeonid Yegoshin if (mm_insn_16bit(*instr_ptr)) { 2103102cedc3SLeonid Yegoshin /* Duplicate the half-word. */ 2104102cedc3SLeonid Yegoshin dec_insn.next_insn = (*instr_ptr << 16) | 2105102cedc3SLeonid Yegoshin (*instr_ptr); 2106102cedc3SLeonid Yegoshin /* 16-bit instruction. */ 2107102cedc3SLeonid Yegoshin dec_insn.next_pc_inc = 2; 2108102cedc3SLeonid Yegoshin } else { 2109102cedc3SLeonid Yegoshin dec_insn.next_insn = (*instr_ptr << 16) | 2110102cedc3SLeonid Yegoshin *(instr_ptr+1); 2111102cedc3SLeonid Yegoshin /* 32-bit instruction. */ 2112102cedc3SLeonid Yegoshin dec_insn.next_pc_inc = 4; 2113102cedc3SLeonid Yegoshin } 2114102cedc3SLeonid Yegoshin dec_insn.micro_mips_mode = 1; 2115102cedc3SLeonid Yegoshin } else { 2116102cedc3SLeonid Yegoshin if ((get_user(dec_insn.insn, 2117102cedc3SLeonid Yegoshin (mips_instruction __user *) xcp->cp0_epc)) || 2118102cedc3SLeonid Yegoshin (get_user(dec_insn.next_insn, 2119102cedc3SLeonid Yegoshin (mips_instruction __user *)(xcp->cp0_epc+4)))) { 2120102cedc3SLeonid Yegoshin MIPS_FPU_EMU_INC_STATS(errors); 2121102cedc3SLeonid Yegoshin return SIGBUS; 2122102cedc3SLeonid Yegoshin } 2123102cedc3SLeonid Yegoshin dec_insn.pc_inc = 4; 2124102cedc3SLeonid Yegoshin dec_insn.next_pc_inc = 4; 2125102cedc3SLeonid Yegoshin dec_insn.micro_mips_mode = 0; 2126102cedc3SLeonid Yegoshin } 2127102cedc3SLeonid Yegoshin 2128102cedc3SLeonid Yegoshin if ((dec_insn.insn == 0) || 2129102cedc3SLeonid Yegoshin ((dec_insn.pc_inc == 2) && 2130102cedc3SLeonid Yegoshin ((dec_insn.insn & 0xffff) == MM_NOP16))) 2131102cedc3SLeonid Yegoshin xcp->cp0_epc += dec_insn.pc_inc; /* Skip NOPs */ 21321da177e4SLinus Torvalds else { 2133cd21dfcfSRalf Baechle /* 2134cd21dfcfSRalf Baechle * The 'ieee754_csr' is an alias of 2135cd21dfcfSRalf Baechle * ctx->fcr31. No need to copy ctx->fcr31 to 2136cd21dfcfSRalf Baechle * ieee754_csr. But ieee754_csr.rm is ieee 2137cd21dfcfSRalf Baechle * library modes. (not mips rounding mode) 2138cd21dfcfSRalf Baechle */ 2139cd21dfcfSRalf Baechle /* convert to ieee library modes */ 2140cd21dfcfSRalf Baechle ieee754_csr.rm = ieee_rm[ieee754_csr.rm]; 2141102cedc3SLeonid Yegoshin sig = cop1Emulate(xcp, ctx, dec_insn, fault_addr); 2142cd21dfcfSRalf Baechle /* revert to mips rounding mode */ 2143cd21dfcfSRalf Baechle ieee754_csr.rm = mips_rm[ieee754_csr.rm]; 21441da177e4SLinus Torvalds } 21451da177e4SLinus Torvalds 2146e04582b7SAtsushi Nemoto if (has_fpu) 21471da177e4SLinus Torvalds break; 21481da177e4SLinus Torvalds if (sig) 21491da177e4SLinus Torvalds break; 21501da177e4SLinus Torvalds 21511da177e4SLinus Torvalds cond_resched(); 21521da177e4SLinus Torvalds } while (xcp->cp0_epc > prevepc); 21531da177e4SLinus Torvalds 21541da177e4SLinus Torvalds /* SIGILL indicates a non-fpu instruction */ 21551da177e4SLinus Torvalds if (sig == SIGILL && xcp->cp0_epc != oldepc) 21561da177e4SLinus Torvalds /* but if epc has advanced, then ignore it */ 21571da177e4SLinus Torvalds sig = 0; 21581da177e4SLinus Torvalds 21591da177e4SLinus Torvalds return sig; 21601da177e4SLinus Torvalds } 216183fd38caSAtsushi Nemoto 216283fd38caSAtsushi Nemoto #ifdef CONFIG_DEBUG_FS 2163b6ee75edSDavid Daney 2164b6ee75edSDavid Daney static int fpuemu_stat_get(void *data, u64 *val) 2165b6ee75edSDavid Daney { 2166b6ee75edSDavid Daney int cpu; 2167b6ee75edSDavid Daney unsigned long sum = 0; 2168b6ee75edSDavid Daney for_each_online_cpu(cpu) { 2169b6ee75edSDavid Daney struct mips_fpu_emulator_stats *ps; 2170b6ee75edSDavid Daney local_t *pv; 2171b6ee75edSDavid Daney ps = &per_cpu(fpuemustats, cpu); 2172b6ee75edSDavid Daney pv = (void *)ps + (unsigned long)data; 2173b6ee75edSDavid Daney sum += local_read(pv); 2174b6ee75edSDavid Daney } 2175b6ee75edSDavid Daney *val = sum; 2176b6ee75edSDavid Daney return 0; 2177b6ee75edSDavid Daney } 2178b6ee75edSDavid Daney DEFINE_SIMPLE_ATTRIBUTE(fops_fpuemu_stat, fpuemu_stat_get, NULL, "%llu\n"); 2179b6ee75edSDavid Daney 218083fd38caSAtsushi Nemoto extern struct dentry *mips_debugfs_dir; 218183fd38caSAtsushi Nemoto static int __init debugfs_fpuemu(void) 218283fd38caSAtsushi Nemoto { 218383fd38caSAtsushi Nemoto struct dentry *d, *dir; 218483fd38caSAtsushi Nemoto 218583fd38caSAtsushi Nemoto if (!mips_debugfs_dir) 218683fd38caSAtsushi Nemoto return -ENODEV; 218783fd38caSAtsushi Nemoto dir = debugfs_create_dir("fpuemustats", mips_debugfs_dir); 2188ecab1f44SZhaolei if (!dir) 2189ecab1f44SZhaolei return -ENOMEM; 2190b6ee75edSDavid Daney 2191b6ee75edSDavid Daney #define FPU_STAT_CREATE(M) \ 2192b6ee75edSDavid Daney do { \ 2193b6ee75edSDavid Daney d = debugfs_create_file(#M , S_IRUGO, dir, \ 2194b6ee75edSDavid Daney (void *)offsetof(struct mips_fpu_emulator_stats, M), \ 2195b6ee75edSDavid Daney &fops_fpuemu_stat); \ 2196b6ee75edSDavid Daney if (!d) \ 2197b6ee75edSDavid Daney return -ENOMEM; \ 2198b6ee75edSDavid Daney } while (0) 2199b6ee75edSDavid Daney 2200b6ee75edSDavid Daney FPU_STAT_CREATE(emulated); 2201b6ee75edSDavid Daney FPU_STAT_CREATE(loads); 2202b6ee75edSDavid Daney FPU_STAT_CREATE(stores); 2203b6ee75edSDavid Daney FPU_STAT_CREATE(cp1ops); 2204b6ee75edSDavid Daney FPU_STAT_CREATE(cp1xops); 2205b6ee75edSDavid Daney FPU_STAT_CREATE(errors); 2206b6ee75edSDavid Daney 220783fd38caSAtsushi Nemoto return 0; 220883fd38caSAtsushi Nemoto } 220983fd38caSAtsushi Nemoto __initcall(debugfs_fpuemu); 221083fd38caSAtsushi Nemoto #endif 2211