11da177e4SLinus Torvalds /* 23f7cac41SRalf Baechle * cp1emu.c: a MIPS coprocessor 1 (FPU) instruction emulator 31da177e4SLinus Torvalds * 41da177e4SLinus Torvalds * MIPS floating point support 51da177e4SLinus Torvalds * Copyright (C) 1994-2000 Algorithmics Ltd. 61da177e4SLinus Torvalds * 71da177e4SLinus Torvalds * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com 81da177e4SLinus Torvalds * Copyright (C) 2000 MIPS Technologies, Inc. 91da177e4SLinus Torvalds * 101da177e4SLinus Torvalds * This program is free software; you can distribute it and/or modify it 111da177e4SLinus Torvalds * under the terms of the GNU General Public License (Version 2) as 121da177e4SLinus Torvalds * published by the Free Software Foundation. 131da177e4SLinus Torvalds * 141da177e4SLinus Torvalds * This program is distributed in the hope it will be useful, but WITHOUT 151da177e4SLinus Torvalds * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 161da177e4SLinus Torvalds * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 171da177e4SLinus Torvalds * for more details. 181da177e4SLinus Torvalds * 191da177e4SLinus Torvalds * You should have received a copy of the GNU General Public License along 201da177e4SLinus Torvalds * with this program; if not, write to the Free Software Foundation, Inc., 213f7cac41SRalf Baechle * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. 221da177e4SLinus Torvalds * 231da177e4SLinus Torvalds * A complete emulator for MIPS coprocessor 1 instructions. This is 241da177e4SLinus Torvalds * required for #float(switch) or #float(trap), where it catches all 251da177e4SLinus Torvalds * COP1 instructions via the "CoProcessor Unusable" exception. 261da177e4SLinus Torvalds * 271da177e4SLinus Torvalds * More surprisingly it is also required for #float(ieee), to help out 283f7cac41SRalf Baechle * the hardware FPU at the boundaries of the IEEE-754 representation 291da177e4SLinus Torvalds * (denormalised values, infinities, underflow, etc). It is made 301da177e4SLinus Torvalds * quite nasty because emulation of some non-COP1 instructions is 311da177e4SLinus Torvalds * required, e.g. in branch delay slots. 321da177e4SLinus Torvalds * 333f7cac41SRalf Baechle * Note if you know that you won't have an FPU, then you'll get much 341da177e4SLinus Torvalds * better performance by compiling with -msoft-float! 351da177e4SLinus Torvalds */ 361da177e4SLinus Torvalds #include <linux/sched.h> 3783fd38caSAtsushi Nemoto #include <linux/debugfs.h> 3808a07904SRalf Baechle #include <linux/kconfig.h> 3985c51c51SRalf Baechle #include <linux/percpu-defs.h> 407f788d2dSDeng-Cheng Zhu #include <linux/perf_event.h> 411da177e4SLinus Torvalds 42cd8ee345SRalf Baechle #include <asm/branch.h> 431da177e4SLinus Torvalds #include <asm/inst.h> 441da177e4SLinus Torvalds #include <asm/ptrace.h> 451da177e4SLinus Torvalds #include <asm/signal.h> 46cd8ee345SRalf Baechle #include <asm/uaccess.h> 47cd8ee345SRalf Baechle 48f6843626SMaciej W. Rozycki #include <asm/cpu-info.h> 49cd8ee345SRalf Baechle #include <asm/processor.h> 501da177e4SLinus Torvalds #include <asm/fpu_emulator.h> 51102cedc3SLeonid Yegoshin #include <asm/fpu.h> 52b0a668fbSLeonid Yegoshin #include <asm/mips-r2-to-r6-emul.h> 531da177e4SLinus Torvalds 541da177e4SLinus Torvalds #include "ieee754.h" 551da177e4SLinus Torvalds 561da177e4SLinus Torvalds /* Function which emulates a floating point instruction. */ 571da177e4SLinus Torvalds 58eae89076SAtsushi Nemoto static int fpu_emu(struct pt_regs *, struct mips_fpu_struct *, 591da177e4SLinus Torvalds mips_instruction); 601da177e4SLinus Torvalds 611da177e4SLinus Torvalds static int fpux_emu(struct pt_regs *, 62515b029dSDavid Daney struct mips_fpu_struct *, mips_instruction, void *__user *); 631da177e4SLinus Torvalds 641da177e4SLinus Torvalds /* Control registers */ 651da177e4SLinus Torvalds 661da177e4SLinus Torvalds #define FPCREG_RID 0 /* $0 = revision id */ 67*c491cfa2SMaciej W. Rozycki #define FPCREG_FCCR 25 /* $25 = fccr */ 68*c491cfa2SMaciej W. Rozycki #define FPCREG_FEXR 26 /* $26 = fexr */ 69*c491cfa2SMaciej W. Rozycki #define FPCREG_FENR 28 /* $28 = fenr */ 701da177e4SLinus Torvalds #define FPCREG_CSR 31 /* $31 = csr */ 711da177e4SLinus Torvalds 721da177e4SLinus Torvalds /* convert condition code register number to csr bit */ 73b0a668fbSLeonid Yegoshin const unsigned int fpucondbit[8] = { 74*c491cfa2SMaciej W. Rozycki FPU_CSR_COND, 751da177e4SLinus Torvalds FPU_CSR_COND1, 761da177e4SLinus Torvalds FPU_CSR_COND2, 771da177e4SLinus Torvalds FPU_CSR_COND3, 781da177e4SLinus Torvalds FPU_CSR_COND4, 791da177e4SLinus Torvalds FPU_CSR_COND5, 801da177e4SLinus Torvalds FPU_CSR_COND6, 811da177e4SLinus Torvalds FPU_CSR_COND7 821da177e4SLinus Torvalds }; 831da177e4SLinus Torvalds 84102cedc3SLeonid Yegoshin /* (microMIPS) Convert certain microMIPS instructions to MIPS32 format. */ 85102cedc3SLeonid Yegoshin static const int sd_format[] = {16, 17, 0, 0, 0, 0, 0, 0}; 86102cedc3SLeonid Yegoshin static const int sdps_format[] = {16, 17, 22, 0, 0, 0, 0, 0}; 87102cedc3SLeonid Yegoshin static const int dwl_format[] = {17, 20, 21, 0, 0, 0, 0, 0}; 88102cedc3SLeonid Yegoshin static const int swl_format[] = {16, 20, 21, 0, 0, 0, 0, 0}; 89102cedc3SLeonid Yegoshin 90102cedc3SLeonid Yegoshin /* 91102cedc3SLeonid Yegoshin * This functions translates a 32-bit microMIPS instruction 92102cedc3SLeonid Yegoshin * into a 32-bit MIPS32 instruction. Returns 0 on success 93102cedc3SLeonid Yegoshin * and SIGILL otherwise. 94102cedc3SLeonid Yegoshin */ 95102cedc3SLeonid Yegoshin static int microMIPS32_to_MIPS32(union mips_instruction *insn_ptr) 96102cedc3SLeonid Yegoshin { 97102cedc3SLeonid Yegoshin union mips_instruction insn = *insn_ptr; 98102cedc3SLeonid Yegoshin union mips_instruction mips32_insn = insn; 99102cedc3SLeonid Yegoshin int func, fmt, op; 100102cedc3SLeonid Yegoshin 101102cedc3SLeonid Yegoshin switch (insn.mm_i_format.opcode) { 102102cedc3SLeonid Yegoshin case mm_ldc132_op: 103102cedc3SLeonid Yegoshin mips32_insn.mm_i_format.opcode = ldc1_op; 104102cedc3SLeonid Yegoshin mips32_insn.mm_i_format.rt = insn.mm_i_format.rs; 105102cedc3SLeonid Yegoshin mips32_insn.mm_i_format.rs = insn.mm_i_format.rt; 106102cedc3SLeonid Yegoshin break; 107102cedc3SLeonid Yegoshin case mm_lwc132_op: 108102cedc3SLeonid Yegoshin mips32_insn.mm_i_format.opcode = lwc1_op; 109102cedc3SLeonid Yegoshin mips32_insn.mm_i_format.rt = insn.mm_i_format.rs; 110102cedc3SLeonid Yegoshin mips32_insn.mm_i_format.rs = insn.mm_i_format.rt; 111102cedc3SLeonid Yegoshin break; 112102cedc3SLeonid Yegoshin case mm_sdc132_op: 113102cedc3SLeonid Yegoshin mips32_insn.mm_i_format.opcode = sdc1_op; 114102cedc3SLeonid Yegoshin mips32_insn.mm_i_format.rt = insn.mm_i_format.rs; 115102cedc3SLeonid Yegoshin mips32_insn.mm_i_format.rs = insn.mm_i_format.rt; 116102cedc3SLeonid Yegoshin break; 117102cedc3SLeonid Yegoshin case mm_swc132_op: 118102cedc3SLeonid Yegoshin mips32_insn.mm_i_format.opcode = swc1_op; 119102cedc3SLeonid Yegoshin mips32_insn.mm_i_format.rt = insn.mm_i_format.rs; 120102cedc3SLeonid Yegoshin mips32_insn.mm_i_format.rs = insn.mm_i_format.rt; 121102cedc3SLeonid Yegoshin break; 122102cedc3SLeonid Yegoshin case mm_pool32i_op: 123102cedc3SLeonid Yegoshin /* NOTE: offset is << by 1 if in microMIPS mode. */ 124102cedc3SLeonid Yegoshin if ((insn.mm_i_format.rt == mm_bc1f_op) || 125102cedc3SLeonid Yegoshin (insn.mm_i_format.rt == mm_bc1t_op)) { 126102cedc3SLeonid Yegoshin mips32_insn.fb_format.opcode = cop1_op; 127102cedc3SLeonid Yegoshin mips32_insn.fb_format.bc = bc_op; 128102cedc3SLeonid Yegoshin mips32_insn.fb_format.flag = 129102cedc3SLeonid Yegoshin (insn.mm_i_format.rt == mm_bc1t_op) ? 1 : 0; 130102cedc3SLeonid Yegoshin } else 131102cedc3SLeonid Yegoshin return SIGILL; 132102cedc3SLeonid Yegoshin break; 133102cedc3SLeonid Yegoshin case mm_pool32f_op: 134102cedc3SLeonid Yegoshin switch (insn.mm_fp0_format.func) { 135102cedc3SLeonid Yegoshin case mm_32f_01_op: 136102cedc3SLeonid Yegoshin case mm_32f_11_op: 137102cedc3SLeonid Yegoshin case mm_32f_02_op: 138102cedc3SLeonid Yegoshin case mm_32f_12_op: 139102cedc3SLeonid Yegoshin case mm_32f_41_op: 140102cedc3SLeonid Yegoshin case mm_32f_51_op: 141102cedc3SLeonid Yegoshin case mm_32f_42_op: 142102cedc3SLeonid Yegoshin case mm_32f_52_op: 143102cedc3SLeonid Yegoshin op = insn.mm_fp0_format.func; 144102cedc3SLeonid Yegoshin if (op == mm_32f_01_op) 145102cedc3SLeonid Yegoshin func = madd_s_op; 146102cedc3SLeonid Yegoshin else if (op == mm_32f_11_op) 147102cedc3SLeonid Yegoshin func = madd_d_op; 148102cedc3SLeonid Yegoshin else if (op == mm_32f_02_op) 149102cedc3SLeonid Yegoshin func = nmadd_s_op; 150102cedc3SLeonid Yegoshin else if (op == mm_32f_12_op) 151102cedc3SLeonid Yegoshin func = nmadd_d_op; 152102cedc3SLeonid Yegoshin else if (op == mm_32f_41_op) 153102cedc3SLeonid Yegoshin func = msub_s_op; 154102cedc3SLeonid Yegoshin else if (op == mm_32f_51_op) 155102cedc3SLeonid Yegoshin func = msub_d_op; 156102cedc3SLeonid Yegoshin else if (op == mm_32f_42_op) 157102cedc3SLeonid Yegoshin func = nmsub_s_op; 158102cedc3SLeonid Yegoshin else 159102cedc3SLeonid Yegoshin func = nmsub_d_op; 160102cedc3SLeonid Yegoshin mips32_insn.fp6_format.opcode = cop1x_op; 161102cedc3SLeonid Yegoshin mips32_insn.fp6_format.fr = insn.mm_fp6_format.fr; 162102cedc3SLeonid Yegoshin mips32_insn.fp6_format.ft = insn.mm_fp6_format.ft; 163102cedc3SLeonid Yegoshin mips32_insn.fp6_format.fs = insn.mm_fp6_format.fs; 164102cedc3SLeonid Yegoshin mips32_insn.fp6_format.fd = insn.mm_fp6_format.fd; 165102cedc3SLeonid Yegoshin mips32_insn.fp6_format.func = func; 166102cedc3SLeonid Yegoshin break; 167102cedc3SLeonid Yegoshin case mm_32f_10_op: 168102cedc3SLeonid Yegoshin func = -1; /* Invalid */ 169102cedc3SLeonid Yegoshin op = insn.mm_fp5_format.op & 0x7; 170102cedc3SLeonid Yegoshin if (op == mm_ldxc1_op) 171102cedc3SLeonid Yegoshin func = ldxc1_op; 172102cedc3SLeonid Yegoshin else if (op == mm_sdxc1_op) 173102cedc3SLeonid Yegoshin func = sdxc1_op; 174102cedc3SLeonid Yegoshin else if (op == mm_lwxc1_op) 175102cedc3SLeonid Yegoshin func = lwxc1_op; 176102cedc3SLeonid Yegoshin else if (op == mm_swxc1_op) 177102cedc3SLeonid Yegoshin func = swxc1_op; 178102cedc3SLeonid Yegoshin 179102cedc3SLeonid Yegoshin if (func != -1) { 180102cedc3SLeonid Yegoshin mips32_insn.r_format.opcode = cop1x_op; 181102cedc3SLeonid Yegoshin mips32_insn.r_format.rs = 182102cedc3SLeonid Yegoshin insn.mm_fp5_format.base; 183102cedc3SLeonid Yegoshin mips32_insn.r_format.rt = 184102cedc3SLeonid Yegoshin insn.mm_fp5_format.index; 185102cedc3SLeonid Yegoshin mips32_insn.r_format.rd = 0; 186102cedc3SLeonid Yegoshin mips32_insn.r_format.re = insn.mm_fp5_format.fd; 187102cedc3SLeonid Yegoshin mips32_insn.r_format.func = func; 188102cedc3SLeonid Yegoshin } else 189102cedc3SLeonid Yegoshin return SIGILL; 190102cedc3SLeonid Yegoshin break; 191102cedc3SLeonid Yegoshin case mm_32f_40_op: 192102cedc3SLeonid Yegoshin op = -1; /* Invalid */ 193102cedc3SLeonid Yegoshin if (insn.mm_fp2_format.op == mm_fmovt_op) 194102cedc3SLeonid Yegoshin op = 1; 195102cedc3SLeonid Yegoshin else if (insn.mm_fp2_format.op == mm_fmovf_op) 196102cedc3SLeonid Yegoshin op = 0; 197102cedc3SLeonid Yegoshin if (op != -1) { 198102cedc3SLeonid Yegoshin mips32_insn.fp0_format.opcode = cop1_op; 199102cedc3SLeonid Yegoshin mips32_insn.fp0_format.fmt = 200102cedc3SLeonid Yegoshin sdps_format[insn.mm_fp2_format.fmt]; 201102cedc3SLeonid Yegoshin mips32_insn.fp0_format.ft = 202102cedc3SLeonid Yegoshin (insn.mm_fp2_format.cc<<2) + op; 203102cedc3SLeonid Yegoshin mips32_insn.fp0_format.fs = 204102cedc3SLeonid Yegoshin insn.mm_fp2_format.fs; 205102cedc3SLeonid Yegoshin mips32_insn.fp0_format.fd = 206102cedc3SLeonid Yegoshin insn.mm_fp2_format.fd; 207102cedc3SLeonid Yegoshin mips32_insn.fp0_format.func = fmovc_op; 208102cedc3SLeonid Yegoshin } else 209102cedc3SLeonid Yegoshin return SIGILL; 210102cedc3SLeonid Yegoshin break; 211102cedc3SLeonid Yegoshin case mm_32f_60_op: 212102cedc3SLeonid Yegoshin func = -1; /* Invalid */ 213102cedc3SLeonid Yegoshin if (insn.mm_fp0_format.op == mm_fadd_op) 214102cedc3SLeonid Yegoshin func = fadd_op; 215102cedc3SLeonid Yegoshin else if (insn.mm_fp0_format.op == mm_fsub_op) 216102cedc3SLeonid Yegoshin func = fsub_op; 217102cedc3SLeonid Yegoshin else if (insn.mm_fp0_format.op == mm_fmul_op) 218102cedc3SLeonid Yegoshin func = fmul_op; 219102cedc3SLeonid Yegoshin else if (insn.mm_fp0_format.op == mm_fdiv_op) 220102cedc3SLeonid Yegoshin func = fdiv_op; 221102cedc3SLeonid Yegoshin if (func != -1) { 222102cedc3SLeonid Yegoshin mips32_insn.fp0_format.opcode = cop1_op; 223102cedc3SLeonid Yegoshin mips32_insn.fp0_format.fmt = 224102cedc3SLeonid Yegoshin sdps_format[insn.mm_fp0_format.fmt]; 225102cedc3SLeonid Yegoshin mips32_insn.fp0_format.ft = 226102cedc3SLeonid Yegoshin insn.mm_fp0_format.ft; 227102cedc3SLeonid Yegoshin mips32_insn.fp0_format.fs = 228102cedc3SLeonid Yegoshin insn.mm_fp0_format.fs; 229102cedc3SLeonid Yegoshin mips32_insn.fp0_format.fd = 230102cedc3SLeonid Yegoshin insn.mm_fp0_format.fd; 231102cedc3SLeonid Yegoshin mips32_insn.fp0_format.func = func; 232102cedc3SLeonid Yegoshin } else 233102cedc3SLeonid Yegoshin return SIGILL; 234102cedc3SLeonid Yegoshin break; 235102cedc3SLeonid Yegoshin case mm_32f_70_op: 236102cedc3SLeonid Yegoshin func = -1; /* Invalid */ 237102cedc3SLeonid Yegoshin if (insn.mm_fp0_format.op == mm_fmovn_op) 238102cedc3SLeonid Yegoshin func = fmovn_op; 239102cedc3SLeonid Yegoshin else if (insn.mm_fp0_format.op == mm_fmovz_op) 240102cedc3SLeonid Yegoshin func = fmovz_op; 241102cedc3SLeonid Yegoshin if (func != -1) { 242102cedc3SLeonid Yegoshin mips32_insn.fp0_format.opcode = cop1_op; 243102cedc3SLeonid Yegoshin mips32_insn.fp0_format.fmt = 244102cedc3SLeonid Yegoshin sdps_format[insn.mm_fp0_format.fmt]; 245102cedc3SLeonid Yegoshin mips32_insn.fp0_format.ft = 246102cedc3SLeonid Yegoshin insn.mm_fp0_format.ft; 247102cedc3SLeonid Yegoshin mips32_insn.fp0_format.fs = 248102cedc3SLeonid Yegoshin insn.mm_fp0_format.fs; 249102cedc3SLeonid Yegoshin mips32_insn.fp0_format.fd = 250102cedc3SLeonid Yegoshin insn.mm_fp0_format.fd; 251102cedc3SLeonid Yegoshin mips32_insn.fp0_format.func = func; 252102cedc3SLeonid Yegoshin } else 253102cedc3SLeonid Yegoshin return SIGILL; 254102cedc3SLeonid Yegoshin break; 255102cedc3SLeonid Yegoshin case mm_32f_73_op: /* POOL32FXF */ 256102cedc3SLeonid Yegoshin switch (insn.mm_fp1_format.op) { 257102cedc3SLeonid Yegoshin case mm_movf0_op: 258102cedc3SLeonid Yegoshin case mm_movf1_op: 259102cedc3SLeonid Yegoshin case mm_movt0_op: 260102cedc3SLeonid Yegoshin case mm_movt1_op: 261102cedc3SLeonid Yegoshin if ((insn.mm_fp1_format.op & 0x7f) == 262102cedc3SLeonid Yegoshin mm_movf0_op) 263102cedc3SLeonid Yegoshin op = 0; 264102cedc3SLeonid Yegoshin else 265102cedc3SLeonid Yegoshin op = 1; 266102cedc3SLeonid Yegoshin mips32_insn.r_format.opcode = spec_op; 267102cedc3SLeonid Yegoshin mips32_insn.r_format.rs = insn.mm_fp4_format.fs; 268102cedc3SLeonid Yegoshin mips32_insn.r_format.rt = 269102cedc3SLeonid Yegoshin (insn.mm_fp4_format.cc << 2) + op; 270102cedc3SLeonid Yegoshin mips32_insn.r_format.rd = insn.mm_fp4_format.rt; 271102cedc3SLeonid Yegoshin mips32_insn.r_format.re = 0; 272102cedc3SLeonid Yegoshin mips32_insn.r_format.func = movc_op; 273102cedc3SLeonid Yegoshin break; 274102cedc3SLeonid Yegoshin case mm_fcvtd0_op: 275102cedc3SLeonid Yegoshin case mm_fcvtd1_op: 276102cedc3SLeonid Yegoshin case mm_fcvts0_op: 277102cedc3SLeonid Yegoshin case mm_fcvts1_op: 278102cedc3SLeonid Yegoshin if ((insn.mm_fp1_format.op & 0x7f) == 279102cedc3SLeonid Yegoshin mm_fcvtd0_op) { 280102cedc3SLeonid Yegoshin func = fcvtd_op; 281102cedc3SLeonid Yegoshin fmt = swl_format[insn.mm_fp3_format.fmt]; 282102cedc3SLeonid Yegoshin } else { 283102cedc3SLeonid Yegoshin func = fcvts_op; 284102cedc3SLeonid Yegoshin fmt = dwl_format[insn.mm_fp3_format.fmt]; 285102cedc3SLeonid Yegoshin } 286102cedc3SLeonid Yegoshin mips32_insn.fp0_format.opcode = cop1_op; 287102cedc3SLeonid Yegoshin mips32_insn.fp0_format.fmt = fmt; 288102cedc3SLeonid Yegoshin mips32_insn.fp0_format.ft = 0; 289102cedc3SLeonid Yegoshin mips32_insn.fp0_format.fs = 290102cedc3SLeonid Yegoshin insn.mm_fp3_format.fs; 291102cedc3SLeonid Yegoshin mips32_insn.fp0_format.fd = 292102cedc3SLeonid Yegoshin insn.mm_fp3_format.rt; 293102cedc3SLeonid Yegoshin mips32_insn.fp0_format.func = func; 294102cedc3SLeonid Yegoshin break; 295102cedc3SLeonid Yegoshin case mm_fmov0_op: 296102cedc3SLeonid Yegoshin case mm_fmov1_op: 297102cedc3SLeonid Yegoshin case mm_fabs0_op: 298102cedc3SLeonid Yegoshin case mm_fabs1_op: 299102cedc3SLeonid Yegoshin case mm_fneg0_op: 300102cedc3SLeonid Yegoshin case mm_fneg1_op: 301102cedc3SLeonid Yegoshin if ((insn.mm_fp1_format.op & 0x7f) == 302102cedc3SLeonid Yegoshin mm_fmov0_op) 303102cedc3SLeonid Yegoshin func = fmov_op; 304102cedc3SLeonid Yegoshin else if ((insn.mm_fp1_format.op & 0x7f) == 305102cedc3SLeonid Yegoshin mm_fabs0_op) 306102cedc3SLeonid Yegoshin func = fabs_op; 307102cedc3SLeonid Yegoshin else 308102cedc3SLeonid Yegoshin func = fneg_op; 309102cedc3SLeonid Yegoshin mips32_insn.fp0_format.opcode = cop1_op; 310102cedc3SLeonid Yegoshin mips32_insn.fp0_format.fmt = 311102cedc3SLeonid Yegoshin sdps_format[insn.mm_fp3_format.fmt]; 312102cedc3SLeonid Yegoshin mips32_insn.fp0_format.ft = 0; 313102cedc3SLeonid Yegoshin mips32_insn.fp0_format.fs = 314102cedc3SLeonid Yegoshin insn.mm_fp3_format.fs; 315102cedc3SLeonid Yegoshin mips32_insn.fp0_format.fd = 316102cedc3SLeonid Yegoshin insn.mm_fp3_format.rt; 317102cedc3SLeonid Yegoshin mips32_insn.fp0_format.func = func; 318102cedc3SLeonid Yegoshin break; 319102cedc3SLeonid Yegoshin case mm_ffloorl_op: 320102cedc3SLeonid Yegoshin case mm_ffloorw_op: 321102cedc3SLeonid Yegoshin case mm_fceill_op: 322102cedc3SLeonid Yegoshin case mm_fceilw_op: 323102cedc3SLeonid Yegoshin case mm_ftruncl_op: 324102cedc3SLeonid Yegoshin case mm_ftruncw_op: 325102cedc3SLeonid Yegoshin case mm_froundl_op: 326102cedc3SLeonid Yegoshin case mm_froundw_op: 327102cedc3SLeonid Yegoshin case mm_fcvtl_op: 328102cedc3SLeonid Yegoshin case mm_fcvtw_op: 329102cedc3SLeonid Yegoshin if (insn.mm_fp1_format.op == mm_ffloorl_op) 330102cedc3SLeonid Yegoshin func = ffloorl_op; 331102cedc3SLeonid Yegoshin else if (insn.mm_fp1_format.op == mm_ffloorw_op) 332102cedc3SLeonid Yegoshin func = ffloor_op; 333102cedc3SLeonid Yegoshin else if (insn.mm_fp1_format.op == mm_fceill_op) 334102cedc3SLeonid Yegoshin func = fceill_op; 335102cedc3SLeonid Yegoshin else if (insn.mm_fp1_format.op == mm_fceilw_op) 336102cedc3SLeonid Yegoshin func = fceil_op; 337102cedc3SLeonid Yegoshin else if (insn.mm_fp1_format.op == mm_ftruncl_op) 338102cedc3SLeonid Yegoshin func = ftruncl_op; 339102cedc3SLeonid Yegoshin else if (insn.mm_fp1_format.op == mm_ftruncw_op) 340102cedc3SLeonid Yegoshin func = ftrunc_op; 341102cedc3SLeonid Yegoshin else if (insn.mm_fp1_format.op == mm_froundl_op) 342102cedc3SLeonid Yegoshin func = froundl_op; 343102cedc3SLeonid Yegoshin else if (insn.mm_fp1_format.op == mm_froundw_op) 344102cedc3SLeonid Yegoshin func = fround_op; 345102cedc3SLeonid Yegoshin else if (insn.mm_fp1_format.op == mm_fcvtl_op) 346102cedc3SLeonid Yegoshin func = fcvtl_op; 347102cedc3SLeonid Yegoshin else 348102cedc3SLeonid Yegoshin func = fcvtw_op; 349102cedc3SLeonid Yegoshin mips32_insn.fp0_format.opcode = cop1_op; 350102cedc3SLeonid Yegoshin mips32_insn.fp0_format.fmt = 351102cedc3SLeonid Yegoshin sd_format[insn.mm_fp1_format.fmt]; 352102cedc3SLeonid Yegoshin mips32_insn.fp0_format.ft = 0; 353102cedc3SLeonid Yegoshin mips32_insn.fp0_format.fs = 354102cedc3SLeonid Yegoshin insn.mm_fp1_format.fs; 355102cedc3SLeonid Yegoshin mips32_insn.fp0_format.fd = 356102cedc3SLeonid Yegoshin insn.mm_fp1_format.rt; 357102cedc3SLeonid Yegoshin mips32_insn.fp0_format.func = func; 358102cedc3SLeonid Yegoshin break; 359102cedc3SLeonid Yegoshin case mm_frsqrt_op: 360102cedc3SLeonid Yegoshin case mm_fsqrt_op: 361102cedc3SLeonid Yegoshin case mm_frecip_op: 362102cedc3SLeonid Yegoshin if (insn.mm_fp1_format.op == mm_frsqrt_op) 363102cedc3SLeonid Yegoshin func = frsqrt_op; 364102cedc3SLeonid Yegoshin else if (insn.mm_fp1_format.op == mm_fsqrt_op) 365102cedc3SLeonid Yegoshin func = fsqrt_op; 366102cedc3SLeonid Yegoshin else 367102cedc3SLeonid Yegoshin func = frecip_op; 368102cedc3SLeonid Yegoshin mips32_insn.fp0_format.opcode = cop1_op; 369102cedc3SLeonid Yegoshin mips32_insn.fp0_format.fmt = 370102cedc3SLeonid Yegoshin sdps_format[insn.mm_fp1_format.fmt]; 371102cedc3SLeonid Yegoshin mips32_insn.fp0_format.ft = 0; 372102cedc3SLeonid Yegoshin mips32_insn.fp0_format.fs = 373102cedc3SLeonid Yegoshin insn.mm_fp1_format.fs; 374102cedc3SLeonid Yegoshin mips32_insn.fp0_format.fd = 375102cedc3SLeonid Yegoshin insn.mm_fp1_format.rt; 376102cedc3SLeonid Yegoshin mips32_insn.fp0_format.func = func; 377102cedc3SLeonid Yegoshin break; 378102cedc3SLeonid Yegoshin case mm_mfc1_op: 379102cedc3SLeonid Yegoshin case mm_mtc1_op: 380102cedc3SLeonid Yegoshin case mm_cfc1_op: 381102cedc3SLeonid Yegoshin case mm_ctc1_op: 3829355e59cSSteven J. Hill case mm_mfhc1_op: 3839355e59cSSteven J. Hill case mm_mthc1_op: 384102cedc3SLeonid Yegoshin if (insn.mm_fp1_format.op == mm_mfc1_op) 385102cedc3SLeonid Yegoshin op = mfc_op; 386102cedc3SLeonid Yegoshin else if (insn.mm_fp1_format.op == mm_mtc1_op) 387102cedc3SLeonid Yegoshin op = mtc_op; 388102cedc3SLeonid Yegoshin else if (insn.mm_fp1_format.op == mm_cfc1_op) 389102cedc3SLeonid Yegoshin op = cfc_op; 3909355e59cSSteven J. Hill else if (insn.mm_fp1_format.op == mm_ctc1_op) 391102cedc3SLeonid Yegoshin op = ctc_op; 3929355e59cSSteven J. Hill else if (insn.mm_fp1_format.op == mm_mfhc1_op) 3939355e59cSSteven J. Hill op = mfhc_op; 3949355e59cSSteven J. Hill else 3959355e59cSSteven J. Hill op = mthc_op; 396102cedc3SLeonid Yegoshin mips32_insn.fp1_format.opcode = cop1_op; 397102cedc3SLeonid Yegoshin mips32_insn.fp1_format.op = op; 398102cedc3SLeonid Yegoshin mips32_insn.fp1_format.rt = 399102cedc3SLeonid Yegoshin insn.mm_fp1_format.rt; 400102cedc3SLeonid Yegoshin mips32_insn.fp1_format.fs = 401102cedc3SLeonid Yegoshin insn.mm_fp1_format.fs; 402102cedc3SLeonid Yegoshin mips32_insn.fp1_format.fd = 0; 403102cedc3SLeonid Yegoshin mips32_insn.fp1_format.func = 0; 404102cedc3SLeonid Yegoshin break; 405102cedc3SLeonid Yegoshin default: 406102cedc3SLeonid Yegoshin return SIGILL; 407102cedc3SLeonid Yegoshin } 408102cedc3SLeonid Yegoshin break; 409102cedc3SLeonid Yegoshin case mm_32f_74_op: /* c.cond.fmt */ 410102cedc3SLeonid Yegoshin mips32_insn.fp0_format.opcode = cop1_op; 411102cedc3SLeonid Yegoshin mips32_insn.fp0_format.fmt = 412102cedc3SLeonid Yegoshin sdps_format[insn.mm_fp4_format.fmt]; 413102cedc3SLeonid Yegoshin mips32_insn.fp0_format.ft = insn.mm_fp4_format.rt; 414102cedc3SLeonid Yegoshin mips32_insn.fp0_format.fs = insn.mm_fp4_format.fs; 415102cedc3SLeonid Yegoshin mips32_insn.fp0_format.fd = insn.mm_fp4_format.cc << 2; 416102cedc3SLeonid Yegoshin mips32_insn.fp0_format.func = 417102cedc3SLeonid Yegoshin insn.mm_fp4_format.cond | MM_MIPS32_COND_FC; 418102cedc3SLeonid Yegoshin break; 419102cedc3SLeonid Yegoshin default: 420102cedc3SLeonid Yegoshin return SIGILL; 421102cedc3SLeonid Yegoshin } 422102cedc3SLeonid Yegoshin break; 423102cedc3SLeonid Yegoshin default: 424102cedc3SLeonid Yegoshin return SIGILL; 425102cedc3SLeonid Yegoshin } 426102cedc3SLeonid Yegoshin 427102cedc3SLeonid Yegoshin *insn_ptr = mips32_insn; 428102cedc3SLeonid Yegoshin return 0; 429102cedc3SLeonid Yegoshin } 430102cedc3SLeonid Yegoshin 4311da177e4SLinus Torvalds /* 4321da177e4SLinus Torvalds * Redundant with logic already in kernel/branch.c, 4331da177e4SLinus Torvalds * embedded in compute_return_epc. At some point, 4341da177e4SLinus Torvalds * a single subroutine should be used across both 4351da177e4SLinus Torvalds * modules. 4361da177e4SLinus Torvalds */ 437102cedc3SLeonid Yegoshin static int isBranchInstr(struct pt_regs *regs, struct mm_decoded_insn dec_insn, 438102cedc3SLeonid Yegoshin unsigned long *contpc) 4391da177e4SLinus Torvalds { 440102cedc3SLeonid Yegoshin union mips_instruction insn = (union mips_instruction)dec_insn.insn; 441102cedc3SLeonid Yegoshin unsigned int fcr31; 442102cedc3SLeonid Yegoshin unsigned int bit = 0; 443102cedc3SLeonid Yegoshin 444102cedc3SLeonid Yegoshin switch (insn.i_format.opcode) { 4451da177e4SLinus Torvalds case spec_op: 446102cedc3SLeonid Yegoshin switch (insn.r_format.func) { 4471da177e4SLinus Torvalds case jalr_op: 448102cedc3SLeonid Yegoshin regs->regs[insn.r_format.rd] = 449102cedc3SLeonid Yegoshin regs->cp0_epc + dec_insn.pc_inc + 450102cedc3SLeonid Yegoshin dec_insn.next_pc_inc; 451102cedc3SLeonid Yegoshin /* Fall through */ 4521da177e4SLinus Torvalds case jr_op: 4535f9f41c4SMarkos Chandras /* For R6, JR already emulated in jalr_op */ 4545f9f41c4SMarkos Chandras if (NO_R6EMU && insn.r_format.opcode == jr_op) 4555f9f41c4SMarkos Chandras break; 456102cedc3SLeonid Yegoshin *contpc = regs->regs[insn.r_format.rs]; 4571da177e4SLinus Torvalds return 1; 4581da177e4SLinus Torvalds } 4591da177e4SLinus Torvalds break; 4601da177e4SLinus Torvalds case bcond_op: 461102cedc3SLeonid Yegoshin switch (insn.i_format.rt) { 4621da177e4SLinus Torvalds case bltzal_op: 4631da177e4SLinus Torvalds case bltzall_op: 464319824eaSMarkos Chandras if (NO_R6EMU && (insn.i_format.rs || 465319824eaSMarkos Chandras insn.i_format.rt == bltzall_op)) 466319824eaSMarkos Chandras break; 467319824eaSMarkos Chandras 468102cedc3SLeonid Yegoshin regs->regs[31] = regs->cp0_epc + 469102cedc3SLeonid Yegoshin dec_insn.pc_inc + 470102cedc3SLeonid Yegoshin dec_insn.next_pc_inc; 471102cedc3SLeonid Yegoshin /* Fall through */ 472102cedc3SLeonid Yegoshin case bltzl_op: 473319824eaSMarkos Chandras if (NO_R6EMU) 474319824eaSMarkos Chandras break; 475319824eaSMarkos Chandras case bltz_op: 476102cedc3SLeonid Yegoshin if ((long)regs->regs[insn.i_format.rs] < 0) 477102cedc3SLeonid Yegoshin *contpc = regs->cp0_epc + 478102cedc3SLeonid Yegoshin dec_insn.pc_inc + 479102cedc3SLeonid Yegoshin (insn.i_format.simmediate << 2); 480102cedc3SLeonid Yegoshin else 481102cedc3SLeonid Yegoshin *contpc = regs->cp0_epc + 482102cedc3SLeonid Yegoshin dec_insn.pc_inc + 483102cedc3SLeonid Yegoshin dec_insn.next_pc_inc; 4841da177e4SLinus Torvalds return 1; 485102cedc3SLeonid Yegoshin case bgezal_op: 486102cedc3SLeonid Yegoshin case bgezall_op: 487319824eaSMarkos Chandras if (NO_R6EMU && (insn.i_format.rs || 488319824eaSMarkos Chandras insn.i_format.rt == bgezall_op)) 489319824eaSMarkos Chandras break; 490319824eaSMarkos Chandras 491102cedc3SLeonid Yegoshin regs->regs[31] = regs->cp0_epc + 492102cedc3SLeonid Yegoshin dec_insn.pc_inc + 493102cedc3SLeonid Yegoshin dec_insn.next_pc_inc; 494102cedc3SLeonid Yegoshin /* Fall through */ 495102cedc3SLeonid Yegoshin case bgezl_op: 496319824eaSMarkos Chandras if (NO_R6EMU) 497319824eaSMarkos Chandras break; 498319824eaSMarkos Chandras case bgez_op: 499102cedc3SLeonid Yegoshin if ((long)regs->regs[insn.i_format.rs] >= 0) 500102cedc3SLeonid Yegoshin *contpc = regs->cp0_epc + 501102cedc3SLeonid Yegoshin dec_insn.pc_inc + 502102cedc3SLeonid Yegoshin (insn.i_format.simmediate << 2); 503102cedc3SLeonid Yegoshin else 504102cedc3SLeonid Yegoshin *contpc = regs->cp0_epc + 505102cedc3SLeonid Yegoshin dec_insn.pc_inc + 506102cedc3SLeonid Yegoshin dec_insn.next_pc_inc; 507102cedc3SLeonid Yegoshin return 1; 5081da177e4SLinus Torvalds } 5091da177e4SLinus Torvalds break; 5101da177e4SLinus Torvalds case jalx_op: 511102cedc3SLeonid Yegoshin set_isa16_mode(bit); 512102cedc3SLeonid Yegoshin case jal_op: 513102cedc3SLeonid Yegoshin regs->regs[31] = regs->cp0_epc + 514102cedc3SLeonid Yegoshin dec_insn.pc_inc + 515102cedc3SLeonid Yegoshin dec_insn.next_pc_inc; 516102cedc3SLeonid Yegoshin /* Fall through */ 517102cedc3SLeonid Yegoshin case j_op: 518102cedc3SLeonid Yegoshin *contpc = regs->cp0_epc + dec_insn.pc_inc; 519102cedc3SLeonid Yegoshin *contpc >>= 28; 520102cedc3SLeonid Yegoshin *contpc <<= 28; 521102cedc3SLeonid Yegoshin *contpc |= (insn.j_format.target << 2); 522102cedc3SLeonid Yegoshin /* Set microMIPS mode bit: XOR for jalx. */ 523102cedc3SLeonid Yegoshin *contpc ^= bit; 5241da177e4SLinus Torvalds return 1; 525102cedc3SLeonid Yegoshin case beql_op: 526319824eaSMarkos Chandras if (NO_R6EMU) 527319824eaSMarkos Chandras break; 528319824eaSMarkos Chandras case beq_op: 529102cedc3SLeonid Yegoshin if (regs->regs[insn.i_format.rs] == 530102cedc3SLeonid Yegoshin regs->regs[insn.i_format.rt]) 531102cedc3SLeonid Yegoshin *contpc = regs->cp0_epc + 532102cedc3SLeonid Yegoshin dec_insn.pc_inc + 533102cedc3SLeonid Yegoshin (insn.i_format.simmediate << 2); 534102cedc3SLeonid Yegoshin else 535102cedc3SLeonid Yegoshin *contpc = regs->cp0_epc + 536102cedc3SLeonid Yegoshin dec_insn.pc_inc + 537102cedc3SLeonid Yegoshin dec_insn.next_pc_inc; 538102cedc3SLeonid Yegoshin return 1; 539102cedc3SLeonid Yegoshin case bnel_op: 540319824eaSMarkos Chandras if (NO_R6EMU) 541319824eaSMarkos Chandras break; 542319824eaSMarkos Chandras case bne_op: 543102cedc3SLeonid Yegoshin if (regs->regs[insn.i_format.rs] != 544102cedc3SLeonid Yegoshin regs->regs[insn.i_format.rt]) 545102cedc3SLeonid Yegoshin *contpc = regs->cp0_epc + 546102cedc3SLeonid Yegoshin dec_insn.pc_inc + 547102cedc3SLeonid Yegoshin (insn.i_format.simmediate << 2); 548102cedc3SLeonid Yegoshin else 549102cedc3SLeonid Yegoshin *contpc = regs->cp0_epc + 550102cedc3SLeonid Yegoshin dec_insn.pc_inc + 551102cedc3SLeonid Yegoshin dec_insn.next_pc_inc; 552102cedc3SLeonid Yegoshin return 1; 553102cedc3SLeonid Yegoshin case blezl_op: 554319824eaSMarkos Chandras if (NO_R6EMU) 555319824eaSMarkos Chandras break; 556319824eaSMarkos Chandras case blez_op: 557a8ff66f5SMarkos Chandras 558a8ff66f5SMarkos Chandras /* 559a8ff66f5SMarkos Chandras * Compact branches for R6 for the 560a8ff66f5SMarkos Chandras * blez and blezl opcodes. 561a8ff66f5SMarkos Chandras * BLEZ | rs = 0 | rt != 0 == BLEZALC 562a8ff66f5SMarkos Chandras * BLEZ | rs = rt != 0 == BGEZALC 563a8ff66f5SMarkos Chandras * BLEZ | rs != 0 | rt != 0 == BGEUC 564a8ff66f5SMarkos Chandras * BLEZL | rs = 0 | rt != 0 == BLEZC 565a8ff66f5SMarkos Chandras * BLEZL | rs = rt != 0 == BGEZC 566a8ff66f5SMarkos Chandras * BLEZL | rs != 0 | rt != 0 == BGEC 567a8ff66f5SMarkos Chandras * 568a8ff66f5SMarkos Chandras * For real BLEZ{,L}, rt is always 0. 569a8ff66f5SMarkos Chandras */ 570a8ff66f5SMarkos Chandras if (cpu_has_mips_r6 && insn.i_format.rt) { 571a8ff66f5SMarkos Chandras if ((insn.i_format.opcode == blez_op) && 572a8ff66f5SMarkos Chandras ((!insn.i_format.rs && insn.i_format.rt) || 573a8ff66f5SMarkos Chandras (insn.i_format.rs == insn.i_format.rt))) 574a8ff66f5SMarkos Chandras regs->regs[31] = regs->cp0_epc + 575a8ff66f5SMarkos Chandras dec_insn.pc_inc; 576a8ff66f5SMarkos Chandras *contpc = regs->cp0_epc + dec_insn.pc_inc + 577a8ff66f5SMarkos Chandras dec_insn.next_pc_inc; 578a8ff66f5SMarkos Chandras 579a8ff66f5SMarkos Chandras return 1; 580a8ff66f5SMarkos Chandras } 581102cedc3SLeonid Yegoshin if ((long)regs->regs[insn.i_format.rs] <= 0) 582102cedc3SLeonid Yegoshin *contpc = regs->cp0_epc + 583102cedc3SLeonid Yegoshin dec_insn.pc_inc + 584102cedc3SLeonid Yegoshin (insn.i_format.simmediate << 2); 585102cedc3SLeonid Yegoshin else 586102cedc3SLeonid Yegoshin *contpc = regs->cp0_epc + 587102cedc3SLeonid Yegoshin dec_insn.pc_inc + 588102cedc3SLeonid Yegoshin dec_insn.next_pc_inc; 589102cedc3SLeonid Yegoshin return 1; 590102cedc3SLeonid Yegoshin case bgtzl_op: 591319824eaSMarkos Chandras if (NO_R6EMU) 592319824eaSMarkos Chandras break; 593319824eaSMarkos Chandras case bgtz_op: 594f1b44067SMarkos Chandras /* 595f1b44067SMarkos Chandras * Compact branches for R6 for the 596f1b44067SMarkos Chandras * bgtz and bgtzl opcodes. 597f1b44067SMarkos Chandras * BGTZ | rs = 0 | rt != 0 == BGTZALC 598f1b44067SMarkos Chandras * BGTZ | rs = rt != 0 == BLTZALC 599f1b44067SMarkos Chandras * BGTZ | rs != 0 | rt != 0 == BLTUC 600f1b44067SMarkos Chandras * BGTZL | rs = 0 | rt != 0 == BGTZC 601f1b44067SMarkos Chandras * BGTZL | rs = rt != 0 == BLTZC 602f1b44067SMarkos Chandras * BGTZL | rs != 0 | rt != 0 == BLTC 603f1b44067SMarkos Chandras * 604f1b44067SMarkos Chandras * *ZALC varint for BGTZ &&& rt != 0 605f1b44067SMarkos Chandras * For real GTZ{,L}, rt is always 0. 606f1b44067SMarkos Chandras */ 607f1b44067SMarkos Chandras if (cpu_has_mips_r6 && insn.i_format.rt) { 608f1b44067SMarkos Chandras if ((insn.i_format.opcode == blez_op) && 609f1b44067SMarkos Chandras ((!insn.i_format.rs && insn.i_format.rt) || 610f1b44067SMarkos Chandras (insn.i_format.rs == insn.i_format.rt))) 611f1b44067SMarkos Chandras regs->regs[31] = regs->cp0_epc + 612f1b44067SMarkos Chandras dec_insn.pc_inc; 613f1b44067SMarkos Chandras *contpc = regs->cp0_epc + dec_insn.pc_inc + 614f1b44067SMarkos Chandras dec_insn.next_pc_inc; 615f1b44067SMarkos Chandras 616f1b44067SMarkos Chandras return 1; 617f1b44067SMarkos Chandras } 618f1b44067SMarkos Chandras 619102cedc3SLeonid Yegoshin if ((long)regs->regs[insn.i_format.rs] > 0) 620102cedc3SLeonid Yegoshin *contpc = regs->cp0_epc + 621102cedc3SLeonid Yegoshin dec_insn.pc_inc + 622102cedc3SLeonid Yegoshin (insn.i_format.simmediate << 2); 623102cedc3SLeonid Yegoshin else 624102cedc3SLeonid Yegoshin *contpc = regs->cp0_epc + 625102cedc3SLeonid Yegoshin dec_insn.pc_inc + 626102cedc3SLeonid Yegoshin dec_insn.next_pc_inc; 627102cedc3SLeonid Yegoshin return 1; 628c893ce38SMarkos Chandras case cbcond0_op: 62910d962d5SMarkos Chandras case cbcond1_op: 630c893ce38SMarkos Chandras if (!cpu_has_mips_r6) 631c893ce38SMarkos Chandras break; 632c893ce38SMarkos Chandras if (insn.i_format.rt && !insn.i_format.rs) 633c893ce38SMarkos Chandras regs->regs[31] = regs->cp0_epc + 4; 634c893ce38SMarkos Chandras *contpc = regs->cp0_epc + dec_insn.pc_inc + 635c893ce38SMarkos Chandras dec_insn.next_pc_inc; 636c893ce38SMarkos Chandras 637c893ce38SMarkos Chandras return 1; 638c26d4219SDavid Daney #ifdef CONFIG_CPU_CAVIUM_OCTEON 639c26d4219SDavid Daney case lwc2_op: /* This is bbit0 on Octeon */ 640c26d4219SDavid Daney if ((regs->regs[insn.i_format.rs] & (1ull<<insn.i_format.rt)) == 0) 641c26d4219SDavid Daney *contpc = regs->cp0_epc + 4 + (insn.i_format.simmediate << 2); 642c26d4219SDavid Daney else 643c26d4219SDavid Daney *contpc = regs->cp0_epc + 8; 644c26d4219SDavid Daney return 1; 645c26d4219SDavid Daney case ldc2_op: /* This is bbit032 on Octeon */ 646c26d4219SDavid Daney if ((regs->regs[insn.i_format.rs] & (1ull<<(insn.i_format.rt + 32))) == 0) 647c26d4219SDavid Daney *contpc = regs->cp0_epc + 4 + (insn.i_format.simmediate << 2); 648c26d4219SDavid Daney else 649c26d4219SDavid Daney *contpc = regs->cp0_epc + 8; 650c26d4219SDavid Daney return 1; 651c26d4219SDavid Daney case swc2_op: /* This is bbit1 on Octeon */ 652c26d4219SDavid Daney if (regs->regs[insn.i_format.rs] & (1ull<<insn.i_format.rt)) 653c26d4219SDavid Daney *contpc = regs->cp0_epc + 4 + (insn.i_format.simmediate << 2); 654c26d4219SDavid Daney else 655c26d4219SDavid Daney *contpc = regs->cp0_epc + 8; 656c26d4219SDavid Daney return 1; 657c26d4219SDavid Daney case sdc2_op: /* This is bbit132 on Octeon */ 658c26d4219SDavid Daney if (regs->regs[insn.i_format.rs] & (1ull<<(insn.i_format.rt + 32))) 659c26d4219SDavid Daney *contpc = regs->cp0_epc + 4 + (insn.i_format.simmediate << 2); 660c26d4219SDavid Daney else 661c26d4219SDavid Daney *contpc = regs->cp0_epc + 8; 662c26d4219SDavid Daney return 1; 6638467ca01SMarkos Chandras #else 6648467ca01SMarkos Chandras case bc6_op: 6658467ca01SMarkos Chandras /* 6668467ca01SMarkos Chandras * Only valid for MIPS R6 but we can still end up 6678467ca01SMarkos Chandras * here from a broken userland so just tell emulator 6688467ca01SMarkos Chandras * this is not a branch and let it break later on. 6698467ca01SMarkos Chandras */ 6708467ca01SMarkos Chandras if (!cpu_has_mips_r6) 6718467ca01SMarkos Chandras break; 6728467ca01SMarkos Chandras *contpc = regs->cp0_epc + dec_insn.pc_inc + 6738467ca01SMarkos Chandras dec_insn.next_pc_inc; 6748467ca01SMarkos Chandras 6758467ca01SMarkos Chandras return 1; 67684fef630SMarkos Chandras case balc6_op: 67784fef630SMarkos Chandras if (!cpu_has_mips_r6) 67884fef630SMarkos Chandras break; 67984fef630SMarkos Chandras regs->regs[31] = regs->cp0_epc + 4; 68084fef630SMarkos Chandras *contpc = regs->cp0_epc + dec_insn.pc_inc + 68184fef630SMarkos Chandras dec_insn.next_pc_inc; 68284fef630SMarkos Chandras 68384fef630SMarkos Chandras return 1; 68469b9a2fdSMarkos Chandras case beqzcjic_op: 68569b9a2fdSMarkos Chandras if (!cpu_has_mips_r6) 68669b9a2fdSMarkos Chandras break; 68769b9a2fdSMarkos Chandras *contpc = regs->cp0_epc + dec_insn.pc_inc + 68869b9a2fdSMarkos Chandras dec_insn.next_pc_inc; 68969b9a2fdSMarkos Chandras 69069b9a2fdSMarkos Chandras return 1; 69128d6f93dSMarkos Chandras case bnezcjialc_op: 69228d6f93dSMarkos Chandras if (!cpu_has_mips_r6) 69328d6f93dSMarkos Chandras break; 69428d6f93dSMarkos Chandras if (!insn.i_format.rs) 69528d6f93dSMarkos Chandras regs->regs[31] = regs->cp0_epc + 4; 69628d6f93dSMarkos Chandras *contpc = regs->cp0_epc + dec_insn.pc_inc + 69728d6f93dSMarkos Chandras dec_insn.next_pc_inc; 69828d6f93dSMarkos Chandras 69928d6f93dSMarkos Chandras return 1; 700c26d4219SDavid Daney #endif 7011da177e4SLinus Torvalds case cop0_op: 7021da177e4SLinus Torvalds case cop1_op: 703c8a34581SMarkos Chandras /* Need to check for R6 bc1nez and bc1eqz branches */ 704c8a34581SMarkos Chandras if (cpu_has_mips_r6 && 705c8a34581SMarkos Chandras ((insn.i_format.rs == bc1eqz_op) || 706c8a34581SMarkos Chandras (insn.i_format.rs == bc1nez_op))) { 707c8a34581SMarkos Chandras bit = 0; 708c8a34581SMarkos Chandras switch (insn.i_format.rs) { 709c8a34581SMarkos Chandras case bc1eqz_op: 710c8a34581SMarkos Chandras if (get_fpr32(¤t->thread.fpu.fpr[insn.i_format.rt], 0) & 0x1) 711c8a34581SMarkos Chandras bit = 1; 712c8a34581SMarkos Chandras break; 713c8a34581SMarkos Chandras case bc1nez_op: 714c8a34581SMarkos Chandras if (!(get_fpr32(¤t->thread.fpu.fpr[insn.i_format.rt], 0) & 0x1)) 715c8a34581SMarkos Chandras bit = 1; 716c8a34581SMarkos Chandras break; 717c8a34581SMarkos Chandras } 718c8a34581SMarkos Chandras if (bit) 719c8a34581SMarkos Chandras *contpc = regs->cp0_epc + 720c8a34581SMarkos Chandras dec_insn.pc_inc + 721c8a34581SMarkos Chandras (insn.i_format.simmediate << 2); 722c8a34581SMarkos Chandras else 723c8a34581SMarkos Chandras *contpc = regs->cp0_epc + 724c8a34581SMarkos Chandras dec_insn.pc_inc + 725c8a34581SMarkos Chandras dec_insn.next_pc_inc; 726c8a34581SMarkos Chandras 727c8a34581SMarkos Chandras return 1; 728c8a34581SMarkos Chandras } 729c8a34581SMarkos Chandras /* R2/R6 compatible cop1 instruction. Fall through */ 7301da177e4SLinus Torvalds case cop2_op: 7311da177e4SLinus Torvalds case cop1x_op: 732102cedc3SLeonid Yegoshin if (insn.i_format.rs == bc_op) { 733102cedc3SLeonid Yegoshin preempt_disable(); 734102cedc3SLeonid Yegoshin if (is_fpu_owner()) 735842dfc11SManuel Lauss fcr31 = read_32bit_cp1_register(CP1_STATUS); 736102cedc3SLeonid Yegoshin else 737102cedc3SLeonid Yegoshin fcr31 = current->thread.fpu.fcr31; 738102cedc3SLeonid Yegoshin preempt_enable(); 739102cedc3SLeonid Yegoshin 740102cedc3SLeonid Yegoshin bit = (insn.i_format.rt >> 2); 741102cedc3SLeonid Yegoshin bit += (bit != 0); 742102cedc3SLeonid Yegoshin bit += 23; 743102cedc3SLeonid Yegoshin switch (insn.i_format.rt & 3) { 744102cedc3SLeonid Yegoshin case 0: /* bc1f */ 745102cedc3SLeonid Yegoshin case 2: /* bc1fl */ 746102cedc3SLeonid Yegoshin if (~fcr31 & (1 << bit)) 747102cedc3SLeonid Yegoshin *contpc = regs->cp0_epc + 748102cedc3SLeonid Yegoshin dec_insn.pc_inc + 749102cedc3SLeonid Yegoshin (insn.i_format.simmediate << 2); 750102cedc3SLeonid Yegoshin else 751102cedc3SLeonid Yegoshin *contpc = regs->cp0_epc + 752102cedc3SLeonid Yegoshin dec_insn.pc_inc + 753102cedc3SLeonid Yegoshin dec_insn.next_pc_inc; 754102cedc3SLeonid Yegoshin return 1; 755102cedc3SLeonid Yegoshin case 1: /* bc1t */ 756102cedc3SLeonid Yegoshin case 3: /* bc1tl */ 757102cedc3SLeonid Yegoshin if (fcr31 & (1 << bit)) 758102cedc3SLeonid Yegoshin *contpc = regs->cp0_epc + 759102cedc3SLeonid Yegoshin dec_insn.pc_inc + 760102cedc3SLeonid Yegoshin (insn.i_format.simmediate << 2); 761102cedc3SLeonid Yegoshin else 762102cedc3SLeonid Yegoshin *contpc = regs->cp0_epc + 763102cedc3SLeonid Yegoshin dec_insn.pc_inc + 764102cedc3SLeonid Yegoshin dec_insn.next_pc_inc; 7651da177e4SLinus Torvalds return 1; 7661da177e4SLinus Torvalds } 767102cedc3SLeonid Yegoshin } 768102cedc3SLeonid Yegoshin break; 769102cedc3SLeonid Yegoshin } 7701da177e4SLinus Torvalds return 0; 7711da177e4SLinus Torvalds } 7721da177e4SLinus Torvalds 7731da177e4SLinus Torvalds /* 7741da177e4SLinus Torvalds * In the Linux kernel, we support selection of FPR format on the 775da0bac33SDavid Daney * basis of the Status.FR bit. If an FPU is not present, the FR bit 776da0bac33SDavid Daney * is hardwired to zero, which would imply a 32-bit FPU even for 777597ce172SPaul Burton * 64-bit CPUs so we rather look at TIF_32BIT_FPREGS. 77851d943f0SRalf Baechle * FPU emu is slow and bulky and optimizing this function offers fairly 77951d943f0SRalf Baechle * sizeable benefits so we try to be clever and make this function return 78051d943f0SRalf Baechle * a constant whenever possible, that is on 64-bit kernels without O32 781597ce172SPaul Burton * compatibility enabled and on 32-bit without 64-bit FPU support. 7821da177e4SLinus Torvalds */ 783da0bac33SDavid Daney static inline int cop1_64bit(struct pt_regs *xcp) 784da0bac33SDavid Daney { 78508a07904SRalf Baechle if (config_enabled(CONFIG_64BIT) && !config_enabled(CONFIG_MIPS32_O32)) 78651d943f0SRalf Baechle return 1; 78708a07904SRalf Baechle else if (config_enabled(CONFIG_32BIT) && 78808a07904SRalf Baechle !config_enabled(CONFIG_MIPS_O32_FP64_SUPPORT)) 789da0bac33SDavid Daney return 0; 79008a07904SRalf Baechle 791597ce172SPaul Burton return !test_thread_flag(TIF_32BIT_FPREGS); 792da0bac33SDavid Daney } 7931da177e4SLinus Torvalds 7944227a2d4SPaul Burton static inline bool hybrid_fprs(void) 7954227a2d4SPaul Burton { 7964227a2d4SPaul Burton return test_thread_flag(TIF_HYBRID_FPREGS); 7974227a2d4SPaul Burton } 7984227a2d4SPaul Burton 79947fa0c02SRalf Baechle #define SIFROMREG(si, x) \ 80047fa0c02SRalf Baechle do { \ 8014227a2d4SPaul Burton if (cop1_64bit(xcp) && !hybrid_fprs()) \ 802c8c0da6bSPaul Burton (si) = (int)get_fpr32(&ctx->fpr[x], 0); \ 803bbd426f5SPaul Burton else \ 804c8c0da6bSPaul Burton (si) = (int)get_fpr32(&ctx->fpr[(x) & ~1], (x) & 1); \ 805bbd426f5SPaul Burton } while (0) 806da0bac33SDavid Daney 80747fa0c02SRalf Baechle #define SITOREG(si, x) \ 80847fa0c02SRalf Baechle do { \ 8094227a2d4SPaul Burton if (cop1_64bit(xcp) && !hybrid_fprs()) { \ 810ef1c47afSPaul Burton unsigned i; \ 811bbd426f5SPaul Burton set_fpr32(&ctx->fpr[x], 0, si); \ 812ef1c47afSPaul Burton for (i = 1; i < ARRAY_SIZE(ctx->fpr[x].val32); i++) \ 813ef1c47afSPaul Burton set_fpr32(&ctx->fpr[x], i, 0); \ 814ef1c47afSPaul Burton } else { \ 815bbd426f5SPaul Burton set_fpr32(&ctx->fpr[(x) & ~1], (x) & 1, si); \ 816ef1c47afSPaul Burton } \ 817bbd426f5SPaul Burton } while (0) 8181da177e4SLinus Torvalds 819c8c0da6bSPaul Burton #define SIFROMHREG(si, x) ((si) = (int)get_fpr32(&ctx->fpr[x], 1)) 820ef1c47afSPaul Burton 82147fa0c02SRalf Baechle #define SITOHREG(si, x) \ 82247fa0c02SRalf Baechle do { \ 823ef1c47afSPaul Burton unsigned i; \ 824ef1c47afSPaul Burton set_fpr32(&ctx->fpr[x], 1, si); \ 825ef1c47afSPaul Burton for (i = 2; i < ARRAY_SIZE(ctx->fpr[x].val32); i++) \ 826ef1c47afSPaul Burton set_fpr32(&ctx->fpr[x], i, 0); \ 827ef1c47afSPaul Burton } while (0) 8281ac94400SLeonid Yegoshin 829bbd426f5SPaul Burton #define DIFROMREG(di, x) \ 830bbd426f5SPaul Burton ((di) = get_fpr64(&ctx->fpr[(x) & ~(cop1_64bit(xcp) == 0)], 0)) 831bbd426f5SPaul Burton 83247fa0c02SRalf Baechle #define DITOREG(di, x) \ 83347fa0c02SRalf Baechle do { \ 834ef1c47afSPaul Burton unsigned fpr, i; \ 835ef1c47afSPaul Burton fpr = (x) & ~(cop1_64bit(xcp) == 0); \ 836ef1c47afSPaul Burton set_fpr64(&ctx->fpr[fpr], 0, di); \ 837ef1c47afSPaul Burton for (i = 1; i < ARRAY_SIZE(ctx->fpr[x].val64); i++) \ 838ef1c47afSPaul Burton set_fpr64(&ctx->fpr[fpr], i, 0); \ 839ef1c47afSPaul Burton } while (0) 8401da177e4SLinus Torvalds 8411da177e4SLinus Torvalds #define SPFROMREG(sp, x) SIFROMREG((sp).bits, x) 8421da177e4SLinus Torvalds #define SPTOREG(sp, x) SITOREG((sp).bits, x) 8431da177e4SLinus Torvalds #define DPFROMREG(dp, x) DIFROMREG((dp).bits, x) 8441da177e4SLinus Torvalds #define DPTOREG(dp, x) DITOREG((dp).bits, x) 8451da177e4SLinus Torvalds 8461da177e4SLinus Torvalds /* 847d4f5b088SMaciej W. Rozycki * Emulate a CFC1 instruction. 848d4f5b088SMaciej W. Rozycki */ 849d4f5b088SMaciej W. Rozycki static inline void cop1_cfc(struct pt_regs *xcp, struct mips_fpu_struct *ctx, 850d4f5b088SMaciej W. Rozycki mips_instruction ir) 851d4f5b088SMaciej W. Rozycki { 852*c491cfa2SMaciej W. Rozycki u32 fcr31 = ctx->fcr31; 853*c491cfa2SMaciej W. Rozycki u32 value = 0; 854d4f5b088SMaciej W. Rozycki 855*c491cfa2SMaciej W. Rozycki switch (MIPSInst_RD(ir)) { 856*c491cfa2SMaciej W. Rozycki case FPCREG_CSR: 857*c491cfa2SMaciej W. Rozycki value = fcr31; 858d4f5b088SMaciej W. Rozycki pr_debug("%p gpr[%d]<-csr=%08x\n", 859*c491cfa2SMaciej W. Rozycki (void *)xcp->cp0_epc, MIPSInst_RT(ir), value); 860*c491cfa2SMaciej W. Rozycki break; 861*c491cfa2SMaciej W. Rozycki 862*c491cfa2SMaciej W. Rozycki case FPCREG_FENR: 863*c491cfa2SMaciej W. Rozycki if (!cpu_has_mips_r) 864*c491cfa2SMaciej W. Rozycki break; 865*c491cfa2SMaciej W. Rozycki value = (fcr31 >> (FPU_CSR_FS_S - MIPS_FENR_FS_S)) & 866*c491cfa2SMaciej W. Rozycki MIPS_FENR_FS; 867*c491cfa2SMaciej W. Rozycki value |= fcr31 & (FPU_CSR_ALL_E | FPU_CSR_RM); 868*c491cfa2SMaciej W. Rozycki pr_debug("%p gpr[%d]<-enr=%08x\n", 869*c491cfa2SMaciej W. Rozycki (void *)xcp->cp0_epc, MIPSInst_RT(ir), value); 870*c491cfa2SMaciej W. Rozycki break; 871*c491cfa2SMaciej W. Rozycki 872*c491cfa2SMaciej W. Rozycki case FPCREG_FEXR: 873*c491cfa2SMaciej W. Rozycki if (!cpu_has_mips_r) 874*c491cfa2SMaciej W. Rozycki break; 875*c491cfa2SMaciej W. Rozycki value = fcr31 & (FPU_CSR_ALL_X | FPU_CSR_ALL_S); 876*c491cfa2SMaciej W. Rozycki pr_debug("%p gpr[%d]<-exr=%08x\n", 877*c491cfa2SMaciej W. Rozycki (void *)xcp->cp0_epc, MIPSInst_RT(ir), value); 878*c491cfa2SMaciej W. Rozycki break; 879*c491cfa2SMaciej W. Rozycki 880*c491cfa2SMaciej W. Rozycki case FPCREG_FCCR: 881*c491cfa2SMaciej W. Rozycki if (!cpu_has_mips_r) 882*c491cfa2SMaciej W. Rozycki break; 883*c491cfa2SMaciej W. Rozycki value = (fcr31 >> (FPU_CSR_COND_S - MIPS_FCCR_COND0_S)) & 884*c491cfa2SMaciej W. Rozycki MIPS_FCCR_COND0; 885*c491cfa2SMaciej W. Rozycki value |= (fcr31 >> (FPU_CSR_COND1_S - MIPS_FCCR_COND1_S)) & 886*c491cfa2SMaciej W. Rozycki (MIPS_FCCR_CONDX & ~MIPS_FCCR_COND0); 887*c491cfa2SMaciej W. Rozycki pr_debug("%p gpr[%d]<-ccr=%08x\n", 888*c491cfa2SMaciej W. Rozycki (void *)xcp->cp0_epc, MIPSInst_RT(ir), value); 889*c491cfa2SMaciej W. Rozycki break; 890*c491cfa2SMaciej W. Rozycki 891*c491cfa2SMaciej W. Rozycki case FPCREG_RID: 892f6843626SMaciej W. Rozycki value = current_cpu_data.fpu_id; 893*c491cfa2SMaciej W. Rozycki break; 894*c491cfa2SMaciej W. Rozycki 895*c491cfa2SMaciej W. Rozycki default: 896*c491cfa2SMaciej W. Rozycki break; 897*c491cfa2SMaciej W. Rozycki } 898*c491cfa2SMaciej W. Rozycki 899d4f5b088SMaciej W. Rozycki if (MIPSInst_RT(ir)) 900d4f5b088SMaciej W. Rozycki xcp->regs[MIPSInst_RT(ir)] = value; 901d4f5b088SMaciej W. Rozycki } 902d4f5b088SMaciej W. Rozycki 903d4f5b088SMaciej W. Rozycki /* 904d4f5b088SMaciej W. Rozycki * Emulate a CTC1 instruction. 905d4f5b088SMaciej W. Rozycki */ 906d4f5b088SMaciej W. Rozycki static inline void cop1_ctc(struct pt_regs *xcp, struct mips_fpu_struct *ctx, 907d4f5b088SMaciej W. Rozycki mips_instruction ir) 908d4f5b088SMaciej W. Rozycki { 909*c491cfa2SMaciej W. Rozycki u32 fcr31 = ctx->fcr31; 910d4f5b088SMaciej W. Rozycki u32 value; 911d4f5b088SMaciej W. Rozycki 912d4f5b088SMaciej W. Rozycki if (MIPSInst_RT(ir) == 0) 913d4f5b088SMaciej W. Rozycki value = 0; 914d4f5b088SMaciej W. Rozycki else 915d4f5b088SMaciej W. Rozycki value = xcp->regs[MIPSInst_RT(ir)]; 916d4f5b088SMaciej W. Rozycki 917*c491cfa2SMaciej W. Rozycki switch (MIPSInst_RD(ir)) { 918*c491cfa2SMaciej W. Rozycki case FPCREG_CSR: 919d4f5b088SMaciej W. Rozycki pr_debug("%p gpr[%d]->csr=%08x\n", 920*c491cfa2SMaciej W. Rozycki (void *)xcp->cp0_epc, MIPSInst_RT(ir), value); 921d4f5b088SMaciej W. Rozycki 922d4f5b088SMaciej W. Rozycki /* Don't write reserved bits. */ 923*c491cfa2SMaciej W. Rozycki fcr31 = value & ~FPU_CSR_RSVD; 924*c491cfa2SMaciej W. Rozycki break; 925*c491cfa2SMaciej W. Rozycki 926*c491cfa2SMaciej W. Rozycki case FPCREG_FENR: 927*c491cfa2SMaciej W. Rozycki if (!cpu_has_mips_r) 928*c491cfa2SMaciej W. Rozycki break; 929*c491cfa2SMaciej W. Rozycki pr_debug("%p gpr[%d]->enr=%08x\n", 930*c491cfa2SMaciej W. Rozycki (void *)xcp->cp0_epc, MIPSInst_RT(ir), value); 931*c491cfa2SMaciej W. Rozycki fcr31 &= ~(FPU_CSR_FS | FPU_CSR_ALL_E | FPU_CSR_RM); 932*c491cfa2SMaciej W. Rozycki fcr31 |= (value << (FPU_CSR_FS_S - MIPS_FENR_FS_S)) & 933*c491cfa2SMaciej W. Rozycki FPU_CSR_FS; 934*c491cfa2SMaciej W. Rozycki fcr31 |= value & (FPU_CSR_ALL_E | FPU_CSR_RM); 935*c491cfa2SMaciej W. Rozycki break; 936*c491cfa2SMaciej W. Rozycki 937*c491cfa2SMaciej W. Rozycki case FPCREG_FEXR: 938*c491cfa2SMaciej W. Rozycki if (!cpu_has_mips_r) 939*c491cfa2SMaciej W. Rozycki break; 940*c491cfa2SMaciej W. Rozycki pr_debug("%p gpr[%d]->exr=%08x\n", 941*c491cfa2SMaciej W. Rozycki (void *)xcp->cp0_epc, MIPSInst_RT(ir), value); 942*c491cfa2SMaciej W. Rozycki fcr31 &= ~(FPU_CSR_ALL_X | FPU_CSR_ALL_S); 943*c491cfa2SMaciej W. Rozycki fcr31 |= value & (FPU_CSR_ALL_X | FPU_CSR_ALL_S); 944*c491cfa2SMaciej W. Rozycki break; 945*c491cfa2SMaciej W. Rozycki 946*c491cfa2SMaciej W. Rozycki case FPCREG_FCCR: 947*c491cfa2SMaciej W. Rozycki if (!cpu_has_mips_r) 948*c491cfa2SMaciej W. Rozycki break; 949*c491cfa2SMaciej W. Rozycki pr_debug("%p gpr[%d]->ccr=%08x\n", 950*c491cfa2SMaciej W. Rozycki (void *)xcp->cp0_epc, MIPSInst_RT(ir), value); 951*c491cfa2SMaciej W. Rozycki fcr31 &= ~(FPU_CSR_CONDX | FPU_CSR_COND); 952*c491cfa2SMaciej W. Rozycki fcr31 |= (value << (FPU_CSR_COND_S - MIPS_FCCR_COND0_S)) & 953*c491cfa2SMaciej W. Rozycki FPU_CSR_COND; 954*c491cfa2SMaciej W. Rozycki fcr31 |= (value << (FPU_CSR_COND1_S - MIPS_FCCR_COND1_S)) & 955*c491cfa2SMaciej W. Rozycki FPU_CSR_CONDX; 956*c491cfa2SMaciej W. Rozycki break; 957*c491cfa2SMaciej W. Rozycki 958*c491cfa2SMaciej W. Rozycki default: 959*c491cfa2SMaciej W. Rozycki break; 960d4f5b088SMaciej W. Rozycki } 961*c491cfa2SMaciej W. Rozycki 962*c491cfa2SMaciej W. Rozycki ctx->fcr31 = fcr31; 963d4f5b088SMaciej W. Rozycki } 964d4f5b088SMaciej W. Rozycki 965d4f5b088SMaciej W. Rozycki /* 9661da177e4SLinus Torvalds * Emulate the single floating point instruction pointed at by EPC. 9671da177e4SLinus Torvalds * Two instructions if the instruction is in a branch delay slot. 9681da177e4SLinus Torvalds */ 9691da177e4SLinus Torvalds 970515b029dSDavid Daney static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_struct *ctx, 971102cedc3SLeonid Yegoshin struct mm_decoded_insn dec_insn, void *__user *fault_addr) 9721da177e4SLinus Torvalds { 973102cedc3SLeonid Yegoshin unsigned long contpc = xcp->cp0_epc + dec_insn.pc_inc; 9743f7cac41SRalf Baechle unsigned int cond, cbit; 9753f7cac41SRalf Baechle mips_instruction ir; 9763f7cac41SRalf Baechle int likely, pc_inc; 9773f7cac41SRalf Baechle u32 __user *wva; 9783f7cac41SRalf Baechle u64 __user *dva; 9793f7cac41SRalf Baechle u32 wval; 9803f7cac41SRalf Baechle u64 dval; 9813f7cac41SRalf Baechle int sig; 9821da177e4SLinus Torvalds 98370e4c234SRalf Baechle /* 98470e4c234SRalf Baechle * These are giving gcc a gentle hint about what to expect in 98570e4c234SRalf Baechle * dec_inst in order to do better optimization. 98670e4c234SRalf Baechle */ 98770e4c234SRalf Baechle if (!cpu_has_mmips && dec_insn.micro_mips_mode) 98870e4c234SRalf Baechle unreachable(); 98970e4c234SRalf Baechle 9901da177e4SLinus Torvalds /* XXX NEC Vr54xx bug workaround */ 991e7e9cae5SRalf Baechle if (delay_slot(xcp)) { 992102cedc3SLeonid Yegoshin if (dec_insn.micro_mips_mode) { 993102cedc3SLeonid Yegoshin if (!mm_isBranchInstr(xcp, dec_insn, &contpc)) 994e7e9cae5SRalf Baechle clear_delay_slot(xcp); 995102cedc3SLeonid Yegoshin } else { 996102cedc3SLeonid Yegoshin if (!isBranchInstr(xcp, dec_insn, &contpc)) 997e7e9cae5SRalf Baechle clear_delay_slot(xcp); 998102cedc3SLeonid Yegoshin } 999102cedc3SLeonid Yegoshin } 10001da177e4SLinus Torvalds 1001e7e9cae5SRalf Baechle if (delay_slot(xcp)) { 10021da177e4SLinus Torvalds /* 10031da177e4SLinus Torvalds * The instruction to be emulated is in a branch delay slot 10041da177e4SLinus Torvalds * which means that we have to emulate the branch instruction 10051da177e4SLinus Torvalds * BEFORE we do the cop1 instruction. 10061da177e4SLinus Torvalds * 10071da177e4SLinus Torvalds * This branch could be a COP1 branch, but in that case we 10081da177e4SLinus Torvalds * would have had a trap for that instruction, and would not 10091da177e4SLinus Torvalds * come through this route. 10101da177e4SLinus Torvalds * 10111da177e4SLinus Torvalds * Linux MIPS branch emulator operates on context, updating the 10121da177e4SLinus Torvalds * cp0_epc. 10131da177e4SLinus Torvalds */ 1014102cedc3SLeonid Yegoshin ir = dec_insn.next_insn; /* process delay slot instr */ 1015102cedc3SLeonid Yegoshin pc_inc = dec_insn.next_pc_inc; 1016333d1f67SRalf Baechle } else { 1017102cedc3SLeonid Yegoshin ir = dec_insn.insn; /* process current instr */ 1018102cedc3SLeonid Yegoshin pc_inc = dec_insn.pc_inc; 1019102cedc3SLeonid Yegoshin } 1020102cedc3SLeonid Yegoshin 1021102cedc3SLeonid Yegoshin /* 1022102cedc3SLeonid Yegoshin * Since microMIPS FPU instructios are a subset of MIPS32 FPU 1023102cedc3SLeonid Yegoshin * instructions, we want to convert microMIPS FPU instructions 1024102cedc3SLeonid Yegoshin * into MIPS32 instructions so that we could reuse all of the 1025102cedc3SLeonid Yegoshin * FPU emulation code. 1026102cedc3SLeonid Yegoshin * 1027102cedc3SLeonid Yegoshin * NOTE: We cannot do this for branch instructions since they 1028102cedc3SLeonid Yegoshin * are not a subset. Example: Cannot emulate a 16-bit 1029102cedc3SLeonid Yegoshin * aligned target address with a MIPS32 instruction. 1030102cedc3SLeonid Yegoshin */ 1031102cedc3SLeonid Yegoshin if (dec_insn.micro_mips_mode) { 1032102cedc3SLeonid Yegoshin /* 1033102cedc3SLeonid Yegoshin * If next instruction is a 16-bit instruction, then it 1034102cedc3SLeonid Yegoshin * it cannot be a FPU instruction. This could happen 1035102cedc3SLeonid Yegoshin * since we can be called for non-FPU instructions. 1036102cedc3SLeonid Yegoshin */ 1037102cedc3SLeonid Yegoshin if ((pc_inc == 2) || 1038102cedc3SLeonid Yegoshin (microMIPS32_to_MIPS32((union mips_instruction *)&ir) 1039102cedc3SLeonid Yegoshin == SIGILL)) 1040102cedc3SLeonid Yegoshin return SIGILL; 10411da177e4SLinus Torvalds } 10421da177e4SLinus Torvalds 10431da177e4SLinus Torvalds emul: 1044a8b0ca17SPeter Zijlstra perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 1, xcp, 0); 1045b6ee75edSDavid Daney MIPS_FPU_EMU_INC_STATS(emulated); 10461da177e4SLinus Torvalds switch (MIPSInst_OPCODE(ir)) { 10473f7cac41SRalf Baechle case ldc1_op: 10483f7cac41SRalf Baechle dva = (u64 __user *) (xcp->regs[MIPSInst_RS(ir)] + 10491da177e4SLinus Torvalds MIPSInst_SIMM(ir)); 1050b6ee75edSDavid Daney MIPS_FPU_EMU_INC_STATS(loads); 1051515b029dSDavid Daney 10523f7cac41SRalf Baechle if (!access_ok(VERIFY_READ, dva, sizeof(u64))) { 1053b6ee75edSDavid Daney MIPS_FPU_EMU_INC_STATS(errors); 10543f7cac41SRalf Baechle *fault_addr = dva; 10551da177e4SLinus Torvalds return SIGBUS; 10561da177e4SLinus Torvalds } 10573f7cac41SRalf Baechle if (__get_user(dval, dva)) { 1058515b029dSDavid Daney MIPS_FPU_EMU_INC_STATS(errors); 10593f7cac41SRalf Baechle *fault_addr = dva; 1060515b029dSDavid Daney return SIGSEGV; 1061515b029dSDavid Daney } 10623f7cac41SRalf Baechle DITOREG(dval, MIPSInst_RT(ir)); 10631da177e4SLinus Torvalds break; 10641da177e4SLinus Torvalds 10653f7cac41SRalf Baechle case sdc1_op: 10663f7cac41SRalf Baechle dva = (u64 __user *) (xcp->regs[MIPSInst_RS(ir)] + 10671da177e4SLinus Torvalds MIPSInst_SIMM(ir)); 1068b6ee75edSDavid Daney MIPS_FPU_EMU_INC_STATS(stores); 10693f7cac41SRalf Baechle DIFROMREG(dval, MIPSInst_RT(ir)); 10703f7cac41SRalf Baechle if (!access_ok(VERIFY_WRITE, dva, sizeof(u64))) { 1071b6ee75edSDavid Daney MIPS_FPU_EMU_INC_STATS(errors); 10723f7cac41SRalf Baechle *fault_addr = dva; 10731da177e4SLinus Torvalds return SIGBUS; 10741da177e4SLinus Torvalds } 10753f7cac41SRalf Baechle if (__put_user(dval, dva)) { 1076515b029dSDavid Daney MIPS_FPU_EMU_INC_STATS(errors); 10773f7cac41SRalf Baechle *fault_addr = dva; 1078515b029dSDavid Daney return SIGSEGV; 1079515b029dSDavid Daney } 10801da177e4SLinus Torvalds break; 10811da177e4SLinus Torvalds 10823f7cac41SRalf Baechle case lwc1_op: 10833f7cac41SRalf Baechle wva = (u32 __user *) (xcp->regs[MIPSInst_RS(ir)] + 10841da177e4SLinus Torvalds MIPSInst_SIMM(ir)); 1085b6ee75edSDavid Daney MIPS_FPU_EMU_INC_STATS(loads); 10863f7cac41SRalf Baechle if (!access_ok(VERIFY_READ, wva, sizeof(u32))) { 1087b6ee75edSDavid Daney MIPS_FPU_EMU_INC_STATS(errors); 10883f7cac41SRalf Baechle *fault_addr = wva; 10891da177e4SLinus Torvalds return SIGBUS; 10901da177e4SLinus Torvalds } 10913f7cac41SRalf Baechle if (__get_user(wval, wva)) { 1092515b029dSDavid Daney MIPS_FPU_EMU_INC_STATS(errors); 10933f7cac41SRalf Baechle *fault_addr = wva; 1094515b029dSDavid Daney return SIGSEGV; 1095515b029dSDavid Daney } 10963f7cac41SRalf Baechle SITOREG(wval, MIPSInst_RT(ir)); 10971da177e4SLinus Torvalds break; 10981da177e4SLinus Torvalds 10993f7cac41SRalf Baechle case swc1_op: 11003f7cac41SRalf Baechle wva = (u32 __user *) (xcp->regs[MIPSInst_RS(ir)] + 11011da177e4SLinus Torvalds MIPSInst_SIMM(ir)); 1102b6ee75edSDavid Daney MIPS_FPU_EMU_INC_STATS(stores); 11033f7cac41SRalf Baechle SIFROMREG(wval, MIPSInst_RT(ir)); 11043f7cac41SRalf Baechle if (!access_ok(VERIFY_WRITE, wva, sizeof(u32))) { 1105b6ee75edSDavid Daney MIPS_FPU_EMU_INC_STATS(errors); 11063f7cac41SRalf Baechle *fault_addr = wva; 11071da177e4SLinus Torvalds return SIGBUS; 11081da177e4SLinus Torvalds } 11093f7cac41SRalf Baechle if (__put_user(wval, wva)) { 1110515b029dSDavid Daney MIPS_FPU_EMU_INC_STATS(errors); 11113f7cac41SRalf Baechle *fault_addr = wva; 1112515b029dSDavid Daney return SIGSEGV; 1113515b029dSDavid Daney } 11141da177e4SLinus Torvalds break; 11151da177e4SLinus Torvalds 11161da177e4SLinus Torvalds case cop1_op: 11171da177e4SLinus Torvalds switch (MIPSInst_RS(ir)) { 11181da177e4SLinus Torvalds case dmfc_op: 111908a07904SRalf Baechle if (!cpu_has_mips_3_4_5 && !cpu_has_mips64) 112008a07904SRalf Baechle return SIGILL; 112108a07904SRalf Baechle 11221da177e4SLinus Torvalds /* copregister fs -> gpr[rt] */ 11231da177e4SLinus Torvalds if (MIPSInst_RT(ir) != 0) { 11241da177e4SLinus Torvalds DIFROMREG(xcp->regs[MIPSInst_RT(ir)], 11251da177e4SLinus Torvalds MIPSInst_RD(ir)); 11261da177e4SLinus Torvalds } 11271da177e4SLinus Torvalds break; 11281da177e4SLinus Torvalds 11291da177e4SLinus Torvalds case dmtc_op: 113008a07904SRalf Baechle if (!cpu_has_mips_3_4_5 && !cpu_has_mips64) 113108a07904SRalf Baechle return SIGILL; 113208a07904SRalf Baechle 11331da177e4SLinus Torvalds /* copregister fs <- rt */ 11341da177e4SLinus Torvalds DITOREG(xcp->regs[MIPSInst_RT(ir)], MIPSInst_RD(ir)); 11351da177e4SLinus Torvalds break; 11361da177e4SLinus Torvalds 11371ac94400SLeonid Yegoshin case mfhc_op: 11381ac94400SLeonid Yegoshin if (!cpu_has_mips_r2) 11391ac94400SLeonid Yegoshin goto sigill; 11401ac94400SLeonid Yegoshin 11411ac94400SLeonid Yegoshin /* copregister rd -> gpr[rt] */ 11421ac94400SLeonid Yegoshin if (MIPSInst_RT(ir) != 0) { 11431ac94400SLeonid Yegoshin SIFROMHREG(xcp->regs[MIPSInst_RT(ir)], 11441ac94400SLeonid Yegoshin MIPSInst_RD(ir)); 11451ac94400SLeonid Yegoshin } 11461ac94400SLeonid Yegoshin break; 11471ac94400SLeonid Yegoshin 11481ac94400SLeonid Yegoshin case mthc_op: 11491ac94400SLeonid Yegoshin if (!cpu_has_mips_r2) 11501ac94400SLeonid Yegoshin goto sigill; 11511ac94400SLeonid Yegoshin 11521ac94400SLeonid Yegoshin /* copregister rd <- gpr[rt] */ 11531ac94400SLeonid Yegoshin SITOHREG(xcp->regs[MIPSInst_RT(ir)], MIPSInst_RD(ir)); 11541ac94400SLeonid Yegoshin break; 11551ac94400SLeonid Yegoshin 11561da177e4SLinus Torvalds case mfc_op: 11571da177e4SLinus Torvalds /* copregister rd -> gpr[rt] */ 11581da177e4SLinus Torvalds if (MIPSInst_RT(ir) != 0) { 11591da177e4SLinus Torvalds SIFROMREG(xcp->regs[MIPSInst_RT(ir)], 11601da177e4SLinus Torvalds MIPSInst_RD(ir)); 11611da177e4SLinus Torvalds } 11621da177e4SLinus Torvalds break; 11631da177e4SLinus Torvalds 11641da177e4SLinus Torvalds case mtc_op: 11651da177e4SLinus Torvalds /* copregister rd <- rt */ 11661da177e4SLinus Torvalds SITOREG(xcp->regs[MIPSInst_RT(ir)], MIPSInst_RD(ir)); 11671da177e4SLinus Torvalds break; 11681da177e4SLinus Torvalds 11693f7cac41SRalf Baechle case cfc_op: 11701da177e4SLinus Torvalds /* cop control register rd -> gpr[rt] */ 1171d4f5b088SMaciej W. Rozycki cop1_cfc(xcp, ctx, ir); 11721da177e4SLinus Torvalds break; 11731da177e4SLinus Torvalds 11743f7cac41SRalf Baechle case ctc_op: 11751da177e4SLinus Torvalds /* copregister rd <- rt */ 1176d4f5b088SMaciej W. Rozycki cop1_ctc(xcp, ctx, ir); 11771da177e4SLinus Torvalds if ((ctx->fcr31 >> 5) & ctx->fcr31 & FPU_CSR_ALL_E) { 11781da177e4SLinus Torvalds return SIGFPE; 11791da177e4SLinus Torvalds } 11801da177e4SLinus Torvalds break; 11811da177e4SLinus Torvalds 11823f7cac41SRalf Baechle case bc_op: 1183e7e9cae5SRalf Baechle if (delay_slot(xcp)) 11841da177e4SLinus Torvalds return SIGILL; 11851da177e4SLinus Torvalds 118608a07904SRalf Baechle if (cpu_has_mips_4_5_r) 118708a07904SRalf Baechle cbit = fpucondbit[MIPSInst_RT(ir) >> 2]; 118808a07904SRalf Baechle else 118908a07904SRalf Baechle cbit = FPU_CSR_COND; 119008a07904SRalf Baechle cond = ctx->fcr31 & cbit; 119108a07904SRalf Baechle 11923f7cac41SRalf Baechle likely = 0; 11931da177e4SLinus Torvalds switch (MIPSInst_RT(ir) & 3) { 11941da177e4SLinus Torvalds case bcfl_op: 11952d83fea7SMaciej W. Rozycki if (cpu_has_mips_2_3_4_5_r) 11961da177e4SLinus Torvalds likely = 1; 11972d83fea7SMaciej W. Rozycki /* Fall through */ 11981da177e4SLinus Torvalds case bcf_op: 11991da177e4SLinus Torvalds cond = !cond; 12001da177e4SLinus Torvalds break; 12011da177e4SLinus Torvalds case bctl_op: 12022d83fea7SMaciej W. Rozycki if (cpu_has_mips_2_3_4_5_r) 12031da177e4SLinus Torvalds likely = 1; 12042d83fea7SMaciej W. Rozycki /* Fall through */ 12051da177e4SLinus Torvalds case bct_op: 12061da177e4SLinus Torvalds break; 12071da177e4SLinus Torvalds } 12081da177e4SLinus Torvalds 1209e7e9cae5SRalf Baechle set_delay_slot(xcp); 12101da177e4SLinus Torvalds if (cond) { 12113f7cac41SRalf Baechle /* 12123f7cac41SRalf Baechle * Branch taken: emulate dslot instruction 12131da177e4SLinus Torvalds */ 12149ab4471cSMaciej W. Rozycki unsigned long bcpc; 12159ab4471cSMaciej W. Rozycki 12169ab4471cSMaciej W. Rozycki /* 12179ab4471cSMaciej W. Rozycki * Remember EPC at the branch to point back 12189ab4471cSMaciej W. Rozycki * at so that any delay-slot instruction 12199ab4471cSMaciej W. Rozycki * signal is not silently ignored. 12209ab4471cSMaciej W. Rozycki */ 12219ab4471cSMaciej W. Rozycki bcpc = xcp->cp0_epc; 1222102cedc3SLeonid Yegoshin xcp->cp0_epc += dec_insn.pc_inc; 12231da177e4SLinus Torvalds 1224102cedc3SLeonid Yegoshin contpc = MIPSInst_SIMM(ir); 1225102cedc3SLeonid Yegoshin ir = dec_insn.next_insn; 1226102cedc3SLeonid Yegoshin if (dec_insn.micro_mips_mode) { 1227102cedc3SLeonid Yegoshin contpc = (xcp->cp0_epc + (contpc << 1)); 1228102cedc3SLeonid Yegoshin 1229102cedc3SLeonid Yegoshin /* If 16-bit instruction, not FPU. */ 1230102cedc3SLeonid Yegoshin if ((dec_insn.next_pc_inc == 2) || 1231102cedc3SLeonid Yegoshin (microMIPS32_to_MIPS32((union mips_instruction *)&ir) == SIGILL)) { 1232102cedc3SLeonid Yegoshin 1233102cedc3SLeonid Yegoshin /* 1234102cedc3SLeonid Yegoshin * Since this instruction will 1235102cedc3SLeonid Yegoshin * be put on the stack with 1236102cedc3SLeonid Yegoshin * 32-bit words, get around 1237102cedc3SLeonid Yegoshin * this problem by putting a 1238102cedc3SLeonid Yegoshin * NOP16 as the second one. 1239102cedc3SLeonid Yegoshin */ 1240102cedc3SLeonid Yegoshin if (dec_insn.next_pc_inc == 2) 1241102cedc3SLeonid Yegoshin ir = (ir & (~0xffff)) | MM_NOP16; 1242102cedc3SLeonid Yegoshin 1243102cedc3SLeonid Yegoshin /* 1244102cedc3SLeonid Yegoshin * Single step the non-CP1 1245102cedc3SLeonid Yegoshin * instruction in the dslot. 1246102cedc3SLeonid Yegoshin */ 12479ab4471cSMaciej W. Rozycki sig = mips_dsemul(xcp, ir, 12489ab4471cSMaciej W. Rozycki contpc); 12499ab4471cSMaciej W. Rozycki if (sig) 12509ab4471cSMaciej W. Rozycki xcp->cp0_epc = bcpc; 12519ab4471cSMaciej W. Rozycki /* 12529ab4471cSMaciej W. Rozycki * SIGILL forces out of 12539ab4471cSMaciej W. Rozycki * the emulation loop. 12549ab4471cSMaciej W. Rozycki */ 12559ab4471cSMaciej W. Rozycki return sig ? sig : SIGILL; 1256515b029dSDavid Daney } 1257102cedc3SLeonid Yegoshin } else 1258102cedc3SLeonid Yegoshin contpc = (xcp->cp0_epc + (contpc << 2)); 12591da177e4SLinus Torvalds 12601da177e4SLinus Torvalds switch (MIPSInst_OPCODE(ir)) { 12611da177e4SLinus Torvalds case lwc1_op: 12621da177e4SLinus Torvalds case swc1_op: 126308a07904SRalf Baechle goto emul; 12643f7cac41SRalf Baechle 12651da177e4SLinus Torvalds case ldc1_op: 12661da177e4SLinus Torvalds case sdc1_op: 12672d83fea7SMaciej W. Rozycki if (cpu_has_mips_2_3_4_5_r) 126808a07904SRalf Baechle goto emul; 126908a07904SRalf Baechle 12709ab4471cSMaciej W. Rozycki goto bc_sigill; 12713f7cac41SRalf Baechle 12721da177e4SLinus Torvalds case cop1_op: 127308a07904SRalf Baechle goto emul; 12743f7cac41SRalf Baechle 12751da177e4SLinus Torvalds case cop1x_op: 12762d83fea7SMaciej W. Rozycki if (cpu_has_mips_4_5_64_r2_r6) 12771da177e4SLinus Torvalds /* its one of ours */ 12781da177e4SLinus Torvalds goto emul; 127908a07904SRalf Baechle 12809ab4471cSMaciej W. Rozycki goto bc_sigill; 12813f7cac41SRalf Baechle 12821da177e4SLinus Torvalds case spec_op: 12832d83fea7SMaciej W. Rozycki switch (MIPSInst_FUNC(ir)) { 12842d83fea7SMaciej W. Rozycki case movc_op: 12852d83fea7SMaciej W. Rozycki if (cpu_has_mips_4_5_r) 12861da177e4SLinus Torvalds goto emul; 12872d83fea7SMaciej W. Rozycki 12889ab4471cSMaciej W. Rozycki goto bc_sigill; 12892d83fea7SMaciej W. Rozycki } 12901da177e4SLinus Torvalds break; 12919ab4471cSMaciej W. Rozycki 12929ab4471cSMaciej W. Rozycki bc_sigill: 12939ab4471cSMaciej W. Rozycki xcp->cp0_epc = bcpc; 12949ab4471cSMaciej W. Rozycki return SIGILL; 12951da177e4SLinus Torvalds } 12961da177e4SLinus Torvalds 12971da177e4SLinus Torvalds /* 12981da177e4SLinus Torvalds * Single step the non-cp1 12991da177e4SLinus Torvalds * instruction in the dslot 13001da177e4SLinus Torvalds */ 13019ab4471cSMaciej W. Rozycki sig = mips_dsemul(xcp, ir, contpc); 13029ab4471cSMaciej W. Rozycki if (sig) 13039ab4471cSMaciej W. Rozycki xcp->cp0_epc = bcpc; 13049ab4471cSMaciej W. Rozycki /* SIGILL forces out of the emulation loop. */ 13059ab4471cSMaciej W. Rozycki return sig ? sig : SIGILL; 13063f7cac41SRalf Baechle } else if (likely) { /* branch not taken */ 13071da177e4SLinus Torvalds /* 13081da177e4SLinus Torvalds * branch likely nullifies 13091da177e4SLinus Torvalds * dslot if not taken 13101da177e4SLinus Torvalds */ 1311102cedc3SLeonid Yegoshin xcp->cp0_epc += dec_insn.pc_inc; 1312102cedc3SLeonid Yegoshin contpc += dec_insn.pc_inc; 13131da177e4SLinus Torvalds /* 13141da177e4SLinus Torvalds * else continue & execute 13151da177e4SLinus Torvalds * dslot as normal insn 13161da177e4SLinus Torvalds */ 13171da177e4SLinus Torvalds } 13181da177e4SLinus Torvalds break; 13191da177e4SLinus Torvalds 13201da177e4SLinus Torvalds default: 13211da177e4SLinus Torvalds if (!(MIPSInst_RS(ir) & 0x10)) 13221da177e4SLinus Torvalds return SIGILL; 13231da177e4SLinus Torvalds 13241da177e4SLinus Torvalds /* a real fpu computation instruction */ 13251da177e4SLinus Torvalds if ((sig = fpu_emu(xcp, ctx, ir))) 13261da177e4SLinus Torvalds return sig; 13271da177e4SLinus Torvalds } 13281da177e4SLinus Torvalds break; 13291da177e4SLinus Torvalds 13303f7cac41SRalf Baechle case cop1x_op: 13312d83fea7SMaciej W. Rozycki if (!cpu_has_mips_4_5_64_r2_r6) 133208a07904SRalf Baechle return SIGILL; 133308a07904SRalf Baechle 133408a07904SRalf Baechle sig = fpux_emu(xcp, ctx, ir, fault_addr); 1335515b029dSDavid Daney if (sig) 13361da177e4SLinus Torvalds return sig; 13371da177e4SLinus Torvalds break; 13381da177e4SLinus Torvalds 13391da177e4SLinus Torvalds case spec_op: 134008a07904SRalf Baechle if (!cpu_has_mips_4_5_r) 134108a07904SRalf Baechle return SIGILL; 134208a07904SRalf Baechle 13431da177e4SLinus Torvalds if (MIPSInst_FUNC(ir) != movc_op) 13441da177e4SLinus Torvalds return SIGILL; 13451da177e4SLinus Torvalds cond = fpucondbit[MIPSInst_RT(ir) >> 2]; 13461da177e4SLinus Torvalds if (((ctx->fcr31 & cond) != 0) == ((MIPSInst_RT(ir) & 1) != 0)) 13471da177e4SLinus Torvalds xcp->regs[MIPSInst_RD(ir)] = 13481da177e4SLinus Torvalds xcp->regs[MIPSInst_RS(ir)]; 13491da177e4SLinus Torvalds break; 13501da177e4SLinus Torvalds default: 13511ac94400SLeonid Yegoshin sigill: 13521da177e4SLinus Torvalds return SIGILL; 13531da177e4SLinus Torvalds } 13541da177e4SLinus Torvalds 13551da177e4SLinus Torvalds /* we did it !! */ 1356e70dfc10SAtsushi Nemoto xcp->cp0_epc = contpc; 1357e7e9cae5SRalf Baechle clear_delay_slot(xcp); 1358333d1f67SRalf Baechle 13591da177e4SLinus Torvalds return 0; 13601da177e4SLinus Torvalds } 13611da177e4SLinus Torvalds 13621da177e4SLinus Torvalds /* 13631da177e4SLinus Torvalds * Conversion table from MIPS compare ops 48-63 13641da177e4SLinus Torvalds * cond = ieee754dp_cmp(x,y,IEEE754_UN,sig); 13651da177e4SLinus Torvalds */ 13661da177e4SLinus Torvalds static const unsigned char cmptab[8] = { 13671da177e4SLinus Torvalds 0, /* cmp_0 (sig) cmp_sf */ 13681da177e4SLinus Torvalds IEEE754_CUN, /* cmp_un (sig) cmp_ngle */ 13691da177e4SLinus Torvalds IEEE754_CEQ, /* cmp_eq (sig) cmp_seq */ 13701da177e4SLinus Torvalds IEEE754_CEQ | IEEE754_CUN, /* cmp_ueq (sig) cmp_ngl */ 13711da177e4SLinus Torvalds IEEE754_CLT, /* cmp_olt (sig) cmp_lt */ 13721da177e4SLinus Torvalds IEEE754_CLT | IEEE754_CUN, /* cmp_ult (sig) cmp_nge */ 13731da177e4SLinus Torvalds IEEE754_CLT | IEEE754_CEQ, /* cmp_ole (sig) cmp_le */ 13741da177e4SLinus Torvalds IEEE754_CLT | IEEE754_CEQ | IEEE754_CUN, /* cmp_ule (sig) cmp_ngt */ 13751da177e4SLinus Torvalds }; 13761da177e4SLinus Torvalds 13771da177e4SLinus Torvalds 13781da177e4SLinus Torvalds /* 13791da177e4SLinus Torvalds * Additional MIPS4 instructions 13801da177e4SLinus Torvalds */ 13811da177e4SLinus Torvalds 13821da177e4SLinus Torvalds #define DEF3OP(name, p, f1, f2, f3) \ 138347fa0c02SRalf Baechle static union ieee754##p fpemu_##p##_##name(union ieee754##p r, \ 138447fa0c02SRalf Baechle union ieee754##p s, union ieee754##p t) \ 13851da177e4SLinus Torvalds { \ 1386cd21dfcfSRalf Baechle struct _ieee754_csr ieee754_csr_save; \ 13871da177e4SLinus Torvalds s = f1(s, t); \ 13881da177e4SLinus Torvalds ieee754_csr_save = ieee754_csr; \ 13891da177e4SLinus Torvalds s = f2(s, r); \ 13901da177e4SLinus Torvalds ieee754_csr_save.cx |= ieee754_csr.cx; \ 13911da177e4SLinus Torvalds ieee754_csr_save.sx |= ieee754_csr.sx; \ 13921da177e4SLinus Torvalds s = f3(s); \ 13931da177e4SLinus Torvalds ieee754_csr.cx |= ieee754_csr_save.cx; \ 13941da177e4SLinus Torvalds ieee754_csr.sx |= ieee754_csr_save.sx; \ 13951da177e4SLinus Torvalds return s; \ 13961da177e4SLinus Torvalds } 13971da177e4SLinus Torvalds 13982209bcb1SRalf Baechle static union ieee754dp fpemu_dp_recip(union ieee754dp d) 13991da177e4SLinus Torvalds { 14001da177e4SLinus Torvalds return ieee754dp_div(ieee754dp_one(0), d); 14011da177e4SLinus Torvalds } 14021da177e4SLinus Torvalds 14032209bcb1SRalf Baechle static union ieee754dp fpemu_dp_rsqrt(union ieee754dp d) 14041da177e4SLinus Torvalds { 14051da177e4SLinus Torvalds return ieee754dp_div(ieee754dp_one(0), ieee754dp_sqrt(d)); 14061da177e4SLinus Torvalds } 14071da177e4SLinus Torvalds 14082209bcb1SRalf Baechle static union ieee754sp fpemu_sp_recip(union ieee754sp s) 14091da177e4SLinus Torvalds { 14101da177e4SLinus Torvalds return ieee754sp_div(ieee754sp_one(0), s); 14111da177e4SLinus Torvalds } 14121da177e4SLinus Torvalds 14132209bcb1SRalf Baechle static union ieee754sp fpemu_sp_rsqrt(union ieee754sp s) 14141da177e4SLinus Torvalds { 14151da177e4SLinus Torvalds return ieee754sp_div(ieee754sp_one(0), ieee754sp_sqrt(s)); 14161da177e4SLinus Torvalds } 14171da177e4SLinus Torvalds 14181da177e4SLinus Torvalds DEF3OP(madd, sp, ieee754sp_mul, ieee754sp_add, ); 14191da177e4SLinus Torvalds DEF3OP(msub, sp, ieee754sp_mul, ieee754sp_sub, ); 14201da177e4SLinus Torvalds DEF3OP(nmadd, sp, ieee754sp_mul, ieee754sp_add, ieee754sp_neg); 14211da177e4SLinus Torvalds DEF3OP(nmsub, sp, ieee754sp_mul, ieee754sp_sub, ieee754sp_neg); 14221da177e4SLinus Torvalds DEF3OP(madd, dp, ieee754dp_mul, ieee754dp_add, ); 14231da177e4SLinus Torvalds DEF3OP(msub, dp, ieee754dp_mul, ieee754dp_sub, ); 14241da177e4SLinus Torvalds DEF3OP(nmadd, dp, ieee754dp_mul, ieee754dp_add, ieee754dp_neg); 14251da177e4SLinus Torvalds DEF3OP(nmsub, dp, ieee754dp_mul, ieee754dp_sub, ieee754dp_neg); 14261da177e4SLinus Torvalds 1427eae89076SAtsushi Nemoto static int fpux_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx, 1428515b029dSDavid Daney mips_instruction ir, void *__user *fault_addr) 14291da177e4SLinus Torvalds { 14301da177e4SLinus Torvalds unsigned rcsr = 0; /* resulting csr */ 14311da177e4SLinus Torvalds 1432b6ee75edSDavid Daney MIPS_FPU_EMU_INC_STATS(cp1xops); 14331da177e4SLinus Torvalds 14341da177e4SLinus Torvalds switch (MIPSInst_FMA_FFMT(ir)) { 14351da177e4SLinus Torvalds case s_fmt:{ /* 0 */ 14361da177e4SLinus Torvalds 14372209bcb1SRalf Baechle union ieee754sp(*handler) (union ieee754sp, union ieee754sp, union ieee754sp); 14382209bcb1SRalf Baechle union ieee754sp fd, fr, fs, ft; 14393fccc015SRalf Baechle u32 __user *va; 14401da177e4SLinus Torvalds u32 val; 14411da177e4SLinus Torvalds 14421da177e4SLinus Torvalds switch (MIPSInst_FUNC(ir)) { 14431da177e4SLinus Torvalds case lwxc1_op: 14443fccc015SRalf Baechle va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] + 14451da177e4SLinus Torvalds xcp->regs[MIPSInst_FT(ir)]); 14461da177e4SLinus Torvalds 1447b6ee75edSDavid Daney MIPS_FPU_EMU_INC_STATS(loads); 1448515b029dSDavid Daney if (!access_ok(VERIFY_READ, va, sizeof(u32))) { 1449b6ee75edSDavid Daney MIPS_FPU_EMU_INC_STATS(errors); 1450515b029dSDavid Daney *fault_addr = va; 14511da177e4SLinus Torvalds return SIGBUS; 14521da177e4SLinus Torvalds } 1453515b029dSDavid Daney if (__get_user(val, va)) { 1454515b029dSDavid Daney MIPS_FPU_EMU_INC_STATS(errors); 1455515b029dSDavid Daney *fault_addr = va; 1456515b029dSDavid Daney return SIGSEGV; 1457515b029dSDavid Daney } 14581da177e4SLinus Torvalds SITOREG(val, MIPSInst_FD(ir)); 14591da177e4SLinus Torvalds break; 14601da177e4SLinus Torvalds 14611da177e4SLinus Torvalds case swxc1_op: 14623fccc015SRalf Baechle va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] + 14631da177e4SLinus Torvalds xcp->regs[MIPSInst_FT(ir)]); 14641da177e4SLinus Torvalds 1465b6ee75edSDavid Daney MIPS_FPU_EMU_INC_STATS(stores); 14661da177e4SLinus Torvalds 14671da177e4SLinus Torvalds SIFROMREG(val, MIPSInst_FS(ir)); 1468515b029dSDavid Daney if (!access_ok(VERIFY_WRITE, va, sizeof(u32))) { 1469515b029dSDavid Daney MIPS_FPU_EMU_INC_STATS(errors); 1470515b029dSDavid Daney *fault_addr = va; 1471515b029dSDavid Daney return SIGBUS; 1472515b029dSDavid Daney } 14731da177e4SLinus Torvalds if (put_user(val, va)) { 1474b6ee75edSDavid Daney MIPS_FPU_EMU_INC_STATS(errors); 1475515b029dSDavid Daney *fault_addr = va; 1476515b029dSDavid Daney return SIGSEGV; 14771da177e4SLinus Torvalds } 14781da177e4SLinus Torvalds break; 14791da177e4SLinus Torvalds 14801da177e4SLinus Torvalds case madd_s_op: 14811da177e4SLinus Torvalds handler = fpemu_sp_madd; 14821da177e4SLinus Torvalds goto scoptop; 14831da177e4SLinus Torvalds case msub_s_op: 14841da177e4SLinus Torvalds handler = fpemu_sp_msub; 14851da177e4SLinus Torvalds goto scoptop; 14861da177e4SLinus Torvalds case nmadd_s_op: 14871da177e4SLinus Torvalds handler = fpemu_sp_nmadd; 14881da177e4SLinus Torvalds goto scoptop; 14891da177e4SLinus Torvalds case nmsub_s_op: 14901da177e4SLinus Torvalds handler = fpemu_sp_nmsub; 14911da177e4SLinus Torvalds goto scoptop; 14921da177e4SLinus Torvalds 14931da177e4SLinus Torvalds scoptop: 14941da177e4SLinus Torvalds SPFROMREG(fr, MIPSInst_FR(ir)); 14951da177e4SLinus Torvalds SPFROMREG(fs, MIPSInst_FS(ir)); 14961da177e4SLinus Torvalds SPFROMREG(ft, MIPSInst_FT(ir)); 14971da177e4SLinus Torvalds fd = (*handler) (fr, fs, ft); 14981da177e4SLinus Torvalds SPTOREG(fd, MIPSInst_FD(ir)); 14991da177e4SLinus Torvalds 15001da177e4SLinus Torvalds copcsr: 1501c4103526SDeng-Cheng Zhu if (ieee754_cxtest(IEEE754_INEXACT)) { 1502c4103526SDeng-Cheng Zhu MIPS_FPU_EMU_INC_STATS(ieee754_inexact); 15031da177e4SLinus Torvalds rcsr |= FPU_CSR_INE_X | FPU_CSR_INE_S; 1504c4103526SDeng-Cheng Zhu } 1505c4103526SDeng-Cheng Zhu if (ieee754_cxtest(IEEE754_UNDERFLOW)) { 1506c4103526SDeng-Cheng Zhu MIPS_FPU_EMU_INC_STATS(ieee754_underflow); 15071da177e4SLinus Torvalds rcsr |= FPU_CSR_UDF_X | FPU_CSR_UDF_S; 1508c4103526SDeng-Cheng Zhu } 1509c4103526SDeng-Cheng Zhu if (ieee754_cxtest(IEEE754_OVERFLOW)) { 1510c4103526SDeng-Cheng Zhu MIPS_FPU_EMU_INC_STATS(ieee754_overflow); 15111da177e4SLinus Torvalds rcsr |= FPU_CSR_OVF_X | FPU_CSR_OVF_S; 1512c4103526SDeng-Cheng Zhu } 1513c4103526SDeng-Cheng Zhu if (ieee754_cxtest(IEEE754_INVALID_OPERATION)) { 1514c4103526SDeng-Cheng Zhu MIPS_FPU_EMU_INC_STATS(ieee754_invalidop); 15151da177e4SLinus Torvalds rcsr |= FPU_CSR_INV_X | FPU_CSR_INV_S; 1516c4103526SDeng-Cheng Zhu } 15171da177e4SLinus Torvalds 15181da177e4SLinus Torvalds ctx->fcr31 = (ctx->fcr31 & ~FPU_CSR_ALL_X) | rcsr; 15191da177e4SLinus Torvalds if ((ctx->fcr31 >> 5) & ctx->fcr31 & FPU_CSR_ALL_E) { 15203f7cac41SRalf Baechle /*printk ("SIGFPE: FPU csr = %08x\n", 15211da177e4SLinus Torvalds ctx->fcr31); */ 15221da177e4SLinus Torvalds return SIGFPE; 15231da177e4SLinus Torvalds } 15241da177e4SLinus Torvalds 15251da177e4SLinus Torvalds break; 15261da177e4SLinus Torvalds 15271da177e4SLinus Torvalds default: 15281da177e4SLinus Torvalds return SIGILL; 15291da177e4SLinus Torvalds } 15301da177e4SLinus Torvalds break; 15311da177e4SLinus Torvalds } 15321da177e4SLinus Torvalds 15331da177e4SLinus Torvalds case d_fmt:{ /* 1 */ 15342209bcb1SRalf Baechle union ieee754dp(*handler) (union ieee754dp, union ieee754dp, union ieee754dp); 15352209bcb1SRalf Baechle union ieee754dp fd, fr, fs, ft; 15363fccc015SRalf Baechle u64 __user *va; 15371da177e4SLinus Torvalds u64 val; 15381da177e4SLinus Torvalds 15391da177e4SLinus Torvalds switch (MIPSInst_FUNC(ir)) { 15401da177e4SLinus Torvalds case ldxc1_op: 15413fccc015SRalf Baechle va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] + 15421da177e4SLinus Torvalds xcp->regs[MIPSInst_FT(ir)]); 15431da177e4SLinus Torvalds 1544b6ee75edSDavid Daney MIPS_FPU_EMU_INC_STATS(loads); 1545515b029dSDavid Daney if (!access_ok(VERIFY_READ, va, sizeof(u64))) { 1546b6ee75edSDavid Daney MIPS_FPU_EMU_INC_STATS(errors); 1547515b029dSDavid Daney *fault_addr = va; 15481da177e4SLinus Torvalds return SIGBUS; 15491da177e4SLinus Torvalds } 1550515b029dSDavid Daney if (__get_user(val, va)) { 1551515b029dSDavid Daney MIPS_FPU_EMU_INC_STATS(errors); 1552515b029dSDavid Daney *fault_addr = va; 1553515b029dSDavid Daney return SIGSEGV; 1554515b029dSDavid Daney } 15551da177e4SLinus Torvalds DITOREG(val, MIPSInst_FD(ir)); 15561da177e4SLinus Torvalds break; 15571da177e4SLinus Torvalds 15581da177e4SLinus Torvalds case sdxc1_op: 15593fccc015SRalf Baechle va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] + 15601da177e4SLinus Torvalds xcp->regs[MIPSInst_FT(ir)]); 15611da177e4SLinus Torvalds 1562b6ee75edSDavid Daney MIPS_FPU_EMU_INC_STATS(stores); 15631da177e4SLinus Torvalds DIFROMREG(val, MIPSInst_FS(ir)); 1564515b029dSDavid Daney if (!access_ok(VERIFY_WRITE, va, sizeof(u64))) { 1565b6ee75edSDavid Daney MIPS_FPU_EMU_INC_STATS(errors); 1566515b029dSDavid Daney *fault_addr = va; 15671da177e4SLinus Torvalds return SIGBUS; 15681da177e4SLinus Torvalds } 1569515b029dSDavid Daney if (__put_user(val, va)) { 1570515b029dSDavid Daney MIPS_FPU_EMU_INC_STATS(errors); 1571515b029dSDavid Daney *fault_addr = va; 1572515b029dSDavid Daney return SIGSEGV; 1573515b029dSDavid Daney } 15741da177e4SLinus Torvalds break; 15751da177e4SLinus Torvalds 15761da177e4SLinus Torvalds case madd_d_op: 15771da177e4SLinus Torvalds handler = fpemu_dp_madd; 15781da177e4SLinus Torvalds goto dcoptop; 15791da177e4SLinus Torvalds case msub_d_op: 15801da177e4SLinus Torvalds handler = fpemu_dp_msub; 15811da177e4SLinus Torvalds goto dcoptop; 15821da177e4SLinus Torvalds case nmadd_d_op: 15831da177e4SLinus Torvalds handler = fpemu_dp_nmadd; 15841da177e4SLinus Torvalds goto dcoptop; 15851da177e4SLinus Torvalds case nmsub_d_op: 15861da177e4SLinus Torvalds handler = fpemu_dp_nmsub; 15871da177e4SLinus Torvalds goto dcoptop; 15881da177e4SLinus Torvalds 15891da177e4SLinus Torvalds dcoptop: 15901da177e4SLinus Torvalds DPFROMREG(fr, MIPSInst_FR(ir)); 15911da177e4SLinus Torvalds DPFROMREG(fs, MIPSInst_FS(ir)); 15921da177e4SLinus Torvalds DPFROMREG(ft, MIPSInst_FT(ir)); 15931da177e4SLinus Torvalds fd = (*handler) (fr, fs, ft); 15941da177e4SLinus Torvalds DPTOREG(fd, MIPSInst_FD(ir)); 15951da177e4SLinus Torvalds goto copcsr; 15961da177e4SLinus Torvalds 15971da177e4SLinus Torvalds default: 15981da177e4SLinus Torvalds return SIGILL; 15991da177e4SLinus Torvalds } 16001da177e4SLinus Torvalds break; 16011da177e4SLinus Torvalds } 16021da177e4SLinus Torvalds 160351061b88SDeng-Cheng Zhu case 0x3: 160451061b88SDeng-Cheng Zhu if (MIPSInst_FUNC(ir) != pfetch_op) 16051da177e4SLinus Torvalds return SIGILL; 160651061b88SDeng-Cheng Zhu 16071da177e4SLinus Torvalds /* ignore prefx operation */ 16081da177e4SLinus Torvalds break; 16091da177e4SLinus Torvalds 16101da177e4SLinus Torvalds default: 16111da177e4SLinus Torvalds return SIGILL; 16121da177e4SLinus Torvalds } 16131da177e4SLinus Torvalds 16141da177e4SLinus Torvalds return 0; 16151da177e4SLinus Torvalds } 16161da177e4SLinus Torvalds 16171da177e4SLinus Torvalds 16181da177e4SLinus Torvalds 16191da177e4SLinus Torvalds /* 16201da177e4SLinus Torvalds * Emulate a single COP1 arithmetic instruction. 16211da177e4SLinus Torvalds */ 1622eae89076SAtsushi Nemoto static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx, 16231da177e4SLinus Torvalds mips_instruction ir) 16241da177e4SLinus Torvalds { 16251da177e4SLinus Torvalds int rfmt; /* resulting format */ 16261da177e4SLinus Torvalds unsigned rcsr = 0; /* resulting csr */ 16273f7cac41SRalf Baechle unsigned int oldrm; 16283f7cac41SRalf Baechle unsigned int cbit; 16291da177e4SLinus Torvalds unsigned cond; 16301da177e4SLinus Torvalds union { 16312209bcb1SRalf Baechle union ieee754dp d; 16322209bcb1SRalf Baechle union ieee754sp s; 16331da177e4SLinus Torvalds int w; 16341da177e4SLinus Torvalds s64 l; 16351da177e4SLinus Torvalds } rv; /* resulting value */ 16363f7cac41SRalf Baechle u64 bits; 16371da177e4SLinus Torvalds 1638b6ee75edSDavid Daney MIPS_FPU_EMU_INC_STATS(cp1ops); 16391da177e4SLinus Torvalds switch (rfmt = (MIPSInst_FFMT(ir) & 0xf)) { 16401da177e4SLinus Torvalds case s_fmt: { /* 0 */ 16411da177e4SLinus Torvalds union { 16422209bcb1SRalf Baechle union ieee754sp(*b) (union ieee754sp, union ieee754sp); 16432209bcb1SRalf Baechle union ieee754sp(*u) (union ieee754sp); 16441da177e4SLinus Torvalds } handler; 16453f7cac41SRalf Baechle union ieee754sp fs, ft; 16461da177e4SLinus Torvalds 16471da177e4SLinus Torvalds switch (MIPSInst_FUNC(ir)) { 16481da177e4SLinus Torvalds /* binary ops */ 16491da177e4SLinus Torvalds case fadd_op: 16501da177e4SLinus Torvalds handler.b = ieee754sp_add; 16511da177e4SLinus Torvalds goto scopbop; 16521da177e4SLinus Torvalds case fsub_op: 16531da177e4SLinus Torvalds handler.b = ieee754sp_sub; 16541da177e4SLinus Torvalds goto scopbop; 16551da177e4SLinus Torvalds case fmul_op: 16561da177e4SLinus Torvalds handler.b = ieee754sp_mul; 16571da177e4SLinus Torvalds goto scopbop; 16581da177e4SLinus Torvalds case fdiv_op: 16591da177e4SLinus Torvalds handler.b = ieee754sp_div; 16601da177e4SLinus Torvalds goto scopbop; 16611da177e4SLinus Torvalds 16621da177e4SLinus Torvalds /* unary ops */ 16631da177e4SLinus Torvalds case fsqrt_op: 16642d83fea7SMaciej W. Rozycki if (!cpu_has_mips_2_3_4_5_r) 166508a07904SRalf Baechle return SIGILL; 166608a07904SRalf Baechle 16671da177e4SLinus Torvalds handler.u = ieee754sp_sqrt; 16681da177e4SLinus Torvalds goto scopuop; 16693f7cac41SRalf Baechle 167008a07904SRalf Baechle /* 167108a07904SRalf Baechle * Note that on some MIPS IV implementations such as the 167208a07904SRalf Baechle * R5000 and R8000 the FSQRT and FRECIP instructions do not 167308a07904SRalf Baechle * achieve full IEEE-754 accuracy - however this emulator does. 167408a07904SRalf Baechle */ 16751da177e4SLinus Torvalds case frsqrt_op: 16762d83fea7SMaciej W. Rozycki if (!cpu_has_mips_4_5_64_r2_r6) 167708a07904SRalf Baechle return SIGILL; 167808a07904SRalf Baechle 16791da177e4SLinus Torvalds handler.u = fpemu_sp_rsqrt; 16801da177e4SLinus Torvalds goto scopuop; 16813f7cac41SRalf Baechle 16821da177e4SLinus Torvalds case frecip_op: 16832d83fea7SMaciej W. Rozycki if (!cpu_has_mips_4_5_64_r2_r6) 168408a07904SRalf Baechle return SIGILL; 168508a07904SRalf Baechle 16861da177e4SLinus Torvalds handler.u = fpemu_sp_recip; 16871da177e4SLinus Torvalds goto scopuop; 168808a07904SRalf Baechle 16891da177e4SLinus Torvalds case fmovc_op: 169008a07904SRalf Baechle if (!cpu_has_mips_4_5_r) 169108a07904SRalf Baechle return SIGILL; 169208a07904SRalf Baechle 16931da177e4SLinus Torvalds cond = fpucondbit[MIPSInst_FT(ir) >> 2]; 16941da177e4SLinus Torvalds if (((ctx->fcr31 & cond) != 0) != 16951da177e4SLinus Torvalds ((MIPSInst_FT(ir) & 1) != 0)) 16961da177e4SLinus Torvalds return 0; 16971da177e4SLinus Torvalds SPFROMREG(rv.s, MIPSInst_FS(ir)); 16981da177e4SLinus Torvalds break; 16993f7cac41SRalf Baechle 17001da177e4SLinus Torvalds case fmovz_op: 170108a07904SRalf Baechle if (!cpu_has_mips_4_5_r) 170208a07904SRalf Baechle return SIGILL; 170308a07904SRalf Baechle 17041da177e4SLinus Torvalds if (xcp->regs[MIPSInst_FT(ir)] != 0) 17051da177e4SLinus Torvalds return 0; 17061da177e4SLinus Torvalds SPFROMREG(rv.s, MIPSInst_FS(ir)); 17071da177e4SLinus Torvalds break; 17083f7cac41SRalf Baechle 17091da177e4SLinus Torvalds case fmovn_op: 171008a07904SRalf Baechle if (!cpu_has_mips_4_5_r) 171108a07904SRalf Baechle return SIGILL; 171208a07904SRalf Baechle 17131da177e4SLinus Torvalds if (xcp->regs[MIPSInst_FT(ir)] == 0) 17141da177e4SLinus Torvalds return 0; 17151da177e4SLinus Torvalds SPFROMREG(rv.s, MIPSInst_FS(ir)); 17161da177e4SLinus Torvalds break; 17173f7cac41SRalf Baechle 17181da177e4SLinus Torvalds case fabs_op: 17191da177e4SLinus Torvalds handler.u = ieee754sp_abs; 17201da177e4SLinus Torvalds goto scopuop; 17213f7cac41SRalf Baechle 17221da177e4SLinus Torvalds case fneg_op: 17231da177e4SLinus Torvalds handler.u = ieee754sp_neg; 17241da177e4SLinus Torvalds goto scopuop; 17253f7cac41SRalf Baechle 17261da177e4SLinus Torvalds case fmov_op: 17271da177e4SLinus Torvalds /* an easy one */ 17281da177e4SLinus Torvalds SPFROMREG(rv.s, MIPSInst_FS(ir)); 17291da177e4SLinus Torvalds goto copcsr; 17301da177e4SLinus Torvalds 17311da177e4SLinus Torvalds /* binary op on handler */ 17321da177e4SLinus Torvalds scopbop: 17331da177e4SLinus Torvalds SPFROMREG(fs, MIPSInst_FS(ir)); 17341da177e4SLinus Torvalds SPFROMREG(ft, MIPSInst_FT(ir)); 17351da177e4SLinus Torvalds 17361da177e4SLinus Torvalds rv.s = (*handler.b) (fs, ft); 17371da177e4SLinus Torvalds goto copcsr; 17381da177e4SLinus Torvalds scopuop: 17391da177e4SLinus Torvalds SPFROMREG(fs, MIPSInst_FS(ir)); 17401da177e4SLinus Torvalds rv.s = (*handler.u) (fs); 17411da177e4SLinus Torvalds goto copcsr; 17421da177e4SLinus Torvalds copcsr: 1743c4103526SDeng-Cheng Zhu if (ieee754_cxtest(IEEE754_INEXACT)) { 1744c4103526SDeng-Cheng Zhu MIPS_FPU_EMU_INC_STATS(ieee754_inexact); 17451da177e4SLinus Torvalds rcsr |= FPU_CSR_INE_X | FPU_CSR_INE_S; 1746c4103526SDeng-Cheng Zhu } 1747c4103526SDeng-Cheng Zhu if (ieee754_cxtest(IEEE754_UNDERFLOW)) { 1748c4103526SDeng-Cheng Zhu MIPS_FPU_EMU_INC_STATS(ieee754_underflow); 17491da177e4SLinus Torvalds rcsr |= FPU_CSR_UDF_X | FPU_CSR_UDF_S; 1750c4103526SDeng-Cheng Zhu } 1751c4103526SDeng-Cheng Zhu if (ieee754_cxtest(IEEE754_OVERFLOW)) { 1752c4103526SDeng-Cheng Zhu MIPS_FPU_EMU_INC_STATS(ieee754_overflow); 17531da177e4SLinus Torvalds rcsr |= FPU_CSR_OVF_X | FPU_CSR_OVF_S; 1754c4103526SDeng-Cheng Zhu } 1755c4103526SDeng-Cheng Zhu if (ieee754_cxtest(IEEE754_ZERO_DIVIDE)) { 1756c4103526SDeng-Cheng Zhu MIPS_FPU_EMU_INC_STATS(ieee754_zerodiv); 17571da177e4SLinus Torvalds rcsr |= FPU_CSR_DIV_X | FPU_CSR_DIV_S; 1758c4103526SDeng-Cheng Zhu } 1759c4103526SDeng-Cheng Zhu if (ieee754_cxtest(IEEE754_INVALID_OPERATION)) { 1760c4103526SDeng-Cheng Zhu MIPS_FPU_EMU_INC_STATS(ieee754_invalidop); 17611da177e4SLinus Torvalds rcsr |= FPU_CSR_INV_X | FPU_CSR_INV_S; 1762c4103526SDeng-Cheng Zhu } 17631da177e4SLinus Torvalds break; 17641da177e4SLinus Torvalds 17651da177e4SLinus Torvalds /* unary conv ops */ 17661da177e4SLinus Torvalds case fcvts_op: 17671da177e4SLinus Torvalds return SIGILL; /* not defined */ 17681da177e4SLinus Torvalds 17693f7cac41SRalf Baechle case fcvtd_op: 17701da177e4SLinus Torvalds SPFROMREG(fs, MIPSInst_FS(ir)); 17711da177e4SLinus Torvalds rv.d = ieee754dp_fsp(fs); 17721da177e4SLinus Torvalds rfmt = d_fmt; 17731da177e4SLinus Torvalds goto copcsr; 17741da177e4SLinus Torvalds 17753f7cac41SRalf Baechle case fcvtw_op: 17761da177e4SLinus Torvalds SPFROMREG(fs, MIPSInst_FS(ir)); 17771da177e4SLinus Torvalds rv.w = ieee754sp_tint(fs); 17781da177e4SLinus Torvalds rfmt = w_fmt; 17791da177e4SLinus Torvalds goto copcsr; 17801da177e4SLinus Torvalds 17811da177e4SLinus Torvalds case fround_op: 17821da177e4SLinus Torvalds case ftrunc_op: 17831da177e4SLinus Torvalds case fceil_op: 17843f7cac41SRalf Baechle case ffloor_op: 17852d83fea7SMaciej W. Rozycki if (!cpu_has_mips_2_3_4_5_r) 178608a07904SRalf Baechle return SIGILL; 178708a07904SRalf Baechle 17883f7cac41SRalf Baechle oldrm = ieee754_csr.rm; 17891da177e4SLinus Torvalds SPFROMREG(fs, MIPSInst_FS(ir)); 17902cfcf8a8SMaciej W. Rozycki ieee754_csr.rm = MIPSInst_FUNC(ir); 17911da177e4SLinus Torvalds rv.w = ieee754sp_tint(fs); 17921da177e4SLinus Torvalds ieee754_csr.rm = oldrm; 17931da177e4SLinus Torvalds rfmt = w_fmt; 17941da177e4SLinus Torvalds goto copcsr; 17951da177e4SLinus Torvalds 17963f7cac41SRalf Baechle case fcvtl_op: 17972d83fea7SMaciej W. Rozycki if (!cpu_has_mips_3_4_5_64_r2_r6) 179808a07904SRalf Baechle return SIGILL; 179908a07904SRalf Baechle 18001da177e4SLinus Torvalds SPFROMREG(fs, MIPSInst_FS(ir)); 18011da177e4SLinus Torvalds rv.l = ieee754sp_tlong(fs); 18021da177e4SLinus Torvalds rfmt = l_fmt; 18031da177e4SLinus Torvalds goto copcsr; 18041da177e4SLinus Torvalds 18051da177e4SLinus Torvalds case froundl_op: 18061da177e4SLinus Torvalds case ftruncl_op: 18071da177e4SLinus Torvalds case fceill_op: 18083f7cac41SRalf Baechle case ffloorl_op: 18092d83fea7SMaciej W. Rozycki if (!cpu_has_mips_3_4_5_64_r2_r6) 181008a07904SRalf Baechle return SIGILL; 181108a07904SRalf Baechle 18123f7cac41SRalf Baechle oldrm = ieee754_csr.rm; 18131da177e4SLinus Torvalds SPFROMREG(fs, MIPSInst_FS(ir)); 18142cfcf8a8SMaciej W. Rozycki ieee754_csr.rm = MIPSInst_FUNC(ir); 18151da177e4SLinus Torvalds rv.l = ieee754sp_tlong(fs); 18161da177e4SLinus Torvalds ieee754_csr.rm = oldrm; 18171da177e4SLinus Torvalds rfmt = l_fmt; 18181da177e4SLinus Torvalds goto copcsr; 18191da177e4SLinus Torvalds 18201da177e4SLinus Torvalds default: 18211da177e4SLinus Torvalds if (MIPSInst_FUNC(ir) >= fcmp_op) { 18221da177e4SLinus Torvalds unsigned cmpop = MIPSInst_FUNC(ir) - fcmp_op; 18232209bcb1SRalf Baechle union ieee754sp fs, ft; 18241da177e4SLinus Torvalds 18251da177e4SLinus Torvalds SPFROMREG(fs, MIPSInst_FS(ir)); 18261da177e4SLinus Torvalds SPFROMREG(ft, MIPSInst_FT(ir)); 18271da177e4SLinus Torvalds rv.w = ieee754sp_cmp(fs, ft, 18281da177e4SLinus Torvalds cmptab[cmpop & 0x7], cmpop & 0x8); 18291da177e4SLinus Torvalds rfmt = -1; 18301da177e4SLinus Torvalds if ((cmpop & 0x8) && ieee754_cxtest 18311da177e4SLinus Torvalds (IEEE754_INVALID_OPERATION)) 18321da177e4SLinus Torvalds rcsr = FPU_CSR_INV_X | FPU_CSR_INV_S; 18331da177e4SLinus Torvalds else 18341da177e4SLinus Torvalds goto copcsr; 18351da177e4SLinus Torvalds 18363f7cac41SRalf Baechle } else 18371da177e4SLinus Torvalds return SIGILL; 18381da177e4SLinus Torvalds break; 18391da177e4SLinus Torvalds } 18401da177e4SLinus Torvalds break; 18411da177e4SLinus Torvalds } 18421da177e4SLinus Torvalds 18431da177e4SLinus Torvalds case d_fmt: { 18443f7cac41SRalf Baechle union ieee754dp fs, ft; 18451da177e4SLinus Torvalds union { 18462209bcb1SRalf Baechle union ieee754dp(*b) (union ieee754dp, union ieee754dp); 18472209bcb1SRalf Baechle union ieee754dp(*u) (union ieee754dp); 18481da177e4SLinus Torvalds } handler; 18491da177e4SLinus Torvalds 18501da177e4SLinus Torvalds switch (MIPSInst_FUNC(ir)) { 18511da177e4SLinus Torvalds /* binary ops */ 18521da177e4SLinus Torvalds case fadd_op: 18531da177e4SLinus Torvalds handler.b = ieee754dp_add; 18541da177e4SLinus Torvalds goto dcopbop; 18551da177e4SLinus Torvalds case fsub_op: 18561da177e4SLinus Torvalds handler.b = ieee754dp_sub; 18571da177e4SLinus Torvalds goto dcopbop; 18581da177e4SLinus Torvalds case fmul_op: 18591da177e4SLinus Torvalds handler.b = ieee754dp_mul; 18601da177e4SLinus Torvalds goto dcopbop; 18611da177e4SLinus Torvalds case fdiv_op: 18621da177e4SLinus Torvalds handler.b = ieee754dp_div; 18631da177e4SLinus Torvalds goto dcopbop; 18641da177e4SLinus Torvalds 18651da177e4SLinus Torvalds /* unary ops */ 18661da177e4SLinus Torvalds case fsqrt_op: 186708a07904SRalf Baechle if (!cpu_has_mips_2_3_4_5_r) 186808a07904SRalf Baechle return SIGILL; 186908a07904SRalf Baechle 18701da177e4SLinus Torvalds handler.u = ieee754dp_sqrt; 18711da177e4SLinus Torvalds goto dcopuop; 187208a07904SRalf Baechle /* 187308a07904SRalf Baechle * Note that on some MIPS IV implementations such as the 187408a07904SRalf Baechle * R5000 and R8000 the FSQRT and FRECIP instructions do not 187508a07904SRalf Baechle * achieve full IEEE-754 accuracy - however this emulator does. 187608a07904SRalf Baechle */ 18771da177e4SLinus Torvalds case frsqrt_op: 18782d83fea7SMaciej W. Rozycki if (!cpu_has_mips_4_5_64_r2_r6) 187908a07904SRalf Baechle return SIGILL; 188008a07904SRalf Baechle 18811da177e4SLinus Torvalds handler.u = fpemu_dp_rsqrt; 18821da177e4SLinus Torvalds goto dcopuop; 18831da177e4SLinus Torvalds case frecip_op: 18842d83fea7SMaciej W. Rozycki if (!cpu_has_mips_4_5_64_r2_r6) 188508a07904SRalf Baechle return SIGILL; 188608a07904SRalf Baechle 18871da177e4SLinus Torvalds handler.u = fpemu_dp_recip; 18881da177e4SLinus Torvalds goto dcopuop; 18891da177e4SLinus Torvalds case fmovc_op: 189008a07904SRalf Baechle if (!cpu_has_mips_4_5_r) 189108a07904SRalf Baechle return SIGILL; 189208a07904SRalf Baechle 18931da177e4SLinus Torvalds cond = fpucondbit[MIPSInst_FT(ir) >> 2]; 18941da177e4SLinus Torvalds if (((ctx->fcr31 & cond) != 0) != 18951da177e4SLinus Torvalds ((MIPSInst_FT(ir) & 1) != 0)) 18961da177e4SLinus Torvalds return 0; 18971da177e4SLinus Torvalds DPFROMREG(rv.d, MIPSInst_FS(ir)); 18981da177e4SLinus Torvalds break; 18991da177e4SLinus Torvalds case fmovz_op: 190008a07904SRalf Baechle if (!cpu_has_mips_4_5_r) 190108a07904SRalf Baechle return SIGILL; 190208a07904SRalf Baechle 19031da177e4SLinus Torvalds if (xcp->regs[MIPSInst_FT(ir)] != 0) 19041da177e4SLinus Torvalds return 0; 19051da177e4SLinus Torvalds DPFROMREG(rv.d, MIPSInst_FS(ir)); 19061da177e4SLinus Torvalds break; 19071da177e4SLinus Torvalds case fmovn_op: 190808a07904SRalf Baechle if (!cpu_has_mips_4_5_r) 190908a07904SRalf Baechle return SIGILL; 191008a07904SRalf Baechle 19111da177e4SLinus Torvalds if (xcp->regs[MIPSInst_FT(ir)] == 0) 19121da177e4SLinus Torvalds return 0; 19131da177e4SLinus Torvalds DPFROMREG(rv.d, MIPSInst_FS(ir)); 19141da177e4SLinus Torvalds break; 19151da177e4SLinus Torvalds case fabs_op: 19161da177e4SLinus Torvalds handler.u = ieee754dp_abs; 19171da177e4SLinus Torvalds goto dcopuop; 19181da177e4SLinus Torvalds 19191da177e4SLinus Torvalds case fneg_op: 19201da177e4SLinus Torvalds handler.u = ieee754dp_neg; 19211da177e4SLinus Torvalds goto dcopuop; 19221da177e4SLinus Torvalds 19231da177e4SLinus Torvalds case fmov_op: 19241da177e4SLinus Torvalds /* an easy one */ 19251da177e4SLinus Torvalds DPFROMREG(rv.d, MIPSInst_FS(ir)); 19261da177e4SLinus Torvalds goto copcsr; 19271da177e4SLinus Torvalds 19281da177e4SLinus Torvalds /* binary op on handler */ 19293f7cac41SRalf Baechle dcopbop: 19301da177e4SLinus Torvalds DPFROMREG(fs, MIPSInst_FS(ir)); 19311da177e4SLinus Torvalds DPFROMREG(ft, MIPSInst_FT(ir)); 19321da177e4SLinus Torvalds 19331da177e4SLinus Torvalds rv.d = (*handler.b) (fs, ft); 19341da177e4SLinus Torvalds goto copcsr; 19353f7cac41SRalf Baechle dcopuop: 19361da177e4SLinus Torvalds DPFROMREG(fs, MIPSInst_FS(ir)); 19371da177e4SLinus Torvalds rv.d = (*handler.u) (fs); 19381da177e4SLinus Torvalds goto copcsr; 19391da177e4SLinus Torvalds 19403f7cac41SRalf Baechle /* 19413f7cac41SRalf Baechle * unary conv ops 19423f7cac41SRalf Baechle */ 19433f7cac41SRalf Baechle case fcvts_op: 19441da177e4SLinus Torvalds DPFROMREG(fs, MIPSInst_FS(ir)); 19451da177e4SLinus Torvalds rv.s = ieee754sp_fdp(fs); 19461da177e4SLinus Torvalds rfmt = s_fmt; 19471da177e4SLinus Torvalds goto copcsr; 19483f7cac41SRalf Baechle 19491da177e4SLinus Torvalds case fcvtd_op: 19501da177e4SLinus Torvalds return SIGILL; /* not defined */ 19511da177e4SLinus Torvalds 19523f7cac41SRalf Baechle case fcvtw_op: 19531da177e4SLinus Torvalds DPFROMREG(fs, MIPSInst_FS(ir)); 19541da177e4SLinus Torvalds rv.w = ieee754dp_tint(fs); /* wrong */ 19551da177e4SLinus Torvalds rfmt = w_fmt; 19561da177e4SLinus Torvalds goto copcsr; 19571da177e4SLinus Torvalds 19581da177e4SLinus Torvalds case fround_op: 19591da177e4SLinus Torvalds case ftrunc_op: 19601da177e4SLinus Torvalds case fceil_op: 19613f7cac41SRalf Baechle case ffloor_op: 196208a07904SRalf Baechle if (!cpu_has_mips_2_3_4_5_r) 196308a07904SRalf Baechle return SIGILL; 196408a07904SRalf Baechle 19653f7cac41SRalf Baechle oldrm = ieee754_csr.rm; 19661da177e4SLinus Torvalds DPFROMREG(fs, MIPSInst_FS(ir)); 19672cfcf8a8SMaciej W. Rozycki ieee754_csr.rm = MIPSInst_FUNC(ir); 19681da177e4SLinus Torvalds rv.w = ieee754dp_tint(fs); 19691da177e4SLinus Torvalds ieee754_csr.rm = oldrm; 19701da177e4SLinus Torvalds rfmt = w_fmt; 19711da177e4SLinus Torvalds goto copcsr; 19721da177e4SLinus Torvalds 19733f7cac41SRalf Baechle case fcvtl_op: 19742d83fea7SMaciej W. Rozycki if (!cpu_has_mips_3_4_5_64_r2_r6) 197508a07904SRalf Baechle return SIGILL; 197608a07904SRalf Baechle 19771da177e4SLinus Torvalds DPFROMREG(fs, MIPSInst_FS(ir)); 19781da177e4SLinus Torvalds rv.l = ieee754dp_tlong(fs); 19791da177e4SLinus Torvalds rfmt = l_fmt; 19801da177e4SLinus Torvalds goto copcsr; 19811da177e4SLinus Torvalds 19821da177e4SLinus Torvalds case froundl_op: 19831da177e4SLinus Torvalds case ftruncl_op: 19841da177e4SLinus Torvalds case fceill_op: 19853f7cac41SRalf Baechle case ffloorl_op: 19862d83fea7SMaciej W. Rozycki if (!cpu_has_mips_3_4_5_64_r2_r6) 198708a07904SRalf Baechle return SIGILL; 198808a07904SRalf Baechle 19893f7cac41SRalf Baechle oldrm = ieee754_csr.rm; 19901da177e4SLinus Torvalds DPFROMREG(fs, MIPSInst_FS(ir)); 19912cfcf8a8SMaciej W. Rozycki ieee754_csr.rm = MIPSInst_FUNC(ir); 19921da177e4SLinus Torvalds rv.l = ieee754dp_tlong(fs); 19931da177e4SLinus Torvalds ieee754_csr.rm = oldrm; 19941da177e4SLinus Torvalds rfmt = l_fmt; 19951da177e4SLinus Torvalds goto copcsr; 19961da177e4SLinus Torvalds 19971da177e4SLinus Torvalds default: 19981da177e4SLinus Torvalds if (MIPSInst_FUNC(ir) >= fcmp_op) { 19991da177e4SLinus Torvalds unsigned cmpop = MIPSInst_FUNC(ir) - fcmp_op; 20002209bcb1SRalf Baechle union ieee754dp fs, ft; 20011da177e4SLinus Torvalds 20021da177e4SLinus Torvalds DPFROMREG(fs, MIPSInst_FS(ir)); 20031da177e4SLinus Torvalds DPFROMREG(ft, MIPSInst_FT(ir)); 20041da177e4SLinus Torvalds rv.w = ieee754dp_cmp(fs, ft, 20051da177e4SLinus Torvalds cmptab[cmpop & 0x7], cmpop & 0x8); 20061da177e4SLinus Torvalds rfmt = -1; 20071da177e4SLinus Torvalds if ((cmpop & 0x8) 20081da177e4SLinus Torvalds && 20091da177e4SLinus Torvalds ieee754_cxtest 20101da177e4SLinus Torvalds (IEEE754_INVALID_OPERATION)) 20111da177e4SLinus Torvalds rcsr = FPU_CSR_INV_X | FPU_CSR_INV_S; 20121da177e4SLinus Torvalds else 20131da177e4SLinus Torvalds goto copcsr; 20141da177e4SLinus Torvalds 20151da177e4SLinus Torvalds } 20161da177e4SLinus Torvalds else { 20171da177e4SLinus Torvalds return SIGILL; 20181da177e4SLinus Torvalds } 20191da177e4SLinus Torvalds break; 20201da177e4SLinus Torvalds } 20211da177e4SLinus Torvalds break; 20221da177e4SLinus Torvalds 20233f7cac41SRalf Baechle case w_fmt: 20241da177e4SLinus Torvalds switch (MIPSInst_FUNC(ir)) { 20251da177e4SLinus Torvalds case fcvts_op: 20261da177e4SLinus Torvalds /* convert word to single precision real */ 20271da177e4SLinus Torvalds SPFROMREG(fs, MIPSInst_FS(ir)); 20281da177e4SLinus Torvalds rv.s = ieee754sp_fint(fs.bits); 20291da177e4SLinus Torvalds rfmt = s_fmt; 20301da177e4SLinus Torvalds goto copcsr; 20311da177e4SLinus Torvalds case fcvtd_op: 20321da177e4SLinus Torvalds /* convert word to double precision real */ 20331da177e4SLinus Torvalds SPFROMREG(fs, MIPSInst_FS(ir)); 20341da177e4SLinus Torvalds rv.d = ieee754dp_fint(fs.bits); 20351da177e4SLinus Torvalds rfmt = d_fmt; 20361da177e4SLinus Torvalds goto copcsr; 20371da177e4SLinus Torvalds default: 20381da177e4SLinus Torvalds return SIGILL; 20391da177e4SLinus Torvalds } 20401da177e4SLinus Torvalds break; 20411da177e4SLinus Torvalds } 20421da177e4SLinus Torvalds 20433f7cac41SRalf Baechle case l_fmt: 204408a07904SRalf Baechle 20452d83fea7SMaciej W. Rozycki if (!cpu_has_mips_3_4_5_64_r2_r6) 204608a07904SRalf Baechle return SIGILL; 204708a07904SRalf Baechle 2048bbd426f5SPaul Burton DIFROMREG(bits, MIPSInst_FS(ir)); 2049bbd426f5SPaul Burton 20501da177e4SLinus Torvalds switch (MIPSInst_FUNC(ir)) { 20511da177e4SLinus Torvalds case fcvts_op: 20521da177e4SLinus Torvalds /* convert long to single precision real */ 2053bbd426f5SPaul Burton rv.s = ieee754sp_flong(bits); 20541da177e4SLinus Torvalds rfmt = s_fmt; 20551da177e4SLinus Torvalds goto copcsr; 20561da177e4SLinus Torvalds case fcvtd_op: 20571da177e4SLinus Torvalds /* convert long to double precision real */ 2058bbd426f5SPaul Burton rv.d = ieee754dp_flong(bits); 20591da177e4SLinus Torvalds rfmt = d_fmt; 20601da177e4SLinus Torvalds goto copcsr; 20611da177e4SLinus Torvalds default: 20621da177e4SLinus Torvalds return SIGILL; 20631da177e4SLinus Torvalds } 20641da177e4SLinus Torvalds break; 20651da177e4SLinus Torvalds 20661da177e4SLinus Torvalds default: 20671da177e4SLinus Torvalds return SIGILL; 20681da177e4SLinus Torvalds } 20691da177e4SLinus Torvalds 20701da177e4SLinus Torvalds /* 20711da177e4SLinus Torvalds * Update the fpu CSR register for this operation. 20721da177e4SLinus Torvalds * If an exception is required, generate a tidy SIGFPE exception, 20731da177e4SLinus Torvalds * without updating the result register. 20741da177e4SLinus Torvalds * Note: cause exception bits do not accumulate, they are rewritten 20751da177e4SLinus Torvalds * for each op; only the flag/sticky bits accumulate. 20761da177e4SLinus Torvalds */ 20771da177e4SLinus Torvalds ctx->fcr31 = (ctx->fcr31 & ~FPU_CSR_ALL_X) | rcsr; 20781da177e4SLinus Torvalds if ((ctx->fcr31 >> 5) & ctx->fcr31 & FPU_CSR_ALL_E) { 20793f7cac41SRalf Baechle /*printk ("SIGFPE: FPU csr = %08x\n",ctx->fcr31); */ 20801da177e4SLinus Torvalds return SIGFPE; 20811da177e4SLinus Torvalds } 20821da177e4SLinus Torvalds 20831da177e4SLinus Torvalds /* 20841da177e4SLinus Torvalds * Now we can safely write the result back to the register file. 20851da177e4SLinus Torvalds */ 20861da177e4SLinus Torvalds switch (rfmt) { 208708a07904SRalf Baechle case -1: 208808a07904SRalf Baechle 208908a07904SRalf Baechle if (cpu_has_mips_4_5_r) 2090c3b9b945SRob Kendrick cbit = fpucondbit[MIPSInst_FD(ir) >> 2]; 20911da177e4SLinus Torvalds else 209208a07904SRalf Baechle cbit = FPU_CSR_COND; 209308a07904SRalf Baechle if (rv.w) 209408a07904SRalf Baechle ctx->fcr31 |= cbit; 209508a07904SRalf Baechle else 209608a07904SRalf Baechle ctx->fcr31 &= ~cbit; 20971da177e4SLinus Torvalds break; 209808a07904SRalf Baechle 20991da177e4SLinus Torvalds case d_fmt: 21001da177e4SLinus Torvalds DPTOREG(rv.d, MIPSInst_FD(ir)); 21011da177e4SLinus Torvalds break; 21021da177e4SLinus Torvalds case s_fmt: 21031da177e4SLinus Torvalds SPTOREG(rv.s, MIPSInst_FD(ir)); 21041da177e4SLinus Torvalds break; 21051da177e4SLinus Torvalds case w_fmt: 21061da177e4SLinus Torvalds SITOREG(rv.w, MIPSInst_FD(ir)); 21071da177e4SLinus Torvalds break; 21081da177e4SLinus Torvalds case l_fmt: 21092d83fea7SMaciej W. Rozycki if (!cpu_has_mips_3_4_5_64_r2_r6) 211008a07904SRalf Baechle return SIGILL; 211108a07904SRalf Baechle 21121da177e4SLinus Torvalds DITOREG(rv.l, MIPSInst_FD(ir)); 21131da177e4SLinus Torvalds break; 21141da177e4SLinus Torvalds default: 21151da177e4SLinus Torvalds return SIGILL; 21161da177e4SLinus Torvalds } 21171da177e4SLinus Torvalds 21181da177e4SLinus Torvalds return 0; 21191da177e4SLinus Torvalds } 21201da177e4SLinus Torvalds 2121e04582b7SAtsushi Nemoto int fpu_emulator_cop1Handler(struct pt_regs *xcp, struct mips_fpu_struct *ctx, 2122515b029dSDavid Daney int has_fpu, void *__user *fault_addr) 21231da177e4SLinus Torvalds { 2124333d1f67SRalf Baechle unsigned long oldepc, prevepc; 2125102cedc3SLeonid Yegoshin struct mm_decoded_insn dec_insn; 2126102cedc3SLeonid Yegoshin u16 instr[4]; 2127102cedc3SLeonid Yegoshin u16 *instr_ptr; 21281da177e4SLinus Torvalds int sig = 0; 21291da177e4SLinus Torvalds 21301da177e4SLinus Torvalds oldepc = xcp->cp0_epc; 21311da177e4SLinus Torvalds do { 21321da177e4SLinus Torvalds prevepc = xcp->cp0_epc; 21331da177e4SLinus Torvalds 2134102cedc3SLeonid Yegoshin if (get_isa16_mode(prevepc) && cpu_has_mmips) { 2135102cedc3SLeonid Yegoshin /* 2136102cedc3SLeonid Yegoshin * Get next 2 microMIPS instructions and convert them 2137102cedc3SLeonid Yegoshin * into 32-bit instructions. 2138102cedc3SLeonid Yegoshin */ 2139102cedc3SLeonid Yegoshin if ((get_user(instr[0], (u16 __user *)msk_isa16_mode(xcp->cp0_epc))) || 2140102cedc3SLeonid Yegoshin (get_user(instr[1], (u16 __user *)msk_isa16_mode(xcp->cp0_epc + 2))) || 2141102cedc3SLeonid Yegoshin (get_user(instr[2], (u16 __user *)msk_isa16_mode(xcp->cp0_epc + 4))) || 2142102cedc3SLeonid Yegoshin (get_user(instr[3], (u16 __user *)msk_isa16_mode(xcp->cp0_epc + 6)))) { 2143b6ee75edSDavid Daney MIPS_FPU_EMU_INC_STATS(errors); 21441da177e4SLinus Torvalds return SIGBUS; 21451da177e4SLinus Torvalds } 2146102cedc3SLeonid Yegoshin instr_ptr = instr; 2147102cedc3SLeonid Yegoshin 2148102cedc3SLeonid Yegoshin /* Get first instruction. */ 2149102cedc3SLeonid Yegoshin if (mm_insn_16bit(*instr_ptr)) { 2150102cedc3SLeonid Yegoshin /* Duplicate the half-word. */ 2151102cedc3SLeonid Yegoshin dec_insn.insn = (*instr_ptr << 16) | 2152102cedc3SLeonid Yegoshin (*instr_ptr); 2153102cedc3SLeonid Yegoshin /* 16-bit instruction. */ 2154102cedc3SLeonid Yegoshin dec_insn.pc_inc = 2; 2155102cedc3SLeonid Yegoshin instr_ptr += 1; 2156102cedc3SLeonid Yegoshin } else { 2157102cedc3SLeonid Yegoshin dec_insn.insn = (*instr_ptr << 16) | 2158102cedc3SLeonid Yegoshin *(instr_ptr+1); 2159102cedc3SLeonid Yegoshin /* 32-bit instruction. */ 2160102cedc3SLeonid Yegoshin dec_insn.pc_inc = 4; 2161102cedc3SLeonid Yegoshin instr_ptr += 2; 2162515b029dSDavid Daney } 2163102cedc3SLeonid Yegoshin /* Get second instruction. */ 2164102cedc3SLeonid Yegoshin if (mm_insn_16bit(*instr_ptr)) { 2165102cedc3SLeonid Yegoshin /* Duplicate the half-word. */ 2166102cedc3SLeonid Yegoshin dec_insn.next_insn = (*instr_ptr << 16) | 2167102cedc3SLeonid Yegoshin (*instr_ptr); 2168102cedc3SLeonid Yegoshin /* 16-bit instruction. */ 2169102cedc3SLeonid Yegoshin dec_insn.next_pc_inc = 2; 2170102cedc3SLeonid Yegoshin } else { 2171102cedc3SLeonid Yegoshin dec_insn.next_insn = (*instr_ptr << 16) | 2172102cedc3SLeonid Yegoshin *(instr_ptr+1); 2173102cedc3SLeonid Yegoshin /* 32-bit instruction. */ 2174102cedc3SLeonid Yegoshin dec_insn.next_pc_inc = 4; 2175102cedc3SLeonid Yegoshin } 2176102cedc3SLeonid Yegoshin dec_insn.micro_mips_mode = 1; 2177102cedc3SLeonid Yegoshin } else { 2178102cedc3SLeonid Yegoshin if ((get_user(dec_insn.insn, 2179102cedc3SLeonid Yegoshin (mips_instruction __user *) xcp->cp0_epc)) || 2180102cedc3SLeonid Yegoshin (get_user(dec_insn.next_insn, 2181102cedc3SLeonid Yegoshin (mips_instruction __user *)(xcp->cp0_epc+4)))) { 2182102cedc3SLeonid Yegoshin MIPS_FPU_EMU_INC_STATS(errors); 2183102cedc3SLeonid Yegoshin return SIGBUS; 2184102cedc3SLeonid Yegoshin } 2185102cedc3SLeonid Yegoshin dec_insn.pc_inc = 4; 2186102cedc3SLeonid Yegoshin dec_insn.next_pc_inc = 4; 2187102cedc3SLeonid Yegoshin dec_insn.micro_mips_mode = 0; 2188102cedc3SLeonid Yegoshin } 2189102cedc3SLeonid Yegoshin 2190102cedc3SLeonid Yegoshin if ((dec_insn.insn == 0) || 2191102cedc3SLeonid Yegoshin ((dec_insn.pc_inc == 2) && 2192102cedc3SLeonid Yegoshin ((dec_insn.insn & 0xffff) == MM_NOP16))) 2193102cedc3SLeonid Yegoshin xcp->cp0_epc += dec_insn.pc_inc; /* Skip NOPs */ 21941da177e4SLinus Torvalds else { 2195cd21dfcfSRalf Baechle /* 21962cfcf8a8SMaciej W. Rozycki * The 'ieee754_csr' is an alias of ctx->fcr31. 21972cfcf8a8SMaciej W. Rozycki * No need to copy ctx->fcr31 to ieee754_csr. 2198cd21dfcfSRalf Baechle */ 2199102cedc3SLeonid Yegoshin sig = cop1Emulate(xcp, ctx, dec_insn, fault_addr); 22001da177e4SLinus Torvalds } 22011da177e4SLinus Torvalds 2202e04582b7SAtsushi Nemoto if (has_fpu) 22031da177e4SLinus Torvalds break; 22041da177e4SLinus Torvalds if (sig) 22051da177e4SLinus Torvalds break; 22061da177e4SLinus Torvalds 22071da177e4SLinus Torvalds cond_resched(); 22081da177e4SLinus Torvalds } while (xcp->cp0_epc > prevepc); 22091da177e4SLinus Torvalds 22101da177e4SLinus Torvalds /* SIGILL indicates a non-fpu instruction */ 22111da177e4SLinus Torvalds if (sig == SIGILL && xcp->cp0_epc != oldepc) 22123f7cac41SRalf Baechle /* but if EPC has advanced, then ignore it */ 22131da177e4SLinus Torvalds sig = 0; 22141da177e4SLinus Torvalds 22151da177e4SLinus Torvalds return sig; 22161da177e4SLinus Torvalds } 2217