11da177e4SLinus Torvalds /* 21da177e4SLinus Torvalds * cp1emu.c: a MIPS coprocessor 1 (fpu) instruction emulator 31da177e4SLinus Torvalds * 41da177e4SLinus Torvalds * MIPS floating point support 51da177e4SLinus Torvalds * Copyright (C) 1994-2000 Algorithmics Ltd. 61da177e4SLinus Torvalds * http://www.algor.co.uk 71da177e4SLinus Torvalds * 81da177e4SLinus Torvalds * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com 91da177e4SLinus Torvalds * Copyright (C) 2000 MIPS Technologies, Inc. 101da177e4SLinus Torvalds * 111da177e4SLinus Torvalds * This program is free software; you can distribute it and/or modify it 121da177e4SLinus Torvalds * under the terms of the GNU General Public License (Version 2) as 131da177e4SLinus Torvalds * published by the Free Software Foundation. 141da177e4SLinus Torvalds * 151da177e4SLinus Torvalds * This program is distributed in the hope it will be useful, but WITHOUT 161da177e4SLinus Torvalds * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 171da177e4SLinus Torvalds * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 181da177e4SLinus Torvalds * for more details. 191da177e4SLinus Torvalds * 201da177e4SLinus Torvalds * You should have received a copy of the GNU General Public License along 211da177e4SLinus Torvalds * with this program; if not, write to the Free Software Foundation, Inc., 221da177e4SLinus Torvalds * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. 231da177e4SLinus Torvalds * 241da177e4SLinus Torvalds * A complete emulator for MIPS coprocessor 1 instructions. This is 251da177e4SLinus Torvalds * required for #float(switch) or #float(trap), where it catches all 261da177e4SLinus Torvalds * COP1 instructions via the "CoProcessor Unusable" exception. 271da177e4SLinus Torvalds * 281da177e4SLinus Torvalds * More surprisingly it is also required for #float(ieee), to help out 291da177e4SLinus Torvalds * the hardware fpu at the boundaries of the IEEE-754 representation 301da177e4SLinus Torvalds * (denormalised values, infinities, underflow, etc). It is made 311da177e4SLinus Torvalds * quite nasty because emulation of some non-COP1 instructions is 321da177e4SLinus Torvalds * required, e.g. in branch delay slots. 331da177e4SLinus Torvalds * 341da177e4SLinus Torvalds * Note if you know that you won't have an fpu, then you'll get much 351da177e4SLinus Torvalds * better performance by compiling with -msoft-float! 361da177e4SLinus Torvalds */ 371da177e4SLinus Torvalds #include <linux/sched.h> 38*b6ee75edSDavid Daney #include <linux/module.h> 3983fd38caSAtsushi Nemoto #include <linux/debugfs.h> 401da177e4SLinus Torvalds 411da177e4SLinus Torvalds #include <asm/inst.h> 421da177e4SLinus Torvalds #include <asm/bootinfo.h> 431da177e4SLinus Torvalds #include <asm/processor.h> 441da177e4SLinus Torvalds #include <asm/ptrace.h> 451da177e4SLinus Torvalds #include <asm/signal.h> 461da177e4SLinus Torvalds #include <asm/mipsregs.h> 471da177e4SLinus Torvalds #include <asm/fpu_emulator.h> 481da177e4SLinus Torvalds #include <asm/uaccess.h> 491da177e4SLinus Torvalds #include <asm/branch.h> 501da177e4SLinus Torvalds 511da177e4SLinus Torvalds #include "ieee754.h" 521da177e4SLinus Torvalds 531da177e4SLinus Torvalds /* Strap kernel emulator for full MIPS IV emulation */ 541da177e4SLinus Torvalds 551da177e4SLinus Torvalds #ifdef __mips 561da177e4SLinus Torvalds #undef __mips 571da177e4SLinus Torvalds #endif 581da177e4SLinus Torvalds #define __mips 4 591da177e4SLinus Torvalds 601da177e4SLinus Torvalds /* Function which emulates a floating point instruction. */ 611da177e4SLinus Torvalds 62eae89076SAtsushi Nemoto static int fpu_emu(struct pt_regs *, struct mips_fpu_struct *, 631da177e4SLinus Torvalds mips_instruction); 641da177e4SLinus Torvalds 651da177e4SLinus Torvalds #if __mips >= 4 && __mips != 32 661da177e4SLinus Torvalds static int fpux_emu(struct pt_regs *, 67eae89076SAtsushi Nemoto struct mips_fpu_struct *, mips_instruction); 681da177e4SLinus Torvalds #endif 691da177e4SLinus Torvalds 70eae89076SAtsushi Nemoto /* Further private data for which no space exists in mips_fpu_struct */ 711da177e4SLinus Torvalds 72*b6ee75edSDavid Daney #ifdef CONFIG_DEBUG_FS 73*b6ee75edSDavid Daney DEFINE_PER_CPU(struct mips_fpu_emulator_stats, fpuemustats); 74*b6ee75edSDavid Daney #endif 751da177e4SLinus Torvalds 761da177e4SLinus Torvalds /* Control registers */ 771da177e4SLinus Torvalds 781da177e4SLinus Torvalds #define FPCREG_RID 0 /* $0 = revision id */ 791da177e4SLinus Torvalds #define FPCREG_CSR 31 /* $31 = csr */ 801da177e4SLinus Torvalds 811da177e4SLinus Torvalds /* Convert Mips rounding mode (0..3) to IEEE library modes. */ 821da177e4SLinus Torvalds static const unsigned char ieee_rm[4] = { 83cd21dfcfSRalf Baechle [FPU_CSR_RN] = IEEE754_RN, 84cd21dfcfSRalf Baechle [FPU_CSR_RZ] = IEEE754_RZ, 85cd21dfcfSRalf Baechle [FPU_CSR_RU] = IEEE754_RU, 86cd21dfcfSRalf Baechle [FPU_CSR_RD] = IEEE754_RD, 87cd21dfcfSRalf Baechle }; 88cd21dfcfSRalf Baechle /* Convert IEEE library modes to Mips rounding mode (0..3). */ 89cd21dfcfSRalf Baechle static const unsigned char mips_rm[4] = { 90cd21dfcfSRalf Baechle [IEEE754_RN] = FPU_CSR_RN, 91cd21dfcfSRalf Baechle [IEEE754_RZ] = FPU_CSR_RZ, 92cd21dfcfSRalf Baechle [IEEE754_RD] = FPU_CSR_RD, 93cd21dfcfSRalf Baechle [IEEE754_RU] = FPU_CSR_RU, 941da177e4SLinus Torvalds }; 951da177e4SLinus Torvalds 961da177e4SLinus Torvalds #if __mips >= 4 971da177e4SLinus Torvalds /* convert condition code register number to csr bit */ 981da177e4SLinus Torvalds static const unsigned int fpucondbit[8] = { 991da177e4SLinus Torvalds FPU_CSR_COND0, 1001da177e4SLinus Torvalds FPU_CSR_COND1, 1011da177e4SLinus Torvalds FPU_CSR_COND2, 1021da177e4SLinus Torvalds FPU_CSR_COND3, 1031da177e4SLinus Torvalds FPU_CSR_COND4, 1041da177e4SLinus Torvalds FPU_CSR_COND5, 1051da177e4SLinus Torvalds FPU_CSR_COND6, 1061da177e4SLinus Torvalds FPU_CSR_COND7 1071da177e4SLinus Torvalds }; 1081da177e4SLinus Torvalds #endif 1091da177e4SLinus Torvalds 1101da177e4SLinus Torvalds 1111da177e4SLinus Torvalds /* 1121da177e4SLinus Torvalds * Redundant with logic already in kernel/branch.c, 1131da177e4SLinus Torvalds * embedded in compute_return_epc. At some point, 1141da177e4SLinus Torvalds * a single subroutine should be used across both 1151da177e4SLinus Torvalds * modules. 1161da177e4SLinus Torvalds */ 1171da177e4SLinus Torvalds static int isBranchInstr(mips_instruction * i) 1181da177e4SLinus Torvalds { 1191da177e4SLinus Torvalds switch (MIPSInst_OPCODE(*i)) { 1201da177e4SLinus Torvalds case spec_op: 1211da177e4SLinus Torvalds switch (MIPSInst_FUNC(*i)) { 1221da177e4SLinus Torvalds case jalr_op: 1231da177e4SLinus Torvalds case jr_op: 1241da177e4SLinus Torvalds return 1; 1251da177e4SLinus Torvalds } 1261da177e4SLinus Torvalds break; 1271da177e4SLinus Torvalds 1281da177e4SLinus Torvalds case bcond_op: 1291da177e4SLinus Torvalds switch (MIPSInst_RT(*i)) { 1301da177e4SLinus Torvalds case bltz_op: 1311da177e4SLinus Torvalds case bgez_op: 1321da177e4SLinus Torvalds case bltzl_op: 1331da177e4SLinus Torvalds case bgezl_op: 1341da177e4SLinus Torvalds case bltzal_op: 1351da177e4SLinus Torvalds case bgezal_op: 1361da177e4SLinus Torvalds case bltzall_op: 1371da177e4SLinus Torvalds case bgezall_op: 1381da177e4SLinus Torvalds return 1; 1391da177e4SLinus Torvalds } 1401da177e4SLinus Torvalds break; 1411da177e4SLinus Torvalds 1421da177e4SLinus Torvalds case j_op: 1431da177e4SLinus Torvalds case jal_op: 1441da177e4SLinus Torvalds case jalx_op: 1451da177e4SLinus Torvalds case beq_op: 1461da177e4SLinus Torvalds case bne_op: 1471da177e4SLinus Torvalds case blez_op: 1481da177e4SLinus Torvalds case bgtz_op: 1491da177e4SLinus Torvalds case beql_op: 1501da177e4SLinus Torvalds case bnel_op: 1511da177e4SLinus Torvalds case blezl_op: 1521da177e4SLinus Torvalds case bgtzl_op: 1531da177e4SLinus Torvalds return 1; 1541da177e4SLinus Torvalds 1551da177e4SLinus Torvalds case cop0_op: 1561da177e4SLinus Torvalds case cop1_op: 1571da177e4SLinus Torvalds case cop2_op: 1581da177e4SLinus Torvalds case cop1x_op: 1591da177e4SLinus Torvalds if (MIPSInst_RS(*i) == bc_op) 1601da177e4SLinus Torvalds return 1; 1611da177e4SLinus Torvalds break; 1621da177e4SLinus Torvalds } 1631da177e4SLinus Torvalds 1641da177e4SLinus Torvalds return 0; 1651da177e4SLinus Torvalds } 1661da177e4SLinus Torvalds 1671da177e4SLinus Torvalds /* 1681da177e4SLinus Torvalds * In the Linux kernel, we support selection of FPR format on the 169da0bac33SDavid Daney * basis of the Status.FR bit. If an FPU is not present, the FR bit 170da0bac33SDavid Daney * is hardwired to zero, which would imply a 32-bit FPU even for 171da0bac33SDavid Daney * 64-bit CPUs. For 64-bit kernels with no FPU we use TIF_32BIT_REGS 172da0bac33SDavid Daney * as a proxy for the FR bit so that a 64-bit FPU is emulated. In any 173da0bac33SDavid Daney * case, for a 32-bit kernel which uses the O32 MIPS ABI, only the 174da0bac33SDavid Daney * even FPRs are used (Status.FR = 0). 1751da177e4SLinus Torvalds */ 176da0bac33SDavid Daney static inline int cop1_64bit(struct pt_regs *xcp) 177da0bac33SDavid Daney { 178da0bac33SDavid Daney if (cpu_has_fpu) 179da0bac33SDavid Daney return xcp->cp0_status & ST0_FR; 180da0bac33SDavid Daney #ifdef CONFIG_64BIT 181da0bac33SDavid Daney return !test_thread_flag(TIF_32BIT_REGS); 1821da177e4SLinus Torvalds #else 183da0bac33SDavid Daney return 0; 1841da177e4SLinus Torvalds #endif 185da0bac33SDavid Daney } 1861da177e4SLinus Torvalds 187da0bac33SDavid Daney #define SIFROMREG(si, x) ((si) = cop1_64bit(xcp) || !(x & 1) ? \ 188da0bac33SDavid Daney (int)ctx->fpr[x] : (int)(ctx->fpr[x & ~1] >> 32)) 189da0bac33SDavid Daney 190da0bac33SDavid Daney #define SITOREG(si, x) (ctx->fpr[x & ~(cop1_64bit(xcp) == 0)] = \ 191da0bac33SDavid Daney cop1_64bit(xcp) || !(x & 1) ? \ 1921da177e4SLinus Torvalds ctx->fpr[x & ~1] >> 32 << 32 | (u32)(si) : \ 1931da177e4SLinus Torvalds ctx->fpr[x & ~1] << 32 >> 32 | (u64)(si) << 32) 1941da177e4SLinus Torvalds 195da0bac33SDavid Daney #define DIFROMREG(di, x) ((di) = ctx->fpr[x & ~(cop1_64bit(xcp) == 0)]) 196da0bac33SDavid Daney #define DITOREG(di, x) (ctx->fpr[x & ~(cop1_64bit(xcp) == 0)] = (di)) 1971da177e4SLinus Torvalds 1981da177e4SLinus Torvalds #define SPFROMREG(sp, x) SIFROMREG((sp).bits, x) 1991da177e4SLinus Torvalds #define SPTOREG(sp, x) SITOREG((sp).bits, x) 2001da177e4SLinus Torvalds #define DPFROMREG(dp, x) DIFROMREG((dp).bits, x) 2011da177e4SLinus Torvalds #define DPTOREG(dp, x) DITOREG((dp).bits, x) 2021da177e4SLinus Torvalds 2031da177e4SLinus Torvalds /* 2041da177e4SLinus Torvalds * Emulate the single floating point instruction pointed at by EPC. 2051da177e4SLinus Torvalds * Two instructions if the instruction is in a branch delay slot. 2061da177e4SLinus Torvalds */ 2071da177e4SLinus Torvalds 208eae89076SAtsushi Nemoto static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_struct *ctx) 2091da177e4SLinus Torvalds { 2101da177e4SLinus Torvalds mips_instruction ir; 211e70dfc10SAtsushi Nemoto unsigned long emulpc, contpc; 2121da177e4SLinus Torvalds unsigned int cond; 2131da177e4SLinus Torvalds 2143fccc015SRalf Baechle if (get_user(ir, (mips_instruction __user *) xcp->cp0_epc)) { 215*b6ee75edSDavid Daney MIPS_FPU_EMU_INC_STATS(errors); 2161da177e4SLinus Torvalds return SIGBUS; 2171da177e4SLinus Torvalds } 2181da177e4SLinus Torvalds 2191da177e4SLinus Torvalds /* XXX NEC Vr54xx bug workaround */ 2201da177e4SLinus Torvalds if ((xcp->cp0_cause & CAUSEF_BD) && !isBranchInstr(&ir)) 2211da177e4SLinus Torvalds xcp->cp0_cause &= ~CAUSEF_BD; 2221da177e4SLinus Torvalds 2231da177e4SLinus Torvalds if (xcp->cp0_cause & CAUSEF_BD) { 2241da177e4SLinus Torvalds /* 2251da177e4SLinus Torvalds * The instruction to be emulated is in a branch delay slot 2261da177e4SLinus Torvalds * which means that we have to emulate the branch instruction 2271da177e4SLinus Torvalds * BEFORE we do the cop1 instruction. 2281da177e4SLinus Torvalds * 2291da177e4SLinus Torvalds * This branch could be a COP1 branch, but in that case we 2301da177e4SLinus Torvalds * would have had a trap for that instruction, and would not 2311da177e4SLinus Torvalds * come through this route. 2321da177e4SLinus Torvalds * 2331da177e4SLinus Torvalds * Linux MIPS branch emulator operates on context, updating the 2341da177e4SLinus Torvalds * cp0_epc. 2351da177e4SLinus Torvalds */ 236e70dfc10SAtsushi Nemoto emulpc = xcp->cp0_epc + 4; /* Snapshot emulation target */ 2371da177e4SLinus Torvalds 2381da177e4SLinus Torvalds if (__compute_return_epc(xcp)) { 2391da177e4SLinus Torvalds #ifdef CP1DBG 2401da177e4SLinus Torvalds printk("failed to emulate branch at %p\n", 241333d1f67SRalf Baechle (void *) (xcp->cp0_epc)); 2421da177e4SLinus Torvalds #endif 2431da177e4SLinus Torvalds return SIGILL; 2441da177e4SLinus Torvalds } 2453fccc015SRalf Baechle if (get_user(ir, (mips_instruction __user *) emulpc)) { 246*b6ee75edSDavid Daney MIPS_FPU_EMU_INC_STATS(errors); 2471da177e4SLinus Torvalds return SIGBUS; 2481da177e4SLinus Torvalds } 2491da177e4SLinus Torvalds /* __compute_return_epc() will have updated cp0_epc */ 250e70dfc10SAtsushi Nemoto contpc = xcp->cp0_epc; 2511da177e4SLinus Torvalds /* In order not to confuse ptrace() et al, tweak context */ 252e70dfc10SAtsushi Nemoto xcp->cp0_epc = emulpc - 4; 253333d1f67SRalf Baechle } else { 254e70dfc10SAtsushi Nemoto emulpc = xcp->cp0_epc; 255e70dfc10SAtsushi Nemoto contpc = xcp->cp0_epc + 4; 2561da177e4SLinus Torvalds } 2571da177e4SLinus Torvalds 2581da177e4SLinus Torvalds emul: 259*b6ee75edSDavid Daney MIPS_FPU_EMU_INC_STATS(emulated); 2601da177e4SLinus Torvalds switch (MIPSInst_OPCODE(ir)) { 2611da177e4SLinus Torvalds case ldc1_op:{ 2623fccc015SRalf Baechle u64 __user *va = (u64 __user *) (xcp->regs[MIPSInst_RS(ir)] + 2631da177e4SLinus Torvalds MIPSInst_SIMM(ir)); 2641da177e4SLinus Torvalds u64 val; 2651da177e4SLinus Torvalds 266*b6ee75edSDavid Daney MIPS_FPU_EMU_INC_STATS(loads); 2671da177e4SLinus Torvalds if (get_user(val, va)) { 268*b6ee75edSDavid Daney MIPS_FPU_EMU_INC_STATS(errors); 2691da177e4SLinus Torvalds return SIGBUS; 2701da177e4SLinus Torvalds } 2711da177e4SLinus Torvalds DITOREG(val, MIPSInst_RT(ir)); 2721da177e4SLinus Torvalds break; 2731da177e4SLinus Torvalds } 2741da177e4SLinus Torvalds 2751da177e4SLinus Torvalds case sdc1_op:{ 2763fccc015SRalf Baechle u64 __user *va = (u64 __user *) (xcp->regs[MIPSInst_RS(ir)] + 2771da177e4SLinus Torvalds MIPSInst_SIMM(ir)); 2781da177e4SLinus Torvalds u64 val; 2791da177e4SLinus Torvalds 280*b6ee75edSDavid Daney MIPS_FPU_EMU_INC_STATS(stores); 2811da177e4SLinus Torvalds DIFROMREG(val, MIPSInst_RT(ir)); 2821da177e4SLinus Torvalds if (put_user(val, va)) { 283*b6ee75edSDavid Daney MIPS_FPU_EMU_INC_STATS(errors); 2841da177e4SLinus Torvalds return SIGBUS; 2851da177e4SLinus Torvalds } 2861da177e4SLinus Torvalds break; 2871da177e4SLinus Torvalds } 2881da177e4SLinus Torvalds 2891da177e4SLinus Torvalds case lwc1_op:{ 2903fccc015SRalf Baechle u32 __user *va = (u32 __user *) (xcp->regs[MIPSInst_RS(ir)] + 2911da177e4SLinus Torvalds MIPSInst_SIMM(ir)); 2921da177e4SLinus Torvalds u32 val; 2931da177e4SLinus Torvalds 294*b6ee75edSDavid Daney MIPS_FPU_EMU_INC_STATS(loads); 2951da177e4SLinus Torvalds if (get_user(val, va)) { 296*b6ee75edSDavid Daney MIPS_FPU_EMU_INC_STATS(errors); 2971da177e4SLinus Torvalds return SIGBUS; 2981da177e4SLinus Torvalds } 2991da177e4SLinus Torvalds SITOREG(val, MIPSInst_RT(ir)); 3001da177e4SLinus Torvalds break; 3011da177e4SLinus Torvalds } 3021da177e4SLinus Torvalds 3031da177e4SLinus Torvalds case swc1_op:{ 3043fccc015SRalf Baechle u32 __user *va = (u32 __user *) (xcp->regs[MIPSInst_RS(ir)] + 3051da177e4SLinus Torvalds MIPSInst_SIMM(ir)); 3061da177e4SLinus Torvalds u32 val; 3071da177e4SLinus Torvalds 308*b6ee75edSDavid Daney MIPS_FPU_EMU_INC_STATS(stores); 3091da177e4SLinus Torvalds SIFROMREG(val, MIPSInst_RT(ir)); 3101da177e4SLinus Torvalds if (put_user(val, va)) { 311*b6ee75edSDavid Daney MIPS_FPU_EMU_INC_STATS(errors); 3121da177e4SLinus Torvalds return SIGBUS; 3131da177e4SLinus Torvalds } 3141da177e4SLinus Torvalds break; 3151da177e4SLinus Torvalds } 3161da177e4SLinus Torvalds 3171da177e4SLinus Torvalds case cop1_op: 3181da177e4SLinus Torvalds switch (MIPSInst_RS(ir)) { 3191da177e4SLinus Torvalds 3204b724efdSRalf Baechle #if defined(__mips64) 3211da177e4SLinus Torvalds case dmfc_op: 3221da177e4SLinus Torvalds /* copregister fs -> gpr[rt] */ 3231da177e4SLinus Torvalds if (MIPSInst_RT(ir) != 0) { 3241da177e4SLinus Torvalds DIFROMREG(xcp->regs[MIPSInst_RT(ir)], 3251da177e4SLinus Torvalds MIPSInst_RD(ir)); 3261da177e4SLinus Torvalds } 3271da177e4SLinus Torvalds break; 3281da177e4SLinus Torvalds 3291da177e4SLinus Torvalds case dmtc_op: 3301da177e4SLinus Torvalds /* copregister fs <- rt */ 3311da177e4SLinus Torvalds DITOREG(xcp->regs[MIPSInst_RT(ir)], MIPSInst_RD(ir)); 3321da177e4SLinus Torvalds break; 3331da177e4SLinus Torvalds #endif 3341da177e4SLinus Torvalds 3351da177e4SLinus Torvalds case mfc_op: 3361da177e4SLinus Torvalds /* copregister rd -> gpr[rt] */ 3371da177e4SLinus Torvalds if (MIPSInst_RT(ir) != 0) { 3381da177e4SLinus Torvalds SIFROMREG(xcp->regs[MIPSInst_RT(ir)], 3391da177e4SLinus Torvalds MIPSInst_RD(ir)); 3401da177e4SLinus Torvalds } 3411da177e4SLinus Torvalds break; 3421da177e4SLinus Torvalds 3431da177e4SLinus Torvalds case mtc_op: 3441da177e4SLinus Torvalds /* copregister rd <- rt */ 3451da177e4SLinus Torvalds SITOREG(xcp->regs[MIPSInst_RT(ir)], MIPSInst_RD(ir)); 3461da177e4SLinus Torvalds break; 3471da177e4SLinus Torvalds 3481da177e4SLinus Torvalds case cfc_op:{ 3491da177e4SLinus Torvalds /* cop control register rd -> gpr[rt] */ 3501da177e4SLinus Torvalds u32 value; 3511da177e4SLinus Torvalds 3521da177e4SLinus Torvalds if (MIPSInst_RD(ir) == FPCREG_CSR) { 3531da177e4SLinus Torvalds value = ctx->fcr31; 354cd21dfcfSRalf Baechle value = (value & ~0x3) | mips_rm[value & 0x3]; 3551da177e4SLinus Torvalds #ifdef CSRTRACE 3561da177e4SLinus Torvalds printk("%p gpr[%d]<-csr=%08x\n", 357333d1f67SRalf Baechle (void *) (xcp->cp0_epc), 3581da177e4SLinus Torvalds MIPSInst_RT(ir), value); 3591da177e4SLinus Torvalds #endif 3601da177e4SLinus Torvalds } 3611da177e4SLinus Torvalds else if (MIPSInst_RD(ir) == FPCREG_RID) 3621da177e4SLinus Torvalds value = 0; 3631da177e4SLinus Torvalds else 3641da177e4SLinus Torvalds value = 0; 3651da177e4SLinus Torvalds if (MIPSInst_RT(ir)) 3661da177e4SLinus Torvalds xcp->regs[MIPSInst_RT(ir)] = value; 3671da177e4SLinus Torvalds break; 3681da177e4SLinus Torvalds } 3691da177e4SLinus Torvalds 3701da177e4SLinus Torvalds case ctc_op:{ 3711da177e4SLinus Torvalds /* copregister rd <- rt */ 3721da177e4SLinus Torvalds u32 value; 3731da177e4SLinus Torvalds 3741da177e4SLinus Torvalds if (MIPSInst_RT(ir) == 0) 3751da177e4SLinus Torvalds value = 0; 3761da177e4SLinus Torvalds else 3771da177e4SLinus Torvalds value = xcp->regs[MIPSInst_RT(ir)]; 3781da177e4SLinus Torvalds 3791da177e4SLinus Torvalds /* we only have one writable control reg 3801da177e4SLinus Torvalds */ 3811da177e4SLinus Torvalds if (MIPSInst_RD(ir) == FPCREG_CSR) { 3821da177e4SLinus Torvalds #ifdef CSRTRACE 3831da177e4SLinus Torvalds printk("%p gpr[%d]->csr=%08x\n", 384333d1f67SRalf Baechle (void *) (xcp->cp0_epc), 3851da177e4SLinus Torvalds MIPSInst_RT(ir), value); 3861da177e4SLinus Torvalds #endif 387cd21dfcfSRalf Baechle value &= (FPU_CSR_FLUSH | FPU_CSR_ALL_E | FPU_CSR_ALL_S | 0x03); 388cd21dfcfSRalf Baechle ctx->fcr31 &= ~(FPU_CSR_FLUSH | FPU_CSR_ALL_E | FPU_CSR_ALL_S | 0x03); 389cd21dfcfSRalf Baechle /* convert to ieee library modes */ 390cd21dfcfSRalf Baechle ctx->fcr31 |= (value & ~0x3) | ieee_rm[value & 0x3]; 3911da177e4SLinus Torvalds } 3921da177e4SLinus Torvalds if ((ctx->fcr31 >> 5) & ctx->fcr31 & FPU_CSR_ALL_E) { 3931da177e4SLinus Torvalds return SIGFPE; 3941da177e4SLinus Torvalds } 3951da177e4SLinus Torvalds break; 3961da177e4SLinus Torvalds } 3971da177e4SLinus Torvalds 3981da177e4SLinus Torvalds case bc_op:{ 3991da177e4SLinus Torvalds int likely = 0; 4001da177e4SLinus Torvalds 4011da177e4SLinus Torvalds if (xcp->cp0_cause & CAUSEF_BD) 4021da177e4SLinus Torvalds return SIGILL; 4031da177e4SLinus Torvalds 4041da177e4SLinus Torvalds #if __mips >= 4 4051da177e4SLinus Torvalds cond = ctx->fcr31 & fpucondbit[MIPSInst_RT(ir) >> 2]; 4061da177e4SLinus Torvalds #else 4071da177e4SLinus Torvalds cond = ctx->fcr31 & FPU_CSR_COND; 4081da177e4SLinus Torvalds #endif 4091da177e4SLinus Torvalds switch (MIPSInst_RT(ir) & 3) { 4101da177e4SLinus Torvalds case bcfl_op: 4111da177e4SLinus Torvalds likely = 1; 4121da177e4SLinus Torvalds case bcf_op: 4131da177e4SLinus Torvalds cond = !cond; 4141da177e4SLinus Torvalds break; 4151da177e4SLinus Torvalds case bctl_op: 4161da177e4SLinus Torvalds likely = 1; 4171da177e4SLinus Torvalds case bct_op: 4181da177e4SLinus Torvalds break; 4191da177e4SLinus Torvalds default: 4201da177e4SLinus Torvalds /* thats an illegal instruction */ 4211da177e4SLinus Torvalds return SIGILL; 4221da177e4SLinus Torvalds } 4231da177e4SLinus Torvalds 4241da177e4SLinus Torvalds xcp->cp0_cause |= CAUSEF_BD; 4251da177e4SLinus Torvalds if (cond) { 4261da177e4SLinus Torvalds /* branch taken: emulate dslot 4271da177e4SLinus Torvalds * instruction 4281da177e4SLinus Torvalds */ 4291da177e4SLinus Torvalds xcp->cp0_epc += 4; 430e70dfc10SAtsushi Nemoto contpc = (xcp->cp0_epc + 4311da177e4SLinus Torvalds (MIPSInst_SIMM(ir) << 2)); 4321da177e4SLinus Torvalds 4333fccc015SRalf Baechle if (get_user(ir, 4343fccc015SRalf Baechle (mips_instruction __user *) xcp->cp0_epc)) { 435*b6ee75edSDavid Daney MIPS_FPU_EMU_INC_STATS(errors); 4361da177e4SLinus Torvalds return SIGBUS; 4371da177e4SLinus Torvalds } 4381da177e4SLinus Torvalds 4391da177e4SLinus Torvalds switch (MIPSInst_OPCODE(ir)) { 4401da177e4SLinus Torvalds case lwc1_op: 4411da177e4SLinus Torvalds case swc1_op: 4424b724efdSRalf Baechle #if (__mips >= 2 || defined(__mips64)) 4431da177e4SLinus Torvalds case ldc1_op: 4441da177e4SLinus Torvalds case sdc1_op: 4451da177e4SLinus Torvalds #endif 4461da177e4SLinus Torvalds case cop1_op: 4471da177e4SLinus Torvalds #if __mips >= 4 && __mips != 32 4481da177e4SLinus Torvalds case cop1x_op: 4491da177e4SLinus Torvalds #endif 4501da177e4SLinus Torvalds /* its one of ours */ 4511da177e4SLinus Torvalds goto emul; 4521da177e4SLinus Torvalds #if __mips >= 4 4531da177e4SLinus Torvalds case spec_op: 4541da177e4SLinus Torvalds if (MIPSInst_FUNC(ir) == movc_op) 4551da177e4SLinus Torvalds goto emul; 4561da177e4SLinus Torvalds break; 4571da177e4SLinus Torvalds #endif 4581da177e4SLinus Torvalds } 4591da177e4SLinus Torvalds 4601da177e4SLinus Torvalds /* 4611da177e4SLinus Torvalds * Single step the non-cp1 4621da177e4SLinus Torvalds * instruction in the dslot 4631da177e4SLinus Torvalds */ 464e70dfc10SAtsushi Nemoto return mips_dsemul(xcp, ir, contpc); 4651da177e4SLinus Torvalds } 4661da177e4SLinus Torvalds else { 4671da177e4SLinus Torvalds /* branch not taken */ 4681da177e4SLinus Torvalds if (likely) { 4691da177e4SLinus Torvalds /* 4701da177e4SLinus Torvalds * branch likely nullifies 4711da177e4SLinus Torvalds * dslot if not taken 4721da177e4SLinus Torvalds */ 4731da177e4SLinus Torvalds xcp->cp0_epc += 4; 4741da177e4SLinus Torvalds contpc += 4; 4751da177e4SLinus Torvalds /* 4761da177e4SLinus Torvalds * else continue & execute 4771da177e4SLinus Torvalds * dslot as normal insn 4781da177e4SLinus Torvalds */ 4791da177e4SLinus Torvalds } 4801da177e4SLinus Torvalds } 4811da177e4SLinus Torvalds break; 4821da177e4SLinus Torvalds } 4831da177e4SLinus Torvalds 4841da177e4SLinus Torvalds default: 4851da177e4SLinus Torvalds if (!(MIPSInst_RS(ir) & 0x10)) 4861da177e4SLinus Torvalds return SIGILL; 4871da177e4SLinus Torvalds { 4881da177e4SLinus Torvalds int sig; 4891da177e4SLinus Torvalds 4901da177e4SLinus Torvalds /* a real fpu computation instruction */ 4911da177e4SLinus Torvalds if ((sig = fpu_emu(xcp, ctx, ir))) 4921da177e4SLinus Torvalds return sig; 4931da177e4SLinus Torvalds } 4941da177e4SLinus Torvalds } 4951da177e4SLinus Torvalds break; 4961da177e4SLinus Torvalds 4971da177e4SLinus Torvalds #if __mips >= 4 && __mips != 32 4981da177e4SLinus Torvalds case cop1x_op:{ 4991da177e4SLinus Torvalds int sig; 5001da177e4SLinus Torvalds 5011da177e4SLinus Torvalds if ((sig = fpux_emu(xcp, ctx, ir))) 5021da177e4SLinus Torvalds return sig; 5031da177e4SLinus Torvalds break; 5041da177e4SLinus Torvalds } 5051da177e4SLinus Torvalds #endif 5061da177e4SLinus Torvalds 5071da177e4SLinus Torvalds #if __mips >= 4 5081da177e4SLinus Torvalds case spec_op: 5091da177e4SLinus Torvalds if (MIPSInst_FUNC(ir) != movc_op) 5101da177e4SLinus Torvalds return SIGILL; 5111da177e4SLinus Torvalds cond = fpucondbit[MIPSInst_RT(ir) >> 2]; 5121da177e4SLinus Torvalds if (((ctx->fcr31 & cond) != 0) == ((MIPSInst_RT(ir) & 1) != 0)) 5131da177e4SLinus Torvalds xcp->regs[MIPSInst_RD(ir)] = 5141da177e4SLinus Torvalds xcp->regs[MIPSInst_RS(ir)]; 5151da177e4SLinus Torvalds break; 5161da177e4SLinus Torvalds #endif 5171da177e4SLinus Torvalds 5181da177e4SLinus Torvalds default: 5191da177e4SLinus Torvalds return SIGILL; 5201da177e4SLinus Torvalds } 5211da177e4SLinus Torvalds 5221da177e4SLinus Torvalds /* we did it !! */ 523e70dfc10SAtsushi Nemoto xcp->cp0_epc = contpc; 5241da177e4SLinus Torvalds xcp->cp0_cause &= ~CAUSEF_BD; 525333d1f67SRalf Baechle 5261da177e4SLinus Torvalds return 0; 5271da177e4SLinus Torvalds } 5281da177e4SLinus Torvalds 5291da177e4SLinus Torvalds /* 5301da177e4SLinus Torvalds * Conversion table from MIPS compare ops 48-63 5311da177e4SLinus Torvalds * cond = ieee754dp_cmp(x,y,IEEE754_UN,sig); 5321da177e4SLinus Torvalds */ 5331da177e4SLinus Torvalds static const unsigned char cmptab[8] = { 5341da177e4SLinus Torvalds 0, /* cmp_0 (sig) cmp_sf */ 5351da177e4SLinus Torvalds IEEE754_CUN, /* cmp_un (sig) cmp_ngle */ 5361da177e4SLinus Torvalds IEEE754_CEQ, /* cmp_eq (sig) cmp_seq */ 5371da177e4SLinus Torvalds IEEE754_CEQ | IEEE754_CUN, /* cmp_ueq (sig) cmp_ngl */ 5381da177e4SLinus Torvalds IEEE754_CLT, /* cmp_olt (sig) cmp_lt */ 5391da177e4SLinus Torvalds IEEE754_CLT | IEEE754_CUN, /* cmp_ult (sig) cmp_nge */ 5401da177e4SLinus Torvalds IEEE754_CLT | IEEE754_CEQ, /* cmp_ole (sig) cmp_le */ 5411da177e4SLinus Torvalds IEEE754_CLT | IEEE754_CEQ | IEEE754_CUN, /* cmp_ule (sig) cmp_ngt */ 5421da177e4SLinus Torvalds }; 5431da177e4SLinus Torvalds 5441da177e4SLinus Torvalds 5451da177e4SLinus Torvalds #if __mips >= 4 && __mips != 32 5461da177e4SLinus Torvalds 5471da177e4SLinus Torvalds /* 5481da177e4SLinus Torvalds * Additional MIPS4 instructions 5491da177e4SLinus Torvalds */ 5501da177e4SLinus Torvalds 5511da177e4SLinus Torvalds #define DEF3OP(name, p, f1, f2, f3) \ 5521da177e4SLinus Torvalds static ieee754##p fpemu_##p##_##name(ieee754##p r, ieee754##p s, \ 5531da177e4SLinus Torvalds ieee754##p t) \ 5541da177e4SLinus Torvalds { \ 555cd21dfcfSRalf Baechle struct _ieee754_csr ieee754_csr_save; \ 5561da177e4SLinus Torvalds s = f1(s, t); \ 5571da177e4SLinus Torvalds ieee754_csr_save = ieee754_csr; \ 5581da177e4SLinus Torvalds s = f2(s, r); \ 5591da177e4SLinus Torvalds ieee754_csr_save.cx |= ieee754_csr.cx; \ 5601da177e4SLinus Torvalds ieee754_csr_save.sx |= ieee754_csr.sx; \ 5611da177e4SLinus Torvalds s = f3(s); \ 5621da177e4SLinus Torvalds ieee754_csr.cx |= ieee754_csr_save.cx; \ 5631da177e4SLinus Torvalds ieee754_csr.sx |= ieee754_csr_save.sx; \ 5641da177e4SLinus Torvalds return s; \ 5651da177e4SLinus Torvalds } 5661da177e4SLinus Torvalds 5671da177e4SLinus Torvalds static ieee754dp fpemu_dp_recip(ieee754dp d) 5681da177e4SLinus Torvalds { 5691da177e4SLinus Torvalds return ieee754dp_div(ieee754dp_one(0), d); 5701da177e4SLinus Torvalds } 5711da177e4SLinus Torvalds 5721da177e4SLinus Torvalds static ieee754dp fpemu_dp_rsqrt(ieee754dp d) 5731da177e4SLinus Torvalds { 5741da177e4SLinus Torvalds return ieee754dp_div(ieee754dp_one(0), ieee754dp_sqrt(d)); 5751da177e4SLinus Torvalds } 5761da177e4SLinus Torvalds 5771da177e4SLinus Torvalds static ieee754sp fpemu_sp_recip(ieee754sp s) 5781da177e4SLinus Torvalds { 5791da177e4SLinus Torvalds return ieee754sp_div(ieee754sp_one(0), s); 5801da177e4SLinus Torvalds } 5811da177e4SLinus Torvalds 5821da177e4SLinus Torvalds static ieee754sp fpemu_sp_rsqrt(ieee754sp s) 5831da177e4SLinus Torvalds { 5841da177e4SLinus Torvalds return ieee754sp_div(ieee754sp_one(0), ieee754sp_sqrt(s)); 5851da177e4SLinus Torvalds } 5861da177e4SLinus Torvalds 5871da177e4SLinus Torvalds DEF3OP(madd, sp, ieee754sp_mul, ieee754sp_add, ); 5881da177e4SLinus Torvalds DEF3OP(msub, sp, ieee754sp_mul, ieee754sp_sub, ); 5891da177e4SLinus Torvalds DEF3OP(nmadd, sp, ieee754sp_mul, ieee754sp_add, ieee754sp_neg); 5901da177e4SLinus Torvalds DEF3OP(nmsub, sp, ieee754sp_mul, ieee754sp_sub, ieee754sp_neg); 5911da177e4SLinus Torvalds DEF3OP(madd, dp, ieee754dp_mul, ieee754dp_add, ); 5921da177e4SLinus Torvalds DEF3OP(msub, dp, ieee754dp_mul, ieee754dp_sub, ); 5931da177e4SLinus Torvalds DEF3OP(nmadd, dp, ieee754dp_mul, ieee754dp_add, ieee754dp_neg); 5941da177e4SLinus Torvalds DEF3OP(nmsub, dp, ieee754dp_mul, ieee754dp_sub, ieee754dp_neg); 5951da177e4SLinus Torvalds 596eae89076SAtsushi Nemoto static int fpux_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx, 5971da177e4SLinus Torvalds mips_instruction ir) 5981da177e4SLinus Torvalds { 5991da177e4SLinus Torvalds unsigned rcsr = 0; /* resulting csr */ 6001da177e4SLinus Torvalds 601*b6ee75edSDavid Daney MIPS_FPU_EMU_INC_STATS(cp1xops); 6021da177e4SLinus Torvalds 6031da177e4SLinus Torvalds switch (MIPSInst_FMA_FFMT(ir)) { 6041da177e4SLinus Torvalds case s_fmt:{ /* 0 */ 6051da177e4SLinus Torvalds 6061da177e4SLinus Torvalds ieee754sp(*handler) (ieee754sp, ieee754sp, ieee754sp); 6071da177e4SLinus Torvalds ieee754sp fd, fr, fs, ft; 6083fccc015SRalf Baechle u32 __user *va; 6091da177e4SLinus Torvalds u32 val; 6101da177e4SLinus Torvalds 6111da177e4SLinus Torvalds switch (MIPSInst_FUNC(ir)) { 6121da177e4SLinus Torvalds case lwxc1_op: 6133fccc015SRalf Baechle va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] + 6141da177e4SLinus Torvalds xcp->regs[MIPSInst_FT(ir)]); 6151da177e4SLinus Torvalds 616*b6ee75edSDavid Daney MIPS_FPU_EMU_INC_STATS(loads); 6171da177e4SLinus Torvalds if (get_user(val, va)) { 618*b6ee75edSDavid Daney MIPS_FPU_EMU_INC_STATS(errors); 6191da177e4SLinus Torvalds return SIGBUS; 6201da177e4SLinus Torvalds } 6211da177e4SLinus Torvalds SITOREG(val, MIPSInst_FD(ir)); 6221da177e4SLinus Torvalds break; 6231da177e4SLinus Torvalds 6241da177e4SLinus Torvalds case swxc1_op: 6253fccc015SRalf Baechle va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] + 6261da177e4SLinus Torvalds xcp->regs[MIPSInst_FT(ir)]); 6271da177e4SLinus Torvalds 628*b6ee75edSDavid Daney MIPS_FPU_EMU_INC_STATS(stores); 6291da177e4SLinus Torvalds 6301da177e4SLinus Torvalds SIFROMREG(val, MIPSInst_FS(ir)); 6311da177e4SLinus Torvalds if (put_user(val, va)) { 632*b6ee75edSDavid Daney MIPS_FPU_EMU_INC_STATS(errors); 6331da177e4SLinus Torvalds return SIGBUS; 6341da177e4SLinus Torvalds } 6351da177e4SLinus Torvalds break; 6361da177e4SLinus Torvalds 6371da177e4SLinus Torvalds case madd_s_op: 6381da177e4SLinus Torvalds handler = fpemu_sp_madd; 6391da177e4SLinus Torvalds goto scoptop; 6401da177e4SLinus Torvalds case msub_s_op: 6411da177e4SLinus Torvalds handler = fpemu_sp_msub; 6421da177e4SLinus Torvalds goto scoptop; 6431da177e4SLinus Torvalds case nmadd_s_op: 6441da177e4SLinus Torvalds handler = fpemu_sp_nmadd; 6451da177e4SLinus Torvalds goto scoptop; 6461da177e4SLinus Torvalds case nmsub_s_op: 6471da177e4SLinus Torvalds handler = fpemu_sp_nmsub; 6481da177e4SLinus Torvalds goto scoptop; 6491da177e4SLinus Torvalds 6501da177e4SLinus Torvalds scoptop: 6511da177e4SLinus Torvalds SPFROMREG(fr, MIPSInst_FR(ir)); 6521da177e4SLinus Torvalds SPFROMREG(fs, MIPSInst_FS(ir)); 6531da177e4SLinus Torvalds SPFROMREG(ft, MIPSInst_FT(ir)); 6541da177e4SLinus Torvalds fd = (*handler) (fr, fs, ft); 6551da177e4SLinus Torvalds SPTOREG(fd, MIPSInst_FD(ir)); 6561da177e4SLinus Torvalds 6571da177e4SLinus Torvalds copcsr: 6581da177e4SLinus Torvalds if (ieee754_cxtest(IEEE754_INEXACT)) 6591da177e4SLinus Torvalds rcsr |= FPU_CSR_INE_X | FPU_CSR_INE_S; 6601da177e4SLinus Torvalds if (ieee754_cxtest(IEEE754_UNDERFLOW)) 6611da177e4SLinus Torvalds rcsr |= FPU_CSR_UDF_X | FPU_CSR_UDF_S; 6621da177e4SLinus Torvalds if (ieee754_cxtest(IEEE754_OVERFLOW)) 6631da177e4SLinus Torvalds rcsr |= FPU_CSR_OVF_X | FPU_CSR_OVF_S; 6641da177e4SLinus Torvalds if (ieee754_cxtest(IEEE754_INVALID_OPERATION)) 6651da177e4SLinus Torvalds rcsr |= FPU_CSR_INV_X | FPU_CSR_INV_S; 6661da177e4SLinus Torvalds 6671da177e4SLinus Torvalds ctx->fcr31 = (ctx->fcr31 & ~FPU_CSR_ALL_X) | rcsr; 6681da177e4SLinus Torvalds if ((ctx->fcr31 >> 5) & ctx->fcr31 & FPU_CSR_ALL_E) { 6691da177e4SLinus Torvalds /*printk ("SIGFPE: fpu csr = %08x\n", 6701da177e4SLinus Torvalds ctx->fcr31); */ 6711da177e4SLinus Torvalds return SIGFPE; 6721da177e4SLinus Torvalds } 6731da177e4SLinus Torvalds 6741da177e4SLinus Torvalds break; 6751da177e4SLinus Torvalds 6761da177e4SLinus Torvalds default: 6771da177e4SLinus Torvalds return SIGILL; 6781da177e4SLinus Torvalds } 6791da177e4SLinus Torvalds break; 6801da177e4SLinus Torvalds } 6811da177e4SLinus Torvalds 6821da177e4SLinus Torvalds case d_fmt:{ /* 1 */ 6831da177e4SLinus Torvalds ieee754dp(*handler) (ieee754dp, ieee754dp, ieee754dp); 6841da177e4SLinus Torvalds ieee754dp fd, fr, fs, ft; 6853fccc015SRalf Baechle u64 __user *va; 6861da177e4SLinus Torvalds u64 val; 6871da177e4SLinus Torvalds 6881da177e4SLinus Torvalds switch (MIPSInst_FUNC(ir)) { 6891da177e4SLinus Torvalds case ldxc1_op: 6903fccc015SRalf Baechle va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] + 6911da177e4SLinus Torvalds xcp->regs[MIPSInst_FT(ir)]); 6921da177e4SLinus Torvalds 693*b6ee75edSDavid Daney MIPS_FPU_EMU_INC_STATS(loads); 6941da177e4SLinus Torvalds if (get_user(val, va)) { 695*b6ee75edSDavid Daney MIPS_FPU_EMU_INC_STATS(errors); 6961da177e4SLinus Torvalds return SIGBUS; 6971da177e4SLinus Torvalds } 6981da177e4SLinus Torvalds DITOREG(val, MIPSInst_FD(ir)); 6991da177e4SLinus Torvalds break; 7001da177e4SLinus Torvalds 7011da177e4SLinus Torvalds case sdxc1_op: 7023fccc015SRalf Baechle va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] + 7031da177e4SLinus Torvalds xcp->regs[MIPSInst_FT(ir)]); 7041da177e4SLinus Torvalds 705*b6ee75edSDavid Daney MIPS_FPU_EMU_INC_STATS(stores); 7061da177e4SLinus Torvalds DIFROMREG(val, MIPSInst_FS(ir)); 7071da177e4SLinus Torvalds if (put_user(val, va)) { 708*b6ee75edSDavid Daney MIPS_FPU_EMU_INC_STATS(errors); 7091da177e4SLinus Torvalds return SIGBUS; 7101da177e4SLinus Torvalds } 7111da177e4SLinus Torvalds break; 7121da177e4SLinus Torvalds 7131da177e4SLinus Torvalds case madd_d_op: 7141da177e4SLinus Torvalds handler = fpemu_dp_madd; 7151da177e4SLinus Torvalds goto dcoptop; 7161da177e4SLinus Torvalds case msub_d_op: 7171da177e4SLinus Torvalds handler = fpemu_dp_msub; 7181da177e4SLinus Torvalds goto dcoptop; 7191da177e4SLinus Torvalds case nmadd_d_op: 7201da177e4SLinus Torvalds handler = fpemu_dp_nmadd; 7211da177e4SLinus Torvalds goto dcoptop; 7221da177e4SLinus Torvalds case nmsub_d_op: 7231da177e4SLinus Torvalds handler = fpemu_dp_nmsub; 7241da177e4SLinus Torvalds goto dcoptop; 7251da177e4SLinus Torvalds 7261da177e4SLinus Torvalds dcoptop: 7271da177e4SLinus Torvalds DPFROMREG(fr, MIPSInst_FR(ir)); 7281da177e4SLinus Torvalds DPFROMREG(fs, MIPSInst_FS(ir)); 7291da177e4SLinus Torvalds DPFROMREG(ft, MIPSInst_FT(ir)); 7301da177e4SLinus Torvalds fd = (*handler) (fr, fs, ft); 7311da177e4SLinus Torvalds DPTOREG(fd, MIPSInst_FD(ir)); 7321da177e4SLinus Torvalds goto copcsr; 7331da177e4SLinus Torvalds 7341da177e4SLinus Torvalds default: 7351da177e4SLinus Torvalds return SIGILL; 7361da177e4SLinus Torvalds } 7371da177e4SLinus Torvalds break; 7381da177e4SLinus Torvalds } 7391da177e4SLinus Torvalds 7401da177e4SLinus Torvalds case 0x7: /* 7 */ 7411da177e4SLinus Torvalds if (MIPSInst_FUNC(ir) != pfetch_op) { 7421da177e4SLinus Torvalds return SIGILL; 7431da177e4SLinus Torvalds } 7441da177e4SLinus Torvalds /* ignore prefx operation */ 7451da177e4SLinus Torvalds break; 7461da177e4SLinus Torvalds 7471da177e4SLinus Torvalds default: 7481da177e4SLinus Torvalds return SIGILL; 7491da177e4SLinus Torvalds } 7501da177e4SLinus Torvalds 7511da177e4SLinus Torvalds return 0; 7521da177e4SLinus Torvalds } 7531da177e4SLinus Torvalds #endif 7541da177e4SLinus Torvalds 7551da177e4SLinus Torvalds 7561da177e4SLinus Torvalds 7571da177e4SLinus Torvalds /* 7581da177e4SLinus Torvalds * Emulate a single COP1 arithmetic instruction. 7591da177e4SLinus Torvalds */ 760eae89076SAtsushi Nemoto static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx, 7611da177e4SLinus Torvalds mips_instruction ir) 7621da177e4SLinus Torvalds { 7631da177e4SLinus Torvalds int rfmt; /* resulting format */ 7641da177e4SLinus Torvalds unsigned rcsr = 0; /* resulting csr */ 7651da177e4SLinus Torvalds unsigned cond; 7661da177e4SLinus Torvalds union { 7671da177e4SLinus Torvalds ieee754dp d; 7681da177e4SLinus Torvalds ieee754sp s; 7691da177e4SLinus Torvalds int w; 770766160c2SYoichi Yuasa #ifdef __mips64 7711da177e4SLinus Torvalds s64 l; 7721da177e4SLinus Torvalds #endif 7731da177e4SLinus Torvalds } rv; /* resulting value */ 7741da177e4SLinus Torvalds 775*b6ee75edSDavid Daney MIPS_FPU_EMU_INC_STATS(cp1ops); 7761da177e4SLinus Torvalds switch (rfmt = (MIPSInst_FFMT(ir) & 0xf)) { 7771da177e4SLinus Torvalds case s_fmt:{ /* 0 */ 7781da177e4SLinus Torvalds union { 7791da177e4SLinus Torvalds ieee754sp(*b) (ieee754sp, ieee754sp); 7801da177e4SLinus Torvalds ieee754sp(*u) (ieee754sp); 7811da177e4SLinus Torvalds } handler; 7821da177e4SLinus Torvalds 7831da177e4SLinus Torvalds switch (MIPSInst_FUNC(ir)) { 7841da177e4SLinus Torvalds /* binary ops */ 7851da177e4SLinus Torvalds case fadd_op: 7861da177e4SLinus Torvalds handler.b = ieee754sp_add; 7871da177e4SLinus Torvalds goto scopbop; 7881da177e4SLinus Torvalds case fsub_op: 7891da177e4SLinus Torvalds handler.b = ieee754sp_sub; 7901da177e4SLinus Torvalds goto scopbop; 7911da177e4SLinus Torvalds case fmul_op: 7921da177e4SLinus Torvalds handler.b = ieee754sp_mul; 7931da177e4SLinus Torvalds goto scopbop; 7941da177e4SLinus Torvalds case fdiv_op: 7951da177e4SLinus Torvalds handler.b = ieee754sp_div; 7961da177e4SLinus Torvalds goto scopbop; 7971da177e4SLinus Torvalds 7981da177e4SLinus Torvalds /* unary ops */ 799587cb98fSRalf Baechle #if __mips >= 2 || defined(__mips64) 8001da177e4SLinus Torvalds case fsqrt_op: 8011da177e4SLinus Torvalds handler.u = ieee754sp_sqrt; 8021da177e4SLinus Torvalds goto scopuop; 8031da177e4SLinus Torvalds #endif 8041da177e4SLinus Torvalds #if __mips >= 4 && __mips != 32 8051da177e4SLinus Torvalds case frsqrt_op: 8061da177e4SLinus Torvalds handler.u = fpemu_sp_rsqrt; 8071da177e4SLinus Torvalds goto scopuop; 8081da177e4SLinus Torvalds case frecip_op: 8091da177e4SLinus Torvalds handler.u = fpemu_sp_recip; 8101da177e4SLinus Torvalds goto scopuop; 8111da177e4SLinus Torvalds #endif 8121da177e4SLinus Torvalds #if __mips >= 4 8131da177e4SLinus Torvalds case fmovc_op: 8141da177e4SLinus Torvalds cond = fpucondbit[MIPSInst_FT(ir) >> 2]; 8151da177e4SLinus Torvalds if (((ctx->fcr31 & cond) != 0) != 8161da177e4SLinus Torvalds ((MIPSInst_FT(ir) & 1) != 0)) 8171da177e4SLinus Torvalds return 0; 8181da177e4SLinus Torvalds SPFROMREG(rv.s, MIPSInst_FS(ir)); 8191da177e4SLinus Torvalds break; 8201da177e4SLinus Torvalds case fmovz_op: 8211da177e4SLinus Torvalds if (xcp->regs[MIPSInst_FT(ir)] != 0) 8221da177e4SLinus Torvalds return 0; 8231da177e4SLinus Torvalds SPFROMREG(rv.s, MIPSInst_FS(ir)); 8241da177e4SLinus Torvalds break; 8251da177e4SLinus Torvalds case fmovn_op: 8261da177e4SLinus Torvalds if (xcp->regs[MIPSInst_FT(ir)] == 0) 8271da177e4SLinus Torvalds return 0; 8281da177e4SLinus Torvalds SPFROMREG(rv.s, MIPSInst_FS(ir)); 8291da177e4SLinus Torvalds break; 8301da177e4SLinus Torvalds #endif 8311da177e4SLinus Torvalds case fabs_op: 8321da177e4SLinus Torvalds handler.u = ieee754sp_abs; 8331da177e4SLinus Torvalds goto scopuop; 8341da177e4SLinus Torvalds case fneg_op: 8351da177e4SLinus Torvalds handler.u = ieee754sp_neg; 8361da177e4SLinus Torvalds goto scopuop; 8371da177e4SLinus Torvalds case fmov_op: 8381da177e4SLinus Torvalds /* an easy one */ 8391da177e4SLinus Torvalds SPFROMREG(rv.s, MIPSInst_FS(ir)); 8401da177e4SLinus Torvalds goto copcsr; 8411da177e4SLinus Torvalds 8421da177e4SLinus Torvalds /* binary op on handler */ 8431da177e4SLinus Torvalds scopbop: 8441da177e4SLinus Torvalds { 8451da177e4SLinus Torvalds ieee754sp fs, ft; 8461da177e4SLinus Torvalds 8471da177e4SLinus Torvalds SPFROMREG(fs, MIPSInst_FS(ir)); 8481da177e4SLinus Torvalds SPFROMREG(ft, MIPSInst_FT(ir)); 8491da177e4SLinus Torvalds 8501da177e4SLinus Torvalds rv.s = (*handler.b) (fs, ft); 8511da177e4SLinus Torvalds goto copcsr; 8521da177e4SLinus Torvalds } 8531da177e4SLinus Torvalds scopuop: 8541da177e4SLinus Torvalds { 8551da177e4SLinus Torvalds ieee754sp fs; 8561da177e4SLinus Torvalds 8571da177e4SLinus Torvalds SPFROMREG(fs, MIPSInst_FS(ir)); 8581da177e4SLinus Torvalds rv.s = (*handler.u) (fs); 8591da177e4SLinus Torvalds goto copcsr; 8601da177e4SLinus Torvalds } 8611da177e4SLinus Torvalds copcsr: 8621da177e4SLinus Torvalds if (ieee754_cxtest(IEEE754_INEXACT)) 8631da177e4SLinus Torvalds rcsr |= FPU_CSR_INE_X | FPU_CSR_INE_S; 8641da177e4SLinus Torvalds if (ieee754_cxtest(IEEE754_UNDERFLOW)) 8651da177e4SLinus Torvalds rcsr |= FPU_CSR_UDF_X | FPU_CSR_UDF_S; 8661da177e4SLinus Torvalds if (ieee754_cxtest(IEEE754_OVERFLOW)) 8671da177e4SLinus Torvalds rcsr |= FPU_CSR_OVF_X | FPU_CSR_OVF_S; 8681da177e4SLinus Torvalds if (ieee754_cxtest(IEEE754_ZERO_DIVIDE)) 8691da177e4SLinus Torvalds rcsr |= FPU_CSR_DIV_X | FPU_CSR_DIV_S; 8701da177e4SLinus Torvalds if (ieee754_cxtest(IEEE754_INVALID_OPERATION)) 8711da177e4SLinus Torvalds rcsr |= FPU_CSR_INV_X | FPU_CSR_INV_S; 8721da177e4SLinus Torvalds break; 8731da177e4SLinus Torvalds 8741da177e4SLinus Torvalds /* unary conv ops */ 8751da177e4SLinus Torvalds case fcvts_op: 8761da177e4SLinus Torvalds return SIGILL; /* not defined */ 8771da177e4SLinus Torvalds case fcvtd_op:{ 8781da177e4SLinus Torvalds ieee754sp fs; 8791da177e4SLinus Torvalds 8801da177e4SLinus Torvalds SPFROMREG(fs, MIPSInst_FS(ir)); 8811da177e4SLinus Torvalds rv.d = ieee754dp_fsp(fs); 8821da177e4SLinus Torvalds rfmt = d_fmt; 8831da177e4SLinus Torvalds goto copcsr; 8841da177e4SLinus Torvalds } 8851da177e4SLinus Torvalds case fcvtw_op:{ 8861da177e4SLinus Torvalds ieee754sp fs; 8871da177e4SLinus Torvalds 8881da177e4SLinus Torvalds SPFROMREG(fs, MIPSInst_FS(ir)); 8891da177e4SLinus Torvalds rv.w = ieee754sp_tint(fs); 8901da177e4SLinus Torvalds rfmt = w_fmt; 8911da177e4SLinus Torvalds goto copcsr; 8921da177e4SLinus Torvalds } 8931da177e4SLinus Torvalds 894587cb98fSRalf Baechle #if __mips >= 2 || defined(__mips64) 8951da177e4SLinus Torvalds case fround_op: 8961da177e4SLinus Torvalds case ftrunc_op: 8971da177e4SLinus Torvalds case fceil_op: 8981da177e4SLinus Torvalds case ffloor_op:{ 8991da177e4SLinus Torvalds unsigned int oldrm = ieee754_csr.rm; 9001da177e4SLinus Torvalds ieee754sp fs; 9011da177e4SLinus Torvalds 9021da177e4SLinus Torvalds SPFROMREG(fs, MIPSInst_FS(ir)); 9031da177e4SLinus Torvalds ieee754_csr.rm = ieee_rm[MIPSInst_FUNC(ir) & 0x3]; 9041da177e4SLinus Torvalds rv.w = ieee754sp_tint(fs); 9051da177e4SLinus Torvalds ieee754_csr.rm = oldrm; 9061da177e4SLinus Torvalds rfmt = w_fmt; 9071da177e4SLinus Torvalds goto copcsr; 9081da177e4SLinus Torvalds } 9091da177e4SLinus Torvalds #endif /* __mips >= 2 */ 9101da177e4SLinus Torvalds 9114b724efdSRalf Baechle #if defined(__mips64) 9121da177e4SLinus Torvalds case fcvtl_op:{ 9131da177e4SLinus Torvalds ieee754sp fs; 9141da177e4SLinus Torvalds 9151da177e4SLinus Torvalds SPFROMREG(fs, MIPSInst_FS(ir)); 9161da177e4SLinus Torvalds rv.l = ieee754sp_tlong(fs); 9171da177e4SLinus Torvalds rfmt = l_fmt; 9181da177e4SLinus Torvalds goto copcsr; 9191da177e4SLinus Torvalds } 9201da177e4SLinus Torvalds 9211da177e4SLinus Torvalds case froundl_op: 9221da177e4SLinus Torvalds case ftruncl_op: 9231da177e4SLinus Torvalds case fceill_op: 9241da177e4SLinus Torvalds case ffloorl_op:{ 9251da177e4SLinus Torvalds unsigned int oldrm = ieee754_csr.rm; 9261da177e4SLinus Torvalds ieee754sp fs; 9271da177e4SLinus Torvalds 9281da177e4SLinus Torvalds SPFROMREG(fs, MIPSInst_FS(ir)); 9291da177e4SLinus Torvalds ieee754_csr.rm = ieee_rm[MIPSInst_FUNC(ir) & 0x3]; 9301da177e4SLinus Torvalds rv.l = ieee754sp_tlong(fs); 9311da177e4SLinus Torvalds ieee754_csr.rm = oldrm; 9321da177e4SLinus Torvalds rfmt = l_fmt; 9331da177e4SLinus Torvalds goto copcsr; 9341da177e4SLinus Torvalds } 9354b724efdSRalf Baechle #endif /* defined(__mips64) */ 9361da177e4SLinus Torvalds 9371da177e4SLinus Torvalds default: 9381da177e4SLinus Torvalds if (MIPSInst_FUNC(ir) >= fcmp_op) { 9391da177e4SLinus Torvalds unsigned cmpop = MIPSInst_FUNC(ir) - fcmp_op; 9401da177e4SLinus Torvalds ieee754sp fs, ft; 9411da177e4SLinus Torvalds 9421da177e4SLinus Torvalds SPFROMREG(fs, MIPSInst_FS(ir)); 9431da177e4SLinus Torvalds SPFROMREG(ft, MIPSInst_FT(ir)); 9441da177e4SLinus Torvalds rv.w = ieee754sp_cmp(fs, ft, 9451da177e4SLinus Torvalds cmptab[cmpop & 0x7], cmpop & 0x8); 9461da177e4SLinus Torvalds rfmt = -1; 9471da177e4SLinus Torvalds if ((cmpop & 0x8) && ieee754_cxtest 9481da177e4SLinus Torvalds (IEEE754_INVALID_OPERATION)) 9491da177e4SLinus Torvalds rcsr = FPU_CSR_INV_X | FPU_CSR_INV_S; 9501da177e4SLinus Torvalds else 9511da177e4SLinus Torvalds goto copcsr; 9521da177e4SLinus Torvalds 9531da177e4SLinus Torvalds } 9541da177e4SLinus Torvalds else { 9551da177e4SLinus Torvalds return SIGILL; 9561da177e4SLinus Torvalds } 9571da177e4SLinus Torvalds break; 9581da177e4SLinus Torvalds } 9591da177e4SLinus Torvalds break; 9601da177e4SLinus Torvalds } 9611da177e4SLinus Torvalds 9621da177e4SLinus Torvalds case d_fmt:{ 9631da177e4SLinus Torvalds union { 9641da177e4SLinus Torvalds ieee754dp(*b) (ieee754dp, ieee754dp); 9651da177e4SLinus Torvalds ieee754dp(*u) (ieee754dp); 9661da177e4SLinus Torvalds } handler; 9671da177e4SLinus Torvalds 9681da177e4SLinus Torvalds switch (MIPSInst_FUNC(ir)) { 9691da177e4SLinus Torvalds /* binary ops */ 9701da177e4SLinus Torvalds case fadd_op: 9711da177e4SLinus Torvalds handler.b = ieee754dp_add; 9721da177e4SLinus Torvalds goto dcopbop; 9731da177e4SLinus Torvalds case fsub_op: 9741da177e4SLinus Torvalds handler.b = ieee754dp_sub; 9751da177e4SLinus Torvalds goto dcopbop; 9761da177e4SLinus Torvalds case fmul_op: 9771da177e4SLinus Torvalds handler.b = ieee754dp_mul; 9781da177e4SLinus Torvalds goto dcopbop; 9791da177e4SLinus Torvalds case fdiv_op: 9801da177e4SLinus Torvalds handler.b = ieee754dp_div; 9811da177e4SLinus Torvalds goto dcopbop; 9821da177e4SLinus Torvalds 9831da177e4SLinus Torvalds /* unary ops */ 984587cb98fSRalf Baechle #if __mips >= 2 || defined(__mips64) 9851da177e4SLinus Torvalds case fsqrt_op: 9861da177e4SLinus Torvalds handler.u = ieee754dp_sqrt; 9871da177e4SLinus Torvalds goto dcopuop; 9881da177e4SLinus Torvalds #endif 9891da177e4SLinus Torvalds #if __mips >= 4 && __mips != 32 9901da177e4SLinus Torvalds case frsqrt_op: 9911da177e4SLinus Torvalds handler.u = fpemu_dp_rsqrt; 9921da177e4SLinus Torvalds goto dcopuop; 9931da177e4SLinus Torvalds case frecip_op: 9941da177e4SLinus Torvalds handler.u = fpemu_dp_recip; 9951da177e4SLinus Torvalds goto dcopuop; 9961da177e4SLinus Torvalds #endif 9971da177e4SLinus Torvalds #if __mips >= 4 9981da177e4SLinus Torvalds case fmovc_op: 9991da177e4SLinus Torvalds cond = fpucondbit[MIPSInst_FT(ir) >> 2]; 10001da177e4SLinus Torvalds if (((ctx->fcr31 & cond) != 0) != 10011da177e4SLinus Torvalds ((MIPSInst_FT(ir) & 1) != 0)) 10021da177e4SLinus Torvalds return 0; 10031da177e4SLinus Torvalds DPFROMREG(rv.d, MIPSInst_FS(ir)); 10041da177e4SLinus Torvalds break; 10051da177e4SLinus Torvalds case fmovz_op: 10061da177e4SLinus Torvalds if (xcp->regs[MIPSInst_FT(ir)] != 0) 10071da177e4SLinus Torvalds return 0; 10081da177e4SLinus Torvalds DPFROMREG(rv.d, MIPSInst_FS(ir)); 10091da177e4SLinus Torvalds break; 10101da177e4SLinus Torvalds case fmovn_op: 10111da177e4SLinus Torvalds if (xcp->regs[MIPSInst_FT(ir)] == 0) 10121da177e4SLinus Torvalds return 0; 10131da177e4SLinus Torvalds DPFROMREG(rv.d, MIPSInst_FS(ir)); 10141da177e4SLinus Torvalds break; 10151da177e4SLinus Torvalds #endif 10161da177e4SLinus Torvalds case fabs_op: 10171da177e4SLinus Torvalds handler.u = ieee754dp_abs; 10181da177e4SLinus Torvalds goto dcopuop; 10191da177e4SLinus Torvalds 10201da177e4SLinus Torvalds case fneg_op: 10211da177e4SLinus Torvalds handler.u = ieee754dp_neg; 10221da177e4SLinus Torvalds goto dcopuop; 10231da177e4SLinus Torvalds 10241da177e4SLinus Torvalds case fmov_op: 10251da177e4SLinus Torvalds /* an easy one */ 10261da177e4SLinus Torvalds DPFROMREG(rv.d, MIPSInst_FS(ir)); 10271da177e4SLinus Torvalds goto copcsr; 10281da177e4SLinus Torvalds 10291da177e4SLinus Torvalds /* binary op on handler */ 10301da177e4SLinus Torvalds dcopbop:{ 10311da177e4SLinus Torvalds ieee754dp fs, ft; 10321da177e4SLinus Torvalds 10331da177e4SLinus Torvalds DPFROMREG(fs, MIPSInst_FS(ir)); 10341da177e4SLinus Torvalds DPFROMREG(ft, MIPSInst_FT(ir)); 10351da177e4SLinus Torvalds 10361da177e4SLinus Torvalds rv.d = (*handler.b) (fs, ft); 10371da177e4SLinus Torvalds goto copcsr; 10381da177e4SLinus Torvalds } 10391da177e4SLinus Torvalds dcopuop:{ 10401da177e4SLinus Torvalds ieee754dp fs; 10411da177e4SLinus Torvalds 10421da177e4SLinus Torvalds DPFROMREG(fs, MIPSInst_FS(ir)); 10431da177e4SLinus Torvalds rv.d = (*handler.u) (fs); 10441da177e4SLinus Torvalds goto copcsr; 10451da177e4SLinus Torvalds } 10461da177e4SLinus Torvalds 10471da177e4SLinus Torvalds /* unary conv ops */ 10481da177e4SLinus Torvalds case fcvts_op:{ 10491da177e4SLinus Torvalds ieee754dp fs; 10501da177e4SLinus Torvalds 10511da177e4SLinus Torvalds DPFROMREG(fs, MIPSInst_FS(ir)); 10521da177e4SLinus Torvalds rv.s = ieee754sp_fdp(fs); 10531da177e4SLinus Torvalds rfmt = s_fmt; 10541da177e4SLinus Torvalds goto copcsr; 10551da177e4SLinus Torvalds } 10561da177e4SLinus Torvalds case fcvtd_op: 10571da177e4SLinus Torvalds return SIGILL; /* not defined */ 10581da177e4SLinus Torvalds 10591da177e4SLinus Torvalds case fcvtw_op:{ 10601da177e4SLinus Torvalds ieee754dp fs; 10611da177e4SLinus Torvalds 10621da177e4SLinus Torvalds DPFROMREG(fs, MIPSInst_FS(ir)); 10631da177e4SLinus Torvalds rv.w = ieee754dp_tint(fs); /* wrong */ 10641da177e4SLinus Torvalds rfmt = w_fmt; 10651da177e4SLinus Torvalds goto copcsr; 10661da177e4SLinus Torvalds } 10671da177e4SLinus Torvalds 1068587cb98fSRalf Baechle #if __mips >= 2 || defined(__mips64) 10691da177e4SLinus Torvalds case fround_op: 10701da177e4SLinus Torvalds case ftrunc_op: 10711da177e4SLinus Torvalds case fceil_op: 10721da177e4SLinus Torvalds case ffloor_op:{ 10731da177e4SLinus Torvalds unsigned int oldrm = ieee754_csr.rm; 10741da177e4SLinus Torvalds ieee754dp fs; 10751da177e4SLinus Torvalds 10761da177e4SLinus Torvalds DPFROMREG(fs, MIPSInst_FS(ir)); 10771da177e4SLinus Torvalds ieee754_csr.rm = ieee_rm[MIPSInst_FUNC(ir) & 0x3]; 10781da177e4SLinus Torvalds rv.w = ieee754dp_tint(fs); 10791da177e4SLinus Torvalds ieee754_csr.rm = oldrm; 10801da177e4SLinus Torvalds rfmt = w_fmt; 10811da177e4SLinus Torvalds goto copcsr; 10821da177e4SLinus Torvalds } 10831da177e4SLinus Torvalds #endif 10841da177e4SLinus Torvalds 10854b724efdSRalf Baechle #if defined(__mips64) 10861da177e4SLinus Torvalds case fcvtl_op:{ 10871da177e4SLinus Torvalds ieee754dp fs; 10881da177e4SLinus Torvalds 10891da177e4SLinus Torvalds DPFROMREG(fs, MIPSInst_FS(ir)); 10901da177e4SLinus Torvalds rv.l = ieee754dp_tlong(fs); 10911da177e4SLinus Torvalds rfmt = l_fmt; 10921da177e4SLinus Torvalds goto copcsr; 10931da177e4SLinus Torvalds } 10941da177e4SLinus Torvalds 10951da177e4SLinus Torvalds case froundl_op: 10961da177e4SLinus Torvalds case ftruncl_op: 10971da177e4SLinus Torvalds case fceill_op: 10981da177e4SLinus Torvalds case ffloorl_op:{ 10991da177e4SLinus Torvalds unsigned int oldrm = ieee754_csr.rm; 11001da177e4SLinus Torvalds ieee754dp fs; 11011da177e4SLinus Torvalds 11021da177e4SLinus Torvalds DPFROMREG(fs, MIPSInst_FS(ir)); 11031da177e4SLinus Torvalds ieee754_csr.rm = ieee_rm[MIPSInst_FUNC(ir) & 0x3]; 11041da177e4SLinus Torvalds rv.l = ieee754dp_tlong(fs); 11051da177e4SLinus Torvalds ieee754_csr.rm = oldrm; 11061da177e4SLinus Torvalds rfmt = l_fmt; 11071da177e4SLinus Torvalds goto copcsr; 11081da177e4SLinus Torvalds } 11094b724efdSRalf Baechle #endif /* __mips >= 3 */ 11101da177e4SLinus Torvalds 11111da177e4SLinus Torvalds default: 11121da177e4SLinus Torvalds if (MIPSInst_FUNC(ir) >= fcmp_op) { 11131da177e4SLinus Torvalds unsigned cmpop = MIPSInst_FUNC(ir) - fcmp_op; 11141da177e4SLinus Torvalds ieee754dp fs, ft; 11151da177e4SLinus Torvalds 11161da177e4SLinus Torvalds DPFROMREG(fs, MIPSInst_FS(ir)); 11171da177e4SLinus Torvalds DPFROMREG(ft, MIPSInst_FT(ir)); 11181da177e4SLinus Torvalds rv.w = ieee754dp_cmp(fs, ft, 11191da177e4SLinus Torvalds cmptab[cmpop & 0x7], cmpop & 0x8); 11201da177e4SLinus Torvalds rfmt = -1; 11211da177e4SLinus Torvalds if ((cmpop & 0x8) 11221da177e4SLinus Torvalds && 11231da177e4SLinus Torvalds ieee754_cxtest 11241da177e4SLinus Torvalds (IEEE754_INVALID_OPERATION)) 11251da177e4SLinus Torvalds rcsr = FPU_CSR_INV_X | FPU_CSR_INV_S; 11261da177e4SLinus Torvalds else 11271da177e4SLinus Torvalds goto copcsr; 11281da177e4SLinus Torvalds 11291da177e4SLinus Torvalds } 11301da177e4SLinus Torvalds else { 11311da177e4SLinus Torvalds return SIGILL; 11321da177e4SLinus Torvalds } 11331da177e4SLinus Torvalds break; 11341da177e4SLinus Torvalds } 11351da177e4SLinus Torvalds break; 11361da177e4SLinus Torvalds } 11371da177e4SLinus Torvalds 11381da177e4SLinus Torvalds case w_fmt:{ 11391da177e4SLinus Torvalds ieee754sp fs; 11401da177e4SLinus Torvalds 11411da177e4SLinus Torvalds switch (MIPSInst_FUNC(ir)) { 11421da177e4SLinus Torvalds case fcvts_op: 11431da177e4SLinus Torvalds /* convert word to single precision real */ 11441da177e4SLinus Torvalds SPFROMREG(fs, MIPSInst_FS(ir)); 11451da177e4SLinus Torvalds rv.s = ieee754sp_fint(fs.bits); 11461da177e4SLinus Torvalds rfmt = s_fmt; 11471da177e4SLinus Torvalds goto copcsr; 11481da177e4SLinus Torvalds case fcvtd_op: 11491da177e4SLinus Torvalds /* convert word to double precision real */ 11501da177e4SLinus Torvalds SPFROMREG(fs, MIPSInst_FS(ir)); 11511da177e4SLinus Torvalds rv.d = ieee754dp_fint(fs.bits); 11521da177e4SLinus Torvalds rfmt = d_fmt; 11531da177e4SLinus Torvalds goto copcsr; 11541da177e4SLinus Torvalds default: 11551da177e4SLinus Torvalds return SIGILL; 11561da177e4SLinus Torvalds } 11571da177e4SLinus Torvalds break; 11581da177e4SLinus Torvalds } 11591da177e4SLinus Torvalds 11604b724efdSRalf Baechle #if defined(__mips64) 11611da177e4SLinus Torvalds case l_fmt:{ 11621da177e4SLinus Torvalds switch (MIPSInst_FUNC(ir)) { 11631da177e4SLinus Torvalds case fcvts_op: 11641da177e4SLinus Torvalds /* convert long to single precision real */ 11651da177e4SLinus Torvalds rv.s = ieee754sp_flong(ctx->fpr[MIPSInst_FS(ir)]); 11661da177e4SLinus Torvalds rfmt = s_fmt; 11671da177e4SLinus Torvalds goto copcsr; 11681da177e4SLinus Torvalds case fcvtd_op: 11691da177e4SLinus Torvalds /* convert long to double precision real */ 11701da177e4SLinus Torvalds rv.d = ieee754dp_flong(ctx->fpr[MIPSInst_FS(ir)]); 11711da177e4SLinus Torvalds rfmt = d_fmt; 11721da177e4SLinus Torvalds goto copcsr; 11731da177e4SLinus Torvalds default: 11741da177e4SLinus Torvalds return SIGILL; 11751da177e4SLinus Torvalds } 11761da177e4SLinus Torvalds break; 11771da177e4SLinus Torvalds } 11781da177e4SLinus Torvalds #endif 11791da177e4SLinus Torvalds 11801da177e4SLinus Torvalds default: 11811da177e4SLinus Torvalds return SIGILL; 11821da177e4SLinus Torvalds } 11831da177e4SLinus Torvalds 11841da177e4SLinus Torvalds /* 11851da177e4SLinus Torvalds * Update the fpu CSR register for this operation. 11861da177e4SLinus Torvalds * If an exception is required, generate a tidy SIGFPE exception, 11871da177e4SLinus Torvalds * without updating the result register. 11881da177e4SLinus Torvalds * Note: cause exception bits do not accumulate, they are rewritten 11891da177e4SLinus Torvalds * for each op; only the flag/sticky bits accumulate. 11901da177e4SLinus Torvalds */ 11911da177e4SLinus Torvalds ctx->fcr31 = (ctx->fcr31 & ~FPU_CSR_ALL_X) | rcsr; 11921da177e4SLinus Torvalds if ((ctx->fcr31 >> 5) & ctx->fcr31 & FPU_CSR_ALL_E) { 11931da177e4SLinus Torvalds /*printk ("SIGFPE: fpu csr = %08x\n",ctx->fcr31); */ 11941da177e4SLinus Torvalds return SIGFPE; 11951da177e4SLinus Torvalds } 11961da177e4SLinus Torvalds 11971da177e4SLinus Torvalds /* 11981da177e4SLinus Torvalds * Now we can safely write the result back to the register file. 11991da177e4SLinus Torvalds */ 12001da177e4SLinus Torvalds switch (rfmt) { 12011da177e4SLinus Torvalds case -1:{ 12021da177e4SLinus Torvalds #if __mips >= 4 12031da177e4SLinus Torvalds cond = fpucondbit[MIPSInst_FD(ir) >> 2]; 12041da177e4SLinus Torvalds #else 12051da177e4SLinus Torvalds cond = FPU_CSR_COND; 12061da177e4SLinus Torvalds #endif 12071da177e4SLinus Torvalds if (rv.w) 12081da177e4SLinus Torvalds ctx->fcr31 |= cond; 12091da177e4SLinus Torvalds else 12101da177e4SLinus Torvalds ctx->fcr31 &= ~cond; 12111da177e4SLinus Torvalds break; 12121da177e4SLinus Torvalds } 12131da177e4SLinus Torvalds case d_fmt: 12141da177e4SLinus Torvalds DPTOREG(rv.d, MIPSInst_FD(ir)); 12151da177e4SLinus Torvalds break; 12161da177e4SLinus Torvalds case s_fmt: 12171da177e4SLinus Torvalds SPTOREG(rv.s, MIPSInst_FD(ir)); 12181da177e4SLinus Torvalds break; 12191da177e4SLinus Torvalds case w_fmt: 12201da177e4SLinus Torvalds SITOREG(rv.w, MIPSInst_FD(ir)); 12211da177e4SLinus Torvalds break; 12224b724efdSRalf Baechle #if defined(__mips64) 12231da177e4SLinus Torvalds case l_fmt: 12241da177e4SLinus Torvalds DITOREG(rv.l, MIPSInst_FD(ir)); 12251da177e4SLinus Torvalds break; 12261da177e4SLinus Torvalds #endif 12271da177e4SLinus Torvalds default: 12281da177e4SLinus Torvalds return SIGILL; 12291da177e4SLinus Torvalds } 12301da177e4SLinus Torvalds 12311da177e4SLinus Torvalds return 0; 12321da177e4SLinus Torvalds } 12331da177e4SLinus Torvalds 1234e04582b7SAtsushi Nemoto int fpu_emulator_cop1Handler(struct pt_regs *xcp, struct mips_fpu_struct *ctx, 1235e04582b7SAtsushi Nemoto int has_fpu) 12361da177e4SLinus Torvalds { 1237333d1f67SRalf Baechle unsigned long oldepc, prevepc; 12381da177e4SLinus Torvalds mips_instruction insn; 12391da177e4SLinus Torvalds int sig = 0; 12401da177e4SLinus Torvalds 12411da177e4SLinus Torvalds oldepc = xcp->cp0_epc; 12421da177e4SLinus Torvalds do { 12431da177e4SLinus Torvalds prevepc = xcp->cp0_epc; 12441da177e4SLinus Torvalds 12453fccc015SRalf Baechle if (get_user(insn, (mips_instruction __user *) xcp->cp0_epc)) { 1246*b6ee75edSDavid Daney MIPS_FPU_EMU_INC_STATS(errors); 12471da177e4SLinus Torvalds return SIGBUS; 12481da177e4SLinus Torvalds } 12491da177e4SLinus Torvalds if (insn == 0) 12501da177e4SLinus Torvalds xcp->cp0_epc += 4; /* skip nops */ 12511da177e4SLinus Torvalds else { 1252cd21dfcfSRalf Baechle /* 1253cd21dfcfSRalf Baechle * The 'ieee754_csr' is an alias of 1254cd21dfcfSRalf Baechle * ctx->fcr31. No need to copy ctx->fcr31 to 1255cd21dfcfSRalf Baechle * ieee754_csr. But ieee754_csr.rm is ieee 1256cd21dfcfSRalf Baechle * library modes. (not mips rounding mode) 1257cd21dfcfSRalf Baechle */ 1258cd21dfcfSRalf Baechle /* convert to ieee library modes */ 1259cd21dfcfSRalf Baechle ieee754_csr.rm = ieee_rm[ieee754_csr.rm]; 12601da177e4SLinus Torvalds sig = cop1Emulate(xcp, ctx); 1261cd21dfcfSRalf Baechle /* revert to mips rounding mode */ 1262cd21dfcfSRalf Baechle ieee754_csr.rm = mips_rm[ieee754_csr.rm]; 12631da177e4SLinus Torvalds } 12641da177e4SLinus Torvalds 1265e04582b7SAtsushi Nemoto if (has_fpu) 12661da177e4SLinus Torvalds break; 12671da177e4SLinus Torvalds if (sig) 12681da177e4SLinus Torvalds break; 12691da177e4SLinus Torvalds 12701da177e4SLinus Torvalds cond_resched(); 12711da177e4SLinus Torvalds } while (xcp->cp0_epc > prevepc); 12721da177e4SLinus Torvalds 12731da177e4SLinus Torvalds /* SIGILL indicates a non-fpu instruction */ 12741da177e4SLinus Torvalds if (sig == SIGILL && xcp->cp0_epc != oldepc) 12751da177e4SLinus Torvalds /* but if epc has advanced, then ignore it */ 12761da177e4SLinus Torvalds sig = 0; 12771da177e4SLinus Torvalds 12781da177e4SLinus Torvalds return sig; 12791da177e4SLinus Torvalds } 128083fd38caSAtsushi Nemoto 128183fd38caSAtsushi Nemoto #ifdef CONFIG_DEBUG_FS 1282*b6ee75edSDavid Daney 1283*b6ee75edSDavid Daney static int fpuemu_stat_get(void *data, u64 *val) 1284*b6ee75edSDavid Daney { 1285*b6ee75edSDavid Daney int cpu; 1286*b6ee75edSDavid Daney unsigned long sum = 0; 1287*b6ee75edSDavid Daney for_each_online_cpu(cpu) { 1288*b6ee75edSDavid Daney struct mips_fpu_emulator_stats *ps; 1289*b6ee75edSDavid Daney local_t *pv; 1290*b6ee75edSDavid Daney ps = &per_cpu(fpuemustats, cpu); 1291*b6ee75edSDavid Daney pv = (void *)ps + (unsigned long)data; 1292*b6ee75edSDavid Daney sum += local_read(pv); 1293*b6ee75edSDavid Daney } 1294*b6ee75edSDavid Daney *val = sum; 1295*b6ee75edSDavid Daney return 0; 1296*b6ee75edSDavid Daney } 1297*b6ee75edSDavid Daney DEFINE_SIMPLE_ATTRIBUTE(fops_fpuemu_stat, fpuemu_stat_get, NULL, "%llu\n"); 1298*b6ee75edSDavid Daney 129983fd38caSAtsushi Nemoto extern struct dentry *mips_debugfs_dir; 130083fd38caSAtsushi Nemoto static int __init debugfs_fpuemu(void) 130183fd38caSAtsushi Nemoto { 130283fd38caSAtsushi Nemoto struct dentry *d, *dir; 130383fd38caSAtsushi Nemoto 130483fd38caSAtsushi Nemoto if (!mips_debugfs_dir) 130583fd38caSAtsushi Nemoto return -ENODEV; 130683fd38caSAtsushi Nemoto dir = debugfs_create_dir("fpuemustats", mips_debugfs_dir); 1307ecab1f44SZhaolei if (!dir) 1308ecab1f44SZhaolei return -ENOMEM; 1309*b6ee75edSDavid Daney 1310*b6ee75edSDavid Daney #define FPU_STAT_CREATE(M) \ 1311*b6ee75edSDavid Daney do { \ 1312*b6ee75edSDavid Daney d = debugfs_create_file(#M , S_IRUGO, dir, \ 1313*b6ee75edSDavid Daney (void *)offsetof(struct mips_fpu_emulator_stats, M), \ 1314*b6ee75edSDavid Daney &fops_fpuemu_stat); \ 1315*b6ee75edSDavid Daney if (!d) \ 1316*b6ee75edSDavid Daney return -ENOMEM; \ 1317*b6ee75edSDavid Daney } while (0) 1318*b6ee75edSDavid Daney 1319*b6ee75edSDavid Daney FPU_STAT_CREATE(emulated); 1320*b6ee75edSDavid Daney FPU_STAT_CREATE(loads); 1321*b6ee75edSDavid Daney FPU_STAT_CREATE(stores); 1322*b6ee75edSDavid Daney FPU_STAT_CREATE(cp1ops); 1323*b6ee75edSDavid Daney FPU_STAT_CREATE(cp1xops); 1324*b6ee75edSDavid Daney FPU_STAT_CREATE(errors); 1325*b6ee75edSDavid Daney 132683fd38caSAtsushi Nemoto return 0; 132783fd38caSAtsushi Nemoto } 132883fd38caSAtsushi Nemoto __initcall(debugfs_fpuemu); 132983fd38caSAtsushi Nemoto #endif 1330