11da177e4SLinus Torvalds /* 23f7cac41SRalf Baechle * cp1emu.c: a MIPS coprocessor 1 (FPU) instruction emulator 31da177e4SLinus Torvalds * 41da177e4SLinus Torvalds * MIPS floating point support 51da177e4SLinus Torvalds * Copyright (C) 1994-2000 Algorithmics Ltd. 61da177e4SLinus Torvalds * 71da177e4SLinus Torvalds * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com 81da177e4SLinus Torvalds * Copyright (C) 2000 MIPS Technologies, Inc. 91da177e4SLinus Torvalds * 101da177e4SLinus Torvalds * This program is free software; you can distribute it and/or modify it 111da177e4SLinus Torvalds * under the terms of the GNU General Public License (Version 2) as 121da177e4SLinus Torvalds * published by the Free Software Foundation. 131da177e4SLinus Torvalds * 141da177e4SLinus Torvalds * This program is distributed in the hope it will be useful, but WITHOUT 151da177e4SLinus Torvalds * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 161da177e4SLinus Torvalds * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 171da177e4SLinus Torvalds * for more details. 181da177e4SLinus Torvalds * 191da177e4SLinus Torvalds * You should have received a copy of the GNU General Public License along 201da177e4SLinus Torvalds * with this program; if not, write to the Free Software Foundation, Inc., 213f7cac41SRalf Baechle * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. 221da177e4SLinus Torvalds * 231da177e4SLinus Torvalds * A complete emulator for MIPS coprocessor 1 instructions. This is 241da177e4SLinus Torvalds * required for #float(switch) or #float(trap), where it catches all 251da177e4SLinus Torvalds * COP1 instructions via the "CoProcessor Unusable" exception. 261da177e4SLinus Torvalds * 271da177e4SLinus Torvalds * More surprisingly it is also required for #float(ieee), to help out 283f7cac41SRalf Baechle * the hardware FPU at the boundaries of the IEEE-754 representation 291da177e4SLinus Torvalds * (denormalised values, infinities, underflow, etc). It is made 301da177e4SLinus Torvalds * quite nasty because emulation of some non-COP1 instructions is 311da177e4SLinus Torvalds * required, e.g. in branch delay slots. 321da177e4SLinus Torvalds * 333f7cac41SRalf Baechle * Note if you know that you won't have an FPU, then you'll get much 341da177e4SLinus Torvalds * better performance by compiling with -msoft-float! 351da177e4SLinus Torvalds */ 361da177e4SLinus Torvalds #include <linux/sched.h> 3783fd38caSAtsushi Nemoto #include <linux/debugfs.h> 3808a07904SRalf Baechle #include <linux/kconfig.h> 3985c51c51SRalf Baechle #include <linux/percpu-defs.h> 407f788d2dSDeng-Cheng Zhu #include <linux/perf_event.h> 411da177e4SLinus Torvalds 42cd8ee345SRalf Baechle #include <asm/branch.h> 431da177e4SLinus Torvalds #include <asm/inst.h> 441da177e4SLinus Torvalds #include <asm/ptrace.h> 451da177e4SLinus Torvalds #include <asm/signal.h> 46cd8ee345SRalf Baechle #include <asm/uaccess.h> 47cd8ee345SRalf Baechle 48cd8ee345SRalf Baechle #include <asm/processor.h> 491da177e4SLinus Torvalds #include <asm/fpu_emulator.h> 50102cedc3SLeonid Yegoshin #include <asm/fpu.h> 511da177e4SLinus Torvalds 521da177e4SLinus Torvalds #include "ieee754.h" 531da177e4SLinus Torvalds 541da177e4SLinus Torvalds /* Function which emulates a floating point instruction. */ 551da177e4SLinus Torvalds 56eae89076SAtsushi Nemoto static int fpu_emu(struct pt_regs *, struct mips_fpu_struct *, 571da177e4SLinus Torvalds mips_instruction); 581da177e4SLinus Torvalds 591da177e4SLinus Torvalds static int fpux_emu(struct pt_regs *, 60515b029dSDavid Daney struct mips_fpu_struct *, mips_instruction, void *__user *); 611da177e4SLinus Torvalds 621da177e4SLinus Torvalds /* Control registers */ 631da177e4SLinus Torvalds 641da177e4SLinus Torvalds #define FPCREG_RID 0 /* $0 = revision id */ 651da177e4SLinus Torvalds #define FPCREG_CSR 31 /* $31 = csr */ 661da177e4SLinus Torvalds 6795e8f634SShane McDonald /* Determine rounding mode from the RM bits of the FCSR */ 6895e8f634SShane McDonald #define modeindex(v) ((v) & FPU_CSR_RM) 6995e8f634SShane McDonald 701da177e4SLinus Torvalds /* convert condition code register number to csr bit */ 711da177e4SLinus Torvalds static const unsigned int fpucondbit[8] = { 721da177e4SLinus Torvalds FPU_CSR_COND0, 731da177e4SLinus Torvalds FPU_CSR_COND1, 741da177e4SLinus Torvalds FPU_CSR_COND2, 751da177e4SLinus Torvalds FPU_CSR_COND3, 761da177e4SLinus Torvalds FPU_CSR_COND4, 771da177e4SLinus Torvalds FPU_CSR_COND5, 781da177e4SLinus Torvalds FPU_CSR_COND6, 791da177e4SLinus Torvalds FPU_CSR_COND7 801da177e4SLinus Torvalds }; 811da177e4SLinus Torvalds 82102cedc3SLeonid Yegoshin /* (microMIPS) Convert certain microMIPS instructions to MIPS32 format. */ 83102cedc3SLeonid Yegoshin static const int sd_format[] = {16, 17, 0, 0, 0, 0, 0, 0}; 84102cedc3SLeonid Yegoshin static const int sdps_format[] = {16, 17, 22, 0, 0, 0, 0, 0}; 85102cedc3SLeonid Yegoshin static const int dwl_format[] = {17, 20, 21, 0, 0, 0, 0, 0}; 86102cedc3SLeonid Yegoshin static const int swl_format[] = {16, 20, 21, 0, 0, 0, 0, 0}; 87102cedc3SLeonid Yegoshin 88102cedc3SLeonid Yegoshin /* 89102cedc3SLeonid Yegoshin * This functions translates a 32-bit microMIPS instruction 90102cedc3SLeonid Yegoshin * into a 32-bit MIPS32 instruction. Returns 0 on success 91102cedc3SLeonid Yegoshin * and SIGILL otherwise. 92102cedc3SLeonid Yegoshin */ 93102cedc3SLeonid Yegoshin static int microMIPS32_to_MIPS32(union mips_instruction *insn_ptr) 94102cedc3SLeonid Yegoshin { 95102cedc3SLeonid Yegoshin union mips_instruction insn = *insn_ptr; 96102cedc3SLeonid Yegoshin union mips_instruction mips32_insn = insn; 97102cedc3SLeonid Yegoshin int func, fmt, op; 98102cedc3SLeonid Yegoshin 99102cedc3SLeonid Yegoshin switch (insn.mm_i_format.opcode) { 100102cedc3SLeonid Yegoshin case mm_ldc132_op: 101102cedc3SLeonid Yegoshin mips32_insn.mm_i_format.opcode = ldc1_op; 102102cedc3SLeonid Yegoshin mips32_insn.mm_i_format.rt = insn.mm_i_format.rs; 103102cedc3SLeonid Yegoshin mips32_insn.mm_i_format.rs = insn.mm_i_format.rt; 104102cedc3SLeonid Yegoshin break; 105102cedc3SLeonid Yegoshin case mm_lwc132_op: 106102cedc3SLeonid Yegoshin mips32_insn.mm_i_format.opcode = lwc1_op; 107102cedc3SLeonid Yegoshin mips32_insn.mm_i_format.rt = insn.mm_i_format.rs; 108102cedc3SLeonid Yegoshin mips32_insn.mm_i_format.rs = insn.mm_i_format.rt; 109102cedc3SLeonid Yegoshin break; 110102cedc3SLeonid Yegoshin case mm_sdc132_op: 111102cedc3SLeonid Yegoshin mips32_insn.mm_i_format.opcode = sdc1_op; 112102cedc3SLeonid Yegoshin mips32_insn.mm_i_format.rt = insn.mm_i_format.rs; 113102cedc3SLeonid Yegoshin mips32_insn.mm_i_format.rs = insn.mm_i_format.rt; 114102cedc3SLeonid Yegoshin break; 115102cedc3SLeonid Yegoshin case mm_swc132_op: 116102cedc3SLeonid Yegoshin mips32_insn.mm_i_format.opcode = swc1_op; 117102cedc3SLeonid Yegoshin mips32_insn.mm_i_format.rt = insn.mm_i_format.rs; 118102cedc3SLeonid Yegoshin mips32_insn.mm_i_format.rs = insn.mm_i_format.rt; 119102cedc3SLeonid Yegoshin break; 120102cedc3SLeonid Yegoshin case mm_pool32i_op: 121102cedc3SLeonid Yegoshin /* NOTE: offset is << by 1 if in microMIPS mode. */ 122102cedc3SLeonid Yegoshin if ((insn.mm_i_format.rt == mm_bc1f_op) || 123102cedc3SLeonid Yegoshin (insn.mm_i_format.rt == mm_bc1t_op)) { 124102cedc3SLeonid Yegoshin mips32_insn.fb_format.opcode = cop1_op; 125102cedc3SLeonid Yegoshin mips32_insn.fb_format.bc = bc_op; 126102cedc3SLeonid Yegoshin mips32_insn.fb_format.flag = 127102cedc3SLeonid Yegoshin (insn.mm_i_format.rt == mm_bc1t_op) ? 1 : 0; 128102cedc3SLeonid Yegoshin } else 129102cedc3SLeonid Yegoshin return SIGILL; 130102cedc3SLeonid Yegoshin break; 131102cedc3SLeonid Yegoshin case mm_pool32f_op: 132102cedc3SLeonid Yegoshin switch (insn.mm_fp0_format.func) { 133102cedc3SLeonid Yegoshin case mm_32f_01_op: 134102cedc3SLeonid Yegoshin case mm_32f_11_op: 135102cedc3SLeonid Yegoshin case mm_32f_02_op: 136102cedc3SLeonid Yegoshin case mm_32f_12_op: 137102cedc3SLeonid Yegoshin case mm_32f_41_op: 138102cedc3SLeonid Yegoshin case mm_32f_51_op: 139102cedc3SLeonid Yegoshin case mm_32f_42_op: 140102cedc3SLeonid Yegoshin case mm_32f_52_op: 141102cedc3SLeonid Yegoshin op = insn.mm_fp0_format.func; 142102cedc3SLeonid Yegoshin if (op == mm_32f_01_op) 143102cedc3SLeonid Yegoshin func = madd_s_op; 144102cedc3SLeonid Yegoshin else if (op == mm_32f_11_op) 145102cedc3SLeonid Yegoshin func = madd_d_op; 146102cedc3SLeonid Yegoshin else if (op == mm_32f_02_op) 147102cedc3SLeonid Yegoshin func = nmadd_s_op; 148102cedc3SLeonid Yegoshin else if (op == mm_32f_12_op) 149102cedc3SLeonid Yegoshin func = nmadd_d_op; 150102cedc3SLeonid Yegoshin else if (op == mm_32f_41_op) 151102cedc3SLeonid Yegoshin func = msub_s_op; 152102cedc3SLeonid Yegoshin else if (op == mm_32f_51_op) 153102cedc3SLeonid Yegoshin func = msub_d_op; 154102cedc3SLeonid Yegoshin else if (op == mm_32f_42_op) 155102cedc3SLeonid Yegoshin func = nmsub_s_op; 156102cedc3SLeonid Yegoshin else 157102cedc3SLeonid Yegoshin func = nmsub_d_op; 158102cedc3SLeonid Yegoshin mips32_insn.fp6_format.opcode = cop1x_op; 159102cedc3SLeonid Yegoshin mips32_insn.fp6_format.fr = insn.mm_fp6_format.fr; 160102cedc3SLeonid Yegoshin mips32_insn.fp6_format.ft = insn.mm_fp6_format.ft; 161102cedc3SLeonid Yegoshin mips32_insn.fp6_format.fs = insn.mm_fp6_format.fs; 162102cedc3SLeonid Yegoshin mips32_insn.fp6_format.fd = insn.mm_fp6_format.fd; 163102cedc3SLeonid Yegoshin mips32_insn.fp6_format.func = func; 164102cedc3SLeonid Yegoshin break; 165102cedc3SLeonid Yegoshin case mm_32f_10_op: 166102cedc3SLeonid Yegoshin func = -1; /* Invalid */ 167102cedc3SLeonid Yegoshin op = insn.mm_fp5_format.op & 0x7; 168102cedc3SLeonid Yegoshin if (op == mm_ldxc1_op) 169102cedc3SLeonid Yegoshin func = ldxc1_op; 170102cedc3SLeonid Yegoshin else if (op == mm_sdxc1_op) 171102cedc3SLeonid Yegoshin func = sdxc1_op; 172102cedc3SLeonid Yegoshin else if (op == mm_lwxc1_op) 173102cedc3SLeonid Yegoshin func = lwxc1_op; 174102cedc3SLeonid Yegoshin else if (op == mm_swxc1_op) 175102cedc3SLeonid Yegoshin func = swxc1_op; 176102cedc3SLeonid Yegoshin 177102cedc3SLeonid Yegoshin if (func != -1) { 178102cedc3SLeonid Yegoshin mips32_insn.r_format.opcode = cop1x_op; 179102cedc3SLeonid Yegoshin mips32_insn.r_format.rs = 180102cedc3SLeonid Yegoshin insn.mm_fp5_format.base; 181102cedc3SLeonid Yegoshin mips32_insn.r_format.rt = 182102cedc3SLeonid Yegoshin insn.mm_fp5_format.index; 183102cedc3SLeonid Yegoshin mips32_insn.r_format.rd = 0; 184102cedc3SLeonid Yegoshin mips32_insn.r_format.re = insn.mm_fp5_format.fd; 185102cedc3SLeonid Yegoshin mips32_insn.r_format.func = func; 186102cedc3SLeonid Yegoshin } else 187102cedc3SLeonid Yegoshin return SIGILL; 188102cedc3SLeonid Yegoshin break; 189102cedc3SLeonid Yegoshin case mm_32f_40_op: 190102cedc3SLeonid Yegoshin op = -1; /* Invalid */ 191102cedc3SLeonid Yegoshin if (insn.mm_fp2_format.op == mm_fmovt_op) 192102cedc3SLeonid Yegoshin op = 1; 193102cedc3SLeonid Yegoshin else if (insn.mm_fp2_format.op == mm_fmovf_op) 194102cedc3SLeonid Yegoshin op = 0; 195102cedc3SLeonid Yegoshin if (op != -1) { 196102cedc3SLeonid Yegoshin mips32_insn.fp0_format.opcode = cop1_op; 197102cedc3SLeonid Yegoshin mips32_insn.fp0_format.fmt = 198102cedc3SLeonid Yegoshin sdps_format[insn.mm_fp2_format.fmt]; 199102cedc3SLeonid Yegoshin mips32_insn.fp0_format.ft = 200102cedc3SLeonid Yegoshin (insn.mm_fp2_format.cc<<2) + op; 201102cedc3SLeonid Yegoshin mips32_insn.fp0_format.fs = 202102cedc3SLeonid Yegoshin insn.mm_fp2_format.fs; 203102cedc3SLeonid Yegoshin mips32_insn.fp0_format.fd = 204102cedc3SLeonid Yegoshin insn.mm_fp2_format.fd; 205102cedc3SLeonid Yegoshin mips32_insn.fp0_format.func = fmovc_op; 206102cedc3SLeonid Yegoshin } else 207102cedc3SLeonid Yegoshin return SIGILL; 208102cedc3SLeonid Yegoshin break; 209102cedc3SLeonid Yegoshin case mm_32f_60_op: 210102cedc3SLeonid Yegoshin func = -1; /* Invalid */ 211102cedc3SLeonid Yegoshin if (insn.mm_fp0_format.op == mm_fadd_op) 212102cedc3SLeonid Yegoshin func = fadd_op; 213102cedc3SLeonid Yegoshin else if (insn.mm_fp0_format.op == mm_fsub_op) 214102cedc3SLeonid Yegoshin func = fsub_op; 215102cedc3SLeonid Yegoshin else if (insn.mm_fp0_format.op == mm_fmul_op) 216102cedc3SLeonid Yegoshin func = fmul_op; 217102cedc3SLeonid Yegoshin else if (insn.mm_fp0_format.op == mm_fdiv_op) 218102cedc3SLeonid Yegoshin func = fdiv_op; 219102cedc3SLeonid Yegoshin if (func != -1) { 220102cedc3SLeonid Yegoshin mips32_insn.fp0_format.opcode = cop1_op; 221102cedc3SLeonid Yegoshin mips32_insn.fp0_format.fmt = 222102cedc3SLeonid Yegoshin sdps_format[insn.mm_fp0_format.fmt]; 223102cedc3SLeonid Yegoshin mips32_insn.fp0_format.ft = 224102cedc3SLeonid Yegoshin insn.mm_fp0_format.ft; 225102cedc3SLeonid Yegoshin mips32_insn.fp0_format.fs = 226102cedc3SLeonid Yegoshin insn.mm_fp0_format.fs; 227102cedc3SLeonid Yegoshin mips32_insn.fp0_format.fd = 228102cedc3SLeonid Yegoshin insn.mm_fp0_format.fd; 229102cedc3SLeonid Yegoshin mips32_insn.fp0_format.func = func; 230102cedc3SLeonid Yegoshin } else 231102cedc3SLeonid Yegoshin return SIGILL; 232102cedc3SLeonid Yegoshin break; 233102cedc3SLeonid Yegoshin case mm_32f_70_op: 234102cedc3SLeonid Yegoshin func = -1; /* Invalid */ 235102cedc3SLeonid Yegoshin if (insn.mm_fp0_format.op == mm_fmovn_op) 236102cedc3SLeonid Yegoshin func = fmovn_op; 237102cedc3SLeonid Yegoshin else if (insn.mm_fp0_format.op == mm_fmovz_op) 238102cedc3SLeonid Yegoshin func = fmovz_op; 239102cedc3SLeonid Yegoshin if (func != -1) { 240102cedc3SLeonid Yegoshin mips32_insn.fp0_format.opcode = cop1_op; 241102cedc3SLeonid Yegoshin mips32_insn.fp0_format.fmt = 242102cedc3SLeonid Yegoshin sdps_format[insn.mm_fp0_format.fmt]; 243102cedc3SLeonid Yegoshin mips32_insn.fp0_format.ft = 244102cedc3SLeonid Yegoshin insn.mm_fp0_format.ft; 245102cedc3SLeonid Yegoshin mips32_insn.fp0_format.fs = 246102cedc3SLeonid Yegoshin insn.mm_fp0_format.fs; 247102cedc3SLeonid Yegoshin mips32_insn.fp0_format.fd = 248102cedc3SLeonid Yegoshin insn.mm_fp0_format.fd; 249102cedc3SLeonid Yegoshin mips32_insn.fp0_format.func = func; 250102cedc3SLeonid Yegoshin } else 251102cedc3SLeonid Yegoshin return SIGILL; 252102cedc3SLeonid Yegoshin break; 253102cedc3SLeonid Yegoshin case mm_32f_73_op: /* POOL32FXF */ 254102cedc3SLeonid Yegoshin switch (insn.mm_fp1_format.op) { 255102cedc3SLeonid Yegoshin case mm_movf0_op: 256102cedc3SLeonid Yegoshin case mm_movf1_op: 257102cedc3SLeonid Yegoshin case mm_movt0_op: 258102cedc3SLeonid Yegoshin case mm_movt1_op: 259102cedc3SLeonid Yegoshin if ((insn.mm_fp1_format.op & 0x7f) == 260102cedc3SLeonid Yegoshin mm_movf0_op) 261102cedc3SLeonid Yegoshin op = 0; 262102cedc3SLeonid Yegoshin else 263102cedc3SLeonid Yegoshin op = 1; 264102cedc3SLeonid Yegoshin mips32_insn.r_format.opcode = spec_op; 265102cedc3SLeonid Yegoshin mips32_insn.r_format.rs = insn.mm_fp4_format.fs; 266102cedc3SLeonid Yegoshin mips32_insn.r_format.rt = 267102cedc3SLeonid Yegoshin (insn.mm_fp4_format.cc << 2) + op; 268102cedc3SLeonid Yegoshin mips32_insn.r_format.rd = insn.mm_fp4_format.rt; 269102cedc3SLeonid Yegoshin mips32_insn.r_format.re = 0; 270102cedc3SLeonid Yegoshin mips32_insn.r_format.func = movc_op; 271102cedc3SLeonid Yegoshin break; 272102cedc3SLeonid Yegoshin case mm_fcvtd0_op: 273102cedc3SLeonid Yegoshin case mm_fcvtd1_op: 274102cedc3SLeonid Yegoshin case mm_fcvts0_op: 275102cedc3SLeonid Yegoshin case mm_fcvts1_op: 276102cedc3SLeonid Yegoshin if ((insn.mm_fp1_format.op & 0x7f) == 277102cedc3SLeonid Yegoshin mm_fcvtd0_op) { 278102cedc3SLeonid Yegoshin func = fcvtd_op; 279102cedc3SLeonid Yegoshin fmt = swl_format[insn.mm_fp3_format.fmt]; 280102cedc3SLeonid Yegoshin } else { 281102cedc3SLeonid Yegoshin func = fcvts_op; 282102cedc3SLeonid Yegoshin fmt = dwl_format[insn.mm_fp3_format.fmt]; 283102cedc3SLeonid Yegoshin } 284102cedc3SLeonid Yegoshin mips32_insn.fp0_format.opcode = cop1_op; 285102cedc3SLeonid Yegoshin mips32_insn.fp0_format.fmt = fmt; 286102cedc3SLeonid Yegoshin mips32_insn.fp0_format.ft = 0; 287102cedc3SLeonid Yegoshin mips32_insn.fp0_format.fs = 288102cedc3SLeonid Yegoshin insn.mm_fp3_format.fs; 289102cedc3SLeonid Yegoshin mips32_insn.fp0_format.fd = 290102cedc3SLeonid Yegoshin insn.mm_fp3_format.rt; 291102cedc3SLeonid Yegoshin mips32_insn.fp0_format.func = func; 292102cedc3SLeonid Yegoshin break; 293102cedc3SLeonid Yegoshin case mm_fmov0_op: 294102cedc3SLeonid Yegoshin case mm_fmov1_op: 295102cedc3SLeonid Yegoshin case mm_fabs0_op: 296102cedc3SLeonid Yegoshin case mm_fabs1_op: 297102cedc3SLeonid Yegoshin case mm_fneg0_op: 298102cedc3SLeonid Yegoshin case mm_fneg1_op: 299102cedc3SLeonid Yegoshin if ((insn.mm_fp1_format.op & 0x7f) == 300102cedc3SLeonid Yegoshin mm_fmov0_op) 301102cedc3SLeonid Yegoshin func = fmov_op; 302102cedc3SLeonid Yegoshin else if ((insn.mm_fp1_format.op & 0x7f) == 303102cedc3SLeonid Yegoshin mm_fabs0_op) 304102cedc3SLeonid Yegoshin func = fabs_op; 305102cedc3SLeonid Yegoshin else 306102cedc3SLeonid Yegoshin func = fneg_op; 307102cedc3SLeonid Yegoshin mips32_insn.fp0_format.opcode = cop1_op; 308102cedc3SLeonid Yegoshin mips32_insn.fp0_format.fmt = 309102cedc3SLeonid Yegoshin sdps_format[insn.mm_fp3_format.fmt]; 310102cedc3SLeonid Yegoshin mips32_insn.fp0_format.ft = 0; 311102cedc3SLeonid Yegoshin mips32_insn.fp0_format.fs = 312102cedc3SLeonid Yegoshin insn.mm_fp3_format.fs; 313102cedc3SLeonid Yegoshin mips32_insn.fp0_format.fd = 314102cedc3SLeonid Yegoshin insn.mm_fp3_format.rt; 315102cedc3SLeonid Yegoshin mips32_insn.fp0_format.func = func; 316102cedc3SLeonid Yegoshin break; 317102cedc3SLeonid Yegoshin case mm_ffloorl_op: 318102cedc3SLeonid Yegoshin case mm_ffloorw_op: 319102cedc3SLeonid Yegoshin case mm_fceill_op: 320102cedc3SLeonid Yegoshin case mm_fceilw_op: 321102cedc3SLeonid Yegoshin case mm_ftruncl_op: 322102cedc3SLeonid Yegoshin case mm_ftruncw_op: 323102cedc3SLeonid Yegoshin case mm_froundl_op: 324102cedc3SLeonid Yegoshin case mm_froundw_op: 325102cedc3SLeonid Yegoshin case mm_fcvtl_op: 326102cedc3SLeonid Yegoshin case mm_fcvtw_op: 327102cedc3SLeonid Yegoshin if (insn.mm_fp1_format.op == mm_ffloorl_op) 328102cedc3SLeonid Yegoshin func = ffloorl_op; 329102cedc3SLeonid Yegoshin else if (insn.mm_fp1_format.op == mm_ffloorw_op) 330102cedc3SLeonid Yegoshin func = ffloor_op; 331102cedc3SLeonid Yegoshin else if (insn.mm_fp1_format.op == mm_fceill_op) 332102cedc3SLeonid Yegoshin func = fceill_op; 333102cedc3SLeonid Yegoshin else if (insn.mm_fp1_format.op == mm_fceilw_op) 334102cedc3SLeonid Yegoshin func = fceil_op; 335102cedc3SLeonid Yegoshin else if (insn.mm_fp1_format.op == mm_ftruncl_op) 336102cedc3SLeonid Yegoshin func = ftruncl_op; 337102cedc3SLeonid Yegoshin else if (insn.mm_fp1_format.op == mm_ftruncw_op) 338102cedc3SLeonid Yegoshin func = ftrunc_op; 339102cedc3SLeonid Yegoshin else if (insn.mm_fp1_format.op == mm_froundl_op) 340102cedc3SLeonid Yegoshin func = froundl_op; 341102cedc3SLeonid Yegoshin else if (insn.mm_fp1_format.op == mm_froundw_op) 342102cedc3SLeonid Yegoshin func = fround_op; 343102cedc3SLeonid Yegoshin else if (insn.mm_fp1_format.op == mm_fcvtl_op) 344102cedc3SLeonid Yegoshin func = fcvtl_op; 345102cedc3SLeonid Yegoshin else 346102cedc3SLeonid Yegoshin func = fcvtw_op; 347102cedc3SLeonid Yegoshin mips32_insn.fp0_format.opcode = cop1_op; 348102cedc3SLeonid Yegoshin mips32_insn.fp0_format.fmt = 349102cedc3SLeonid Yegoshin sd_format[insn.mm_fp1_format.fmt]; 350102cedc3SLeonid Yegoshin mips32_insn.fp0_format.ft = 0; 351102cedc3SLeonid Yegoshin mips32_insn.fp0_format.fs = 352102cedc3SLeonid Yegoshin insn.mm_fp1_format.fs; 353102cedc3SLeonid Yegoshin mips32_insn.fp0_format.fd = 354102cedc3SLeonid Yegoshin insn.mm_fp1_format.rt; 355102cedc3SLeonid Yegoshin mips32_insn.fp0_format.func = func; 356102cedc3SLeonid Yegoshin break; 357102cedc3SLeonid Yegoshin case mm_frsqrt_op: 358102cedc3SLeonid Yegoshin case mm_fsqrt_op: 359102cedc3SLeonid Yegoshin case mm_frecip_op: 360102cedc3SLeonid Yegoshin if (insn.mm_fp1_format.op == mm_frsqrt_op) 361102cedc3SLeonid Yegoshin func = frsqrt_op; 362102cedc3SLeonid Yegoshin else if (insn.mm_fp1_format.op == mm_fsqrt_op) 363102cedc3SLeonid Yegoshin func = fsqrt_op; 364102cedc3SLeonid Yegoshin else 365102cedc3SLeonid Yegoshin func = frecip_op; 366102cedc3SLeonid Yegoshin mips32_insn.fp0_format.opcode = cop1_op; 367102cedc3SLeonid Yegoshin mips32_insn.fp0_format.fmt = 368102cedc3SLeonid Yegoshin sdps_format[insn.mm_fp1_format.fmt]; 369102cedc3SLeonid Yegoshin mips32_insn.fp0_format.ft = 0; 370102cedc3SLeonid Yegoshin mips32_insn.fp0_format.fs = 371102cedc3SLeonid Yegoshin insn.mm_fp1_format.fs; 372102cedc3SLeonid Yegoshin mips32_insn.fp0_format.fd = 373102cedc3SLeonid Yegoshin insn.mm_fp1_format.rt; 374102cedc3SLeonid Yegoshin mips32_insn.fp0_format.func = func; 375102cedc3SLeonid Yegoshin break; 376102cedc3SLeonid Yegoshin case mm_mfc1_op: 377102cedc3SLeonid Yegoshin case mm_mtc1_op: 378102cedc3SLeonid Yegoshin case mm_cfc1_op: 379102cedc3SLeonid Yegoshin case mm_ctc1_op: 3809355e59cSSteven J. Hill case mm_mfhc1_op: 3819355e59cSSteven J. Hill case mm_mthc1_op: 382102cedc3SLeonid Yegoshin if (insn.mm_fp1_format.op == mm_mfc1_op) 383102cedc3SLeonid Yegoshin op = mfc_op; 384102cedc3SLeonid Yegoshin else if (insn.mm_fp1_format.op == mm_mtc1_op) 385102cedc3SLeonid Yegoshin op = mtc_op; 386102cedc3SLeonid Yegoshin else if (insn.mm_fp1_format.op == mm_cfc1_op) 387102cedc3SLeonid Yegoshin op = cfc_op; 3889355e59cSSteven J. Hill else if (insn.mm_fp1_format.op == mm_ctc1_op) 389102cedc3SLeonid Yegoshin op = ctc_op; 3909355e59cSSteven J. Hill else if (insn.mm_fp1_format.op == mm_mfhc1_op) 3919355e59cSSteven J. Hill op = mfhc_op; 3929355e59cSSteven J. Hill else 3939355e59cSSteven J. Hill op = mthc_op; 394102cedc3SLeonid Yegoshin mips32_insn.fp1_format.opcode = cop1_op; 395102cedc3SLeonid Yegoshin mips32_insn.fp1_format.op = op; 396102cedc3SLeonid Yegoshin mips32_insn.fp1_format.rt = 397102cedc3SLeonid Yegoshin insn.mm_fp1_format.rt; 398102cedc3SLeonid Yegoshin mips32_insn.fp1_format.fs = 399102cedc3SLeonid Yegoshin insn.mm_fp1_format.fs; 400102cedc3SLeonid Yegoshin mips32_insn.fp1_format.fd = 0; 401102cedc3SLeonid Yegoshin mips32_insn.fp1_format.func = 0; 402102cedc3SLeonid Yegoshin break; 403102cedc3SLeonid Yegoshin default: 404102cedc3SLeonid Yegoshin return SIGILL; 405102cedc3SLeonid Yegoshin } 406102cedc3SLeonid Yegoshin break; 407102cedc3SLeonid Yegoshin case mm_32f_74_op: /* c.cond.fmt */ 408102cedc3SLeonid Yegoshin mips32_insn.fp0_format.opcode = cop1_op; 409102cedc3SLeonid Yegoshin mips32_insn.fp0_format.fmt = 410102cedc3SLeonid Yegoshin sdps_format[insn.mm_fp4_format.fmt]; 411102cedc3SLeonid Yegoshin mips32_insn.fp0_format.ft = insn.mm_fp4_format.rt; 412102cedc3SLeonid Yegoshin mips32_insn.fp0_format.fs = insn.mm_fp4_format.fs; 413102cedc3SLeonid Yegoshin mips32_insn.fp0_format.fd = insn.mm_fp4_format.cc << 2; 414102cedc3SLeonid Yegoshin mips32_insn.fp0_format.func = 415102cedc3SLeonid Yegoshin insn.mm_fp4_format.cond | MM_MIPS32_COND_FC; 416102cedc3SLeonid Yegoshin break; 417102cedc3SLeonid Yegoshin default: 418102cedc3SLeonid Yegoshin return SIGILL; 419102cedc3SLeonid Yegoshin } 420102cedc3SLeonid Yegoshin break; 421102cedc3SLeonid Yegoshin default: 422102cedc3SLeonid Yegoshin return SIGILL; 423102cedc3SLeonid Yegoshin } 424102cedc3SLeonid Yegoshin 425102cedc3SLeonid Yegoshin *insn_ptr = mips32_insn; 426102cedc3SLeonid Yegoshin return 0; 427102cedc3SLeonid Yegoshin } 428102cedc3SLeonid Yegoshin 4291da177e4SLinus Torvalds /* 4301da177e4SLinus Torvalds * Redundant with logic already in kernel/branch.c, 4311da177e4SLinus Torvalds * embedded in compute_return_epc. At some point, 4321da177e4SLinus Torvalds * a single subroutine should be used across both 4331da177e4SLinus Torvalds * modules. 4341da177e4SLinus Torvalds */ 435102cedc3SLeonid Yegoshin static int isBranchInstr(struct pt_regs *regs, struct mm_decoded_insn dec_insn, 436102cedc3SLeonid Yegoshin unsigned long *contpc) 4371da177e4SLinus Torvalds { 438102cedc3SLeonid Yegoshin union mips_instruction insn = (union mips_instruction)dec_insn.insn; 439102cedc3SLeonid Yegoshin unsigned int fcr31; 440102cedc3SLeonid Yegoshin unsigned int bit = 0; 441102cedc3SLeonid Yegoshin 442102cedc3SLeonid Yegoshin switch (insn.i_format.opcode) { 4431da177e4SLinus Torvalds case spec_op: 444102cedc3SLeonid Yegoshin switch (insn.r_format.func) { 4451da177e4SLinus Torvalds case jalr_op: 446102cedc3SLeonid Yegoshin regs->regs[insn.r_format.rd] = 447102cedc3SLeonid Yegoshin regs->cp0_epc + dec_insn.pc_inc + 448102cedc3SLeonid Yegoshin dec_insn.next_pc_inc; 449102cedc3SLeonid Yegoshin /* Fall through */ 4501da177e4SLinus Torvalds case jr_op: 4515f9f41c4SMarkos Chandras /* For R6, JR already emulated in jalr_op */ 4525f9f41c4SMarkos Chandras if (NO_R6EMU && insn.r_format.opcode == jr_op) 4535f9f41c4SMarkos Chandras break; 454102cedc3SLeonid Yegoshin *contpc = regs->regs[insn.r_format.rs]; 4551da177e4SLinus Torvalds return 1; 4561da177e4SLinus Torvalds } 4571da177e4SLinus Torvalds break; 4581da177e4SLinus Torvalds case bcond_op: 459102cedc3SLeonid Yegoshin switch (insn.i_format.rt) { 4601da177e4SLinus Torvalds case bltzal_op: 4611da177e4SLinus Torvalds case bltzall_op: 462319824eaSMarkos Chandras if (NO_R6EMU && (insn.i_format.rs || 463319824eaSMarkos Chandras insn.i_format.rt == bltzall_op)) 464319824eaSMarkos Chandras break; 465319824eaSMarkos Chandras 466102cedc3SLeonid Yegoshin regs->regs[31] = regs->cp0_epc + 467102cedc3SLeonid Yegoshin dec_insn.pc_inc + 468102cedc3SLeonid Yegoshin dec_insn.next_pc_inc; 469102cedc3SLeonid Yegoshin /* Fall through */ 470102cedc3SLeonid Yegoshin case bltzl_op: 471319824eaSMarkos Chandras if (NO_R6EMU) 472319824eaSMarkos Chandras break; 473319824eaSMarkos Chandras case bltz_op: 474102cedc3SLeonid Yegoshin if ((long)regs->regs[insn.i_format.rs] < 0) 475102cedc3SLeonid Yegoshin *contpc = regs->cp0_epc + 476102cedc3SLeonid Yegoshin dec_insn.pc_inc + 477102cedc3SLeonid Yegoshin (insn.i_format.simmediate << 2); 478102cedc3SLeonid Yegoshin else 479102cedc3SLeonid Yegoshin *contpc = regs->cp0_epc + 480102cedc3SLeonid Yegoshin dec_insn.pc_inc + 481102cedc3SLeonid Yegoshin dec_insn.next_pc_inc; 4821da177e4SLinus Torvalds return 1; 483102cedc3SLeonid Yegoshin case bgezal_op: 484102cedc3SLeonid Yegoshin case bgezall_op: 485319824eaSMarkos Chandras if (NO_R6EMU && (insn.i_format.rs || 486319824eaSMarkos Chandras insn.i_format.rt == bgezall_op)) 487319824eaSMarkos Chandras break; 488319824eaSMarkos Chandras 489102cedc3SLeonid Yegoshin regs->regs[31] = regs->cp0_epc + 490102cedc3SLeonid Yegoshin dec_insn.pc_inc + 491102cedc3SLeonid Yegoshin dec_insn.next_pc_inc; 492102cedc3SLeonid Yegoshin /* Fall through */ 493102cedc3SLeonid Yegoshin case bgezl_op: 494319824eaSMarkos Chandras if (NO_R6EMU) 495319824eaSMarkos Chandras break; 496319824eaSMarkos Chandras case bgez_op: 497102cedc3SLeonid Yegoshin if ((long)regs->regs[insn.i_format.rs] >= 0) 498102cedc3SLeonid Yegoshin *contpc = regs->cp0_epc + 499102cedc3SLeonid Yegoshin dec_insn.pc_inc + 500102cedc3SLeonid Yegoshin (insn.i_format.simmediate << 2); 501102cedc3SLeonid Yegoshin else 502102cedc3SLeonid Yegoshin *contpc = regs->cp0_epc + 503102cedc3SLeonid Yegoshin dec_insn.pc_inc + 504102cedc3SLeonid Yegoshin dec_insn.next_pc_inc; 505102cedc3SLeonid Yegoshin return 1; 5061da177e4SLinus Torvalds } 5071da177e4SLinus Torvalds break; 5081da177e4SLinus Torvalds case jalx_op: 509102cedc3SLeonid Yegoshin set_isa16_mode(bit); 510102cedc3SLeonid Yegoshin case jal_op: 511102cedc3SLeonid Yegoshin regs->regs[31] = regs->cp0_epc + 512102cedc3SLeonid Yegoshin dec_insn.pc_inc + 513102cedc3SLeonid Yegoshin dec_insn.next_pc_inc; 514102cedc3SLeonid Yegoshin /* Fall through */ 515102cedc3SLeonid Yegoshin case j_op: 516102cedc3SLeonid Yegoshin *contpc = regs->cp0_epc + dec_insn.pc_inc; 517102cedc3SLeonid Yegoshin *contpc >>= 28; 518102cedc3SLeonid Yegoshin *contpc <<= 28; 519102cedc3SLeonid Yegoshin *contpc |= (insn.j_format.target << 2); 520102cedc3SLeonid Yegoshin /* Set microMIPS mode bit: XOR for jalx. */ 521102cedc3SLeonid Yegoshin *contpc ^= bit; 5221da177e4SLinus Torvalds return 1; 523102cedc3SLeonid Yegoshin case beql_op: 524319824eaSMarkos Chandras if (NO_R6EMU) 525319824eaSMarkos Chandras break; 526319824eaSMarkos Chandras case beq_op: 527102cedc3SLeonid Yegoshin if (regs->regs[insn.i_format.rs] == 528102cedc3SLeonid Yegoshin regs->regs[insn.i_format.rt]) 529102cedc3SLeonid Yegoshin *contpc = regs->cp0_epc + 530102cedc3SLeonid Yegoshin dec_insn.pc_inc + 531102cedc3SLeonid Yegoshin (insn.i_format.simmediate << 2); 532102cedc3SLeonid Yegoshin else 533102cedc3SLeonid Yegoshin *contpc = regs->cp0_epc + 534102cedc3SLeonid Yegoshin dec_insn.pc_inc + 535102cedc3SLeonid Yegoshin dec_insn.next_pc_inc; 536102cedc3SLeonid Yegoshin return 1; 537102cedc3SLeonid Yegoshin case bnel_op: 538319824eaSMarkos Chandras if (NO_R6EMU) 539319824eaSMarkos Chandras break; 540319824eaSMarkos Chandras case bne_op: 541102cedc3SLeonid Yegoshin if (regs->regs[insn.i_format.rs] != 542102cedc3SLeonid Yegoshin regs->regs[insn.i_format.rt]) 543102cedc3SLeonid Yegoshin *contpc = regs->cp0_epc + 544102cedc3SLeonid Yegoshin dec_insn.pc_inc + 545102cedc3SLeonid Yegoshin (insn.i_format.simmediate << 2); 546102cedc3SLeonid Yegoshin else 547102cedc3SLeonid Yegoshin *contpc = regs->cp0_epc + 548102cedc3SLeonid Yegoshin dec_insn.pc_inc + 549102cedc3SLeonid Yegoshin dec_insn.next_pc_inc; 550102cedc3SLeonid Yegoshin return 1; 551102cedc3SLeonid Yegoshin case blezl_op: 552319824eaSMarkos Chandras if (NO_R6EMU) 553319824eaSMarkos Chandras break; 554319824eaSMarkos Chandras case blez_op: 555a8ff66f5SMarkos Chandras 556a8ff66f5SMarkos Chandras /* 557a8ff66f5SMarkos Chandras * Compact branches for R6 for the 558a8ff66f5SMarkos Chandras * blez and blezl opcodes. 559a8ff66f5SMarkos Chandras * BLEZ | rs = 0 | rt != 0 == BLEZALC 560a8ff66f5SMarkos Chandras * BLEZ | rs = rt != 0 == BGEZALC 561a8ff66f5SMarkos Chandras * BLEZ | rs != 0 | rt != 0 == BGEUC 562a8ff66f5SMarkos Chandras * BLEZL | rs = 0 | rt != 0 == BLEZC 563a8ff66f5SMarkos Chandras * BLEZL | rs = rt != 0 == BGEZC 564a8ff66f5SMarkos Chandras * BLEZL | rs != 0 | rt != 0 == BGEC 565a8ff66f5SMarkos Chandras * 566a8ff66f5SMarkos Chandras * For real BLEZ{,L}, rt is always 0. 567a8ff66f5SMarkos Chandras */ 568a8ff66f5SMarkos Chandras if (cpu_has_mips_r6 && insn.i_format.rt) { 569a8ff66f5SMarkos Chandras if ((insn.i_format.opcode == blez_op) && 570a8ff66f5SMarkos Chandras ((!insn.i_format.rs && insn.i_format.rt) || 571a8ff66f5SMarkos Chandras (insn.i_format.rs == insn.i_format.rt))) 572a8ff66f5SMarkos Chandras regs->regs[31] = regs->cp0_epc + 573a8ff66f5SMarkos Chandras dec_insn.pc_inc; 574a8ff66f5SMarkos Chandras *contpc = regs->cp0_epc + dec_insn.pc_inc + 575a8ff66f5SMarkos Chandras dec_insn.next_pc_inc; 576a8ff66f5SMarkos Chandras 577a8ff66f5SMarkos Chandras return 1; 578a8ff66f5SMarkos Chandras } 579102cedc3SLeonid Yegoshin if ((long)regs->regs[insn.i_format.rs] <= 0) 580102cedc3SLeonid Yegoshin *contpc = regs->cp0_epc + 581102cedc3SLeonid Yegoshin dec_insn.pc_inc + 582102cedc3SLeonid Yegoshin (insn.i_format.simmediate << 2); 583102cedc3SLeonid Yegoshin else 584102cedc3SLeonid Yegoshin *contpc = regs->cp0_epc + 585102cedc3SLeonid Yegoshin dec_insn.pc_inc + 586102cedc3SLeonid Yegoshin dec_insn.next_pc_inc; 587102cedc3SLeonid Yegoshin return 1; 588102cedc3SLeonid Yegoshin case bgtzl_op: 589319824eaSMarkos Chandras if (NO_R6EMU) 590319824eaSMarkos Chandras break; 591319824eaSMarkos Chandras case bgtz_op: 592f1b44067SMarkos Chandras /* 593f1b44067SMarkos Chandras * Compact branches for R6 for the 594f1b44067SMarkos Chandras * bgtz and bgtzl opcodes. 595f1b44067SMarkos Chandras * BGTZ | rs = 0 | rt != 0 == BGTZALC 596f1b44067SMarkos Chandras * BGTZ | rs = rt != 0 == BLTZALC 597f1b44067SMarkos Chandras * BGTZ | rs != 0 | rt != 0 == BLTUC 598f1b44067SMarkos Chandras * BGTZL | rs = 0 | rt != 0 == BGTZC 599f1b44067SMarkos Chandras * BGTZL | rs = rt != 0 == BLTZC 600f1b44067SMarkos Chandras * BGTZL | rs != 0 | rt != 0 == BLTC 601f1b44067SMarkos Chandras * 602f1b44067SMarkos Chandras * *ZALC varint for BGTZ &&& rt != 0 603f1b44067SMarkos Chandras * For real GTZ{,L}, rt is always 0. 604f1b44067SMarkos Chandras */ 605f1b44067SMarkos Chandras if (cpu_has_mips_r6 && insn.i_format.rt) { 606f1b44067SMarkos Chandras if ((insn.i_format.opcode == blez_op) && 607f1b44067SMarkos Chandras ((!insn.i_format.rs && insn.i_format.rt) || 608f1b44067SMarkos Chandras (insn.i_format.rs == insn.i_format.rt))) 609f1b44067SMarkos Chandras regs->regs[31] = regs->cp0_epc + 610f1b44067SMarkos Chandras dec_insn.pc_inc; 611f1b44067SMarkos Chandras *contpc = regs->cp0_epc + dec_insn.pc_inc + 612f1b44067SMarkos Chandras dec_insn.next_pc_inc; 613f1b44067SMarkos Chandras 614f1b44067SMarkos Chandras return 1; 615f1b44067SMarkos Chandras } 616f1b44067SMarkos Chandras 617102cedc3SLeonid Yegoshin if ((long)regs->regs[insn.i_format.rs] > 0) 618102cedc3SLeonid Yegoshin *contpc = regs->cp0_epc + 619102cedc3SLeonid Yegoshin dec_insn.pc_inc + 620102cedc3SLeonid Yegoshin (insn.i_format.simmediate << 2); 621102cedc3SLeonid Yegoshin else 622102cedc3SLeonid Yegoshin *contpc = regs->cp0_epc + 623102cedc3SLeonid Yegoshin dec_insn.pc_inc + 624102cedc3SLeonid Yegoshin dec_insn.next_pc_inc; 625102cedc3SLeonid Yegoshin return 1; 626c893ce38SMarkos Chandras case cbcond0_op: 62710d962d5SMarkos Chandras case cbcond1_op: 628c893ce38SMarkos Chandras if (!cpu_has_mips_r6) 629c893ce38SMarkos Chandras break; 630c893ce38SMarkos Chandras if (insn.i_format.rt && !insn.i_format.rs) 631c893ce38SMarkos Chandras regs->regs[31] = regs->cp0_epc + 4; 632c893ce38SMarkos Chandras *contpc = regs->cp0_epc + dec_insn.pc_inc + 633c893ce38SMarkos Chandras dec_insn.next_pc_inc; 634c893ce38SMarkos Chandras 635c893ce38SMarkos Chandras return 1; 636c26d4219SDavid Daney #ifdef CONFIG_CPU_CAVIUM_OCTEON 637c26d4219SDavid Daney case lwc2_op: /* This is bbit0 on Octeon */ 638c26d4219SDavid Daney if ((regs->regs[insn.i_format.rs] & (1ull<<insn.i_format.rt)) == 0) 639c26d4219SDavid Daney *contpc = regs->cp0_epc + 4 + (insn.i_format.simmediate << 2); 640c26d4219SDavid Daney else 641c26d4219SDavid Daney *contpc = regs->cp0_epc + 8; 642c26d4219SDavid Daney return 1; 643c26d4219SDavid Daney case ldc2_op: /* This is bbit032 on Octeon */ 644c26d4219SDavid Daney if ((regs->regs[insn.i_format.rs] & (1ull<<(insn.i_format.rt + 32))) == 0) 645c26d4219SDavid Daney *contpc = regs->cp0_epc + 4 + (insn.i_format.simmediate << 2); 646c26d4219SDavid Daney else 647c26d4219SDavid Daney *contpc = regs->cp0_epc + 8; 648c26d4219SDavid Daney return 1; 649c26d4219SDavid Daney case swc2_op: /* This is bbit1 on Octeon */ 650c26d4219SDavid Daney if (regs->regs[insn.i_format.rs] & (1ull<<insn.i_format.rt)) 651c26d4219SDavid Daney *contpc = regs->cp0_epc + 4 + (insn.i_format.simmediate << 2); 652c26d4219SDavid Daney else 653c26d4219SDavid Daney *contpc = regs->cp0_epc + 8; 654c26d4219SDavid Daney return 1; 655c26d4219SDavid Daney case sdc2_op: /* This is bbit132 on Octeon */ 656c26d4219SDavid Daney if (regs->regs[insn.i_format.rs] & (1ull<<(insn.i_format.rt + 32))) 657c26d4219SDavid Daney *contpc = regs->cp0_epc + 4 + (insn.i_format.simmediate << 2); 658c26d4219SDavid Daney else 659c26d4219SDavid Daney *contpc = regs->cp0_epc + 8; 660c26d4219SDavid Daney return 1; 6618467ca01SMarkos Chandras #else 6628467ca01SMarkos Chandras case bc6_op: 6638467ca01SMarkos Chandras /* 6648467ca01SMarkos Chandras * Only valid for MIPS R6 but we can still end up 6658467ca01SMarkos Chandras * here from a broken userland so just tell emulator 6668467ca01SMarkos Chandras * this is not a branch and let it break later on. 6678467ca01SMarkos Chandras */ 6688467ca01SMarkos Chandras if (!cpu_has_mips_r6) 6698467ca01SMarkos Chandras break; 6708467ca01SMarkos Chandras *contpc = regs->cp0_epc + dec_insn.pc_inc + 6718467ca01SMarkos Chandras dec_insn.next_pc_inc; 6728467ca01SMarkos Chandras 6738467ca01SMarkos Chandras return 1; 674*84fef630SMarkos Chandras case balc6_op: 675*84fef630SMarkos Chandras if (!cpu_has_mips_r6) 676*84fef630SMarkos Chandras break; 677*84fef630SMarkos Chandras regs->regs[31] = regs->cp0_epc + 4; 678*84fef630SMarkos Chandras *contpc = regs->cp0_epc + dec_insn.pc_inc + 679*84fef630SMarkos Chandras dec_insn.next_pc_inc; 680*84fef630SMarkos Chandras 681*84fef630SMarkos Chandras return 1; 682c26d4219SDavid Daney #endif 6831da177e4SLinus Torvalds case cop0_op: 6841da177e4SLinus Torvalds case cop1_op: 685c8a34581SMarkos Chandras /* Need to check for R6 bc1nez and bc1eqz branches */ 686c8a34581SMarkos Chandras if (cpu_has_mips_r6 && 687c8a34581SMarkos Chandras ((insn.i_format.rs == bc1eqz_op) || 688c8a34581SMarkos Chandras (insn.i_format.rs == bc1nez_op))) { 689c8a34581SMarkos Chandras bit = 0; 690c8a34581SMarkos Chandras switch (insn.i_format.rs) { 691c8a34581SMarkos Chandras case bc1eqz_op: 692c8a34581SMarkos Chandras if (get_fpr32(¤t->thread.fpu.fpr[insn.i_format.rt], 0) & 0x1) 693c8a34581SMarkos Chandras bit = 1; 694c8a34581SMarkos Chandras break; 695c8a34581SMarkos Chandras case bc1nez_op: 696c8a34581SMarkos Chandras if (!(get_fpr32(¤t->thread.fpu.fpr[insn.i_format.rt], 0) & 0x1)) 697c8a34581SMarkos Chandras bit = 1; 698c8a34581SMarkos Chandras break; 699c8a34581SMarkos Chandras } 700c8a34581SMarkos Chandras if (bit) 701c8a34581SMarkos Chandras *contpc = regs->cp0_epc + 702c8a34581SMarkos Chandras dec_insn.pc_inc + 703c8a34581SMarkos Chandras (insn.i_format.simmediate << 2); 704c8a34581SMarkos Chandras else 705c8a34581SMarkos Chandras *contpc = regs->cp0_epc + 706c8a34581SMarkos Chandras dec_insn.pc_inc + 707c8a34581SMarkos Chandras dec_insn.next_pc_inc; 708c8a34581SMarkos Chandras 709c8a34581SMarkos Chandras return 1; 710c8a34581SMarkos Chandras } 711c8a34581SMarkos Chandras /* R2/R6 compatible cop1 instruction. Fall through */ 7121da177e4SLinus Torvalds case cop2_op: 7131da177e4SLinus Torvalds case cop1x_op: 714102cedc3SLeonid Yegoshin if (insn.i_format.rs == bc_op) { 715102cedc3SLeonid Yegoshin preempt_disable(); 716102cedc3SLeonid Yegoshin if (is_fpu_owner()) 717842dfc11SManuel Lauss fcr31 = read_32bit_cp1_register(CP1_STATUS); 718102cedc3SLeonid Yegoshin else 719102cedc3SLeonid Yegoshin fcr31 = current->thread.fpu.fcr31; 720102cedc3SLeonid Yegoshin preempt_enable(); 721102cedc3SLeonid Yegoshin 722102cedc3SLeonid Yegoshin bit = (insn.i_format.rt >> 2); 723102cedc3SLeonid Yegoshin bit += (bit != 0); 724102cedc3SLeonid Yegoshin bit += 23; 725102cedc3SLeonid Yegoshin switch (insn.i_format.rt & 3) { 726102cedc3SLeonid Yegoshin case 0: /* bc1f */ 727102cedc3SLeonid Yegoshin case 2: /* bc1fl */ 728102cedc3SLeonid Yegoshin if (~fcr31 & (1 << bit)) 729102cedc3SLeonid Yegoshin *contpc = regs->cp0_epc + 730102cedc3SLeonid Yegoshin dec_insn.pc_inc + 731102cedc3SLeonid Yegoshin (insn.i_format.simmediate << 2); 732102cedc3SLeonid Yegoshin else 733102cedc3SLeonid Yegoshin *contpc = regs->cp0_epc + 734102cedc3SLeonid Yegoshin dec_insn.pc_inc + 735102cedc3SLeonid Yegoshin dec_insn.next_pc_inc; 736102cedc3SLeonid Yegoshin return 1; 737102cedc3SLeonid Yegoshin case 1: /* bc1t */ 738102cedc3SLeonid Yegoshin case 3: /* bc1tl */ 739102cedc3SLeonid Yegoshin if (fcr31 & (1 << bit)) 740102cedc3SLeonid Yegoshin *contpc = regs->cp0_epc + 741102cedc3SLeonid Yegoshin dec_insn.pc_inc + 742102cedc3SLeonid Yegoshin (insn.i_format.simmediate << 2); 743102cedc3SLeonid Yegoshin else 744102cedc3SLeonid Yegoshin *contpc = regs->cp0_epc + 745102cedc3SLeonid Yegoshin dec_insn.pc_inc + 746102cedc3SLeonid Yegoshin dec_insn.next_pc_inc; 7471da177e4SLinus Torvalds return 1; 7481da177e4SLinus Torvalds } 749102cedc3SLeonid Yegoshin } 750102cedc3SLeonid Yegoshin break; 751102cedc3SLeonid Yegoshin } 7521da177e4SLinus Torvalds return 0; 7531da177e4SLinus Torvalds } 7541da177e4SLinus Torvalds 7551da177e4SLinus Torvalds /* 7561da177e4SLinus Torvalds * In the Linux kernel, we support selection of FPR format on the 757da0bac33SDavid Daney * basis of the Status.FR bit. If an FPU is not present, the FR bit 758da0bac33SDavid Daney * is hardwired to zero, which would imply a 32-bit FPU even for 759597ce172SPaul Burton * 64-bit CPUs so we rather look at TIF_32BIT_FPREGS. 76051d943f0SRalf Baechle * FPU emu is slow and bulky and optimizing this function offers fairly 76151d943f0SRalf Baechle * sizeable benefits so we try to be clever and make this function return 76251d943f0SRalf Baechle * a constant whenever possible, that is on 64-bit kernels without O32 763597ce172SPaul Burton * compatibility enabled and on 32-bit without 64-bit FPU support. 7641da177e4SLinus Torvalds */ 765da0bac33SDavid Daney static inline int cop1_64bit(struct pt_regs *xcp) 766da0bac33SDavid Daney { 76708a07904SRalf Baechle if (config_enabled(CONFIG_64BIT) && !config_enabled(CONFIG_MIPS32_O32)) 76851d943f0SRalf Baechle return 1; 76908a07904SRalf Baechle else if (config_enabled(CONFIG_32BIT) && 77008a07904SRalf Baechle !config_enabled(CONFIG_MIPS_O32_FP64_SUPPORT)) 771da0bac33SDavid Daney return 0; 77208a07904SRalf Baechle 773597ce172SPaul Burton return !test_thread_flag(TIF_32BIT_FPREGS); 774da0bac33SDavid Daney } 7751da177e4SLinus Torvalds 7764227a2d4SPaul Burton static inline bool hybrid_fprs(void) 7774227a2d4SPaul Burton { 7784227a2d4SPaul Burton return test_thread_flag(TIF_HYBRID_FPREGS); 7794227a2d4SPaul Burton } 7804227a2d4SPaul Burton 78147fa0c02SRalf Baechle #define SIFROMREG(si, x) \ 78247fa0c02SRalf Baechle do { \ 7834227a2d4SPaul Burton if (cop1_64bit(xcp) && !hybrid_fprs()) \ 784c8c0da6bSPaul Burton (si) = (int)get_fpr32(&ctx->fpr[x], 0); \ 785bbd426f5SPaul Burton else \ 786c8c0da6bSPaul Burton (si) = (int)get_fpr32(&ctx->fpr[(x) & ~1], (x) & 1); \ 787bbd426f5SPaul Burton } while (0) 788da0bac33SDavid Daney 78947fa0c02SRalf Baechle #define SITOREG(si, x) \ 79047fa0c02SRalf Baechle do { \ 7914227a2d4SPaul Burton if (cop1_64bit(xcp) && !hybrid_fprs()) { \ 792ef1c47afSPaul Burton unsigned i; \ 793bbd426f5SPaul Burton set_fpr32(&ctx->fpr[x], 0, si); \ 794ef1c47afSPaul Burton for (i = 1; i < ARRAY_SIZE(ctx->fpr[x].val32); i++) \ 795ef1c47afSPaul Burton set_fpr32(&ctx->fpr[x], i, 0); \ 796ef1c47afSPaul Burton } else { \ 797bbd426f5SPaul Burton set_fpr32(&ctx->fpr[(x) & ~1], (x) & 1, si); \ 798ef1c47afSPaul Burton } \ 799bbd426f5SPaul Burton } while (0) 8001da177e4SLinus Torvalds 801c8c0da6bSPaul Burton #define SIFROMHREG(si, x) ((si) = (int)get_fpr32(&ctx->fpr[x], 1)) 802ef1c47afSPaul Burton 80347fa0c02SRalf Baechle #define SITOHREG(si, x) \ 80447fa0c02SRalf Baechle do { \ 805ef1c47afSPaul Burton unsigned i; \ 806ef1c47afSPaul Burton set_fpr32(&ctx->fpr[x], 1, si); \ 807ef1c47afSPaul Burton for (i = 2; i < ARRAY_SIZE(ctx->fpr[x].val32); i++) \ 808ef1c47afSPaul Burton set_fpr32(&ctx->fpr[x], i, 0); \ 809ef1c47afSPaul Burton } while (0) 8101ac94400SLeonid Yegoshin 811bbd426f5SPaul Burton #define DIFROMREG(di, x) \ 812bbd426f5SPaul Burton ((di) = get_fpr64(&ctx->fpr[(x) & ~(cop1_64bit(xcp) == 0)], 0)) 813bbd426f5SPaul Burton 81447fa0c02SRalf Baechle #define DITOREG(di, x) \ 81547fa0c02SRalf Baechle do { \ 816ef1c47afSPaul Burton unsigned fpr, i; \ 817ef1c47afSPaul Burton fpr = (x) & ~(cop1_64bit(xcp) == 0); \ 818ef1c47afSPaul Burton set_fpr64(&ctx->fpr[fpr], 0, di); \ 819ef1c47afSPaul Burton for (i = 1; i < ARRAY_SIZE(ctx->fpr[x].val64); i++) \ 820ef1c47afSPaul Burton set_fpr64(&ctx->fpr[fpr], i, 0); \ 821ef1c47afSPaul Burton } while (0) 8221da177e4SLinus Torvalds 8231da177e4SLinus Torvalds #define SPFROMREG(sp, x) SIFROMREG((sp).bits, x) 8241da177e4SLinus Torvalds #define SPTOREG(sp, x) SITOREG((sp).bits, x) 8251da177e4SLinus Torvalds #define DPFROMREG(dp, x) DIFROMREG((dp).bits, x) 8261da177e4SLinus Torvalds #define DPTOREG(dp, x) DITOREG((dp).bits, x) 8271da177e4SLinus Torvalds 8281da177e4SLinus Torvalds /* 8291da177e4SLinus Torvalds * Emulate the single floating point instruction pointed at by EPC. 8301da177e4SLinus Torvalds * Two instructions if the instruction is in a branch delay slot. 8311da177e4SLinus Torvalds */ 8321da177e4SLinus Torvalds 833515b029dSDavid Daney static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_struct *ctx, 834102cedc3SLeonid Yegoshin struct mm_decoded_insn dec_insn, void *__user *fault_addr) 8351da177e4SLinus Torvalds { 836102cedc3SLeonid Yegoshin unsigned long contpc = xcp->cp0_epc + dec_insn.pc_inc; 8373f7cac41SRalf Baechle unsigned int cond, cbit; 8383f7cac41SRalf Baechle mips_instruction ir; 8393f7cac41SRalf Baechle int likely, pc_inc; 8403f7cac41SRalf Baechle u32 __user *wva; 8413f7cac41SRalf Baechle u64 __user *dva; 8423f7cac41SRalf Baechle u32 value; 8433f7cac41SRalf Baechle u32 wval; 8443f7cac41SRalf Baechle u64 dval; 8453f7cac41SRalf Baechle int sig; 8461da177e4SLinus Torvalds 84770e4c234SRalf Baechle /* 84870e4c234SRalf Baechle * These are giving gcc a gentle hint about what to expect in 84970e4c234SRalf Baechle * dec_inst in order to do better optimization. 85070e4c234SRalf Baechle */ 85170e4c234SRalf Baechle if (!cpu_has_mmips && dec_insn.micro_mips_mode) 85270e4c234SRalf Baechle unreachable(); 85370e4c234SRalf Baechle 8541da177e4SLinus Torvalds /* XXX NEC Vr54xx bug workaround */ 855e7e9cae5SRalf Baechle if (delay_slot(xcp)) { 856102cedc3SLeonid Yegoshin if (dec_insn.micro_mips_mode) { 857102cedc3SLeonid Yegoshin if (!mm_isBranchInstr(xcp, dec_insn, &contpc)) 858e7e9cae5SRalf Baechle clear_delay_slot(xcp); 859102cedc3SLeonid Yegoshin } else { 860102cedc3SLeonid Yegoshin if (!isBranchInstr(xcp, dec_insn, &contpc)) 861e7e9cae5SRalf Baechle clear_delay_slot(xcp); 862102cedc3SLeonid Yegoshin } 863102cedc3SLeonid Yegoshin } 8641da177e4SLinus Torvalds 865e7e9cae5SRalf Baechle if (delay_slot(xcp)) { 8661da177e4SLinus Torvalds /* 8671da177e4SLinus Torvalds * The instruction to be emulated is in a branch delay slot 8681da177e4SLinus Torvalds * which means that we have to emulate the branch instruction 8691da177e4SLinus Torvalds * BEFORE we do the cop1 instruction. 8701da177e4SLinus Torvalds * 8711da177e4SLinus Torvalds * This branch could be a COP1 branch, but in that case we 8721da177e4SLinus Torvalds * would have had a trap for that instruction, and would not 8731da177e4SLinus Torvalds * come through this route. 8741da177e4SLinus Torvalds * 8751da177e4SLinus Torvalds * Linux MIPS branch emulator operates on context, updating the 8761da177e4SLinus Torvalds * cp0_epc. 8771da177e4SLinus Torvalds */ 878102cedc3SLeonid Yegoshin ir = dec_insn.next_insn; /* process delay slot instr */ 879102cedc3SLeonid Yegoshin pc_inc = dec_insn.next_pc_inc; 880333d1f67SRalf Baechle } else { 881102cedc3SLeonid Yegoshin ir = dec_insn.insn; /* process current instr */ 882102cedc3SLeonid Yegoshin pc_inc = dec_insn.pc_inc; 883102cedc3SLeonid Yegoshin } 884102cedc3SLeonid Yegoshin 885102cedc3SLeonid Yegoshin /* 886102cedc3SLeonid Yegoshin * Since microMIPS FPU instructios are a subset of MIPS32 FPU 887102cedc3SLeonid Yegoshin * instructions, we want to convert microMIPS FPU instructions 888102cedc3SLeonid Yegoshin * into MIPS32 instructions so that we could reuse all of the 889102cedc3SLeonid Yegoshin * FPU emulation code. 890102cedc3SLeonid Yegoshin * 891102cedc3SLeonid Yegoshin * NOTE: We cannot do this for branch instructions since they 892102cedc3SLeonid Yegoshin * are not a subset. Example: Cannot emulate a 16-bit 893102cedc3SLeonid Yegoshin * aligned target address with a MIPS32 instruction. 894102cedc3SLeonid Yegoshin */ 895102cedc3SLeonid Yegoshin if (dec_insn.micro_mips_mode) { 896102cedc3SLeonid Yegoshin /* 897102cedc3SLeonid Yegoshin * If next instruction is a 16-bit instruction, then it 898102cedc3SLeonid Yegoshin * it cannot be a FPU instruction. This could happen 899102cedc3SLeonid Yegoshin * since we can be called for non-FPU instructions. 900102cedc3SLeonid Yegoshin */ 901102cedc3SLeonid Yegoshin if ((pc_inc == 2) || 902102cedc3SLeonid Yegoshin (microMIPS32_to_MIPS32((union mips_instruction *)&ir) 903102cedc3SLeonid Yegoshin == SIGILL)) 904102cedc3SLeonid Yegoshin return SIGILL; 9051da177e4SLinus Torvalds } 9061da177e4SLinus Torvalds 9071da177e4SLinus Torvalds emul: 908a8b0ca17SPeter Zijlstra perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 1, xcp, 0); 909b6ee75edSDavid Daney MIPS_FPU_EMU_INC_STATS(emulated); 9101da177e4SLinus Torvalds switch (MIPSInst_OPCODE(ir)) { 9113f7cac41SRalf Baechle case ldc1_op: 9123f7cac41SRalf Baechle dva = (u64 __user *) (xcp->regs[MIPSInst_RS(ir)] + 9131da177e4SLinus Torvalds MIPSInst_SIMM(ir)); 914b6ee75edSDavid Daney MIPS_FPU_EMU_INC_STATS(loads); 915515b029dSDavid Daney 9163f7cac41SRalf Baechle if (!access_ok(VERIFY_READ, dva, sizeof(u64))) { 917b6ee75edSDavid Daney MIPS_FPU_EMU_INC_STATS(errors); 9183f7cac41SRalf Baechle *fault_addr = dva; 9191da177e4SLinus Torvalds return SIGBUS; 9201da177e4SLinus Torvalds } 9213f7cac41SRalf Baechle if (__get_user(dval, dva)) { 922515b029dSDavid Daney MIPS_FPU_EMU_INC_STATS(errors); 9233f7cac41SRalf Baechle *fault_addr = dva; 924515b029dSDavid Daney return SIGSEGV; 925515b029dSDavid Daney } 9263f7cac41SRalf Baechle DITOREG(dval, MIPSInst_RT(ir)); 9271da177e4SLinus Torvalds break; 9281da177e4SLinus Torvalds 9293f7cac41SRalf Baechle case sdc1_op: 9303f7cac41SRalf Baechle dva = (u64 __user *) (xcp->regs[MIPSInst_RS(ir)] + 9311da177e4SLinus Torvalds MIPSInst_SIMM(ir)); 932b6ee75edSDavid Daney MIPS_FPU_EMU_INC_STATS(stores); 9333f7cac41SRalf Baechle DIFROMREG(dval, MIPSInst_RT(ir)); 9343f7cac41SRalf Baechle if (!access_ok(VERIFY_WRITE, dva, sizeof(u64))) { 935b6ee75edSDavid Daney MIPS_FPU_EMU_INC_STATS(errors); 9363f7cac41SRalf Baechle *fault_addr = dva; 9371da177e4SLinus Torvalds return SIGBUS; 9381da177e4SLinus Torvalds } 9393f7cac41SRalf Baechle if (__put_user(dval, dva)) { 940515b029dSDavid Daney MIPS_FPU_EMU_INC_STATS(errors); 9413f7cac41SRalf Baechle *fault_addr = dva; 942515b029dSDavid Daney return SIGSEGV; 943515b029dSDavid Daney } 9441da177e4SLinus Torvalds break; 9451da177e4SLinus Torvalds 9463f7cac41SRalf Baechle case lwc1_op: 9473f7cac41SRalf Baechle wva = (u32 __user *) (xcp->regs[MIPSInst_RS(ir)] + 9481da177e4SLinus Torvalds MIPSInst_SIMM(ir)); 949b6ee75edSDavid Daney MIPS_FPU_EMU_INC_STATS(loads); 9503f7cac41SRalf Baechle if (!access_ok(VERIFY_READ, wva, sizeof(u32))) { 951b6ee75edSDavid Daney MIPS_FPU_EMU_INC_STATS(errors); 9523f7cac41SRalf Baechle *fault_addr = wva; 9531da177e4SLinus Torvalds return SIGBUS; 9541da177e4SLinus Torvalds } 9553f7cac41SRalf Baechle if (__get_user(wval, wva)) { 956515b029dSDavid Daney MIPS_FPU_EMU_INC_STATS(errors); 9573f7cac41SRalf Baechle *fault_addr = wva; 958515b029dSDavid Daney return SIGSEGV; 959515b029dSDavid Daney } 9603f7cac41SRalf Baechle SITOREG(wval, MIPSInst_RT(ir)); 9611da177e4SLinus Torvalds break; 9621da177e4SLinus Torvalds 9633f7cac41SRalf Baechle case swc1_op: 9643f7cac41SRalf Baechle wva = (u32 __user *) (xcp->regs[MIPSInst_RS(ir)] + 9651da177e4SLinus Torvalds MIPSInst_SIMM(ir)); 966b6ee75edSDavid Daney MIPS_FPU_EMU_INC_STATS(stores); 9673f7cac41SRalf Baechle SIFROMREG(wval, MIPSInst_RT(ir)); 9683f7cac41SRalf Baechle if (!access_ok(VERIFY_WRITE, wva, sizeof(u32))) { 969b6ee75edSDavid Daney MIPS_FPU_EMU_INC_STATS(errors); 9703f7cac41SRalf Baechle *fault_addr = wva; 9711da177e4SLinus Torvalds return SIGBUS; 9721da177e4SLinus Torvalds } 9733f7cac41SRalf Baechle if (__put_user(wval, wva)) { 974515b029dSDavid Daney MIPS_FPU_EMU_INC_STATS(errors); 9753f7cac41SRalf Baechle *fault_addr = wva; 976515b029dSDavid Daney return SIGSEGV; 977515b029dSDavid Daney } 9781da177e4SLinus Torvalds break; 9791da177e4SLinus Torvalds 9801da177e4SLinus Torvalds case cop1_op: 9811da177e4SLinus Torvalds switch (MIPSInst_RS(ir)) { 9821da177e4SLinus Torvalds case dmfc_op: 98308a07904SRalf Baechle if (!cpu_has_mips_3_4_5 && !cpu_has_mips64) 98408a07904SRalf Baechle return SIGILL; 98508a07904SRalf Baechle 9861da177e4SLinus Torvalds /* copregister fs -> gpr[rt] */ 9871da177e4SLinus Torvalds if (MIPSInst_RT(ir) != 0) { 9881da177e4SLinus Torvalds DIFROMREG(xcp->regs[MIPSInst_RT(ir)], 9891da177e4SLinus Torvalds MIPSInst_RD(ir)); 9901da177e4SLinus Torvalds } 9911da177e4SLinus Torvalds break; 9921da177e4SLinus Torvalds 9931da177e4SLinus Torvalds case dmtc_op: 99408a07904SRalf Baechle if (!cpu_has_mips_3_4_5 && !cpu_has_mips64) 99508a07904SRalf Baechle return SIGILL; 99608a07904SRalf Baechle 9971da177e4SLinus Torvalds /* copregister fs <- rt */ 9981da177e4SLinus Torvalds DITOREG(xcp->regs[MIPSInst_RT(ir)], MIPSInst_RD(ir)); 9991da177e4SLinus Torvalds break; 10001da177e4SLinus Torvalds 10011ac94400SLeonid Yegoshin case mfhc_op: 10021ac94400SLeonid Yegoshin if (!cpu_has_mips_r2) 10031ac94400SLeonid Yegoshin goto sigill; 10041ac94400SLeonid Yegoshin 10051ac94400SLeonid Yegoshin /* copregister rd -> gpr[rt] */ 10061ac94400SLeonid Yegoshin if (MIPSInst_RT(ir) != 0) { 10071ac94400SLeonid Yegoshin SIFROMHREG(xcp->regs[MIPSInst_RT(ir)], 10081ac94400SLeonid Yegoshin MIPSInst_RD(ir)); 10091ac94400SLeonid Yegoshin } 10101ac94400SLeonid Yegoshin break; 10111ac94400SLeonid Yegoshin 10121ac94400SLeonid Yegoshin case mthc_op: 10131ac94400SLeonid Yegoshin if (!cpu_has_mips_r2) 10141ac94400SLeonid Yegoshin goto sigill; 10151ac94400SLeonid Yegoshin 10161ac94400SLeonid Yegoshin /* copregister rd <- gpr[rt] */ 10171ac94400SLeonid Yegoshin SITOHREG(xcp->regs[MIPSInst_RT(ir)], MIPSInst_RD(ir)); 10181ac94400SLeonid Yegoshin break; 10191ac94400SLeonid Yegoshin 10201da177e4SLinus Torvalds case mfc_op: 10211da177e4SLinus Torvalds /* copregister rd -> gpr[rt] */ 10221da177e4SLinus Torvalds if (MIPSInst_RT(ir) != 0) { 10231da177e4SLinus Torvalds SIFROMREG(xcp->regs[MIPSInst_RT(ir)], 10241da177e4SLinus Torvalds MIPSInst_RD(ir)); 10251da177e4SLinus Torvalds } 10261da177e4SLinus Torvalds break; 10271da177e4SLinus Torvalds 10281da177e4SLinus Torvalds case mtc_op: 10291da177e4SLinus Torvalds /* copregister rd <- rt */ 10301da177e4SLinus Torvalds SITOREG(xcp->regs[MIPSInst_RT(ir)], MIPSInst_RD(ir)); 10311da177e4SLinus Torvalds break; 10321da177e4SLinus Torvalds 10333f7cac41SRalf Baechle case cfc_op: 10341da177e4SLinus Torvalds /* cop control register rd -> gpr[rt] */ 10351da177e4SLinus Torvalds if (MIPSInst_RD(ir) == FPCREG_CSR) { 10361da177e4SLinus Torvalds value = ctx->fcr31; 103756a64733SRalf Baechle value = (value & ~FPU_CSR_RM) | modeindex(value); 103892df0f8bSRalf Baechle pr_debug("%p gpr[%d]<-csr=%08x\n", 1039333d1f67SRalf Baechle (void *) (xcp->cp0_epc), 10401da177e4SLinus Torvalds MIPSInst_RT(ir), value); 10411da177e4SLinus Torvalds } 10421da177e4SLinus Torvalds else if (MIPSInst_RD(ir) == FPCREG_RID) 10431da177e4SLinus Torvalds value = 0; 10441da177e4SLinus Torvalds else 10451da177e4SLinus Torvalds value = 0; 10461da177e4SLinus Torvalds if (MIPSInst_RT(ir)) 10471da177e4SLinus Torvalds xcp->regs[MIPSInst_RT(ir)] = value; 10481da177e4SLinus Torvalds break; 10491da177e4SLinus Torvalds 10503f7cac41SRalf Baechle case ctc_op: 10511da177e4SLinus Torvalds /* copregister rd <- rt */ 10521da177e4SLinus Torvalds if (MIPSInst_RT(ir) == 0) 10531da177e4SLinus Torvalds value = 0; 10541da177e4SLinus Torvalds else 10551da177e4SLinus Torvalds value = xcp->regs[MIPSInst_RT(ir)]; 10561da177e4SLinus Torvalds 10571da177e4SLinus Torvalds /* we only have one writable control reg 10581da177e4SLinus Torvalds */ 10591da177e4SLinus Torvalds if (MIPSInst_RD(ir) == FPCREG_CSR) { 106092df0f8bSRalf Baechle pr_debug("%p gpr[%d]->csr=%08x\n", 1061333d1f67SRalf Baechle (void *) (xcp->cp0_epc), 10621da177e4SLinus Torvalds MIPSInst_RT(ir), value); 106395e8f634SShane McDonald 106495e8f634SShane McDonald /* 106595e8f634SShane McDonald * Don't write reserved bits, 106695e8f634SShane McDonald * and convert to ieee library modes 106795e8f634SShane McDonald */ 106856a64733SRalf Baechle ctx->fcr31 = (value & ~(FPU_CSR_RSVD | FPU_CSR_RM)) | 106956a64733SRalf Baechle modeindex(value); 10701da177e4SLinus Torvalds } 10711da177e4SLinus Torvalds if ((ctx->fcr31 >> 5) & ctx->fcr31 & FPU_CSR_ALL_E) { 10721da177e4SLinus Torvalds return SIGFPE; 10731da177e4SLinus Torvalds } 10741da177e4SLinus Torvalds break; 10751da177e4SLinus Torvalds 10763f7cac41SRalf Baechle case bc_op: 1077e7e9cae5SRalf Baechle if (delay_slot(xcp)) 10781da177e4SLinus Torvalds return SIGILL; 10791da177e4SLinus Torvalds 108008a07904SRalf Baechle if (cpu_has_mips_4_5_r) 108108a07904SRalf Baechle cbit = fpucondbit[MIPSInst_RT(ir) >> 2]; 108208a07904SRalf Baechle else 108308a07904SRalf Baechle cbit = FPU_CSR_COND; 108408a07904SRalf Baechle cond = ctx->fcr31 & cbit; 108508a07904SRalf Baechle 10863f7cac41SRalf Baechle likely = 0; 10871da177e4SLinus Torvalds switch (MIPSInst_RT(ir) & 3) { 10881da177e4SLinus Torvalds case bcfl_op: 10891da177e4SLinus Torvalds likely = 1; 10901da177e4SLinus Torvalds case bcf_op: 10911da177e4SLinus Torvalds cond = !cond; 10921da177e4SLinus Torvalds break; 10931da177e4SLinus Torvalds case bctl_op: 10941da177e4SLinus Torvalds likely = 1; 10951da177e4SLinus Torvalds case bct_op: 10961da177e4SLinus Torvalds break; 10971da177e4SLinus Torvalds default: 10981da177e4SLinus Torvalds /* thats an illegal instruction */ 10991da177e4SLinus Torvalds return SIGILL; 11001da177e4SLinus Torvalds } 11011da177e4SLinus Torvalds 1102e7e9cae5SRalf Baechle set_delay_slot(xcp); 11031da177e4SLinus Torvalds if (cond) { 11043f7cac41SRalf Baechle /* 11053f7cac41SRalf Baechle * Branch taken: emulate dslot instruction 11061da177e4SLinus Torvalds */ 1107102cedc3SLeonid Yegoshin xcp->cp0_epc += dec_insn.pc_inc; 11081da177e4SLinus Torvalds 1109102cedc3SLeonid Yegoshin contpc = MIPSInst_SIMM(ir); 1110102cedc3SLeonid Yegoshin ir = dec_insn.next_insn; 1111102cedc3SLeonid Yegoshin if (dec_insn.micro_mips_mode) { 1112102cedc3SLeonid Yegoshin contpc = (xcp->cp0_epc + (contpc << 1)); 1113102cedc3SLeonid Yegoshin 1114102cedc3SLeonid Yegoshin /* If 16-bit instruction, not FPU. */ 1115102cedc3SLeonid Yegoshin if ((dec_insn.next_pc_inc == 2) || 1116102cedc3SLeonid Yegoshin (microMIPS32_to_MIPS32((union mips_instruction *)&ir) == SIGILL)) { 1117102cedc3SLeonid Yegoshin 1118102cedc3SLeonid Yegoshin /* 1119102cedc3SLeonid Yegoshin * Since this instruction will 1120102cedc3SLeonid Yegoshin * be put on the stack with 1121102cedc3SLeonid Yegoshin * 32-bit words, get around 1122102cedc3SLeonid Yegoshin * this problem by putting a 1123102cedc3SLeonid Yegoshin * NOP16 as the second one. 1124102cedc3SLeonid Yegoshin */ 1125102cedc3SLeonid Yegoshin if (dec_insn.next_pc_inc == 2) 1126102cedc3SLeonid Yegoshin ir = (ir & (~0xffff)) | MM_NOP16; 1127102cedc3SLeonid Yegoshin 1128102cedc3SLeonid Yegoshin /* 1129102cedc3SLeonid Yegoshin * Single step the non-CP1 1130102cedc3SLeonid Yegoshin * instruction in the dslot. 1131102cedc3SLeonid Yegoshin */ 1132102cedc3SLeonid Yegoshin return mips_dsemul(xcp, ir, contpc); 1133515b029dSDavid Daney } 1134102cedc3SLeonid Yegoshin } else 1135102cedc3SLeonid Yegoshin contpc = (xcp->cp0_epc + (contpc << 2)); 11361da177e4SLinus Torvalds 11371da177e4SLinus Torvalds switch (MIPSInst_OPCODE(ir)) { 11381da177e4SLinus Torvalds case lwc1_op: 113908a07904SRalf Baechle goto emul; 11403f7cac41SRalf Baechle 11411da177e4SLinus Torvalds case swc1_op: 114208a07904SRalf Baechle goto emul; 11433f7cac41SRalf Baechle 11441da177e4SLinus Torvalds case ldc1_op: 11451da177e4SLinus Torvalds case sdc1_op: 114608a07904SRalf Baechle if (cpu_has_mips_2_3_4_5 || 114708a07904SRalf Baechle cpu_has_mips64) 114808a07904SRalf Baechle goto emul; 114908a07904SRalf Baechle 115008a07904SRalf Baechle return SIGILL; 115108a07904SRalf Baechle goto emul; 11523f7cac41SRalf Baechle 11531da177e4SLinus Torvalds case cop1_op: 115408a07904SRalf Baechle goto emul; 11553f7cac41SRalf Baechle 11561da177e4SLinus Torvalds case cop1x_op: 1157a5466d7bSMarkos Chandras if (cpu_has_mips_4_5 || cpu_has_mips64 || cpu_has_mips32r2) 11581da177e4SLinus Torvalds /* its one of ours */ 11591da177e4SLinus Torvalds goto emul; 116008a07904SRalf Baechle 116108a07904SRalf Baechle return SIGILL; 11623f7cac41SRalf Baechle 11631da177e4SLinus Torvalds case spec_op: 116408a07904SRalf Baechle if (!cpu_has_mips_4_5_r) 116508a07904SRalf Baechle return SIGILL; 116608a07904SRalf Baechle 11671da177e4SLinus Torvalds if (MIPSInst_FUNC(ir) == movc_op) 11681da177e4SLinus Torvalds goto emul; 11691da177e4SLinus Torvalds break; 11701da177e4SLinus Torvalds } 11711da177e4SLinus Torvalds 11721da177e4SLinus Torvalds /* 11731da177e4SLinus Torvalds * Single step the non-cp1 11741da177e4SLinus Torvalds * instruction in the dslot 11751da177e4SLinus Torvalds */ 1176e70dfc10SAtsushi Nemoto return mips_dsemul(xcp, ir, contpc); 11773f7cac41SRalf Baechle } else if (likely) { /* branch not taken */ 11781da177e4SLinus Torvalds /* 11791da177e4SLinus Torvalds * branch likely nullifies 11801da177e4SLinus Torvalds * dslot if not taken 11811da177e4SLinus Torvalds */ 1182102cedc3SLeonid Yegoshin xcp->cp0_epc += dec_insn.pc_inc; 1183102cedc3SLeonid Yegoshin contpc += dec_insn.pc_inc; 11841da177e4SLinus Torvalds /* 11851da177e4SLinus Torvalds * else continue & execute 11861da177e4SLinus Torvalds * dslot as normal insn 11871da177e4SLinus Torvalds */ 11881da177e4SLinus Torvalds } 11891da177e4SLinus Torvalds break; 11901da177e4SLinus Torvalds 11911da177e4SLinus Torvalds default: 11921da177e4SLinus Torvalds if (!(MIPSInst_RS(ir) & 0x10)) 11931da177e4SLinus Torvalds return SIGILL; 11941da177e4SLinus Torvalds 11951da177e4SLinus Torvalds /* a real fpu computation instruction */ 11961da177e4SLinus Torvalds if ((sig = fpu_emu(xcp, ctx, ir))) 11971da177e4SLinus Torvalds return sig; 11981da177e4SLinus Torvalds } 11991da177e4SLinus Torvalds break; 12001da177e4SLinus Torvalds 12013f7cac41SRalf Baechle case cop1x_op: 1202a5466d7bSMarkos Chandras if (!cpu_has_mips_4_5 && !cpu_has_mips64 && !cpu_has_mips32r2) 120308a07904SRalf Baechle return SIGILL; 120408a07904SRalf Baechle 120508a07904SRalf Baechle sig = fpux_emu(xcp, ctx, ir, fault_addr); 1206515b029dSDavid Daney if (sig) 12071da177e4SLinus Torvalds return sig; 12081da177e4SLinus Torvalds break; 12091da177e4SLinus Torvalds 12101da177e4SLinus Torvalds case spec_op: 121108a07904SRalf Baechle if (!cpu_has_mips_4_5_r) 121208a07904SRalf Baechle return SIGILL; 121308a07904SRalf Baechle 12141da177e4SLinus Torvalds if (MIPSInst_FUNC(ir) != movc_op) 12151da177e4SLinus Torvalds return SIGILL; 12161da177e4SLinus Torvalds cond = fpucondbit[MIPSInst_RT(ir) >> 2]; 12171da177e4SLinus Torvalds if (((ctx->fcr31 & cond) != 0) == ((MIPSInst_RT(ir) & 1) != 0)) 12181da177e4SLinus Torvalds xcp->regs[MIPSInst_RD(ir)] = 12191da177e4SLinus Torvalds xcp->regs[MIPSInst_RS(ir)]; 12201da177e4SLinus Torvalds break; 12211da177e4SLinus Torvalds default: 12221ac94400SLeonid Yegoshin sigill: 12231da177e4SLinus Torvalds return SIGILL; 12241da177e4SLinus Torvalds } 12251da177e4SLinus Torvalds 12261da177e4SLinus Torvalds /* we did it !! */ 1227e70dfc10SAtsushi Nemoto xcp->cp0_epc = contpc; 1228e7e9cae5SRalf Baechle clear_delay_slot(xcp); 1229333d1f67SRalf Baechle 12301da177e4SLinus Torvalds return 0; 12311da177e4SLinus Torvalds } 12321da177e4SLinus Torvalds 12331da177e4SLinus Torvalds /* 12341da177e4SLinus Torvalds * Conversion table from MIPS compare ops 48-63 12351da177e4SLinus Torvalds * cond = ieee754dp_cmp(x,y,IEEE754_UN,sig); 12361da177e4SLinus Torvalds */ 12371da177e4SLinus Torvalds static const unsigned char cmptab[8] = { 12381da177e4SLinus Torvalds 0, /* cmp_0 (sig) cmp_sf */ 12391da177e4SLinus Torvalds IEEE754_CUN, /* cmp_un (sig) cmp_ngle */ 12401da177e4SLinus Torvalds IEEE754_CEQ, /* cmp_eq (sig) cmp_seq */ 12411da177e4SLinus Torvalds IEEE754_CEQ | IEEE754_CUN, /* cmp_ueq (sig) cmp_ngl */ 12421da177e4SLinus Torvalds IEEE754_CLT, /* cmp_olt (sig) cmp_lt */ 12431da177e4SLinus Torvalds IEEE754_CLT | IEEE754_CUN, /* cmp_ult (sig) cmp_nge */ 12441da177e4SLinus Torvalds IEEE754_CLT | IEEE754_CEQ, /* cmp_ole (sig) cmp_le */ 12451da177e4SLinus Torvalds IEEE754_CLT | IEEE754_CEQ | IEEE754_CUN, /* cmp_ule (sig) cmp_ngt */ 12461da177e4SLinus Torvalds }; 12471da177e4SLinus Torvalds 12481da177e4SLinus Torvalds 12491da177e4SLinus Torvalds /* 12501da177e4SLinus Torvalds * Additional MIPS4 instructions 12511da177e4SLinus Torvalds */ 12521da177e4SLinus Torvalds 12531da177e4SLinus Torvalds #define DEF3OP(name, p, f1, f2, f3) \ 125447fa0c02SRalf Baechle static union ieee754##p fpemu_##p##_##name(union ieee754##p r, \ 125547fa0c02SRalf Baechle union ieee754##p s, union ieee754##p t) \ 12561da177e4SLinus Torvalds { \ 1257cd21dfcfSRalf Baechle struct _ieee754_csr ieee754_csr_save; \ 12581da177e4SLinus Torvalds s = f1(s, t); \ 12591da177e4SLinus Torvalds ieee754_csr_save = ieee754_csr; \ 12601da177e4SLinus Torvalds s = f2(s, r); \ 12611da177e4SLinus Torvalds ieee754_csr_save.cx |= ieee754_csr.cx; \ 12621da177e4SLinus Torvalds ieee754_csr_save.sx |= ieee754_csr.sx; \ 12631da177e4SLinus Torvalds s = f3(s); \ 12641da177e4SLinus Torvalds ieee754_csr.cx |= ieee754_csr_save.cx; \ 12651da177e4SLinus Torvalds ieee754_csr.sx |= ieee754_csr_save.sx; \ 12661da177e4SLinus Torvalds return s; \ 12671da177e4SLinus Torvalds } 12681da177e4SLinus Torvalds 12692209bcb1SRalf Baechle static union ieee754dp fpemu_dp_recip(union ieee754dp d) 12701da177e4SLinus Torvalds { 12711da177e4SLinus Torvalds return ieee754dp_div(ieee754dp_one(0), d); 12721da177e4SLinus Torvalds } 12731da177e4SLinus Torvalds 12742209bcb1SRalf Baechle static union ieee754dp fpemu_dp_rsqrt(union ieee754dp d) 12751da177e4SLinus Torvalds { 12761da177e4SLinus Torvalds return ieee754dp_div(ieee754dp_one(0), ieee754dp_sqrt(d)); 12771da177e4SLinus Torvalds } 12781da177e4SLinus Torvalds 12792209bcb1SRalf Baechle static union ieee754sp fpemu_sp_recip(union ieee754sp s) 12801da177e4SLinus Torvalds { 12811da177e4SLinus Torvalds return ieee754sp_div(ieee754sp_one(0), s); 12821da177e4SLinus Torvalds } 12831da177e4SLinus Torvalds 12842209bcb1SRalf Baechle static union ieee754sp fpemu_sp_rsqrt(union ieee754sp s) 12851da177e4SLinus Torvalds { 12861da177e4SLinus Torvalds return ieee754sp_div(ieee754sp_one(0), ieee754sp_sqrt(s)); 12871da177e4SLinus Torvalds } 12881da177e4SLinus Torvalds 12891da177e4SLinus Torvalds DEF3OP(madd, sp, ieee754sp_mul, ieee754sp_add, ); 12901da177e4SLinus Torvalds DEF3OP(msub, sp, ieee754sp_mul, ieee754sp_sub, ); 12911da177e4SLinus Torvalds DEF3OP(nmadd, sp, ieee754sp_mul, ieee754sp_add, ieee754sp_neg); 12921da177e4SLinus Torvalds DEF3OP(nmsub, sp, ieee754sp_mul, ieee754sp_sub, ieee754sp_neg); 12931da177e4SLinus Torvalds DEF3OP(madd, dp, ieee754dp_mul, ieee754dp_add, ); 12941da177e4SLinus Torvalds DEF3OP(msub, dp, ieee754dp_mul, ieee754dp_sub, ); 12951da177e4SLinus Torvalds DEF3OP(nmadd, dp, ieee754dp_mul, ieee754dp_add, ieee754dp_neg); 12961da177e4SLinus Torvalds DEF3OP(nmsub, dp, ieee754dp_mul, ieee754dp_sub, ieee754dp_neg); 12971da177e4SLinus Torvalds 1298eae89076SAtsushi Nemoto static int fpux_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx, 1299515b029dSDavid Daney mips_instruction ir, void *__user *fault_addr) 13001da177e4SLinus Torvalds { 13011da177e4SLinus Torvalds unsigned rcsr = 0; /* resulting csr */ 13021da177e4SLinus Torvalds 1303b6ee75edSDavid Daney MIPS_FPU_EMU_INC_STATS(cp1xops); 13041da177e4SLinus Torvalds 13051da177e4SLinus Torvalds switch (MIPSInst_FMA_FFMT(ir)) { 13061da177e4SLinus Torvalds case s_fmt:{ /* 0 */ 13071da177e4SLinus Torvalds 13082209bcb1SRalf Baechle union ieee754sp(*handler) (union ieee754sp, union ieee754sp, union ieee754sp); 13092209bcb1SRalf Baechle union ieee754sp fd, fr, fs, ft; 13103fccc015SRalf Baechle u32 __user *va; 13111da177e4SLinus Torvalds u32 val; 13121da177e4SLinus Torvalds 13131da177e4SLinus Torvalds switch (MIPSInst_FUNC(ir)) { 13141da177e4SLinus Torvalds case lwxc1_op: 13153fccc015SRalf Baechle va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] + 13161da177e4SLinus Torvalds xcp->regs[MIPSInst_FT(ir)]); 13171da177e4SLinus Torvalds 1318b6ee75edSDavid Daney MIPS_FPU_EMU_INC_STATS(loads); 1319515b029dSDavid Daney if (!access_ok(VERIFY_READ, va, sizeof(u32))) { 1320b6ee75edSDavid Daney MIPS_FPU_EMU_INC_STATS(errors); 1321515b029dSDavid Daney *fault_addr = va; 13221da177e4SLinus Torvalds return SIGBUS; 13231da177e4SLinus Torvalds } 1324515b029dSDavid Daney if (__get_user(val, va)) { 1325515b029dSDavid Daney MIPS_FPU_EMU_INC_STATS(errors); 1326515b029dSDavid Daney *fault_addr = va; 1327515b029dSDavid Daney return SIGSEGV; 1328515b029dSDavid Daney } 13291da177e4SLinus Torvalds SITOREG(val, MIPSInst_FD(ir)); 13301da177e4SLinus Torvalds break; 13311da177e4SLinus Torvalds 13321da177e4SLinus Torvalds case swxc1_op: 13333fccc015SRalf Baechle va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] + 13341da177e4SLinus Torvalds xcp->regs[MIPSInst_FT(ir)]); 13351da177e4SLinus Torvalds 1336b6ee75edSDavid Daney MIPS_FPU_EMU_INC_STATS(stores); 13371da177e4SLinus Torvalds 13381da177e4SLinus Torvalds SIFROMREG(val, MIPSInst_FS(ir)); 1339515b029dSDavid Daney if (!access_ok(VERIFY_WRITE, va, sizeof(u32))) { 1340515b029dSDavid Daney MIPS_FPU_EMU_INC_STATS(errors); 1341515b029dSDavid Daney *fault_addr = va; 1342515b029dSDavid Daney return SIGBUS; 1343515b029dSDavid Daney } 13441da177e4SLinus Torvalds if (put_user(val, va)) { 1345b6ee75edSDavid Daney MIPS_FPU_EMU_INC_STATS(errors); 1346515b029dSDavid Daney *fault_addr = va; 1347515b029dSDavid Daney return SIGSEGV; 13481da177e4SLinus Torvalds } 13491da177e4SLinus Torvalds break; 13501da177e4SLinus Torvalds 13511da177e4SLinus Torvalds case madd_s_op: 13521da177e4SLinus Torvalds handler = fpemu_sp_madd; 13531da177e4SLinus Torvalds goto scoptop; 13541da177e4SLinus Torvalds case msub_s_op: 13551da177e4SLinus Torvalds handler = fpemu_sp_msub; 13561da177e4SLinus Torvalds goto scoptop; 13571da177e4SLinus Torvalds case nmadd_s_op: 13581da177e4SLinus Torvalds handler = fpemu_sp_nmadd; 13591da177e4SLinus Torvalds goto scoptop; 13601da177e4SLinus Torvalds case nmsub_s_op: 13611da177e4SLinus Torvalds handler = fpemu_sp_nmsub; 13621da177e4SLinus Torvalds goto scoptop; 13631da177e4SLinus Torvalds 13641da177e4SLinus Torvalds scoptop: 13651da177e4SLinus Torvalds SPFROMREG(fr, MIPSInst_FR(ir)); 13661da177e4SLinus Torvalds SPFROMREG(fs, MIPSInst_FS(ir)); 13671da177e4SLinus Torvalds SPFROMREG(ft, MIPSInst_FT(ir)); 13681da177e4SLinus Torvalds fd = (*handler) (fr, fs, ft); 13691da177e4SLinus Torvalds SPTOREG(fd, MIPSInst_FD(ir)); 13701da177e4SLinus Torvalds 13711da177e4SLinus Torvalds copcsr: 1372c4103526SDeng-Cheng Zhu if (ieee754_cxtest(IEEE754_INEXACT)) { 1373c4103526SDeng-Cheng Zhu MIPS_FPU_EMU_INC_STATS(ieee754_inexact); 13741da177e4SLinus Torvalds rcsr |= FPU_CSR_INE_X | FPU_CSR_INE_S; 1375c4103526SDeng-Cheng Zhu } 1376c4103526SDeng-Cheng Zhu if (ieee754_cxtest(IEEE754_UNDERFLOW)) { 1377c4103526SDeng-Cheng Zhu MIPS_FPU_EMU_INC_STATS(ieee754_underflow); 13781da177e4SLinus Torvalds rcsr |= FPU_CSR_UDF_X | FPU_CSR_UDF_S; 1379c4103526SDeng-Cheng Zhu } 1380c4103526SDeng-Cheng Zhu if (ieee754_cxtest(IEEE754_OVERFLOW)) { 1381c4103526SDeng-Cheng Zhu MIPS_FPU_EMU_INC_STATS(ieee754_overflow); 13821da177e4SLinus Torvalds rcsr |= FPU_CSR_OVF_X | FPU_CSR_OVF_S; 1383c4103526SDeng-Cheng Zhu } 1384c4103526SDeng-Cheng Zhu if (ieee754_cxtest(IEEE754_INVALID_OPERATION)) { 1385c4103526SDeng-Cheng Zhu MIPS_FPU_EMU_INC_STATS(ieee754_invalidop); 13861da177e4SLinus Torvalds rcsr |= FPU_CSR_INV_X | FPU_CSR_INV_S; 1387c4103526SDeng-Cheng Zhu } 13881da177e4SLinus Torvalds 13891da177e4SLinus Torvalds ctx->fcr31 = (ctx->fcr31 & ~FPU_CSR_ALL_X) | rcsr; 13901da177e4SLinus Torvalds if ((ctx->fcr31 >> 5) & ctx->fcr31 & FPU_CSR_ALL_E) { 13913f7cac41SRalf Baechle /*printk ("SIGFPE: FPU csr = %08x\n", 13921da177e4SLinus Torvalds ctx->fcr31); */ 13931da177e4SLinus Torvalds return SIGFPE; 13941da177e4SLinus Torvalds } 13951da177e4SLinus Torvalds 13961da177e4SLinus Torvalds break; 13971da177e4SLinus Torvalds 13981da177e4SLinus Torvalds default: 13991da177e4SLinus Torvalds return SIGILL; 14001da177e4SLinus Torvalds } 14011da177e4SLinus Torvalds break; 14021da177e4SLinus Torvalds } 14031da177e4SLinus Torvalds 14041da177e4SLinus Torvalds case d_fmt:{ /* 1 */ 14052209bcb1SRalf Baechle union ieee754dp(*handler) (union ieee754dp, union ieee754dp, union ieee754dp); 14062209bcb1SRalf Baechle union ieee754dp fd, fr, fs, ft; 14073fccc015SRalf Baechle u64 __user *va; 14081da177e4SLinus Torvalds u64 val; 14091da177e4SLinus Torvalds 14101da177e4SLinus Torvalds switch (MIPSInst_FUNC(ir)) { 14111da177e4SLinus Torvalds case ldxc1_op: 14123fccc015SRalf Baechle va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] + 14131da177e4SLinus Torvalds xcp->regs[MIPSInst_FT(ir)]); 14141da177e4SLinus Torvalds 1415b6ee75edSDavid Daney MIPS_FPU_EMU_INC_STATS(loads); 1416515b029dSDavid Daney if (!access_ok(VERIFY_READ, va, sizeof(u64))) { 1417b6ee75edSDavid Daney MIPS_FPU_EMU_INC_STATS(errors); 1418515b029dSDavid Daney *fault_addr = va; 14191da177e4SLinus Torvalds return SIGBUS; 14201da177e4SLinus Torvalds } 1421515b029dSDavid Daney if (__get_user(val, va)) { 1422515b029dSDavid Daney MIPS_FPU_EMU_INC_STATS(errors); 1423515b029dSDavid Daney *fault_addr = va; 1424515b029dSDavid Daney return SIGSEGV; 1425515b029dSDavid Daney } 14261da177e4SLinus Torvalds DITOREG(val, MIPSInst_FD(ir)); 14271da177e4SLinus Torvalds break; 14281da177e4SLinus Torvalds 14291da177e4SLinus Torvalds case sdxc1_op: 14303fccc015SRalf Baechle va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] + 14311da177e4SLinus Torvalds xcp->regs[MIPSInst_FT(ir)]); 14321da177e4SLinus Torvalds 1433b6ee75edSDavid Daney MIPS_FPU_EMU_INC_STATS(stores); 14341da177e4SLinus Torvalds DIFROMREG(val, MIPSInst_FS(ir)); 1435515b029dSDavid Daney if (!access_ok(VERIFY_WRITE, va, sizeof(u64))) { 1436b6ee75edSDavid Daney MIPS_FPU_EMU_INC_STATS(errors); 1437515b029dSDavid Daney *fault_addr = va; 14381da177e4SLinus Torvalds return SIGBUS; 14391da177e4SLinus Torvalds } 1440515b029dSDavid Daney if (__put_user(val, va)) { 1441515b029dSDavid Daney MIPS_FPU_EMU_INC_STATS(errors); 1442515b029dSDavid Daney *fault_addr = va; 1443515b029dSDavid Daney return SIGSEGV; 1444515b029dSDavid Daney } 14451da177e4SLinus Torvalds break; 14461da177e4SLinus Torvalds 14471da177e4SLinus Torvalds case madd_d_op: 14481da177e4SLinus Torvalds handler = fpemu_dp_madd; 14491da177e4SLinus Torvalds goto dcoptop; 14501da177e4SLinus Torvalds case msub_d_op: 14511da177e4SLinus Torvalds handler = fpemu_dp_msub; 14521da177e4SLinus Torvalds goto dcoptop; 14531da177e4SLinus Torvalds case nmadd_d_op: 14541da177e4SLinus Torvalds handler = fpemu_dp_nmadd; 14551da177e4SLinus Torvalds goto dcoptop; 14561da177e4SLinus Torvalds case nmsub_d_op: 14571da177e4SLinus Torvalds handler = fpemu_dp_nmsub; 14581da177e4SLinus Torvalds goto dcoptop; 14591da177e4SLinus Torvalds 14601da177e4SLinus Torvalds dcoptop: 14611da177e4SLinus Torvalds DPFROMREG(fr, MIPSInst_FR(ir)); 14621da177e4SLinus Torvalds DPFROMREG(fs, MIPSInst_FS(ir)); 14631da177e4SLinus Torvalds DPFROMREG(ft, MIPSInst_FT(ir)); 14641da177e4SLinus Torvalds fd = (*handler) (fr, fs, ft); 14651da177e4SLinus Torvalds DPTOREG(fd, MIPSInst_FD(ir)); 14661da177e4SLinus Torvalds goto copcsr; 14671da177e4SLinus Torvalds 14681da177e4SLinus Torvalds default: 14691da177e4SLinus Torvalds return SIGILL; 14701da177e4SLinus Torvalds } 14711da177e4SLinus Torvalds break; 14721da177e4SLinus Torvalds } 14731da177e4SLinus Torvalds 147451061b88SDeng-Cheng Zhu case 0x3: 147551061b88SDeng-Cheng Zhu if (MIPSInst_FUNC(ir) != pfetch_op) 14761da177e4SLinus Torvalds return SIGILL; 147751061b88SDeng-Cheng Zhu 14781da177e4SLinus Torvalds /* ignore prefx operation */ 14791da177e4SLinus Torvalds break; 14801da177e4SLinus Torvalds 14811da177e4SLinus Torvalds default: 14821da177e4SLinus Torvalds return SIGILL; 14831da177e4SLinus Torvalds } 14841da177e4SLinus Torvalds 14851da177e4SLinus Torvalds return 0; 14861da177e4SLinus Torvalds } 14871da177e4SLinus Torvalds 14881da177e4SLinus Torvalds 14891da177e4SLinus Torvalds 14901da177e4SLinus Torvalds /* 14911da177e4SLinus Torvalds * Emulate a single COP1 arithmetic instruction. 14921da177e4SLinus Torvalds */ 1493eae89076SAtsushi Nemoto static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx, 14941da177e4SLinus Torvalds mips_instruction ir) 14951da177e4SLinus Torvalds { 14961da177e4SLinus Torvalds int rfmt; /* resulting format */ 14971da177e4SLinus Torvalds unsigned rcsr = 0; /* resulting csr */ 14983f7cac41SRalf Baechle unsigned int oldrm; 14993f7cac41SRalf Baechle unsigned int cbit; 15001da177e4SLinus Torvalds unsigned cond; 15011da177e4SLinus Torvalds union { 15022209bcb1SRalf Baechle union ieee754dp d; 15032209bcb1SRalf Baechle union ieee754sp s; 15041da177e4SLinus Torvalds int w; 15051da177e4SLinus Torvalds s64 l; 15061da177e4SLinus Torvalds } rv; /* resulting value */ 15073f7cac41SRalf Baechle u64 bits; 15081da177e4SLinus Torvalds 1509b6ee75edSDavid Daney MIPS_FPU_EMU_INC_STATS(cp1ops); 15101da177e4SLinus Torvalds switch (rfmt = (MIPSInst_FFMT(ir) & 0xf)) { 15111da177e4SLinus Torvalds case s_fmt: { /* 0 */ 15121da177e4SLinus Torvalds union { 15132209bcb1SRalf Baechle union ieee754sp(*b) (union ieee754sp, union ieee754sp); 15142209bcb1SRalf Baechle union ieee754sp(*u) (union ieee754sp); 15151da177e4SLinus Torvalds } handler; 15163f7cac41SRalf Baechle union ieee754sp fs, ft; 15171da177e4SLinus Torvalds 15181da177e4SLinus Torvalds switch (MIPSInst_FUNC(ir)) { 15191da177e4SLinus Torvalds /* binary ops */ 15201da177e4SLinus Torvalds case fadd_op: 15211da177e4SLinus Torvalds handler.b = ieee754sp_add; 15221da177e4SLinus Torvalds goto scopbop; 15231da177e4SLinus Torvalds case fsub_op: 15241da177e4SLinus Torvalds handler.b = ieee754sp_sub; 15251da177e4SLinus Torvalds goto scopbop; 15261da177e4SLinus Torvalds case fmul_op: 15271da177e4SLinus Torvalds handler.b = ieee754sp_mul; 15281da177e4SLinus Torvalds goto scopbop; 15291da177e4SLinus Torvalds case fdiv_op: 15301da177e4SLinus Torvalds handler.b = ieee754sp_div; 15311da177e4SLinus Torvalds goto scopbop; 15321da177e4SLinus Torvalds 15331da177e4SLinus Torvalds /* unary ops */ 15341da177e4SLinus Torvalds case fsqrt_op: 153508a07904SRalf Baechle if (!cpu_has_mips_4_5_r) 153608a07904SRalf Baechle return SIGILL; 153708a07904SRalf Baechle 15381da177e4SLinus Torvalds handler.u = ieee754sp_sqrt; 15391da177e4SLinus Torvalds goto scopuop; 15403f7cac41SRalf Baechle 154108a07904SRalf Baechle /* 154208a07904SRalf Baechle * Note that on some MIPS IV implementations such as the 154308a07904SRalf Baechle * R5000 and R8000 the FSQRT and FRECIP instructions do not 154408a07904SRalf Baechle * achieve full IEEE-754 accuracy - however this emulator does. 154508a07904SRalf Baechle */ 15461da177e4SLinus Torvalds case frsqrt_op: 154708a07904SRalf Baechle if (!cpu_has_mips_4_5_r2) 154808a07904SRalf Baechle return SIGILL; 154908a07904SRalf Baechle 15501da177e4SLinus Torvalds handler.u = fpemu_sp_rsqrt; 15511da177e4SLinus Torvalds goto scopuop; 15523f7cac41SRalf Baechle 15531da177e4SLinus Torvalds case frecip_op: 155408a07904SRalf Baechle if (!cpu_has_mips_4_5_r2) 155508a07904SRalf Baechle return SIGILL; 155608a07904SRalf Baechle 15571da177e4SLinus Torvalds handler.u = fpemu_sp_recip; 15581da177e4SLinus Torvalds goto scopuop; 155908a07904SRalf Baechle 15601da177e4SLinus Torvalds case fmovc_op: 156108a07904SRalf Baechle if (!cpu_has_mips_4_5_r) 156208a07904SRalf Baechle return SIGILL; 156308a07904SRalf Baechle 15641da177e4SLinus Torvalds cond = fpucondbit[MIPSInst_FT(ir) >> 2]; 15651da177e4SLinus Torvalds if (((ctx->fcr31 & cond) != 0) != 15661da177e4SLinus Torvalds ((MIPSInst_FT(ir) & 1) != 0)) 15671da177e4SLinus Torvalds return 0; 15681da177e4SLinus Torvalds SPFROMREG(rv.s, MIPSInst_FS(ir)); 15691da177e4SLinus Torvalds break; 15703f7cac41SRalf Baechle 15711da177e4SLinus Torvalds case fmovz_op: 157208a07904SRalf Baechle if (!cpu_has_mips_4_5_r) 157308a07904SRalf Baechle return SIGILL; 157408a07904SRalf Baechle 15751da177e4SLinus Torvalds if (xcp->regs[MIPSInst_FT(ir)] != 0) 15761da177e4SLinus Torvalds return 0; 15771da177e4SLinus Torvalds SPFROMREG(rv.s, MIPSInst_FS(ir)); 15781da177e4SLinus Torvalds break; 15793f7cac41SRalf Baechle 15801da177e4SLinus Torvalds case fmovn_op: 158108a07904SRalf Baechle if (!cpu_has_mips_4_5_r) 158208a07904SRalf Baechle return SIGILL; 158308a07904SRalf Baechle 15841da177e4SLinus Torvalds if (xcp->regs[MIPSInst_FT(ir)] == 0) 15851da177e4SLinus Torvalds return 0; 15861da177e4SLinus Torvalds SPFROMREG(rv.s, MIPSInst_FS(ir)); 15871da177e4SLinus Torvalds break; 15883f7cac41SRalf Baechle 15891da177e4SLinus Torvalds case fabs_op: 15901da177e4SLinus Torvalds handler.u = ieee754sp_abs; 15911da177e4SLinus Torvalds goto scopuop; 15923f7cac41SRalf Baechle 15931da177e4SLinus Torvalds case fneg_op: 15941da177e4SLinus Torvalds handler.u = ieee754sp_neg; 15951da177e4SLinus Torvalds goto scopuop; 15963f7cac41SRalf Baechle 15971da177e4SLinus Torvalds case fmov_op: 15981da177e4SLinus Torvalds /* an easy one */ 15991da177e4SLinus Torvalds SPFROMREG(rv.s, MIPSInst_FS(ir)); 16001da177e4SLinus Torvalds goto copcsr; 16011da177e4SLinus Torvalds 16021da177e4SLinus Torvalds /* binary op on handler */ 16031da177e4SLinus Torvalds scopbop: 16041da177e4SLinus Torvalds SPFROMREG(fs, MIPSInst_FS(ir)); 16051da177e4SLinus Torvalds SPFROMREG(ft, MIPSInst_FT(ir)); 16061da177e4SLinus Torvalds 16071da177e4SLinus Torvalds rv.s = (*handler.b) (fs, ft); 16081da177e4SLinus Torvalds goto copcsr; 16091da177e4SLinus Torvalds scopuop: 16101da177e4SLinus Torvalds SPFROMREG(fs, MIPSInst_FS(ir)); 16111da177e4SLinus Torvalds rv.s = (*handler.u) (fs); 16121da177e4SLinus Torvalds goto copcsr; 16131da177e4SLinus Torvalds copcsr: 1614c4103526SDeng-Cheng Zhu if (ieee754_cxtest(IEEE754_INEXACT)) { 1615c4103526SDeng-Cheng Zhu MIPS_FPU_EMU_INC_STATS(ieee754_inexact); 16161da177e4SLinus Torvalds rcsr |= FPU_CSR_INE_X | FPU_CSR_INE_S; 1617c4103526SDeng-Cheng Zhu } 1618c4103526SDeng-Cheng Zhu if (ieee754_cxtest(IEEE754_UNDERFLOW)) { 1619c4103526SDeng-Cheng Zhu MIPS_FPU_EMU_INC_STATS(ieee754_underflow); 16201da177e4SLinus Torvalds rcsr |= FPU_CSR_UDF_X | FPU_CSR_UDF_S; 1621c4103526SDeng-Cheng Zhu } 1622c4103526SDeng-Cheng Zhu if (ieee754_cxtest(IEEE754_OVERFLOW)) { 1623c4103526SDeng-Cheng Zhu MIPS_FPU_EMU_INC_STATS(ieee754_overflow); 16241da177e4SLinus Torvalds rcsr |= FPU_CSR_OVF_X | FPU_CSR_OVF_S; 1625c4103526SDeng-Cheng Zhu } 1626c4103526SDeng-Cheng Zhu if (ieee754_cxtest(IEEE754_ZERO_DIVIDE)) { 1627c4103526SDeng-Cheng Zhu MIPS_FPU_EMU_INC_STATS(ieee754_zerodiv); 16281da177e4SLinus Torvalds rcsr |= FPU_CSR_DIV_X | FPU_CSR_DIV_S; 1629c4103526SDeng-Cheng Zhu } 1630c4103526SDeng-Cheng Zhu if (ieee754_cxtest(IEEE754_INVALID_OPERATION)) { 1631c4103526SDeng-Cheng Zhu MIPS_FPU_EMU_INC_STATS(ieee754_invalidop); 16321da177e4SLinus Torvalds rcsr |= FPU_CSR_INV_X | FPU_CSR_INV_S; 1633c4103526SDeng-Cheng Zhu } 16341da177e4SLinus Torvalds break; 16351da177e4SLinus Torvalds 16361da177e4SLinus Torvalds /* unary conv ops */ 16371da177e4SLinus Torvalds case fcvts_op: 16381da177e4SLinus Torvalds return SIGILL; /* not defined */ 16391da177e4SLinus Torvalds 16403f7cac41SRalf Baechle case fcvtd_op: 16411da177e4SLinus Torvalds SPFROMREG(fs, MIPSInst_FS(ir)); 16421da177e4SLinus Torvalds rv.d = ieee754dp_fsp(fs); 16431da177e4SLinus Torvalds rfmt = d_fmt; 16441da177e4SLinus Torvalds goto copcsr; 16451da177e4SLinus Torvalds 16463f7cac41SRalf Baechle case fcvtw_op: 16471da177e4SLinus Torvalds SPFROMREG(fs, MIPSInst_FS(ir)); 16481da177e4SLinus Torvalds rv.w = ieee754sp_tint(fs); 16491da177e4SLinus Torvalds rfmt = w_fmt; 16501da177e4SLinus Torvalds goto copcsr; 16511da177e4SLinus Torvalds 16521da177e4SLinus Torvalds case fround_op: 16531da177e4SLinus Torvalds case ftrunc_op: 16541da177e4SLinus Torvalds case fceil_op: 16553f7cac41SRalf Baechle case ffloor_op: 165608a07904SRalf Baechle if (!cpu_has_mips_2_3_4_5 && !cpu_has_mips64) 165708a07904SRalf Baechle return SIGILL; 165808a07904SRalf Baechle 16593f7cac41SRalf Baechle oldrm = ieee754_csr.rm; 16601da177e4SLinus Torvalds SPFROMREG(fs, MIPSInst_FS(ir)); 166156a64733SRalf Baechle ieee754_csr.rm = modeindex(MIPSInst_FUNC(ir)); 16621da177e4SLinus Torvalds rv.w = ieee754sp_tint(fs); 16631da177e4SLinus Torvalds ieee754_csr.rm = oldrm; 16641da177e4SLinus Torvalds rfmt = w_fmt; 16651da177e4SLinus Torvalds goto copcsr; 16661da177e4SLinus Torvalds 16673f7cac41SRalf Baechle case fcvtl_op: 166808a07904SRalf Baechle if (!cpu_has_mips_3_4_5 && !cpu_has_mips64) 166908a07904SRalf Baechle return SIGILL; 167008a07904SRalf Baechle 16711da177e4SLinus Torvalds SPFROMREG(fs, MIPSInst_FS(ir)); 16721da177e4SLinus Torvalds rv.l = ieee754sp_tlong(fs); 16731da177e4SLinus Torvalds rfmt = l_fmt; 16741da177e4SLinus Torvalds goto copcsr; 16751da177e4SLinus Torvalds 16761da177e4SLinus Torvalds case froundl_op: 16771da177e4SLinus Torvalds case ftruncl_op: 16781da177e4SLinus Torvalds case fceill_op: 16793f7cac41SRalf Baechle case ffloorl_op: 168008a07904SRalf Baechle if (!cpu_has_mips_3_4_5 && !cpu_has_mips64) 168108a07904SRalf Baechle return SIGILL; 168208a07904SRalf Baechle 16833f7cac41SRalf Baechle oldrm = ieee754_csr.rm; 16841da177e4SLinus Torvalds SPFROMREG(fs, MIPSInst_FS(ir)); 168556a64733SRalf Baechle ieee754_csr.rm = modeindex(MIPSInst_FUNC(ir)); 16861da177e4SLinus Torvalds rv.l = ieee754sp_tlong(fs); 16871da177e4SLinus Torvalds ieee754_csr.rm = oldrm; 16881da177e4SLinus Torvalds rfmt = l_fmt; 16891da177e4SLinus Torvalds goto copcsr; 16901da177e4SLinus Torvalds 16911da177e4SLinus Torvalds default: 16921da177e4SLinus Torvalds if (MIPSInst_FUNC(ir) >= fcmp_op) { 16931da177e4SLinus Torvalds unsigned cmpop = MIPSInst_FUNC(ir) - fcmp_op; 16942209bcb1SRalf Baechle union ieee754sp fs, ft; 16951da177e4SLinus Torvalds 16961da177e4SLinus Torvalds SPFROMREG(fs, MIPSInst_FS(ir)); 16971da177e4SLinus Torvalds SPFROMREG(ft, MIPSInst_FT(ir)); 16981da177e4SLinus Torvalds rv.w = ieee754sp_cmp(fs, ft, 16991da177e4SLinus Torvalds cmptab[cmpop & 0x7], cmpop & 0x8); 17001da177e4SLinus Torvalds rfmt = -1; 17011da177e4SLinus Torvalds if ((cmpop & 0x8) && ieee754_cxtest 17021da177e4SLinus Torvalds (IEEE754_INVALID_OPERATION)) 17031da177e4SLinus Torvalds rcsr = FPU_CSR_INV_X | FPU_CSR_INV_S; 17041da177e4SLinus Torvalds else 17051da177e4SLinus Torvalds goto copcsr; 17061da177e4SLinus Torvalds 17073f7cac41SRalf Baechle } else 17081da177e4SLinus Torvalds return SIGILL; 17091da177e4SLinus Torvalds break; 17101da177e4SLinus Torvalds } 17111da177e4SLinus Torvalds break; 17121da177e4SLinus Torvalds } 17131da177e4SLinus Torvalds 17141da177e4SLinus Torvalds case d_fmt: { 17153f7cac41SRalf Baechle union ieee754dp fs, ft; 17161da177e4SLinus Torvalds union { 17172209bcb1SRalf Baechle union ieee754dp(*b) (union ieee754dp, union ieee754dp); 17182209bcb1SRalf Baechle union ieee754dp(*u) (union ieee754dp); 17191da177e4SLinus Torvalds } handler; 17201da177e4SLinus Torvalds 17211da177e4SLinus Torvalds switch (MIPSInst_FUNC(ir)) { 17221da177e4SLinus Torvalds /* binary ops */ 17231da177e4SLinus Torvalds case fadd_op: 17241da177e4SLinus Torvalds handler.b = ieee754dp_add; 17251da177e4SLinus Torvalds goto dcopbop; 17261da177e4SLinus Torvalds case fsub_op: 17271da177e4SLinus Torvalds handler.b = ieee754dp_sub; 17281da177e4SLinus Torvalds goto dcopbop; 17291da177e4SLinus Torvalds case fmul_op: 17301da177e4SLinus Torvalds handler.b = ieee754dp_mul; 17311da177e4SLinus Torvalds goto dcopbop; 17321da177e4SLinus Torvalds case fdiv_op: 17331da177e4SLinus Torvalds handler.b = ieee754dp_div; 17341da177e4SLinus Torvalds goto dcopbop; 17351da177e4SLinus Torvalds 17361da177e4SLinus Torvalds /* unary ops */ 17371da177e4SLinus Torvalds case fsqrt_op: 173808a07904SRalf Baechle if (!cpu_has_mips_2_3_4_5_r) 173908a07904SRalf Baechle return SIGILL; 174008a07904SRalf Baechle 17411da177e4SLinus Torvalds handler.u = ieee754dp_sqrt; 17421da177e4SLinus Torvalds goto dcopuop; 174308a07904SRalf Baechle /* 174408a07904SRalf Baechle * Note that on some MIPS IV implementations such as the 174508a07904SRalf Baechle * R5000 and R8000 the FSQRT and FRECIP instructions do not 174608a07904SRalf Baechle * achieve full IEEE-754 accuracy - however this emulator does. 174708a07904SRalf Baechle */ 17481da177e4SLinus Torvalds case frsqrt_op: 174908a07904SRalf Baechle if (!cpu_has_mips_4_5_r2) 175008a07904SRalf Baechle return SIGILL; 175108a07904SRalf Baechle 17521da177e4SLinus Torvalds handler.u = fpemu_dp_rsqrt; 17531da177e4SLinus Torvalds goto dcopuop; 17541da177e4SLinus Torvalds case frecip_op: 175508a07904SRalf Baechle if (!cpu_has_mips_4_5_r2) 175608a07904SRalf Baechle return SIGILL; 175708a07904SRalf Baechle 17581da177e4SLinus Torvalds handler.u = fpemu_dp_recip; 17591da177e4SLinus Torvalds goto dcopuop; 17601da177e4SLinus Torvalds case fmovc_op: 176108a07904SRalf Baechle if (!cpu_has_mips_4_5_r) 176208a07904SRalf Baechle return SIGILL; 176308a07904SRalf Baechle 17641da177e4SLinus Torvalds cond = fpucondbit[MIPSInst_FT(ir) >> 2]; 17651da177e4SLinus Torvalds if (((ctx->fcr31 & cond) != 0) != 17661da177e4SLinus Torvalds ((MIPSInst_FT(ir) & 1) != 0)) 17671da177e4SLinus Torvalds return 0; 17681da177e4SLinus Torvalds DPFROMREG(rv.d, MIPSInst_FS(ir)); 17691da177e4SLinus Torvalds break; 17701da177e4SLinus Torvalds case fmovz_op: 177108a07904SRalf Baechle if (!cpu_has_mips_4_5_r) 177208a07904SRalf Baechle return SIGILL; 177308a07904SRalf Baechle 17741da177e4SLinus Torvalds if (xcp->regs[MIPSInst_FT(ir)] != 0) 17751da177e4SLinus Torvalds return 0; 17761da177e4SLinus Torvalds DPFROMREG(rv.d, MIPSInst_FS(ir)); 17771da177e4SLinus Torvalds break; 17781da177e4SLinus Torvalds case fmovn_op: 177908a07904SRalf Baechle if (!cpu_has_mips_4_5_r) 178008a07904SRalf Baechle return SIGILL; 178108a07904SRalf Baechle 17821da177e4SLinus Torvalds if (xcp->regs[MIPSInst_FT(ir)] == 0) 17831da177e4SLinus Torvalds return 0; 17841da177e4SLinus Torvalds DPFROMREG(rv.d, MIPSInst_FS(ir)); 17851da177e4SLinus Torvalds break; 17861da177e4SLinus Torvalds case fabs_op: 17871da177e4SLinus Torvalds handler.u = ieee754dp_abs; 17881da177e4SLinus Torvalds goto dcopuop; 17891da177e4SLinus Torvalds 17901da177e4SLinus Torvalds case fneg_op: 17911da177e4SLinus Torvalds handler.u = ieee754dp_neg; 17921da177e4SLinus Torvalds goto dcopuop; 17931da177e4SLinus Torvalds 17941da177e4SLinus Torvalds case fmov_op: 17951da177e4SLinus Torvalds /* an easy one */ 17961da177e4SLinus Torvalds DPFROMREG(rv.d, MIPSInst_FS(ir)); 17971da177e4SLinus Torvalds goto copcsr; 17981da177e4SLinus Torvalds 17991da177e4SLinus Torvalds /* binary op on handler */ 18003f7cac41SRalf Baechle dcopbop: 18011da177e4SLinus Torvalds DPFROMREG(fs, MIPSInst_FS(ir)); 18021da177e4SLinus Torvalds DPFROMREG(ft, MIPSInst_FT(ir)); 18031da177e4SLinus Torvalds 18041da177e4SLinus Torvalds rv.d = (*handler.b) (fs, ft); 18051da177e4SLinus Torvalds goto copcsr; 18063f7cac41SRalf Baechle dcopuop: 18071da177e4SLinus Torvalds DPFROMREG(fs, MIPSInst_FS(ir)); 18081da177e4SLinus Torvalds rv.d = (*handler.u) (fs); 18091da177e4SLinus Torvalds goto copcsr; 18101da177e4SLinus Torvalds 18113f7cac41SRalf Baechle /* 18123f7cac41SRalf Baechle * unary conv ops 18133f7cac41SRalf Baechle */ 18143f7cac41SRalf Baechle case fcvts_op: 18151da177e4SLinus Torvalds DPFROMREG(fs, MIPSInst_FS(ir)); 18161da177e4SLinus Torvalds rv.s = ieee754sp_fdp(fs); 18171da177e4SLinus Torvalds rfmt = s_fmt; 18181da177e4SLinus Torvalds goto copcsr; 18193f7cac41SRalf Baechle 18201da177e4SLinus Torvalds case fcvtd_op: 18211da177e4SLinus Torvalds return SIGILL; /* not defined */ 18221da177e4SLinus Torvalds 18233f7cac41SRalf Baechle case fcvtw_op: 18241da177e4SLinus Torvalds DPFROMREG(fs, MIPSInst_FS(ir)); 18251da177e4SLinus Torvalds rv.w = ieee754dp_tint(fs); /* wrong */ 18261da177e4SLinus Torvalds rfmt = w_fmt; 18271da177e4SLinus Torvalds goto copcsr; 18281da177e4SLinus Torvalds 18291da177e4SLinus Torvalds case fround_op: 18301da177e4SLinus Torvalds case ftrunc_op: 18311da177e4SLinus Torvalds case fceil_op: 18323f7cac41SRalf Baechle case ffloor_op: 183308a07904SRalf Baechle if (!cpu_has_mips_2_3_4_5_r) 183408a07904SRalf Baechle return SIGILL; 183508a07904SRalf Baechle 18363f7cac41SRalf Baechle oldrm = ieee754_csr.rm; 18371da177e4SLinus Torvalds DPFROMREG(fs, MIPSInst_FS(ir)); 183856a64733SRalf Baechle ieee754_csr.rm = modeindex(MIPSInst_FUNC(ir)); 18391da177e4SLinus Torvalds rv.w = ieee754dp_tint(fs); 18401da177e4SLinus Torvalds ieee754_csr.rm = oldrm; 18411da177e4SLinus Torvalds rfmt = w_fmt; 18421da177e4SLinus Torvalds goto copcsr; 18431da177e4SLinus Torvalds 18443f7cac41SRalf Baechle case fcvtl_op: 184508a07904SRalf Baechle if (!cpu_has_mips_3_4_5 && !cpu_has_mips64) 184608a07904SRalf Baechle return SIGILL; 184708a07904SRalf Baechle 18481da177e4SLinus Torvalds DPFROMREG(fs, MIPSInst_FS(ir)); 18491da177e4SLinus Torvalds rv.l = ieee754dp_tlong(fs); 18501da177e4SLinus Torvalds rfmt = l_fmt; 18511da177e4SLinus Torvalds goto copcsr; 18521da177e4SLinus Torvalds 18531da177e4SLinus Torvalds case froundl_op: 18541da177e4SLinus Torvalds case ftruncl_op: 18551da177e4SLinus Torvalds case fceill_op: 18563f7cac41SRalf Baechle case ffloorl_op: 185708a07904SRalf Baechle if (!cpu_has_mips_3_4_5 && !cpu_has_mips64) 185808a07904SRalf Baechle return SIGILL; 185908a07904SRalf Baechle 18603f7cac41SRalf Baechle oldrm = ieee754_csr.rm; 18611da177e4SLinus Torvalds DPFROMREG(fs, MIPSInst_FS(ir)); 186256a64733SRalf Baechle ieee754_csr.rm = modeindex(MIPSInst_FUNC(ir)); 18631da177e4SLinus Torvalds rv.l = ieee754dp_tlong(fs); 18641da177e4SLinus Torvalds ieee754_csr.rm = oldrm; 18651da177e4SLinus Torvalds rfmt = l_fmt; 18661da177e4SLinus Torvalds goto copcsr; 18671da177e4SLinus Torvalds 18681da177e4SLinus Torvalds default: 18691da177e4SLinus Torvalds if (MIPSInst_FUNC(ir) >= fcmp_op) { 18701da177e4SLinus Torvalds unsigned cmpop = MIPSInst_FUNC(ir) - fcmp_op; 18712209bcb1SRalf Baechle union ieee754dp fs, ft; 18721da177e4SLinus Torvalds 18731da177e4SLinus Torvalds DPFROMREG(fs, MIPSInst_FS(ir)); 18741da177e4SLinus Torvalds DPFROMREG(ft, MIPSInst_FT(ir)); 18751da177e4SLinus Torvalds rv.w = ieee754dp_cmp(fs, ft, 18761da177e4SLinus Torvalds cmptab[cmpop & 0x7], cmpop & 0x8); 18771da177e4SLinus Torvalds rfmt = -1; 18781da177e4SLinus Torvalds if ((cmpop & 0x8) 18791da177e4SLinus Torvalds && 18801da177e4SLinus Torvalds ieee754_cxtest 18811da177e4SLinus Torvalds (IEEE754_INVALID_OPERATION)) 18821da177e4SLinus Torvalds rcsr = FPU_CSR_INV_X | FPU_CSR_INV_S; 18831da177e4SLinus Torvalds else 18841da177e4SLinus Torvalds goto copcsr; 18851da177e4SLinus Torvalds 18861da177e4SLinus Torvalds } 18871da177e4SLinus Torvalds else { 18881da177e4SLinus Torvalds return SIGILL; 18891da177e4SLinus Torvalds } 18901da177e4SLinus Torvalds break; 18911da177e4SLinus Torvalds } 18921da177e4SLinus Torvalds break; 18931da177e4SLinus Torvalds 18943f7cac41SRalf Baechle case w_fmt: 18951da177e4SLinus Torvalds switch (MIPSInst_FUNC(ir)) { 18961da177e4SLinus Torvalds case fcvts_op: 18971da177e4SLinus Torvalds /* convert word to single precision real */ 18981da177e4SLinus Torvalds SPFROMREG(fs, MIPSInst_FS(ir)); 18991da177e4SLinus Torvalds rv.s = ieee754sp_fint(fs.bits); 19001da177e4SLinus Torvalds rfmt = s_fmt; 19011da177e4SLinus Torvalds goto copcsr; 19021da177e4SLinus Torvalds case fcvtd_op: 19031da177e4SLinus Torvalds /* convert word to double precision real */ 19041da177e4SLinus Torvalds SPFROMREG(fs, MIPSInst_FS(ir)); 19051da177e4SLinus Torvalds rv.d = ieee754dp_fint(fs.bits); 19061da177e4SLinus Torvalds rfmt = d_fmt; 19071da177e4SLinus Torvalds goto copcsr; 19081da177e4SLinus Torvalds default: 19091da177e4SLinus Torvalds return SIGILL; 19101da177e4SLinus Torvalds } 19111da177e4SLinus Torvalds break; 19121da177e4SLinus Torvalds } 19131da177e4SLinus Torvalds 19143f7cac41SRalf Baechle case l_fmt: 191508a07904SRalf Baechle 191608a07904SRalf Baechle if (!cpu_has_mips_3_4_5 && !cpu_has_mips64) 191708a07904SRalf Baechle return SIGILL; 191808a07904SRalf Baechle 1919bbd426f5SPaul Burton DIFROMREG(bits, MIPSInst_FS(ir)); 1920bbd426f5SPaul Burton 19211da177e4SLinus Torvalds switch (MIPSInst_FUNC(ir)) { 19221da177e4SLinus Torvalds case fcvts_op: 19231da177e4SLinus Torvalds /* convert long to single precision real */ 1924bbd426f5SPaul Burton rv.s = ieee754sp_flong(bits); 19251da177e4SLinus Torvalds rfmt = s_fmt; 19261da177e4SLinus Torvalds goto copcsr; 19271da177e4SLinus Torvalds case fcvtd_op: 19281da177e4SLinus Torvalds /* convert long to double precision real */ 1929bbd426f5SPaul Burton rv.d = ieee754dp_flong(bits); 19301da177e4SLinus Torvalds rfmt = d_fmt; 19311da177e4SLinus Torvalds goto copcsr; 19321da177e4SLinus Torvalds default: 19331da177e4SLinus Torvalds return SIGILL; 19341da177e4SLinus Torvalds } 19351da177e4SLinus Torvalds break; 19361da177e4SLinus Torvalds 19371da177e4SLinus Torvalds default: 19381da177e4SLinus Torvalds return SIGILL; 19391da177e4SLinus Torvalds } 19401da177e4SLinus Torvalds 19411da177e4SLinus Torvalds /* 19421da177e4SLinus Torvalds * Update the fpu CSR register for this operation. 19431da177e4SLinus Torvalds * If an exception is required, generate a tidy SIGFPE exception, 19441da177e4SLinus Torvalds * without updating the result register. 19451da177e4SLinus Torvalds * Note: cause exception bits do not accumulate, they are rewritten 19461da177e4SLinus Torvalds * for each op; only the flag/sticky bits accumulate. 19471da177e4SLinus Torvalds */ 19481da177e4SLinus Torvalds ctx->fcr31 = (ctx->fcr31 & ~FPU_CSR_ALL_X) | rcsr; 19491da177e4SLinus Torvalds if ((ctx->fcr31 >> 5) & ctx->fcr31 & FPU_CSR_ALL_E) { 19503f7cac41SRalf Baechle /*printk ("SIGFPE: FPU csr = %08x\n",ctx->fcr31); */ 19511da177e4SLinus Torvalds return SIGFPE; 19521da177e4SLinus Torvalds } 19531da177e4SLinus Torvalds 19541da177e4SLinus Torvalds /* 19551da177e4SLinus Torvalds * Now we can safely write the result back to the register file. 19561da177e4SLinus Torvalds */ 19571da177e4SLinus Torvalds switch (rfmt) { 195808a07904SRalf Baechle case -1: 195908a07904SRalf Baechle 196008a07904SRalf Baechle if (cpu_has_mips_4_5_r) 1961c3b9b945SRob Kendrick cbit = fpucondbit[MIPSInst_FD(ir) >> 2]; 19621da177e4SLinus Torvalds else 196308a07904SRalf Baechle cbit = FPU_CSR_COND; 196408a07904SRalf Baechle if (rv.w) 196508a07904SRalf Baechle ctx->fcr31 |= cbit; 196608a07904SRalf Baechle else 196708a07904SRalf Baechle ctx->fcr31 &= ~cbit; 19681da177e4SLinus Torvalds break; 196908a07904SRalf Baechle 19701da177e4SLinus Torvalds case d_fmt: 19711da177e4SLinus Torvalds DPTOREG(rv.d, MIPSInst_FD(ir)); 19721da177e4SLinus Torvalds break; 19731da177e4SLinus Torvalds case s_fmt: 19741da177e4SLinus Torvalds SPTOREG(rv.s, MIPSInst_FD(ir)); 19751da177e4SLinus Torvalds break; 19761da177e4SLinus Torvalds case w_fmt: 19771da177e4SLinus Torvalds SITOREG(rv.w, MIPSInst_FD(ir)); 19781da177e4SLinus Torvalds break; 19791da177e4SLinus Torvalds case l_fmt: 198008a07904SRalf Baechle if (!cpu_has_mips_3_4_5 && !cpu_has_mips64) 198108a07904SRalf Baechle return SIGILL; 198208a07904SRalf Baechle 19831da177e4SLinus Torvalds DITOREG(rv.l, MIPSInst_FD(ir)); 19841da177e4SLinus Torvalds break; 19851da177e4SLinus Torvalds default: 19861da177e4SLinus Torvalds return SIGILL; 19871da177e4SLinus Torvalds } 19881da177e4SLinus Torvalds 19891da177e4SLinus Torvalds return 0; 19901da177e4SLinus Torvalds } 19911da177e4SLinus Torvalds 1992e04582b7SAtsushi Nemoto int fpu_emulator_cop1Handler(struct pt_regs *xcp, struct mips_fpu_struct *ctx, 1993515b029dSDavid Daney int has_fpu, void *__user *fault_addr) 19941da177e4SLinus Torvalds { 1995333d1f67SRalf Baechle unsigned long oldepc, prevepc; 1996102cedc3SLeonid Yegoshin struct mm_decoded_insn dec_insn; 1997102cedc3SLeonid Yegoshin u16 instr[4]; 1998102cedc3SLeonid Yegoshin u16 *instr_ptr; 19991da177e4SLinus Torvalds int sig = 0; 20001da177e4SLinus Torvalds 20011da177e4SLinus Torvalds oldepc = xcp->cp0_epc; 20021da177e4SLinus Torvalds do { 20031da177e4SLinus Torvalds prevepc = xcp->cp0_epc; 20041da177e4SLinus Torvalds 2005102cedc3SLeonid Yegoshin if (get_isa16_mode(prevepc) && cpu_has_mmips) { 2006102cedc3SLeonid Yegoshin /* 2007102cedc3SLeonid Yegoshin * Get next 2 microMIPS instructions and convert them 2008102cedc3SLeonid Yegoshin * into 32-bit instructions. 2009102cedc3SLeonid Yegoshin */ 2010102cedc3SLeonid Yegoshin if ((get_user(instr[0], (u16 __user *)msk_isa16_mode(xcp->cp0_epc))) || 2011102cedc3SLeonid Yegoshin (get_user(instr[1], (u16 __user *)msk_isa16_mode(xcp->cp0_epc + 2))) || 2012102cedc3SLeonid Yegoshin (get_user(instr[2], (u16 __user *)msk_isa16_mode(xcp->cp0_epc + 4))) || 2013102cedc3SLeonid Yegoshin (get_user(instr[3], (u16 __user *)msk_isa16_mode(xcp->cp0_epc + 6)))) { 2014b6ee75edSDavid Daney MIPS_FPU_EMU_INC_STATS(errors); 20151da177e4SLinus Torvalds return SIGBUS; 20161da177e4SLinus Torvalds } 2017102cedc3SLeonid Yegoshin instr_ptr = instr; 2018102cedc3SLeonid Yegoshin 2019102cedc3SLeonid Yegoshin /* Get first instruction. */ 2020102cedc3SLeonid Yegoshin if (mm_insn_16bit(*instr_ptr)) { 2021102cedc3SLeonid Yegoshin /* Duplicate the half-word. */ 2022102cedc3SLeonid Yegoshin dec_insn.insn = (*instr_ptr << 16) | 2023102cedc3SLeonid Yegoshin (*instr_ptr); 2024102cedc3SLeonid Yegoshin /* 16-bit instruction. */ 2025102cedc3SLeonid Yegoshin dec_insn.pc_inc = 2; 2026102cedc3SLeonid Yegoshin instr_ptr += 1; 2027102cedc3SLeonid Yegoshin } else { 2028102cedc3SLeonid Yegoshin dec_insn.insn = (*instr_ptr << 16) | 2029102cedc3SLeonid Yegoshin *(instr_ptr+1); 2030102cedc3SLeonid Yegoshin /* 32-bit instruction. */ 2031102cedc3SLeonid Yegoshin dec_insn.pc_inc = 4; 2032102cedc3SLeonid Yegoshin instr_ptr += 2; 2033515b029dSDavid Daney } 2034102cedc3SLeonid Yegoshin /* Get second instruction. */ 2035102cedc3SLeonid Yegoshin if (mm_insn_16bit(*instr_ptr)) { 2036102cedc3SLeonid Yegoshin /* Duplicate the half-word. */ 2037102cedc3SLeonid Yegoshin dec_insn.next_insn = (*instr_ptr << 16) | 2038102cedc3SLeonid Yegoshin (*instr_ptr); 2039102cedc3SLeonid Yegoshin /* 16-bit instruction. */ 2040102cedc3SLeonid Yegoshin dec_insn.next_pc_inc = 2; 2041102cedc3SLeonid Yegoshin } else { 2042102cedc3SLeonid Yegoshin dec_insn.next_insn = (*instr_ptr << 16) | 2043102cedc3SLeonid Yegoshin *(instr_ptr+1); 2044102cedc3SLeonid Yegoshin /* 32-bit instruction. */ 2045102cedc3SLeonid Yegoshin dec_insn.next_pc_inc = 4; 2046102cedc3SLeonid Yegoshin } 2047102cedc3SLeonid Yegoshin dec_insn.micro_mips_mode = 1; 2048102cedc3SLeonid Yegoshin } else { 2049102cedc3SLeonid Yegoshin if ((get_user(dec_insn.insn, 2050102cedc3SLeonid Yegoshin (mips_instruction __user *) xcp->cp0_epc)) || 2051102cedc3SLeonid Yegoshin (get_user(dec_insn.next_insn, 2052102cedc3SLeonid Yegoshin (mips_instruction __user *)(xcp->cp0_epc+4)))) { 2053102cedc3SLeonid Yegoshin MIPS_FPU_EMU_INC_STATS(errors); 2054102cedc3SLeonid Yegoshin return SIGBUS; 2055102cedc3SLeonid Yegoshin } 2056102cedc3SLeonid Yegoshin dec_insn.pc_inc = 4; 2057102cedc3SLeonid Yegoshin dec_insn.next_pc_inc = 4; 2058102cedc3SLeonid Yegoshin dec_insn.micro_mips_mode = 0; 2059102cedc3SLeonid Yegoshin } 2060102cedc3SLeonid Yegoshin 2061102cedc3SLeonid Yegoshin if ((dec_insn.insn == 0) || 2062102cedc3SLeonid Yegoshin ((dec_insn.pc_inc == 2) && 2063102cedc3SLeonid Yegoshin ((dec_insn.insn & 0xffff) == MM_NOP16))) 2064102cedc3SLeonid Yegoshin xcp->cp0_epc += dec_insn.pc_inc; /* Skip NOPs */ 20651da177e4SLinus Torvalds else { 2066cd21dfcfSRalf Baechle /* 2067cd21dfcfSRalf Baechle * The 'ieee754_csr' is an alias of 2068cd21dfcfSRalf Baechle * ctx->fcr31. No need to copy ctx->fcr31 to 2069cd21dfcfSRalf Baechle * ieee754_csr. But ieee754_csr.rm is ieee 2070cd21dfcfSRalf Baechle * library modes. (not mips rounding mode) 2071cd21dfcfSRalf Baechle */ 2072102cedc3SLeonid Yegoshin sig = cop1Emulate(xcp, ctx, dec_insn, fault_addr); 20731da177e4SLinus Torvalds } 20741da177e4SLinus Torvalds 2075e04582b7SAtsushi Nemoto if (has_fpu) 20761da177e4SLinus Torvalds break; 20771da177e4SLinus Torvalds if (sig) 20781da177e4SLinus Torvalds break; 20791da177e4SLinus Torvalds 20801da177e4SLinus Torvalds cond_resched(); 20811da177e4SLinus Torvalds } while (xcp->cp0_epc > prevepc); 20821da177e4SLinus Torvalds 20831da177e4SLinus Torvalds /* SIGILL indicates a non-fpu instruction */ 20841da177e4SLinus Torvalds if (sig == SIGILL && xcp->cp0_epc != oldepc) 20853f7cac41SRalf Baechle /* but if EPC has advanced, then ignore it */ 20861da177e4SLinus Torvalds sig = 0; 20871da177e4SLinus Torvalds 20881da177e4SLinus Torvalds return sig; 20891da177e4SLinus Torvalds } 2090